From 02507124868144145526a39b0718319bf9db12a7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 12:50:49 -0700 Subject: Initial progress on xilinx_srl --- passes/pmgen/Makefile.inc | 6 +++ passes/pmgen/xilinx_srl.cc | 115 ++++++++++++++++++++++++++++++++++++++++++++ passes/pmgen/xilinx_srl.pmg | 92 +++++++++++++++++++++++++++++++++++ 3 files changed, 213 insertions(+) create mode 100644 passes/pmgen/xilinx_srl.cc create mode 100644 passes/pmgen/xilinx_srl.pmg (limited to 'passes') diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index 382a1b4ad..479e03a56 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -30,3 +30,9 @@ PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN) $(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^) + +# -------------------------------------- + +OBJS += passes/pmgen/xilinx_srl.o +passes/pmgen/xilinx_srl.o: passes/pmgen/xilinx_srl_pm.h +$(eval $(call add_extra_objs,passes/pmgen/xilinx_srl_pm.h)) diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc new file mode 100644 index 000000000..2d052534d --- /dev/null +++ b/passes/pmgen/xilinx_srl.cc @@ -0,0 +1,115 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// for peepopt_pm +bool did_something; + +#include "passes/pmgen/xilinx_srl_pm.h" +#include "passes/pmgen/ice40_dsp_pm.h" +#include "passes/pmgen/peepopt_pm.h" + +void reduce_chain(xilinx_srl_pm &pm, int minlen) +{ + auto &st = pm.st_reduce; + auto &ud = pm.ud_reduce; + + if (GetSize(ud.longest_chain) < minlen) + return; + + log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); + + auto last_cell = ud.longest_chain.back(); + + for (auto cell : ud.longest_chain) { + log_debug(" %s\n", log_id(cell)); + if (cell != last_cell) + pm.autoremove(cell); + } + + Cell *c = last_cell; + SigSpec Q = st.first->getPort(ID(Q)); + c->setPort(ID(Q), Q); + + if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { + c->parameters.clear(); + c->setParam(ID(DEPTH), GetSize(ud.longest_chain)); + // TODO c->setParam(ID(INIT), init); + if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + c->setParam(ID(CLKPOL), 1); + else + log_abort(); + if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) + c->setParam(ID(ENPOL), 1); + else if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PN_))) + c->setParam(ID(ENPOL), 0); + else + c->setParam(ID(ENPOL), 2); + if (c->type.in(ID($_DFF_N_), ID($_DFF_P_))) + c->setPort(ID(E), State::S1); + c->setPort(ID(L), GetSize(ud.longest_chain)-1); + c->type = ID($__XILINX_SHREG_); + } + else + log_abort(); + + log(" -> %s (%s)\n", log_id(c), log_id(c->type)); +} + +struct XilinxSrlPass : public Pass { + XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" xilinx_srl [options] [selection]\n"); + log("\n"); + log("TODO.\n"); + log("\n"); + } + + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n"); + + int minlen = 3; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-minlen" && argidx+1 < args.size()) { + minlen = atoi(args[++argidx].c_str()); + continue; + } + break; + } + extra_args(args, argidx, design); + + auto f = std::bind(reduce_chain, std::placeholders::_1, minlen); + for (auto module : design->selected_modules()) + while (xilinx_srl_pm(module, module->selected_cells()).run_reduce(f)) {} + } +} XilinxSrlPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg new file mode 100644 index 000000000..ae29ac6c9 --- /dev/null +++ b/passes/pmgen/xilinx_srl.pmg @@ -0,0 +1,92 @@ +pattern reduce + +udata > chain longest_chain +udata > non_first_cells + +code + non_first_cells.clear(); + subpattern(setup); +endcode + +match first + select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) + filter !non_first_cells.count(first) +//generate +// SigSpec A = module->addWire(NEW_ID); +// SigSpec B = module->addWire(NEW_ID); +// SigSpec Y = module->addWire(NEW_ID); +// switch (rng(3)) +// { +// case 0: +// module->addAndGate(NEW_ID, A, B, Y); +// break; +// case 1: +// module->addOrGate(NEW_ID, A, B, Y); +// break; +// case 2: +// module->addXorGate(NEW_ID, A, B, Y); +// break; +// } +endmatch + +code + longest_chain.clear(); + chain.push_back(first); + subpattern(tail); +finally + chain.pop_back(); + log_assert(chain.empty()); + if (GetSize(longest_chain) > 1) + accept; +endcode + +// ------------------------------------------------------------------ + +subpattern setup + +match first + select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) +endmatch + +match next + select nusers(port(next, \Q)) == 2 + select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) + index next->type === first->type + index port(next, \Q) === port(first, \D) +endmatch + +code + non_first_cells.insert(next); +endcode + +// ------------------------------------------------------------------ + +subpattern tail +arg first + +match next + semioptional + select nusers(port(next, \Q)) == 2 + select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) + index next->type === chain.back()->type + index port(next, \Q) === port(chain.back(), \D) +//generate 10 +// SigSpec A = module->addWire(NEW_ID); +// SigSpec B = module->addWire(NEW_ID); +// SigSpec Y = port(chain.back().first, chain.back().second); +// Cell *c = module->addAndGate(NEW_ID, A, B, Y); +// c->type = chain.back().first->type; +endmatch + +code + if (next) { + chain.push_back(next); + subpattern(tail); + } else { + if (GetSize(chain) > GetSize(longest_chain)) + longest_chain = chain; + } +finally + if (next) + chain.pop_back(); +endcode -- cgit v1.2.3 From df53fe12e7ed667d36d3829681cfc43a3355b834 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 12:54:11 -0700 Subject: Fix spacing --- passes/pmgen/xilinx_srl.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 2d052534d..bfda55af0 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -93,7 +93,7 @@ struct XilinxSrlPass : public Pass { { log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n"); - int minlen = 3; + int minlen = 3; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -106,7 +106,7 @@ struct XilinxSrlPass : public Pass { } extra_args(args, argidx, design); - auto f = std::bind(reduce_chain, std::placeholders::_1, minlen); + auto f = std::bind(reduce_chain, std::placeholders::_1, minlen); for (auto module : design->selected_modules()) while (xilinx_srl_pm(module, module->selected_cells()).run_reduce(f)) {} } -- cgit v1.2.3 From 5ce0c31d0e01603264b23cff8f6d431902f08b63 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 13:05:10 -0700 Subject: Add init support --- passes/pmgen/xilinx_srl.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index bfda55af0..7240c2fa3 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -42,20 +42,29 @@ void reduce_chain(xilinx_srl_pm &pm, int minlen) auto last_cell = ud.longest_chain.back(); + SigSpec initval; for (auto cell : ud.longest_chain) { log_debug(" %s\n", log_id(cell)); + SigBit Q = cell->getPort(ID(Q)); + log_assert(Q.wire); + auto it = Q.wire->attributes.find(ID(init)); + if (it != Q.wire->attributes.end()) { + initval.append(it->second[Q.offset]); + } + else + initval.append(State::Sx); if (cell != last_cell) pm.autoremove(cell); } Cell *c = last_cell; - SigSpec Q = st.first->getPort(ID(Q)); + SigBit Q = st.first->getPort(ID(Q)); c->setPort(ID(Q), Q); if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { c->parameters.clear(); c->setParam(ID(DEPTH), GetSize(ud.longest_chain)); - // TODO c->setParam(ID(INIT), init); + c->setParam(ID(INIT), initval.as_const()); if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) c->setParam(ID(CLKPOL), 1); else -- cgit v1.2.3 From 52fea5b65829745988de00a5e15975026060e76c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 13:42:03 -0700 Subject: Respect \keep on cells or wires --- passes/pmgen/xilinx_srl.pmg | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index ae29ac6c9..cd7461052 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -10,6 +10,8 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) + select !first->get_bool_attribute(\keep) + select !port(first, \Q).as_wire()->get_bool_attribute(\keep) filter !non_first_cells.count(first) //generate // SigSpec A = module->addWire(NEW_ID); @@ -46,11 +48,15 @@ subpattern setup match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) + select !first->get_bool_attribute(\keep) + select !port(first, \Q).as_wire()->get_bool_attribute(\keep) endmatch match next - select nusers(port(next, \Q)) == 2 select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) + select !next->get_bool_attribute(\keep) + select !port(next, \Q).as_wire()->get_bool_attribute(\keep) + select nusers(port(next, \Q)) == 2 index next->type === first->type index port(next, \Q) === port(first, \D) endmatch @@ -66,8 +72,10 @@ arg first match next semioptional - select nusers(port(next, \Q)) == 2 select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) + select !next->get_bool_attribute(\keep) + select !port(next, \Q).as_wire()->get_bool_attribute(\keep) + select nusers(port(next, \Q)) == 2 index next->type === chain.back()->type index port(next, \Q) === port(chain.back(), \D) //generate 10 -- cgit v1.2.3 From cab2bd083ed25ebe1113d5fd054df5983e5086e7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 13:47:47 -0700 Subject: Get wire via SigBit --- passes/pmgen/xilinx_srl.pmg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index cd7461052..69a9c7af2 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -11,7 +11,7 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->get_bool_attribute(\keep) - select !port(first, \Q).as_wire()->get_bool_attribute(\keep) + select !port(first, \Q)[0].wire->get_bool_attribute(\keep) filter !non_first_cells.count(first) //generate // SigSpec A = module->addWire(NEW_ID); @@ -49,13 +49,13 @@ subpattern setup match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->get_bool_attribute(\keep) - select !port(first, \Q).as_wire()->get_bool_attribute(\keep) + select !port(first, \Q)[0].wire->get_bool_attribute(\keep) endmatch match next select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !next->get_bool_attribute(\keep) - select !port(next, \Q).as_wire()->get_bool_attribute(\keep) + select !port(next, \Q)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === first->type index port(next, \Q) === port(first, \D) @@ -74,7 +74,7 @@ match next semioptional select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !next->get_bool_attribute(\keep) - select !port(next, \Q).as_wire()->get_bool_attribute(\keep) + select !port(next, \Q)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === chain.back()->type index port(next, \Q) === port(chain.back(), \D) -- cgit v1.2.3 From 1c7d721558737292a6e1c5492ac8032fcdd8e31e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 14:26:24 -0700 Subject: Reject if not minlen from inside pattern matcher --- passes/pmgen/xilinx_srl.cc | 16 +++++++++------- passes/pmgen/xilinx_srl.pmg | 3 ++- 2 files changed, 11 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 7240c2fa3..a4a893307 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -30,14 +30,11 @@ bool did_something; #include "passes/pmgen/ice40_dsp_pm.h" #include "passes/pmgen/peepopt_pm.h" -void reduce_chain(xilinx_srl_pm &pm, int minlen) +void reduce_chain(xilinx_srl_pm &pm) { auto &st = pm.st_reduce; auto &ud = pm.ud_reduce; - if (GetSize(ud.longest_chain) < minlen) - return; - log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); auto last_cell = ud.longest_chain.back(); @@ -115,9 +112,14 @@ struct XilinxSrlPass : public Pass { } extra_args(args, argidx, design); - auto f = std::bind(reduce_chain, std::placeholders::_1, minlen); - for (auto module : design->selected_modules()) - while (xilinx_srl_pm(module, module->selected_cells()).run_reduce(f)) {} + for (auto module : design->selected_modules()) { + bool did_something = false; + do { + auto pm = xilinx_srl_pm(module, module->selected_cells()); + pm.ud_reduce.minlen = minlen; + did_something = pm.run_reduce(reduce_chain); + } while (did_something); + } } } XilinxSrlPass; diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 69a9c7af2..3a2096653 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -2,6 +2,7 @@ pattern reduce udata > chain longest_chain udata > non_first_cells +udata minlen code non_first_cells.clear(); @@ -38,7 +39,7 @@ code finally chain.pop_back(); log_assert(chain.empty()); - if (GetSize(longest_chain) > 1) + if (GetSize(longest_chain) >= minlen) accept; endcode -- cgit v1.2.3 From a980f0d4be218040ee2ecf42186583e416f82d91 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 14:35:40 -0700 Subject: Add CLKPOL == 0 --- passes/pmgen/xilinx_srl.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index a4a893307..4a3a30f83 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -64,6 +64,8 @@ void reduce_chain(xilinx_srl_pm &pm) c->setParam(ID(INIT), initval.as_const()); if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) c->setParam(ID(CLKPOL), 1); + else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) + c->setParam(ID(CLKPOL), 0); else log_abort(); if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) -- cgit v1.2.3 From 3c8e8521a6c5431c9350038abcb50dff5dfe8469 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 14:42:11 -0700 Subject: Fix polarity of EN_POL --- passes/pmgen/xilinx_srl.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 4a3a30f83..bd4dc59ab 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -68,9 +68,9 @@ void reduce_chain(xilinx_srl_pm &pm) c->setParam(ID(CLKPOL), 0); else log_abort(); - if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) + if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) c->setParam(ID(ENPOL), 1); - else if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PN_))) + else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) c->setParam(ID(ENPOL), 0); else c->setParam(ID(ENPOL), 2); -- cgit v1.2.3 From 6fa9e03e4cdb981fa829469a94d8c7c6d4c7a22e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 15:35:29 -0700 Subject: xilinx_srl to support FDRE and FDRE_1 --- passes/pmgen/xilinx_srl.cc | 29 +++++++++++++++++++----- passes/pmgen/xilinx_srl.pmg | 54 +++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 73 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index bd4dc59ab..862b44bb0 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -34,6 +34,10 @@ void reduce_chain(xilinx_srl_pm &pm) { auto &st = pm.st_reduce; auto &ud = pm.ud_reduce; + auto param_def = [&ud](Cell *cell, IdString param) { + auto def = ud.default_params.at(std::make_pair(cell->type,param)); + return cell->parameters.at(param, def); + }; log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); @@ -42,14 +46,20 @@ void reduce_chain(xilinx_srl_pm &pm) SigSpec initval; for (auto cell : ud.longest_chain) { log_debug(" %s\n", log_id(cell)); - SigBit Q = cell->getPort(ID(Q)); - log_assert(Q.wire); - auto it = Q.wire->attributes.find(ID(init)); - if (it != Q.wire->attributes.end()) { - initval.append(it->second[Q.offset]); + if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { + SigBit Q = cell->getPort(ID(Q)); + log_assert(Q.wire); + auto it = Q.wire->attributes.find(ID(init)); + if (it != Q.wire->attributes.end()) { + initval.append(it->second[Q.offset]); + } + else + initval.append(State::Sx); } + else if (cell->type.in(ID(FDRE), ID(FDRE_1))) + initval.append(param_def(cell, ID(INIT))); else - initval.append(State::Sx); + log_abort(); if (cell != last_cell) pm.autoremove(cell); } @@ -66,6 +76,8 @@ void reduce_chain(xilinx_srl_pm &pm) c->setParam(ID(CLKPOL), 1); else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) c->setParam(ID(CLKPOL), 0); + else if (c->type.in(ID(FDRE))) + c->setParam(ID(CLKPOL), param_def(c, ID(IS_C_INVERTED)).as_bool() ? 0 : 1); else log_abort(); if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) @@ -119,6 +131,11 @@ struct XilinxSrlPass : public Pass { do { auto pm = xilinx_srl_pm(module, module->selected_cells()); pm.ud_reduce.minlen = minlen; + // TODO: How to get these automatically? + pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; + pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; + pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; + pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; did_something = pm.run_reduce(reduce_chain); } while (did_something); } diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 3a2096653..5ae7690c8 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -3,6 +3,7 @@ pattern reduce udata > chain longest_chain udata > non_first_cells udata minlen +udata ,Const>> default_params code non_first_cells.clear(); @@ -12,7 +13,6 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->get_bool_attribute(\keep) - select !port(first, \Q)[0].wire->get_bool_attribute(\keep) filter !non_first_cells.count(first) //generate // SigSpec A = module->addWire(NEW_ID); @@ -50,19 +50,50 @@ subpattern setup match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->get_bool_attribute(\keep) - select !port(first, \Q)[0].wire->get_bool_attribute(\keep) endmatch +code + if (first->type.in(\FDRE, \FDRE_1)) { + SigBit R = port(first, \R); + if (first->type == \FDRE) { + auto inverted = first->parameters.at(\IS_R_INVERTED, default_params.at(std::make_pair(first->type,\IS_R_INVERTED))).as_bool(); + if (!inverted && R != State::S0) + reject; + if (inverted && R != State::S1) + reject; + } + else if (first->type == \FDRE_1) { + if (R == State::S0) + reject; + } + else log_abort(); + } +endcode + match next select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !next->get_bool_attribute(\keep) - select !port(next, \Q)[0].wire->get_bool_attribute(\keep) + select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === first->type index port(next, \Q) === port(first, \D) endmatch code + if (next->type.in(\FDRE, \FDRE_1)) { + for (auto p : { \R }) + if (port(next, p) != port(first, p)) + reject; + + if (next->type == \FDRE) { + for (auto p : { \IS_C_INVERTED, \IS_D_INVERTED, \IS_R_INVERTED }) { + auto n = next->parameters.at(p, default_params.at(std::make_pair(next->type,p))); + auto f = first->parameters.at(p, default_params.at(std::make_pair(first->type,p))); + if (n != f) + reject; + } + } + } non_first_cells.insert(next); endcode @@ -75,7 +106,7 @@ match next semioptional select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !next->get_bool_attribute(\keep) - select !port(next, \Q)[0].wire->get_bool_attribute(\keep) + select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === chain.back()->type index port(next, \Q) === port(chain.back(), \D) @@ -89,6 +120,21 @@ endmatch code if (next) { + if (next->type.in(\FDRE, \FDRE_1)) { + for (auto p : { \R }) + if (port(next, p) != port(first, p)) + reject; + + if (next->type == \FDRE) { + for (auto p : { \IS_C_INVERTED, \IS_D_INVERTED, \IS_R_INVERTED }) { + auto n = next->parameters.at(p, default_params.at(std::make_pair(next->type,p))); + auto f = first->parameters.at(p, default_params.at(std::make_pair(first->type,p))); + if (n != f) + reject; + } + } + } + chain.push_back(next); subpattern(tail); } else { -- cgit v1.2.3 From 61b4d7ae13c9bdb3c8aca10eb5540eca4c6d6007 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 15:41:46 -0700 Subject: Use Cell::has_keep_attribute() --- passes/pmgen/xilinx_srl.pmg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 5ae7690c8..e90bac68d 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -12,7 +12,7 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) - select !first->get_bool_attribute(\keep) + select !first->has_keep_attribute() filter !non_first_cells.count(first) //generate // SigSpec A = module->addWire(NEW_ID); @@ -49,7 +49,7 @@ subpattern setup match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) - select !first->get_bool_attribute(\keep) + select !first->has_keep_attribute() endmatch code @@ -72,7 +72,7 @@ endcode match next select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) - select !next->get_bool_attribute(\keep) + select !next->has_keep_attribute() select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === first->type @@ -105,7 +105,7 @@ arg first match next semioptional select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) - select !next->get_bool_attribute(\keep) + select !next->has_keep_attribute() select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === chain.back()->type -- cgit v1.2.3 From b0a3b430bf1a54b00daf9a33818598057f67cf7c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 15:44:07 -0700 Subject: attribute -> attr --- passes/pmgen/xilinx_srl.pmg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index e90bac68d..6c740b7a7 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -12,7 +12,7 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) - select !first->has_keep_attribute() + select !first->has_keep_attr() filter !non_first_cells.count(first) //generate // SigSpec A = module->addWire(NEW_ID); @@ -49,7 +49,7 @@ subpattern setup match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) - select !first->has_keep_attribute() + select !first->has_keep_attr() endmatch code @@ -72,7 +72,7 @@ endcode match next select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) - select !next->has_keep_attribute() + select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === first->type @@ -105,7 +105,7 @@ arg first match next semioptional select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) - select !next->has_keep_attribute() + select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === chain.back()->type -- cgit v1.2.3 From 6d76ae4c65d3a7b403888219900a3c0f85ee737d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 15:46:58 -0700 Subject: Rename pattern to fixed --- passes/pmgen/xilinx_srl.cc | 18 +++++++++--------- passes/pmgen/xilinx_srl.pmg | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 862b44bb0..029cb3235 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -30,10 +30,10 @@ bool did_something; #include "passes/pmgen/ice40_dsp_pm.h" #include "passes/pmgen/peepopt_pm.h" -void reduce_chain(xilinx_srl_pm &pm) +void fixed(xilinx_srl_pm &pm) { - auto &st = pm.st_reduce; - auto &ud = pm.ud_reduce; + auto &st = pm.st_fixed; + auto &ud = pm.ud_fixed; auto param_def = [&ud](Cell *cell, IdString param) { auto def = ud.default_params.at(std::make_pair(cell->type,param)); return cell->parameters.at(param, def); @@ -130,13 +130,13 @@ struct XilinxSrlPass : public Pass { bool did_something = false; do { auto pm = xilinx_srl_pm(module, module->selected_cells()); - pm.ud_reduce.minlen = minlen; + pm.ud_fixed.minlen = minlen; // TODO: How to get these automatically? - pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; - pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; - pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; - pm.ud_reduce.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; - did_something = pm.run_reduce(reduce_chain); + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; + did_something = pm.run_fixed(fixed); } while (did_something); } } diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 6c740b7a7..e7086c424 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -1,4 +1,4 @@ -pattern reduce +pattern fixed udata > chain longest_chain udata > non_first_cells -- cgit v1.2.3 From 15188033da68c89c409af0839f22e6acc573abb7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 17:34:40 -0700 Subject: Add variable length support to xilinx_srl --- passes/pmgen/xilinx_srl.cc | 112 +++++++++++++++++++++++++++++++++++++++----- passes/pmgen/xilinx_srl.pmg | 66 +++++++++++++++++++++++++- 2 files changed, 164 insertions(+), 14 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 029cb3235..ce77a3308 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -30,7 +30,7 @@ bool did_something; #include "passes/pmgen/ice40_dsp_pm.h" #include "passes/pmgen/peepopt_pm.h" -void fixed(xilinx_srl_pm &pm) +void run_fixed(xilinx_srl_pm &pm) { auto &st = pm.st_fixed; auto &ud = pm.ud_fixed; @@ -39,7 +39,7 @@ void fixed(xilinx_srl_pm &pm) return cell->parameters.at(param, def); }; - log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); + log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); auto last_cell = ud.longest_chain.back(); @@ -97,6 +97,68 @@ void fixed(xilinx_srl_pm &pm) log(" -> %s (%s)\n", log_id(c), log_id(c->type)); } +void run_variable(xilinx_srl_pm &pm) +{ + auto &st = pm.st_variable; + auto &ud = pm.ud_variable; + + log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type)); + + auto last_cell = ud.chain.back(); + + SigSpec initval; + for (auto cell : ud.chain) { + log_debug(" %s\n", log_id(cell)); + if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { + SigBit Q = cell->getPort(ID(Q)); + log_assert(Q.wire); + auto it = Q.wire->attributes.find(ID(init)); + if (it != Q.wire->attributes.end()) { + initval.append(it->second[Q.offset]); + } + else + initval.append(State::Sx); + } + else + log_abort(); + if (cell != last_cell) + pm.autoremove(cell); + } + pm.autoremove(st.shiftx); + + Cell *c = last_cell; + SigBit Q = st.first->getPort(ID(Q)); + c->setPort(ID(Q), Q); + + if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { + c->parameters.clear(); + c->setParam(ID(DEPTH), GetSize(ud.chain)); + c->setParam(ID(INIT), initval.as_const()); + if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + c->setParam(ID(CLKPOL), 1); + else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) + c->setParam(ID(CLKPOL), 0); + else + log_abort(); + if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) + c->setParam(ID(ENPOL), 1); + else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) + c->setParam(ID(ENPOL), 0); + else + c->setParam(ID(ENPOL), 2); + if (c->type.in(ID($_DFF_N_), ID($_DFF_P_))) + c->setPort(ID(E), State::S1); + c->setPort(ID(L), st.shiftx->getPort(ID(B))); + c->setPort(ID(Q), st.shiftx->getPort(ID(Y))); + c->type = ID($__XILINX_SHREG_); + } + else + log_abort(); + + log(" -> %s (%s)\n", log_id(c), log_id(c->type)); + +} + struct XilinxSrlPass : public Pass { XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { } void help() YS_OVERRIDE @@ -113,6 +175,8 @@ struct XilinxSrlPass : public Pass { { log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n"); + bool fixed = false; + bool variable = false; int minlen = 3; size_t argidx; @@ -122,22 +186,46 @@ struct XilinxSrlPass : public Pass { minlen = atoi(args[++argidx].c_str()); continue; } + if (args[argidx] == "-fixed") { + fixed = true; + continue; + } + if (args[argidx] == "-variable") { + variable = true; + continue; + } break; } extra_args(args, argidx, design); + if (!fixed && !variable) + log_cmd_error("'-fixed' and/or '-variable' must be specified.\n"); + for (auto module : design->selected_modules()) { bool did_something = false; - do { - auto pm = xilinx_srl_pm(module, module->selected_cells()); - pm.ud_fixed.minlen = minlen; - // TODO: How to get these automatically? - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; - did_something = pm.run_fixed(fixed); - } while (did_something); + if (fixed) + do { + auto pm = xilinx_srl_pm(module, module->selected_cells()); + pm.ud_fixed.minlen = minlen; + // TODO: How to get these automatically? + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; + did_something = pm.run_fixed(run_fixed); + } while (did_something); + if (variable) + do { + auto pm = xilinx_srl_pm(module, module->selected_cells()); + pm.ud_variable.minlen = minlen; + for (auto p : module->ports) { + auto w = module->wire(p); + if (w->port_output) + for (auto b : pm.sigmap(w)) + pm.ud_variable.output_bits.insert(b); + } + did_something = pm.run_variable(run_variable); + } while (did_something); } } } XilinxSrlPass; diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index e7086c424..3f4efebe9 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -76,7 +76,7 @@ match next select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === first->type - index port(next, \Q) === port(first, \D) + index port(next, \Q) === port(first, \D) endmatch code @@ -109,7 +109,7 @@ match next select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === chain.back()->type - index port(next, \Q) === port(chain.back(), \D) + index port(next, \Q) === port(chain.back(), \D) //generate 10 // SigSpec A = module->addWire(NEW_ID); // SigSpec B = module->addWire(NEW_ID); @@ -145,3 +145,65 @@ finally if (next) chain.pop_back(); endcode + +// ----------- + +pattern variable + +state shiftx_width +udata minlen +udata > output_bits +udata > chain + +match shiftx + select shiftx->type.in($shiftx) + select !shiftx->has_keep_attr() + select param(shiftx, \Y_WIDTH) == 1 + filter param(shiftx, \A_WIDTH).as_int() >= minlen +endmatch + +code shiftx_width + shiftx_width = param(shiftx, \A_WIDTH).as_int(); +endcode + +match first + select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_) + select nusers(port(first, \Q)) == 2 + index port(first, \Q) === port(shiftx, \A)[shiftx_width-1] + filter !output_bits.count(port(first, \Q)) +endmatch + +code + chain.push_back(first); + subpattern(tail); +finally + if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int()) + accept; + chain.clear(); +endcode + +// ------------------------------------------------------------------ + +subpattern tail +arg shiftx +arg shiftx_width + +match next + semioptional + select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_) + select !next->has_keep_attr() + select !port(next, \D)[0].wire->get_bool_attribute(\keep) + select nusers(port(next, \Q)) == 3 + filter !output_bits.count(port(next, \Q)) + index next->type === chain.back()->type + index port(next, \Q) === port(chain.back(), \D) + index port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] +endmatch + +code + if (next) { + chain.push_back(next); + if (GetSize(chain) < shiftx_width) + subpattern(tail); + } +endcode -- cgit v1.2.3 From ed7be3e6b68521b2f147034f811a19bd7af86d1a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 17:36:38 -0700 Subject: Add comment --- passes/pmgen/xilinx_srl.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index ce77a3308..71112e3bc 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -218,6 +218,10 @@ struct XilinxSrlPass : public Pass { do { auto pm = xilinx_srl_pm(module, module->selected_cells()); pm.ud_variable.minlen = minlen; + // Since `nusers` does not count module ports as a user, + // and since `sigmap` does not always make such ports + // the canonical signal.. need to maintain a pool these + // ourselves for (auto p : module->ports) { auto w = module->wire(p); if (w->port_output) -- cgit v1.2.3 From 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 18:43:17 -0700 Subject: Trim shiftx_width when upper bits are 1'bx --- passes/pmgen/xilinx_srl.pmg | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 3f4efebe9..d3ba0109f 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -164,6 +164,11 @@ endmatch code shiftx_width shiftx_width = param(shiftx, \A_WIDTH).as_int(); + while (shiftx_width > 1) { + if (port(shiftx, \A)[shiftx_width-1] != State::Sx) + break; + --shiftx_width; + } endcode match first @@ -177,7 +182,7 @@ code chain.push_back(first); subpattern(tail); finally - if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int()) + if (GetSize(chain) == shiftx_width) accept; chain.clear(); endcode -- cgit v1.2.3 From c7859531c2cf56df67a0767a6333ecf9acab7251 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 19:18:05 -0700 Subject: opt_expr to trim A port of $shiftx if Y_WIDTH == 1 --- passes/opt/opt_expr.cc | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'passes') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 858b3560c..b56ce252f 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -745,6 +745,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } + if (cell->type == ID($shiftx) && cell->getPort(ID::Y).size() == 1) { + SigSpec sig_a = assign_map(cell->getPort(ID::A)); + int width; + for (width = GetSize(sig_a); width > 1; width--) { + if (sig_a[width-1] != State::Sx) + break; + } + + if (width < GetSize(sig_a)) { + sig_a.remove(width, GetSize(sig_a)-width); + cell->setPort(ID::A, sig_a); + cell->setParam(ID(A_WIDTH), width); + did_something = true; + goto next_cell; + } + } + if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID::Y).size() == 1 && invert_map.count(assign_map(cell->getPort(ID::A))) != 0) { cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); -- cgit v1.2.3 From 5c8344363f6405d1d6e21868b10b6dc9e02148a4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 19:18:27 -0700 Subject: Revert "Trim shiftx_width when upper bits are 1'bx" This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb. --- passes/pmgen/xilinx_srl.pmg | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index d3ba0109f..3f4efebe9 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -164,11 +164,6 @@ endmatch code shiftx_width shiftx_width = param(shiftx, \A_WIDTH).as_int(); - while (shiftx_width > 1) { - if (port(shiftx, \A)[shiftx_width-1] != State::Sx) - break; - --shiftx_width; - } endcode match first @@ -182,7 +177,7 @@ code chain.push_back(first); subpattern(tail); finally - if (GetSize(chain) == shiftx_width) + if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int()) accept; chain.clear(); endcode -- cgit v1.2.3 From 7d02d17b16d1f120697a5513f29d4eba8deae2a5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 21 Aug 2019 19:18:40 -0700 Subject: Reuse var --- passes/pmgen/xilinx_srl.pmg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 3f4efebe9..4558234de 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -177,7 +177,7 @@ code chain.push_back(first); subpattern(tail); finally - if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int()) + if (GetSize(chain) == shiftx_width) accept; chain.clear(); endcode -- cgit v1.2.3 From 61639d5387cceec6f6c50b851c4c44d6b4f93dad Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 10:51:04 -0700 Subject: Do not run xilinx_srl_pm in fixed loop --- passes/pmgen/xilinx_srl.cc | 52 +++++++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 28 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 71112e3bc..36833839b 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -202,34 +202,30 @@ struct XilinxSrlPass : public Pass { log_cmd_error("'-fixed' and/or '-variable' must be specified.\n"); for (auto module : design->selected_modules()) { - bool did_something = false; - if (fixed) - do { - auto pm = xilinx_srl_pm(module, module->selected_cells()); - pm.ud_fixed.minlen = minlen; - // TODO: How to get these automatically? - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; - did_something = pm.run_fixed(run_fixed); - } while (did_something); - if (variable) - do { - auto pm = xilinx_srl_pm(module, module->selected_cells()); - pm.ud_variable.minlen = minlen; - // Since `nusers` does not count module ports as a user, - // and since `sigmap` does not always make such ports - // the canonical signal.. need to maintain a pool these - // ourselves - for (auto p : module->ports) { - auto w = module->wire(p); - if (w->port_output) - for (auto b : pm.sigmap(w)) - pm.ud_variable.output_bits.insert(b); - } - did_something = pm.run_variable(run_variable); - } while (did_something); + auto pm = xilinx_srl_pm(module, module->selected_cells()); + pm.ud_fixed.minlen = minlen; + + if (fixed) { + // TODO: How to get these automatically? + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; + pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; + pm.run_fixed(run_fixed); + } + if (variable) { + // Since `nusers` does not count module ports as a user, + // and since `sigmap` does not always make such ports + // the canonical signal.. need to maintain a pool these + // ourselves + for (auto p : module->ports) { + auto w = module->wire(p); + if (w->port_output) + for (auto b : pm.sigmap(w)) + pm.ud_variable.output_bits.insert(b); + } + pm.run_variable(run_variable); + } } } } XilinxSrlPass; -- cgit v1.2.3 From 231ddbf95cb2541eb73622e7dcb2744b2308f584 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:02:17 -0700 Subject: Forgot to set ud_variable.minlen --- passes/pmgen/xilinx_srl.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 36833839b..d1dbd77ae 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -204,6 +204,7 @@ struct XilinxSrlPass : public Pass { for (auto module : design->selected_modules()) { auto pm = xilinx_srl_pm(module, module->selected_cells()); pm.ud_fixed.minlen = minlen; + pm.ud_variable.minlen = minlen; if (fixed) { // TODO: How to get these automatically? -- cgit v1.2.3 From 74bd190d3bb3d606f95e9c565ca8ccec70fca290 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:14:59 -0700 Subject: Remove output_bits --- passes/pmgen/xilinx_srl.cc | 13 +------------ passes/pmgen/xilinx_srl.pmg | 10 ++++++---- 2 files changed, 7 insertions(+), 16 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index d1dbd77ae..0120a6c2c 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -214,19 +214,8 @@ struct XilinxSrlPass : public Pass { pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; pm.run_fixed(run_fixed); } - if (variable) { - // Since `nusers` does not count module ports as a user, - // and since `sigmap` does not always make such ports - // the canonical signal.. need to maintain a pool these - // ourselves - for (auto p : module->ports) { - auto w = module->wire(p); - if (w->port_output) - for (auto b : pm.sigmap(w)) - pm.ud_variable.output_bits.insert(b); - } + if (variable) pm.run_variable(run_variable); - } } } } XilinxSrlPass; diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 4558234de..0cc551e92 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -152,13 +152,12 @@ pattern variable state shiftx_width udata minlen -udata > output_bits udata > chain match shiftx select shiftx->type.in($shiftx) select !shiftx->has_keep_attr() - select param(shiftx, \Y_WIDTH) == 1 + select param(shiftx, \Y_WIDTH).as_int() == 1 filter param(shiftx, \A_WIDTH).as_int() >= minlen endmatch @@ -170,7 +169,6 @@ match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_) select nusers(port(first, \Q)) == 2 index port(first, \Q) === port(shiftx, \A)[shiftx_width-1] - filter !output_bits.count(port(first, \Q)) endmatch code @@ -194,7 +192,6 @@ match next select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 3 - filter !output_bits.count(port(next, \Q)) index next->type === chain.back()->type index port(next, \Q) === port(chain.back(), \D) index port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] @@ -202,6 +199,11 @@ endmatch code if (next) { + auto sig = port(next, \Q); + log_warning("nusers of '%s'\n", log_signal(sig)); + for (auto bit : sigmap(sig)) + for (auto user : sigusers[bit]) + log_warning("\t%s\n", log_id(user)); chain.push_back(next); if (GetSize(chain) < shiftx_width) subpattern(tail); -- cgit v1.2.3 From 9f3ed1726ea82d18b5f3410fd60d3a96c652f447 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:15:16 -0700 Subject: pmgen to also iterate over all module ports --- passes/pmgen/pmgen.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 18c3bf5a5..8944ac2bf 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -390,8 +390,6 @@ with open(outfile, "w") as f: print(" void add_siguser(const SigSpec &sig, Cell *cell) {", file=f) print(" for (auto bit : sigmap(sig)) {", file=f) print(" if (bit.wire == nullptr) continue;", file=f) - print(" if (sigusers.count(bit) == 0 && bit.wire->port_id)", file=f) - print(" sigusers[bit].insert(nullptr);", file=f) print(" sigusers[bit].insert(cell);", file=f) print(" }", file=f) print(" }", file=f) @@ -450,6 +448,10 @@ with open(outfile, "w") as f: print(" for (auto &conn : cell->connections())", file=f) print(" add_siguser(conn.second, cell);", file=f) print(" }", file=f) + print(" for (auto port : module->ports)", file=f) + print(" add_siguser(module->wire(port), nullptr);", file=f) + print(" ", file=f) + print(" for (auto cell : cells) {", file=f) for index in range(len(blocks)): -- cgit v1.2.3 From 36d94caec169d232e8bf1a668ef9062ab38395ea Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:22:09 -0700 Subject: Remove `shregmap -tech xilinx` additions --- passes/techmap/shregmap.cc | 197 ++------------------------------------------- 1 file changed, 8 insertions(+), 189 deletions(-) (limited to 'passes') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 5e298d8dd..d472d1275 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -26,9 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct ShregmapTech { virtual ~ShregmapTech() { } - virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {} - virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} - virtual bool analyze(vector &taps, const vector &qbits) = 0; + virtual bool analyze(vector &taps) = 0; virtual bool fixup(Cell *cell, dict &taps) = 0; }; @@ -56,7 +54,7 @@ struct ShregmapOptions struct ShregmapTechGreenpak4 : ShregmapTech { - bool analyze(vector &taps, const vector &/*qbits*/) + bool analyze(vector &taps) { if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) { taps.clear(); @@ -93,155 +91,6 @@ struct ShregmapTechGreenpak4 : ShregmapTech } }; -struct ShregmapTechXilinx7 : ShregmapTech -{ - dict> sigbit_to_shiftx_offset; - const ShregmapOptions &opts; - - ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {} - - virtual void init(const Module* module, const SigMap &sigmap) override - { - for (const auto &i : module->cells_) { - auto cell = i.second; - if (cell->type == ID($shiftx)) { - if (cell->getParam(ID(Y_WIDTH)) != 1) continue; - int j = 0; - for (auto bit : sigmap(cell->getPort(ID::A))) - sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0); - log_assert(j == cell->getParam(ID(A_WIDTH)).as_int()); - } - else if (cell->type == ID($mux)) { - int j = 0; - for (auto bit : sigmap(cell->getPort(ID::A))) - sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++); - j = 0; - for (auto bit : sigmap(cell->getPort(ID::B))) - sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++); - } - } - } - - virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override - { - auto it = sigbit_to_shiftx_offset.find(bit); - if (it == sigbit_to_shiftx_offset.end()) - return; - if (cell) { - if (cell->type == ID($shiftx) && port == ID::A) - return; - if (cell->type == ID($mux) && port.in(ID::A, ID::B)) - return; - } - sigbit_to_shiftx_offset.erase(it); - } - - virtual bool analyze(vector &taps, const vector &qbits) override - { - if (GetSize(taps) == 1) - return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]); - - if (taps.back() < opts.minlen-1) - return false; - - Cell *shiftx = nullptr; - int group = 0; - for (int i = 0; i < GetSize(taps); ++i) { - auto it = sigbit_to_shiftx_offset.find(qbits[i]); - if (it == sigbit_to_shiftx_offset.end()) - return false; - - // Check taps are sequential - if (i != taps[i]) - return false; - // Check taps are not connected to a shift register, - // or sequential to the same shift register - if (i == 0) { - int offset; - std::tie(shiftx,offset,group) = it->second; - if (offset != i) - return false; - } - else { - Cell *shiftx_ = std::get<0>(it->second); - if (shiftx_ != shiftx) - return false; - int offset = std::get<1>(it->second); - if (offset != i) - return false; - int group_ = std::get<2>(it->second); - if (group_ != group) - return false; - } - } - log_assert(shiftx); - - // Only map if $shiftx exclusively covers the shift register - if (shiftx->type == ID($shiftx)) { - if (GetSize(taps) > shiftx->getParam(ID(A_WIDTH)).as_int()) - return false; - // Due to padding the most significant bits of A may be 1'bx, - // and if so, discount them - if (GetSize(taps) < shiftx->getParam(ID(A_WIDTH)).as_int()) { - const SigSpec A = shiftx->getPort(ID::A); - const int A_width = shiftx->getParam(ID(A_WIDTH)).as_int(); - for (int i = GetSize(taps); i < A_width; ++i) - if (A[i] != RTLIL::Sx) return false; - } - else if (GetSize(taps) != shiftx->getParam(ID(A_WIDTH)).as_int()) - return false; - } - else if (shiftx->type == ID($mux)) { - if (GetSize(taps) != 2) - return false; - } - else log_abort(); - - return true; - } - - virtual bool fixup(Cell *cell, dict &taps) override - { - const auto &tap = *taps.begin(); - auto bit = tap.second; - - auto it = sigbit_to_shiftx_offset.find(bit); - log_assert(it != sigbit_to_shiftx_offset.end()); - - auto newcell = cell->module->addCell(NEW_ID, ID($__XILINX_SHREG_)); - newcell->set_src_attribute(cell->get_src_attribute()); - newcell->setParam(ID(DEPTH), cell->getParam(ID(DEPTH))); - newcell->setParam(ID(INIT), cell->getParam(ID(INIT))); - newcell->setParam(ID(CLKPOL), cell->getParam(ID(CLKPOL))); - newcell->setParam(ID(ENPOL), cell->getParam(ID(ENPOL))); - - newcell->setPort(ID(C), cell->getPort(ID(C))); - newcell->setPort(ID(D), cell->getPort(ID(D))); - if (cell->hasPort(ID(E))) - newcell->setPort(ID(E), cell->getPort(ID(E))); - - Cell* shiftx = std::get<0>(it->second); - RTLIL::SigSpec l_wire, q_wire; - if (shiftx->type == ID($shiftx)) { - l_wire = shiftx->getPort(ID::B); - q_wire = shiftx->getPort(ID::Y); - shiftx->setPort(ID::Y, cell->module->addWire(NEW_ID)); - } - else if (shiftx->type == ID($mux)) { - l_wire = shiftx->getPort(ID(S)); - q_wire = shiftx->getPort(ID::Y); - shiftx->setPort(ID::Y, cell->module->addWire(NEW_ID)); - } - else log_abort(); - - newcell->setPort(ID(Q), q_wire); - newcell->setPort(ID(L), l_wire); - - return false; - } -}; - - struct ShregmapWorker { Module *module; @@ -264,10 +113,8 @@ struct ShregmapWorker for (auto wire : module->wires()) { if (wire->port_output || wire->get_bool_attribute(ID::keep)) { - for (auto bit : sigmap(wire)) { + for (auto bit : sigmap(wire)) sigbit_with_non_chain_users.insert(bit); - if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); - } } if (wire->attributes.count(ID(init))) { @@ -293,22 +140,10 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) { - // Insertion not successful means that d_bit is already - // connected to another register, thus mark it as a - // non chain user ... + if (sigbit_chain_next.count(d_bit)) { sigbit_with_non_chain_users.insert(d_bit); - // ... and clone d_bit into another wire, and use that - // wire as a different key in the d_bit-to-cell dictionary - // so that it can be identified as another chain - // (omitting this common flop) - // Link: https://github.com/YosysHQ/yosys/pull/1085 - Wire *wire = module->addWire(NEW_ID); - module->connect(wire, d_bit); - sigmap.add(wire, d_bit); - sigbit_chain_next.insert(std::make_pair(wire, cell)); - } + } else + sigbit_chain_next[d_bit] = cell; sigbit_chain_prev[q_bit] = cell; continue; @@ -317,10 +152,8 @@ struct ShregmapWorker for (auto conn : cell->connections()) if (cell->input(conn.first)) - for (auto bit : sigmap(conn.second)) { + for (auto bit : sigmap(conn.second)) sigbit_with_non_chain_users.insert(bit); - if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first); - } } } @@ -425,7 +258,7 @@ struct ShregmapWorker if (taps.empty() || taps.back() < depth-1) taps.push_back(depth-1); - if (opts.tech->analyze(taps, qbits)) + if (opts.tech->analyze(taps)) break; taps.pop_back(); @@ -544,9 +377,6 @@ struct ShregmapWorker ShregmapWorker(Module *module, const ShregmapOptions &opts) : module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0) { - if (opts.tech) - opts.tech->init(module, sigmap); - make_sigbit_chain_next_prev(); find_chain_start_cells(); @@ -617,11 +447,6 @@ struct ShregmapPass : public Pass { log("\n"); log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); - log(" this option also implies -clkpol pos -zinit\n"); - log("\n"); - log(" -tech xilinx\n"); - log(" map to xilinx dynamic-length shift registers.\n"); - log(" this option also implies -params -init\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -676,12 +501,6 @@ struct ShregmapPass : public Pass { clkpol = "pos"; opts.zinit = true; opts.tech = new ShregmapTechGreenpak4; - } - else if (tech == "xilinx") { - opts.init = true; - opts.params = true; - enpol = "any_or_none"; - opts.tech = new ShregmapTechXilinx7(opts); } else { argidx--; break; -- cgit v1.2.3 From cabadb85e2520bd07fa5071d553235da3614b462 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:25:19 -0700 Subject: Add copyright --- passes/pmgen/xilinx_srl.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 0120a6c2c..45a78a320 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf + * (C) 2019 Eddie Hung * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above -- cgit v1.2.3 From 6e8fda8bf074ca14c5bd58c0dbafc3a5c8ec8e7f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 11:52:24 -0700 Subject: Add doc --- passes/pmgen/xilinx_srl.cc | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 45a78a320..22fb93e18 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -168,7 +168,20 @@ struct XilinxSrlPass : public Pass { log("\n"); log(" xilinx_srl [options] [selection]\n"); log("\n"); - log("TODO.\n"); + log("This pass converts chains of built-in flops ($_DFF_[NP]_, $_DFFE_*) as well as\n"); + log("Xilinx flops (FDRE, FDRE_1) into a $__XILINX_SHREG cell. Chains must be of the\n"); + log("same type, clock, clock polarity, enable, enable polarity (when relevant).\n"); + log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred."); + log("\n"); + log(" -minlen N\n"); + log(" min length of shift register (default = 3)\n"); + log("\n"); + log(" -fixed\n"); + log(" infer fixed-length shift registers.\n"); + log("\n"); + log(" -variable\n"); + log(" infer variable-length shift registers (i.e. fixed-length shifts where\n"); + log(" each element also fans-out to a $shiftx cell.\n"); log("\n"); } -- cgit v1.2.3 From e1fff34dde994f6d175311c61c5a63b5a21b549b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 16:16:40 -0700 Subject: If d_bit already in sigbit_chain_next, create extra wire --- passes/techmap/shregmap.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index d472d1275..6c00d4d53 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -140,10 +140,13 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - if (sigbit_chain_next.count(d_bit)) { + auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); + if (!r.second) { sigbit_with_non_chain_users.insert(d_bit); - } else - sigbit_chain_next[d_bit] = cell; + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; -- cgit v1.2.3 From 5ff75b1cdce45fdc8422dbe2ac327217a5d2a2e6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 15:48:20 -0700 Subject: Try way that doesn't involve creating a new wire --- passes/techmap/shregmap.cc | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 6c00d4d53..811b40eac 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -141,12 +141,8 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) { + if (!r.second) sigbit_with_non_chain_users.insert(d_bit); - Wire *wire = module->addWire(NEW_ID); - module->connect(wire, d_bit); - sigbit_chain_next.insert(std::make_pair(wire, cell)); - } sigbit_chain_prev[q_bit] = cell; continue; @@ -164,14 +160,14 @@ struct ShregmapWorker { for (auto it : sigbit_chain_next) { + Cell *c1, *c2 = it.second; + if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first)) goto start_cell; - if (sigbit_chain_prev.count(it.first) != 0) + c1 = sigbit_chain_prev.at(it.first, nullptr); + if (c1 != nullptr) { - Cell *c1 = sigbit_chain_prev.at(it.first); - Cell *c2 = it.second; - if (c1->type != c2->type) goto start_cell; @@ -181,6 +177,15 @@ struct ShregmapWorker IdString d_port = opts.ffcells.at(c1->type).first; IdString q_port = opts.ffcells.at(c1->type).second; + // If the previous cell's D has other non chain users, + // then it is possible that this previous cell could + // be a start of the chain + SigBit d_bit = sigmap(c1->getPort(d_port).as_bit()); + if (sigbit_with_non_chain_users.count(d_bit)) { + c2 = c1; + goto start_cell; + } + auto c1_conn = c1->connections(); auto c2_conn = c1->connections(); @@ -197,7 +202,7 @@ struct ShregmapWorker } start_cell: - chain_start_cells.insert(it.second); + chain_start_cells.insert(c2); } } -- cgit v1.2.3 From 8691596d19e2384ccf946f2b391bf5c17db0d60e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 16:05:42 -0700 Subject: Revert "Try way that doesn't involve creating a new wire" This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. --- passes/techmap/shregmap.cc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) (limited to 'passes') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 811b40eac..6c00d4d53 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -141,8 +141,12 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) + if (!r.second) { sigbit_with_non_chain_users.insert(d_bit); + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; @@ -160,14 +164,14 @@ struct ShregmapWorker { for (auto it : sigbit_chain_next) { - Cell *c1, *c2 = it.second; - if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first)) goto start_cell; - c1 = sigbit_chain_prev.at(it.first, nullptr); - if (c1 != nullptr) + if (sigbit_chain_prev.count(it.first) != 0) { + Cell *c1 = sigbit_chain_prev.at(it.first); + Cell *c2 = it.second; + if (c1->type != c2->type) goto start_cell; @@ -177,15 +181,6 @@ struct ShregmapWorker IdString d_port = opts.ffcells.at(c1->type).first; IdString q_port = opts.ffcells.at(c1->type).second; - // If the previous cell's D has other non chain users, - // then it is possible that this previous cell could - // be a start of the chain - SigBit d_bit = sigmap(c1->getPort(d_port).as_bit()); - if (sigbit_with_non_chain_users.count(d_bit)) { - c2 = c1; - goto start_cell; - } - auto c1_conn = c1->connections(); auto c2_conn = c1->connections(); @@ -202,7 +197,7 @@ struct ShregmapWorker } start_cell: - chain_start_cells.insert(c2); + chain_start_cells.insert(it.second); } } -- cgit v1.2.3 From cfafd360d52795c9c76c69d008f765d171e2b0ed Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 20 Jun 2019 16:57:54 -0700 Subject: Add comment as per @cliffordwolf --- passes/techmap/shregmap.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'passes') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 6c00d4d53..f308292fa 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -142,7 +142,18 @@ struct ShregmapWorker { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); if (!r.second) { + // Insertion not successful means that d_bit is already + // connected to another register, thus mark it as a + // non chain user ... sigbit_with_non_chain_users.insert(d_bit); + // ... and clone d_bit into another wire, and use that + // wire as a different key in the d_bit-to-cell dictionary + // so that it can be identified as another chain + // (omitting this common flop) + // Link: https://github.com/YosysHQ/yosys/pull/1085 + // NB: This relies on us not updating sigmap with this + // alias otherwise it would think they are the same + // wire Wire *wire = module->addWire(NEW_ID); module->connect(wire, d_bit); sigbit_chain_next.insert(std::make_pair(wire, cell)); -- cgit v1.2.3 From 53fed4f7e9cd6512762cf93c74464d8e40efb414 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 20 Jun 2019 17:03:05 -0700 Subject: Actually, there might not be any harm in updating sigmap... --- passes/techmap/shregmap.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index f308292fa..9da69e8ba 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -151,11 +151,9 @@ struct ShregmapWorker // so that it can be identified as another chain // (omitting this common flop) // Link: https://github.com/YosysHQ/yosys/pull/1085 - // NB: This relies on us not updating sigmap with this - // alias otherwise it would think they are the same - // wire Wire *wire = module->addWire(NEW_ID); module->connect(wire, d_bit); + sigmap.add(wire, d_bit); sigbit_chain_next.insert(std::make_pair(wire, cell)); } -- cgit v1.2.3 From 2b37a093e95036b267481b2dae2046278eef4040 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:42:19 -0700 Subject: In sat: 'x' in init attr should not override constant --- passes/sat/sat.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index dd56d8c71..bcc690fa3 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,6 +268,8 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); + if (bit.is_fully_const() && rhs[i] == State::Sx) + rhs[i] = bit; if (!satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); -- cgit v1.2.3 From 18b64609c25313c73ac18af1c5963bf830f95dba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 12:22:06 -0700 Subject: xilinx_srl to use 'slice' features of pmgen for word level --- passes/pmgen/xilinx_srl.cc | 47 ++++++++++++++++++++++++++++++--------------- passes/pmgen/xilinx_srl.pmg | 34 +++++++++++++++++--------------- 2 files changed, 49 insertions(+), 32 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 22fb93e18..da7acf745 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -105,13 +105,15 @@ void run_variable(xilinx_srl_pm &pm) log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type)); - auto last_cell = ud.chain.back(); + auto last_cell = ud.chain.back().first; SigSpec initval; - for (auto cell : ud.chain) { + for (const auto &i : ud.chain) { + auto cell = i.first; + auto slice = i.second; log_debug(" %s\n", log_id(cell)); - if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { - SigBit Q = cell->getPort(ID(Q)); + if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { + SigBit Q = cell->getPort(ID(Q))[slice]; log_assert(Q.wire); auto it = Q.wire->attributes.find(ID(init)); if (it != Q.wire->attributes.end()) { @@ -123,7 +125,7 @@ void run_variable(xilinx_srl_pm &pm) else log_abort(); if (cell != last_cell) - pm.autoremove(cell); + cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID); } pm.autoremove(st.shiftx); @@ -131,23 +133,36 @@ void run_variable(xilinx_srl_pm &pm) SigBit Q = st.first->getPort(ID(Q)); c->setPort(ID(Q), Q); - if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { - c->parameters.clear(); - c->setParam(ID(DEPTH), GetSize(ud.chain)); - c->setParam(ID(INIT), initval.as_const()); + if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { + Const clkpol, enpol; if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) - c->setParam(ID(CLKPOL), 1); - else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) - c->setParam(ID(CLKPOL), 0); + clkpol = 1; + else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_))) + clkpol = 0; + else if (c->type.in(ID($dff), ID($dffe))) { + clkpol = c->getParam(ID(CLK_POLARITY)); + c->setPort(ID(C), c->getPort(ID(CLK))); + c->unsetPort(ID(CLK)); + } else log_abort(); if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) - c->setParam(ID(ENPOL), 1); + enpol = 1; else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) - c->setParam(ID(ENPOL), 0); + enpol = 0; + else if (c->type.in(ID($dffe))) { + enpol = c->getParam(ID(EN_POLARITY)); + c->setPort(ID(E), c->getPort(ID(EN))); + c->unsetPort(ID(EN)); + } else - c->setParam(ID(ENPOL), 2); - if (c->type.in(ID($_DFF_N_), ID($_DFF_P_))) + enpol = 2; + c->parameters.clear(); + c->setParam(ID(DEPTH), GetSize(ud.chain)); + c->setParam(ID(INIT), initval.as_const()); + c->setParam(ID(CLKPOL), clkpol); + c->setParam(ID(ENPOL), enpol); + if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff))) c->setPort(ID(E), State::S1); c->setPort(ID(L), st.shiftx->getPort(ID(B))); c->setPort(ID(Q), st.shiftx->getPort(ID(Y))); diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 0cc551e92..fffff91e8 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -151,8 +151,9 @@ endcode pattern variable state shiftx_width +state slice udata minlen -udata > chain +udata >> chain match shiftx select shiftx->type.in($shiftx) @@ -166,13 +167,16 @@ code shiftx_width endcode match first - select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_) - select nusers(port(first, \Q)) == 2 - index port(first, \Q) === port(shiftx, \A)[shiftx_width-1] + select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) + select !first->has_keep_attr() + slice idx GetSize(port(first, \Q)) + select nusers(port(first, \Q)[idx]) == 2 + index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] + set slice idx endmatch code - chain.push_back(first); + chain.emplace_back(first, slice); subpattern(tail); finally if (GetSize(chain) == shiftx_width) @@ -185,26 +189,24 @@ endcode subpattern tail arg shiftx arg shiftx_width +arg slice match next semioptional - select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_) + select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) - select nusers(port(next, \Q)) == 3 - index next->type === chain.back()->type - index port(next, \Q) === port(chain.back(), \D) - index port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] + slice idx GetSize(port(next, \Q)) + select nusers(port(next, \Q)[idx]) == 3 + index next->type === chain.back().first->type + index port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] + index port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] + set slice idx endmatch code if (next) { - auto sig = port(next, \Q); - log_warning("nusers of '%s'\n", log_signal(sig)); - for (auto bit : sigmap(sig)) - for (auto user : sigusers[bit]) - log_warning("\t%s\n", log_id(user)); - chain.push_back(next); + chain.emplace_back(next, slice); if (GetSize(chain) < shiftx_width) subpattern(tail); } -- cgit v1.2.3 From 242b3083eac817c927624db735ca3196223f97c0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 13:06:31 -0700 Subject: Cope with possibility that D could connect to Q on same cell --- passes/pmgen/xilinx_srl.pmg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index fffff91e8..5d74b91bc 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -197,7 +197,7 @@ match next select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(next, \Q)) - select nusers(port(next, \Q)[idx]) == 3 + select nusers(port(next, \Q)[idx]) <= 3 index next->type === chain.back().first->type index port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] index port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] -- cgit v1.2.3 From 5939ffdc077eb155e5ecf21da08bb18b69924854 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 13:06:59 -0700 Subject: Forgot to slice --- passes/pmgen/xilinx_srl.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index da7acf745..e21a826df 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -106,6 +106,7 @@ void run_variable(xilinx_srl_pm &pm) log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type)); auto last_cell = ud.chain.back().first; + auto last_slice = ud.chain.back().second; SigSpec initval; for (const auto &i : ud.chain) { @@ -130,7 +131,7 @@ void run_variable(xilinx_srl_pm &pm) pm.autoremove(st.shiftx); Cell *c = last_cell; - SigBit Q = st.first->getPort(ID(Q)); + SigBit Q = st.first->getPort(ID(Q))[last_slice]; c->setPort(ID(Q), Q); if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { -- cgit v1.2.3 From a1f78eab0466ca328b39750b7746deb336c5c973 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 13:15:41 -0700 Subject: indo -> into --- passes/pmgen/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 27ed77091..0856c9ba3 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -195,7 +195,7 @@ create matches for different sections of a cell. For example: The first argument to `slice` is the local variable name used to identify the slice. The second argument is the number of slices that should be created for -this cell. The `set` statement can be used to copy that index indo a state +this cell. The `set` statement can be used to copy that index into a state variable so that later matches and/or code blocks can refer to it. A similar mechanism is "choices", where a list of options is given as -- cgit v1.2.3 From 3d7f4aa0c8841739eb30fa667181475ce22b4187 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 13:56:01 -0700 Subject: Remove (* init *) entry when consumed into SRL --- passes/pmgen/xilinx_srl.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index e21a826df..d446bf47a 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -52,7 +52,9 @@ void run_fixed(xilinx_srl_pm &pm) log_assert(Q.wire); auto it = Q.wire->attributes.find(ID(init)); if (it != Q.wire->attributes.end()) { - initval.append(it->second[Q.offset]); + auto &i = it->second[Q.offset]; + initval.append(i); + i = State::Sx; } else initval.append(State::Sx); @@ -118,7 +120,9 @@ void run_variable(xilinx_srl_pm &pm) log_assert(Q.wire); auto it = Q.wire->attributes.find(ID(init)); if (it != Q.wire->attributes.end()) { - initval.append(it->second[Q.offset]); + auto &i = it->second[Q.offset]; + initval.append(i); + i = State::Sx; } else initval.append(State::Sx); -- cgit v1.2.3 From 8ecfd55d5a02854abf2f59f4bc19ce94479b82fb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 14:16:41 -0700 Subject: Update doc --- passes/pmgen/xilinx_srl.cc | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index d446bf47a..ef3e61661 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -42,7 +42,7 @@ void run_fixed(xilinx_srl_pm &pm) log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); - auto last_cell = ud.longest_chain.back(); + auto first_cell = ud.longest_chain.back(); SigSpec initval; for (auto cell : ud.longest_chain) { @@ -63,11 +63,11 @@ void run_fixed(xilinx_srl_pm &pm) initval.append(param_def(cell, ID(INIT))); else log_abort(); - if (cell != last_cell) + if (cell != first_cell) pm.autoremove(cell); } - Cell *c = last_cell; + Cell *c = first_cell; SigBit Q = st.first->getPort(ID(Q)); c->setPort(ID(Q), Q); @@ -107,8 +107,8 @@ void run_variable(xilinx_srl_pm &pm) log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type)); - auto last_cell = ud.chain.back().first; - auto last_slice = ud.chain.back().second; + auto first_cell = ud.chain.back().first; + auto first_slice = ud.chain.back().second; SigSpec initval; for (const auto &i : ud.chain) { @@ -129,14 +129,21 @@ void run_variable(xilinx_srl_pm &pm) } else log_abort(); - if (cell != last_cell) + if (cell != first_cell) cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID); } pm.autoremove(st.shiftx); + auto last_cell = ud.chain.front().first; + auto last_slice = ud.chain.front().second; + Cell *c = last_cell; - SigBit Q = st.first->getPort(ID(Q))[last_slice]; - c->setPort(ID(Q), Q); + if (c->type.in(ID($dff), ID($dffe))) { + auto &Q = last_cell->connections_.at(ID(Q)); + Q = Q[last_slice]; + auto &D = first_cell->connections_.at(ID(D)); + D = D[first_slice]; + } if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { Const clkpol, enpol; @@ -177,7 +184,6 @@ void run_variable(xilinx_srl_pm &pm) log_abort(); log(" -> %s (%s)\n", log_id(c), log_id(c->type)); - } struct XilinxSrlPass : public Pass { @@ -188,9 +194,10 @@ struct XilinxSrlPass : public Pass { log("\n"); log(" xilinx_srl [options] [selection]\n"); log("\n"); - log("This pass converts chains of built-in flops ($_DFF_[NP]_, $_DFFE_*) as well as\n"); - log("Xilinx flops (FDRE, FDRE_1) into a $__XILINX_SHREG cell. Chains must be of the\n"); - log("same type, clock, clock polarity, enable, enable polarity (when relevant).\n"); + log("This pass converts chains of built-in flops (bit-level: $_DFF_[NP]_, $_DFFE_*\n"); + log("and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a\n"); + log("$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock polarity,\n"); + log("enable, and enable polarity (where relevant).\n"); log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred."); log("\n"); log(" -minlen N\n"); -- cgit v1.2.3 From 1d88887cfdbeedff7dce9024d8fb4ceb014cb2ef Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 14:32:17 -0700 Subject: Add a unique argument to pmgen's nusers() --- passes/pmgen/pmgen.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 573722d68..2f2545c22 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -458,12 +458,16 @@ with open(outfile, "w") as f: print(" }", file=f) print("", file=f) - print(" int nusers(const SigSpec &sig) {", file=f) + print(" int nusers(const SigSpec &sig, bool unique=true) {", file=f) + print(" int i = 0;", file=f) print(" pool users;", file=f) print(" for (auto bit : sigmap(sig))", file=f) - print(" for (auto user : sigusers[bit])", file=f) - print(" users.insert(user);", file=f) - print(" return GetSize(users);", file=f) + print(" if (unique)", file=f); + print(" i += GetSize(sigusers[bit]);", file=f); + print(" else", file=f); + print(" for (auto user : sigusers[bit])", file=f) + print(" users.insert(user);", file=f) + print(" return unique ? GetSize(users) : i;", file=f) print(" }", file=f) print("", file=f) -- cgit v1.2.3 From c2757613b643f11e1b735b8bc4506750bb0f9522 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 14:32:36 -0700 Subject: Check for non unique nusers/fanouts --- passes/pmgen/xilinx_srl.pmg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 5d74b91bc..99fefba00 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -170,7 +170,7 @@ match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !first->has_keep_attr() slice idx GetSize(port(first, \Q)) - select nusers(port(first, \Q)[idx]) == 2 + select nusers(port(first, \Q)[idx], false /* unique */) == 2 index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] set slice idx endmatch @@ -197,7 +197,7 @@ match next select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(next, \Q)) - select nusers(port(next, \Q)[idx]) <= 3 + select nusers(port(next, \Q)[idx], false /* unique */) == 3 index next->type === chain.back().first->type index port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] index port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] -- cgit v1.2.3 From 9cd23cf0feda3e12ceda1f8fa5d28d2b38f2314d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 14:49:34 -0700 Subject: Fix polarity --- passes/pmgen/pmgen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 2f2545c22..c21fe8f87 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -462,7 +462,7 @@ with open(outfile, "w") as f: print(" int i = 0;", file=f) print(" pool users;", file=f) print(" for (auto bit : sigmap(sig))", file=f) - print(" if (unique)", file=f); + print(" if (!unique)", file=f); print(" i += GetSize(sigusers[bit]);", file=f); print(" else", file=f); print(" for (auto user : sigusers[bit])", file=f) -- cgit v1.2.3 From e85e6e8d452e8f2605214cc40a5b4fc4b0e2cdc2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 15:03:42 -0700 Subject: Revert "Fix polarity" This reverts commit 9cd23cf0feda3e12ceda1f8fa5d28d2b38f2314d. --- passes/pmgen/pmgen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index c21fe8f87..2f2545c22 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -462,7 +462,7 @@ with open(outfile, "w") as f: print(" int i = 0;", file=f) print(" pool users;", file=f) print(" for (auto bit : sigmap(sig))", file=f) - print(" if (!unique)", file=f); + print(" if (unique)", file=f); print(" i += GetSize(sigusers[bit]);", file=f); print(" else", file=f); print(" for (auto user : sigusers[bit])", file=f) -- cgit v1.2.3 From ca5de78e762172a6c602470560354eff1de73cf7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 15:04:00 -0700 Subject: Revert "Add a unique argument to pmgen's nusers()" This reverts commit 1d88887cfdbeedff7dce9024d8fb4ceb014cb2ef. --- passes/pmgen/pmgen.py | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 2f2545c22..573722d68 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -458,16 +458,12 @@ with open(outfile, "w") as f: print(" }", file=f) print("", file=f) - print(" int nusers(const SigSpec &sig, bool unique=true) {", file=f) - print(" int i = 0;", file=f) + print(" int nusers(const SigSpec &sig) {", file=f) print(" pool users;", file=f) print(" for (auto bit : sigmap(sig))", file=f) - print(" if (unique)", file=f); - print(" i += GetSize(sigusers[bit]);", file=f); - print(" else", file=f); - print(" for (auto user : sigusers[bit])", file=f) - print(" users.insert(user);", file=f) - print(" return unique ? GetSize(users) : i;", file=f) + print(" for (auto user : sigusers[bit])", file=f) + print(" users.insert(user);", file=f) + print(" return GetSize(users);", file=f) print(" }", file=f) print("", file=f) -- cgit v1.2.3 From c76261878340bc87fc5ab2f5ac8c7a1fb5a1b3a2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 15:08:49 -0700 Subject: Fix last_cell.D --- passes/pmgen/xilinx_srl.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index ef3e61661..c0c827a25 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -141,8 +141,7 @@ void run_variable(xilinx_srl_pm &pm) if (c->type.in(ID($dff), ID($dffe))) { auto &Q = last_cell->connections_.at(ID(Q)); Q = Q[last_slice]; - auto &D = first_cell->connections_.at(ID(D)); - D = D[first_slice]; + last_cell->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]); } if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { -- cgit v1.2.3 From 513af10d77b865fa0a1a6d9a320298ed08a8b4ac Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 15:18:26 -0700 Subject: Check clock is consistent --- passes/pmgen/xilinx_srl.pmg | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 99fefba00..df78cc18e 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -1,5 +1,6 @@ pattern fixed +state clk_port udata > chain longest_chain udata > non_first_cells udata minlen @@ -32,7 +33,10 @@ match first // } endmatch -code +code clk_port + if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)) + clk_port = \C; + else log_abort(); longest_chain.clear(); chain.push_back(first); subpattern(tail); @@ -46,13 +50,17 @@ endcode // ------------------------------------------------------------------ subpattern setup +arg clk_port match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->has_keep_attr() endmatch -code +code clk_port + if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)) + clk_port = \C; + else log_abort(); if (first->type.in(\FDRE, \FDRE_1)) { SigBit R = port(first, \R); if (first->type == \FDRE) { @@ -77,6 +85,7 @@ match next select nusers(port(next, \Q)) == 2 index next->type === first->type index port(next, \Q) === port(first, \D) + filter port(next, clk_port) == port(first, clk_port) endmatch code @@ -101,6 +110,7 @@ endcode subpattern tail arg first +arg clk_port match next semioptional @@ -110,6 +120,7 @@ match next select nusers(port(next, \Q)) == 2 index next->type === chain.back()->type index port(next, \Q) === port(chain.back(), \D) + filter port(next, clk_port) == port(first, clk_port) //generate 10 // SigSpec A = module->addWire(NEW_ID); // SigSpec B = module->addWire(NEW_ID); @@ -150,6 +161,7 @@ endcode pattern variable +state clk_port state shiftx_width state slice udata minlen @@ -170,12 +182,17 @@ match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !first->has_keep_attr() slice idx GetSize(port(first, \Q)) - select nusers(port(first, \Q)[idx], false /* unique */) == 2 + select nusers(port(first, \Q)[idx]) <= 2 index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] set slice idx endmatch -code +code clk_port + if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)) + clk_port = \C; + else if (first->type.in($dff, $dffe)) + clk_port = \CLK; + else log_abort(); chain.emplace_back(first, slice); subpattern(tail); finally @@ -187,9 +204,11 @@ endcode // ------------------------------------------------------------------ subpattern tail +arg first arg shiftx arg shiftx_width arg slice +arg clk_port match next semioptional @@ -197,10 +216,11 @@ match next select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(next, \Q)) - select nusers(port(next, \Q)[idx], false /* unique */) == 3 + select nusers(port(next, \Q)[idx]) <= 3 index next->type === chain.back().first->type index port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] index port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] + filter port(next, clk_port) == port(first, clk_port) set slice idx endmatch -- cgit v1.2.3 From b1caf7be5eef134f7bd84c5336560dd3dff1e29b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 16:09:46 -0700 Subject: Filter on en_port for fixed length --- passes/pmgen/xilinx_srl.pmg | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index df78cc18e..cefd1ea71 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -1,6 +1,6 @@ pattern fixed -state clk_port +state clk_port en_port udata > chain longest_chain udata > non_first_cells udata minlen @@ -33,10 +33,18 @@ match first // } endmatch -code clk_port +code clk_port en_port if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)) clk_port = \C; else log_abort(); + if (first->type.in($_DFF_N_, $_DFF_P_)) + en_port = IdString(); + else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)) + en_port = \E; + else if (first->type.in(\FDRE, \FDRE_1)) + en_port = \CE; + else log_abort(); + longest_chain.clear(); chain.push_back(first); subpattern(tail); @@ -51,16 +59,24 @@ endcode subpattern setup arg clk_port +arg en_port match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->has_keep_attr() endmatch -code clk_port +code clk_port en_port if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)) clk_port = \C; else log_abort(); + if (first->type.in($_DFF_N_, $_DFF_P_)) + en_port = IdString(); + else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)) + en_port = \E; + else if (first->type.in(\FDRE, \FDRE_1)) + en_port = \CE; + else log_abort(); if (first->type.in(\FDRE, \FDRE_1)) { SigBit R = port(first, \R); if (first->type == \FDRE) { @@ -86,6 +102,7 @@ match next index next->type === first->type index port(next, \Q) === port(first, \D) filter port(next, clk_port) == port(first, clk_port) + filter en_port == IdString() || port(next, en_port) == port(first, en_port) endmatch code @@ -111,6 +128,7 @@ endcode subpattern tail arg first arg clk_port +arg en_port match next semioptional @@ -121,6 +139,7 @@ match next index next->type === chain.back()->type index port(next, \Q) === port(chain.back(), \D) filter port(next, clk_port) == port(first, clk_port) + filter en_port == IdString() || port(next, en_port) == port(first, en_port) //generate 10 // SigSpec A = module->addWire(NEW_ID); // SigSpec B = module->addWire(NEW_ID); @@ -131,6 +150,8 @@ endmatch code if (next) { + chain.push_back(next); + if (next->type.in(\FDRE, \FDRE_1)) { for (auto p : { \R }) if (port(next, p) != port(first, p)) @@ -146,7 +167,6 @@ code } } - chain.push_back(next); subpattern(tail); } else { if (GetSize(chain) > GetSize(longest_chain)) -- cgit v1.2.3 From 2217d926a9d353d732ba7dd81a3782f964463f5d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 16:13:16 -0700 Subject: Same for variable length --- passes/pmgen/xilinx_srl.pmg | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index cefd1ea71..531ea1828 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -181,7 +181,7 @@ endcode pattern variable -state clk_port +state clk_port en_port state shiftx_width state slice udata minlen @@ -207,12 +207,18 @@ match first set slice idx endmatch -code clk_port +code clk_port en_port if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)) clk_port = \C; else if (first->type.in($dff, $dffe)) clk_port = \CLK; else log_abort(); + if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)) + en_port = \E; + else if (first->type.in($dff, $dffe)) + en_port = \EN; + else log_abort(); + chain.emplace_back(first, slice); subpattern(tail); finally @@ -229,6 +235,7 @@ arg shiftx arg shiftx_width arg slice arg clk_port +arg en_port match next semioptional @@ -241,6 +248,7 @@ match next index port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] index port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] filter port(next, clk_port) == port(first, clk_port) + filter en_port == IdString() || port(next, en_port) == port(first, en_port) set slice idx endmatch -- cgit v1.2.3 From f2d48142843f2ed8bc9f0e55197ba347d210a6e1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 16:14:57 -0700 Subject: Don't forget $dff has no EN --- passes/pmgen/xilinx_srl.pmg | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 531ea1828..fcfa79ea6 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -213,9 +213,11 @@ code clk_port en_port else if (first->type.in($dff, $dffe)) clk_port = \CLK; else log_abort(); - if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)) + if (first->type.in($_DFF_N_, $_DFF_P_, $dff)) + en_port = IdString(); + else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)) en_port = \E; - else if (first->type.in($dff, $dffe)) + else if (first->type.in($dffe)) en_port = \EN; else log_abort(); -- cgit v1.2.3 From 83e2d87fb80cc5aed018b0f3409f256ef7f7b385 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 16:21:10 -0700 Subject: Keep track of bits in variable length chain, to check for taps --- passes/pmgen/xilinx_srl.pmg | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index fcfa79ea6..d17799208 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -186,6 +186,11 @@ state shiftx_width state slice udata minlen udata >> chain +udata > chain_bits + +code + chain_bits.clear(); +endcode match shiftx select shiftx->type.in($shiftx) @@ -251,13 +256,20 @@ match next index port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] filter port(next, clk_port) == port(first, clk_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port) + filter !chain_bits.count(port(next, \D)[idx]) set slice idx endmatch code if (next) { + chain_bits.insert(port(next, \Q)[slice]); chain.emplace_back(next, slice); if (GetSize(chain) < shiftx_width) subpattern(tail); } +finally + if (next) { + chain_bits.erase(port(next, \Q)[slice]); + chain.pop_back(); + } endcode -- cgit v1.2.3 From 54488cfb82907429f7637201e925e84977f7f5ba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 16:39:37 -0700 Subject: Oops don't need a finally block --- passes/pmgen/xilinx_srl.pmg | 5 ----- 1 file changed, 5 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index d17799208..622655ce8 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -267,9 +267,4 @@ code if (GetSize(chain) < shiftx_width) subpattern(tail); } -finally - if (next) { - chain_bits.erase(port(next, \Q)[slice]); - chain.pop_back(); - } endcode -- cgit v1.2.3 From e081303ee895f2f65465e930d0df8c92fc26c058 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 17:23:52 -0700 Subject: Cleanup FDRE matching --- passes/pmgen/xilinx_srl.pmg | 64 ++++++++++++++------------------------------- 1 file changed, 19 insertions(+), 45 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 622655ce8..9f9308c2a 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -14,6 +14,9 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->has_keep_attr() + select !first->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || !param(first, \IS_R_INVERTED).as_bool() + select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool() + select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0 filter !non_first_cells.count(first) //generate // SigSpec A = module->addWire(NEW_ID); @@ -64,6 +67,9 @@ arg en_port match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->has_keep_attr() + select !first->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || !param(first, \IS_R_INVERTED).as_bool() + select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool() + select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0 endmatch code clk_port en_port @@ -77,21 +83,6 @@ code clk_port en_port else if (first->type.in(\FDRE, \FDRE_1)) en_port = \CE; else log_abort(); - if (first->type.in(\FDRE, \FDRE_1)) { - SigBit R = port(first, \R); - if (first->type == \FDRE) { - auto inverted = first->parameters.at(\IS_R_INVERTED, default_params.at(std::make_pair(first->type,\IS_R_INVERTED))).as_bool(); - if (!inverted && R != State::S0) - reject; - if (inverted && R != State::S1) - reject; - } - else if (first->type == \FDRE_1) { - if (R == State::S0) - reject; - } - else log_abort(); - } endcode match next @@ -99,27 +90,18 @@ match next select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 + select !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == State::S0 index next->type === first->type index port(next, \Q) === port(first, \D) filter port(next, clk_port) == port(first, clk_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port) + filter !next->type.in(\FDRE) || !first->hasParam(\IS_C_INVERTED) || (next->hasParam(\IS_C_INVERTED) && param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()) + filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) + filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) + filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) endmatch code - if (next->type.in(\FDRE, \FDRE_1)) { - for (auto p : { \R }) - if (port(next, p) != port(first, p)) - reject; - - if (next->type == \FDRE) { - for (auto p : { \IS_C_INVERTED, \IS_D_INVERTED, \IS_R_INVERTED }) { - auto n = next->parameters.at(p, default_params.at(std::make_pair(next->type,p))); - auto f = first->parameters.at(p, default_params.at(std::make_pair(first->type,p))); - if (n != f) - reject; - } - } - } non_first_cells.insert(next); endcode @@ -140,6 +122,10 @@ match next index port(next, \Q) === port(chain.back(), \D) filter port(next, clk_port) == port(first, clk_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port) + filter !next->type.in(\FDRE) || !first->hasParam(\IS_C_INVERTED) || (next->hasParam(\IS_C_INVERTED) && param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()) + filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) + filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) + filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) //generate 10 // SigSpec A = module->addWire(NEW_ID); // SigSpec B = module->addWire(NEW_ID); @@ -151,22 +137,6 @@ endmatch code if (next) { chain.push_back(next); - - if (next->type.in(\FDRE, \FDRE_1)) { - for (auto p : { \R }) - if (port(next, p) != port(first, p)) - reject; - - if (next->type == \FDRE) { - for (auto p : { \IS_C_INVERTED, \IS_D_INVERTED, \IS_R_INVERTED }) { - auto n = next->parameters.at(p, default_params.at(std::make_pair(next->type,p))); - auto f = first->parameters.at(p, default_params.at(std::make_pair(first->type,p))); - if (n != f) - reject; - } - } - } - subpattern(tail); } else { if (GetSize(chain) > GetSize(longest_chain)) @@ -206,6 +176,7 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !first->has_keep_attr() + select !first->type.in($dffe) || !param(first, \EN_POLARITY).as_bool() slice idx GetSize(port(first, \Q)) select nusers(port(first, \Q)[idx]) <= 2 index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] @@ -249,6 +220,7 @@ match next select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) + select !next->type.in($dffe) || !param(next, \EN_POLARITY).as_bool() slice idx GetSize(port(next, \Q)) select nusers(port(next, \Q)[idx]) <= 3 index next->type === chain.back().first->type @@ -256,6 +228,8 @@ match next index port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)] filter port(next, clk_port) == port(first, clk_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port) + filter !next->type.in($dff, $dffe) || param(next, \CLK_POLARITY).as_bool() == param(first, \CLK_POLARITY).as_bool() + filter !next->type.in($dffe) || param(next, \EN_POLARITY).as_bool() == param(first, \EN_POLARITY).as_bool() filter !chain_bits.count(port(next, \D)[idx]) set slice idx endmatch -- cgit v1.2.3 From 188b49378a47c7bfc311b4e439ac74635ba85a77 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 17:25:30 -0700 Subject: Create new cell for fixed length SRL --- passes/pmgen/xilinx_srl.cc | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index c0c827a25..e1d38d7bd 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -67,32 +67,40 @@ void run_fixed(xilinx_srl_pm &pm) pm.autoremove(cell); } - Cell *c = first_cell; - SigBit Q = st.first->getPort(ID(Q)); - c->setPort(ID(Q), Q); + auto last_cell = ud.longest_chain.front(); + Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); + pm.module->swap_names(c, first_cell); - if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { - c->parameters.clear(); + if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { c->setParam(ID(DEPTH), GetSize(ud.longest_chain)); c->setParam(ID(INIT), initval.as_const()); - if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) c->setParam(ID(CLKPOL), 1); - else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) + else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) c->setParam(ID(CLKPOL), 0); - else if (c->type.in(ID(FDRE))) - c->setParam(ID(CLKPOL), param_def(c, ID(IS_C_INVERTED)).as_bool() ? 0 : 1); + else if (first_cell->type.in(ID(FDRE))) + c->setParam(ID(CLKPOL), param_def(first_cell, ID(IS_C_INVERTED)).as_bool() ? 0 : 1); else log_abort(); - if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) + if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) c->setParam(ID(ENPOL), 1); - else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) + else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) c->setParam(ID(ENPOL), 0); else c->setParam(ID(ENPOL), 2); - if (c->type.in(ID($_DFF_N_), ID($_DFF_P_))) - c->setPort(ID(E), State::S1); + + c->setPort(ID(C), first_cell->getPort(ID(C))); + c->setPort(ID(D), first_cell->getPort(ID(D))); + c->setPort(ID(Q), last_cell->getPort(ID(Q))); c->setPort(ID(L), GetSize(ud.longest_chain)-1); - c->type = ID($__XILINX_SHREG_); + if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) + c->setPort(ID(E), State::S1); + else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + c->setPort(ID(E), first_cell->getPort(ID(E))); + else if (first_cell->type.in(ID(FDRE), ID(FDRE_1))) + c->setPort(ID(E), first_cell->getPort(ID(CE))); + else + log_abort(); } else log_abort(); -- cgit v1.2.3 From 70ce3d067010d67154c3cd5437caa16b4c8ca195 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 18:11:28 -0700 Subject: Do not enforce !EN_POLARITY on $dffe --- passes/pmgen/xilinx_srl.pmg | 2 -- 1 file changed, 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 9f9308c2a..d41bd3be9 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -176,7 +176,6 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !first->has_keep_attr() - select !first->type.in($dffe) || !param(first, \EN_POLARITY).as_bool() slice idx GetSize(port(first, \Q)) select nusers(port(first, \Q)[idx]) <= 2 index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] @@ -220,7 +219,6 @@ match next select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) - select !next->type.in($dffe) || !param(next, \EN_POLARITY).as_bool() slice idx GetSize(port(next, \Q)) select nusers(port(next, \Q)[idx]) <= 3 index next->type === chain.back().first->type -- cgit v1.2.3 From ee9f6e6243cbea9efbd0f1b0a236e33ac6a0450e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 18:14:06 -0700 Subject: Also add first.Q to chain_bits since variable length --- passes/pmgen/xilinx_srl.pmg | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index d41bd3be9..76134de1a 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -196,6 +196,7 @@ code clk_port en_port en_port = \EN; else log_abort(); + chain_bits.insert(port(first, \Q)[slice]); chain.emplace_back(first, slice); subpattern(tail); finally -- cgit v1.2.3 From a048fc93e8cf187b28bd5ed924643671b9314678 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 18:15:24 -0700 Subject: Do not allow Q of last cell of variable length SRL to be (* keep *) --- passes/pmgen/xilinx_srl.pmg | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 76134de1a..cfa1cacfb 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -176,6 +176,7 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !first->has_keep_attr() + select !port(first, \Q)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(first, \Q)) select nusers(port(first, \Q)[idx]) <= 2 index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] -- cgit v1.2.3 From 791114382774cdf70b16cc5f1cec689f0ddb5c0b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 18:15:49 -0700 Subject: Create new $__XILINX_SHREG_ cell for variable length too --- passes/pmgen/xilinx_srl.cc | 61 +++++++++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 31 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index e1d38d7bd..c332ccb9f 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -142,50 +142,49 @@ void run_variable(xilinx_srl_pm &pm) } pm.autoremove(st.shiftx); - auto last_cell = ud.chain.front().first; - auto last_slice = ud.chain.front().second; - - Cell *c = last_cell; - if (c->type.in(ID($dff), ID($dffe))) { - auto &Q = last_cell->connections_.at(ID(Q)); - Q = Q[last_slice]; - last_cell->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]); - } + Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); + pm.module->swap_names(c, first_cell); - if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { + if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { + c->setParam(ID(DEPTH), GetSize(ud.chain)); + c->setParam(ID(INIT), initval.as_const()); Const clkpol, enpol; - if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) clkpol = 1; - else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_))) + else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_))) clkpol = 0; - else if (c->type.in(ID($dff), ID($dffe))) { - clkpol = c->getParam(ID(CLK_POLARITY)); - c->setPort(ID(C), c->getPort(ID(CLK))); - c->unsetPort(ID(CLK)); - } + else if (first_cell->type.in(ID($dff), ID($dffe))) + clkpol = first_cell->getParam(ID(CLK_POLARITY)); else log_abort(); - if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) + if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) enpol = 1; - else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) + else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) enpol = 0; - else if (c->type.in(ID($dffe))) { - enpol = c->getParam(ID(EN_POLARITY)); - c->setPort(ID(E), c->getPort(ID(EN))); - c->unsetPort(ID(EN)); - } + else if (first_cell->type.in(ID($dffe))) + enpol = first_cell->getParam(ID(EN_POLARITY)); else enpol = 2; - c->parameters.clear(); - c->setParam(ID(DEPTH), GetSize(ud.chain)); - c->setParam(ID(INIT), initval.as_const()); c->setParam(ID(CLKPOL), clkpol); c->setParam(ID(ENPOL), enpol); - if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff))) - c->setPort(ID(E), State::S1); - c->setPort(ID(L), st.shiftx->getPort(ID(B))); + + if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + c->setPort(ID(C), first_cell->getPort(ID(C))); + else if (first_cell->type.in(ID($dff), ID($dffe))) + c->setPort(ID(C), first_cell->getPort(ID(CLK))); + else + log_abort(); + c->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]); c->setPort(ID(Q), st.shiftx->getPort(ID(Y))); - c->type = ID($__XILINX_SHREG_); + c->setPort(ID(L), st.shiftx->getPort(ID(B))); + if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff))) + c->setPort(ID(E), State::S1); + else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + c->setPort(ID(E), first_cell->getPort(ID(E))); + else if (first_cell->type.in(ID($dffe))) + c->setPort(ID(E), first_cell->getPort(ID(EN))); + else + log_abort(); } else log_abort(); -- cgit v1.2.3 From cf9e0171273daa1bc36174aa83bd02f9cfdb5e7a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 14:20:06 -0700 Subject: Add xilinx_srl_fixed, fix typos --- passes/pmgen/test_pmgen.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 0ad769dfd..b406f90f8 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -28,6 +28,7 @@ bool did_something; #include "passes/pmgen/test_pmgen_pm.h" #include "passes/pmgen/ice40_dsp_pm.h" +#include "passes/pmgen/xilinx_srl_pm.h" #include "passes/pmgen/peepopt_pm.h" void reduce_chain(test_pmgen_pm &pm) @@ -180,7 +181,7 @@ void generate_pattern(std::function)> run, const while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000) { if (timeout++ > 10000) - log_error("pmgen generator is stuck: 10000 iterations an no matching module generated.\n"); + log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n"); pm matcher(mod, mod->cells()); @@ -349,13 +350,16 @@ struct TestPmgenPass : public Pass { if (pattern == "ice40_dsp") return GENERATE_PATTERN(ice40_dsp_pm, ice40_dsp); + if (pattern == "xilinx_srl_fixed") + return GENERATE_PATTERN(xilinx_srl_pm, fixed); + if (pattern == "peepopt-muldiv") return GENERATE_PATTERN(peepopt_pm, muldiv); if (pattern == "peepopt-shiftmul") return GENERATE_PATTERN(peepopt_pm, shiftmul); - log_cmd_error("Unkown pattern: %s\n", pattern.c_str()); + log_cmd_error("Unknown pattern: %s\n", pattern.c_str()); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE -- cgit v1.2.3 From e574edc3e920c687856a0d69e358ba0c8ab678ff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 14:21:17 -0700 Subject: Populate generate for xilinx_srl.fixed pattern --- passes/pmgen/xilinx_srl.pmg | 76 ++++++++++++++++++++++++++++++++------------- 1 file changed, 54 insertions(+), 22 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index cfa1cacfb..355f0aa90 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -18,22 +18,46 @@ match first select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool() select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0 filter !non_first_cells.count(first) -//generate -// SigSpec A = module->addWire(NEW_ID); -// SigSpec B = module->addWire(NEW_ID); -// SigSpec Y = module->addWire(NEW_ID); -// switch (rng(3)) -// { -// case 0: -// module->addAndGate(NEW_ID, A, B, Y); -// break; -// case 1: -// module->addOrGate(NEW_ID, A, B, Y); -// break; -// case 2: -// module->addXorGate(NEW_ID, A, B, Y); -// break; -// } +generate + SigSpec C = module->addWire(NEW_ID); + SigSpec D = module->addWire(NEW_ID); + SigSpec Q = module->addWire(NEW_ID); + auto r = rng(8); + Cell* cell; + switch (r) + { + case 0: + case 1: + case 2: + case 3: + cell = module->addCell(NEW_ID, \FDRE); + if (r & 1) + cell->setPort(\R, State::S1); + else + cell->setPort(\R, State::S0); + if (r & 2) + cell->setPort(\CE, State::S1); + else + cell->setPort(\CE, State::S0); + break; + case 4: + cell = module->addCell(NEW_ID, $_DFF_N_); + break; + case 5: + case 6: + cell = module->addCell(NEW_ID, $_DFFE_PP_); + if (r & 1) + cell->setPort(\E, State::S1); + else + cell->setPort(\E, State::S0); + break; + case 7: + cell = module->addCell(NEW_ID, \foobar); + break; + } + cell->setPort(\C, C); + cell->setPort(\D, D); + cell->setPort(\Q, Q); endmatch code clk_port en_port @@ -126,12 +150,20 @@ match next filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) -//generate 10 -// SigSpec A = module->addWire(NEW_ID); -// SigSpec B = module->addWire(NEW_ID); -// SigSpec Y = port(chain.back().first, chain.back().second); -// Cell *c = module->addAndGate(NEW_ID, A, B, Y); -// c->type = chain.back().first->type; +generate 10 + SigSpec C = chain.back()->getPort(\C); + SigSpec D = module->addWire(NEW_ID); + SigSpec Q = chain.back()->getPort(\D); + Cell *cell = module->addCell(NEW_ID, chain.back()->type); + cell->setPort(\C, C); + cell->setPort(\D, D); + cell->setPort(\Q, Q); + if (cell->type == \FDRE) { + cell->setPort(\R, chain.back()->getPort(\R)); + cell->setPort(\CE, chain.back()->getPort(\CE)); + } + else if (cell->type == $_DFFE_PP_) + cell->setPort(\E, chain.back()->getPort(\E)); endmatch code -- cgit v1.2.3 From b32d6bf403baa15539e1ceae2c1af6b3c63b2e8e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 17:44:57 -0700 Subject: Add xilinx_srl_pm.variable to test_pmgen --- passes/pmgen/test_pmgen.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index b406f90f8..5b0cf0751 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -352,6 +352,8 @@ struct TestPmgenPass : public Pass { if (pattern == "xilinx_srl_fixed") return GENERATE_PATTERN(xilinx_srl_pm, fixed); + if (pattern == "xilinx_srl_variable") + return GENERATE_PATTERN(xilinx_srl_pm, variable); if (pattern == "peepopt-muldiv") return GENERATE_PATTERN(peepopt_pm, muldiv); -- cgit v1.2.3 From 45c34c87eeb0a530a7aae14a0d538c5b6ff53faa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 17:48:54 -0700 Subject: Account for maxsubcnt overflowing --- passes/pmgen/test_pmgen.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 5b0cf0751..2695fe802 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -217,7 +217,7 @@ void generate_pattern(std::function)> run, const run(matcher, [](){}); } - if (submodcnt) + if (submodcnt && maxsubcnt < (1 << 16)) maxsubcnt *= 2; design->remove(mod); -- cgit v1.2.3 From e95fb24574a033bda54740733c931868d3bc1df5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 17:49:08 -0700 Subject: Improve xilinx_srl.fixed generate, add .variable generate --- passes/pmgen/xilinx_srl.pmg | 101 ++++++++++++++++++++++++++++++++------------ 1 file changed, 75 insertions(+), 26 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 355f0aa90..e8288c54a 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -28,36 +28,28 @@ generate { case 0: case 1: - case 2: - case 3: cell = module->addCell(NEW_ID, \FDRE); + cell->setPort(\C, C); + cell->setPort(\D, D); + cell->setPort(\Q, Q); + cell->setPort(\CE, module->addWire(NEW_ID)); if (r & 1) - cell->setPort(\R, State::S1); + cell->setPort(\R, module->addWire(NEW_ID)); else cell->setPort(\R, State::S0); - if (r & 2) - cell->setPort(\CE, State::S1); - else - cell->setPort(\CE, State::S0); break; - case 4: - cell = module->addCell(NEW_ID, $_DFF_N_); + case 2: + case 3: + cell = module->addDffGate(NEW_ID, C, D, Q, r & 1); break; + case 4: case 5: case 6: - cell = module->addCell(NEW_ID, $_DFFE_PP_); - if (r & 1) - cell->setPort(\E, State::S1); - else - cell->setPort(\E, State::S0); - break; case 7: - cell = module->addCell(NEW_ID, \foobar); + cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2); break; + default: log_abort(); } - cell->setPort(\C, C); - cell->setPort(\D, D); - cell->setPort(\Q, Q); endmatch code clk_port en_port @@ -151,18 +143,15 @@ match next filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) generate 10 - SigSpec C = chain.back()->getPort(\C); - SigSpec D = module->addWire(NEW_ID); - SigSpec Q = chain.back()->getPort(\D); Cell *cell = module->addCell(NEW_ID, chain.back()->type); - cell->setPort(\C, C); - cell->setPort(\D, D); - cell->setPort(\Q, Q); + cell->setPort(\C, chain.back()->getPort(\C)); + cell->setPort(\D, module->addWire(NEW_ID)); + cell->setPort(\Q, chain.back()->getPort(\D)); if (cell->type == \FDRE) { cell->setPort(\R, chain.back()->getPort(\R)); cell->setPort(\CE, chain.back()->getPort(\CE)); } - else if (cell->type == $_DFFE_PP_) + else if (cell->type.begins_with("$_DFFE_")) cell->setPort(\E, chain.back()->getPort(\E)); endmatch @@ -199,6 +188,9 @@ match shiftx select !shiftx->has_keep_attr() select param(shiftx, \Y_WIDTH).as_int() == 1 filter param(shiftx, \A_WIDTH).as_int() >= minlen +generate + minlen = 3; + module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID)); endmatch code shiftx_width @@ -213,6 +205,33 @@ match first select nusers(port(first, \Q)[idx]) <= 2 index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] set slice idx +generate + SigSpec C = module->addWire(NEW_ID); + auto WIDTH = rng(3)+1; + SigSpec D = module->addWire(NEW_ID, WIDTH); + SigSpec Q = module->addWire(NEW_ID, WIDTH); + auto r = rng(8); + Cell *cell = nullptr; + switch (r) + { + case 0: + case 1: + cell = module->addDff(NEW_ID, C, D, Q, r & 1); + break; + case 2: + case 3: + case 4: + case 5: + //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4); + //break; + case 6: + case 7: + WIDTH = 1; + cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1); + break; + default: log_abort(); + } + shiftx->connections_.at(\A)[shiftx_width-1] = port(cell, \Q)[rng(WIDTH)]; endmatch code clk_port en_port @@ -264,6 +283,36 @@ match next filter !next->type.in($dffe) || param(next, \EN_POLARITY).as_bool() == param(first, \EN_POLARITY).as_bool() filter !chain_bits.count(port(next, \D)[idx]) set slice idx +generate + if (GetSize(chain) < shiftx_width) { + auto back = chain.back().first; + auto slice = chain.back().second; + if (back->type.in($dff, $dffe)) { + auto WIDTH = GetSize(port(back, \D)); + if (rng(2) == 0 && slice < WIDTH-1) { + auto new_slice = slice + rng(WIDTH-1-slice); + back->connections_.at(\D)[slice] = port(back, \Q)[new_slice]; + } + else { + auto D = module->addWire(NEW_ID, WIDTH); + if (back->type == $dff) + module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool()); + else if (back->type == $dffe) + module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool()); + else + log_abort(); + } + } + else if (back->type.begins_with("$_DFF_")) { + Cell *cell = module->addCell(NEW_ID, back->type); + cell->setPort(\C, back->getPort(\C)); + cell->setPort(\D, module->addWire(NEW_ID)); + cell->setPort(\Q, back->getPort(\D)); + } + else + log_abort(); + shiftx->connections_.at(\A)[shiftx_width-1-GetSize(chain)] = port(back, \D)[slice]; + } endmatch code -- cgit v1.2.3 From 54422c5bb4cdd3488fa1849af9049d0f4bb24603 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 17:51:13 -0700 Subject: Remove leftover header --- passes/pmgen/xilinx_srl.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index c332ccb9f..a8264cab2 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -28,7 +28,6 @@ PRIVATE_NAMESPACE_BEGIN bool did_something; #include "passes/pmgen/xilinx_srl_pm.h" -#include "passes/pmgen/ice40_dsp_pm.h" #include "passes/pmgen/peepopt_pm.h" void run_fixed(xilinx_srl_pm &pm) -- cgit v1.2.3 From 6b5e65919a6ec14d4bfc85f80d1f7492d5b86c16 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 17:52:57 -0700 Subject: Revert "In sat: 'x' in init attr should not override constant" This reverts commit 2b37a093e95036b267481b2dae2046278eef4040. --- passes/sat/sat.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index bcc690fa3..dd56d8c71 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,8 +268,6 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (bit.is_fully_const() && rhs[i] == State::Sx) - rhs[i] = bit; if (!satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); -- cgit v1.2.3 From 9172d4a6740145e7b3c7c34b8fb5effd23598a94 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 26 Aug 2019 21:02:52 -0700 Subject: Missing close bracket --- passes/pmgen/xilinx_srl.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index a8264cab2..b9cdbfaa1 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -213,7 +213,7 @@ struct XilinxSrlPass : public Pass { log("\n"); log(" -variable\n"); log(" infer variable-length shift registers (i.e. fixed-length shifts where\n"); - log(" each element also fans-out to a $shiftx cell.\n"); + log(" each element also fans-out to a $shiftx cell).\n"); log("\n"); } -- cgit v1.2.3 From 0ebe2c9831591d4f969139c5ec0776911284a954 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:27:03 -0700 Subject: Rename test_pmgen arg xilinx_srl.{fixed,variable} --- passes/pmgen/test_pmgen.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 2695fe802..4f3eec935 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -350,9 +350,9 @@ struct TestPmgenPass : public Pass { if (pattern == "ice40_dsp") return GENERATE_PATTERN(ice40_dsp_pm, ice40_dsp); - if (pattern == "xilinx_srl_fixed") + if (pattern == "xilinx_srl.fixed") return GENERATE_PATTERN(xilinx_srl_pm, fixed); - if (pattern == "xilinx_srl_variable") + if (pattern == "xilinx_srl.variable") return GENERATE_PATTERN(xilinx_srl_pm, variable); if (pattern == "peepopt-muldiv") -- cgit v1.2.3 From c3e9627afeb6b69f244983f2f23fb5473e61ab19 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:54:56 -0700 Subject: Always generate if no match --- passes/pmgen/xilinx_srl.pmg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index e8288c54a..bdb59c2f7 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -142,7 +142,7 @@ match next filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) -generate 10 +generate Cell *cell = module->addCell(NEW_ID, chain.back()->type); cell->setPort(\C, chain.back()->getPort(\C)); cell->setPort(\D, module->addWire(NEW_ID)); -- cgit v1.2.3 From c4d1bd988b1198f8a656576bd6cf67781aa5b156 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 10:06:40 -0700 Subject: Do not use default_params dict, hardcode default values, cleanup --- passes/pmgen/xilinx_srl.cc | 29 +++++++++++++---------------- passes/pmgen/xilinx_srl.pmg | 17 ++++++++--------- 2 files changed, 21 insertions(+), 25 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index b9cdbfaa1..b3bab6021 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -34,11 +34,6 @@ void run_fixed(xilinx_srl_pm &pm) { auto &st = pm.st_fixed; auto &ud = pm.ud_fixed; - auto param_def = [&ud](Cell *cell, IdString param) { - auto def = ud.default_params.at(std::make_pair(cell->type,param)); - return cell->parameters.at(param, def); - }; - log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); auto first_cell = ud.longest_chain.back(); @@ -58,8 +53,12 @@ void run_fixed(xilinx_srl_pm &pm) else initval.append(State::Sx); } - else if (cell->type.in(ID(FDRE), ID(FDRE_1))) - initval.append(param_def(cell, ID(INIT))); + else if (cell->type.in(ID(FDRE), ID(FDRE_1))) { + if (cell->parameters.at(ID(INIT), State::S0).as_bool()) + initval.append(State::S1); + else + initval.append(State::S0); + } else log_abort(); if (cell != first_cell) @@ -77,8 +76,12 @@ void run_fixed(xilinx_srl_pm &pm) c->setParam(ID(CLKPOL), 1); else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) c->setParam(ID(CLKPOL), 0); - else if (first_cell->type.in(ID(FDRE))) - c->setParam(ID(CLKPOL), param_def(first_cell, ID(IS_C_INVERTED)).as_bool() ? 0 : 1); + else if (first_cell->type.in(ID(FDRE))) { + if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool()) + c->setParam(ID(CLKPOL), 1); + else + c->setParam(ID(CLKPOL), 0); + } else log_abort(); if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) @@ -252,14 +255,8 @@ struct XilinxSrlPass : public Pass { pm.ud_fixed.minlen = minlen; pm.ud_variable.minlen = minlen; - if (fixed) { - // TODO: How to get these automatically? - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0; - pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0; + if (fixed) pm.run_fixed(run_fixed); - } if (variable) pm.run_variable(run_variable); } diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index bdb59c2f7..8bdcb0bcd 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -4,7 +4,6 @@ state clk_port en_port udata > chain longest_chain udata > non_first_cells udata minlen -udata ,Const>> default_params code non_first_cells.clear(); @@ -111,10 +110,10 @@ match next index port(next, \Q) === port(first, \D) filter port(next, clk_port) == port(first, clk_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port) - filter !next->type.in(\FDRE) || !first->hasParam(\IS_C_INVERTED) || (next->hasParam(\IS_C_INVERTED) && param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()) - filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) - filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) - filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) + filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool() + filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() + filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() + filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) endmatch code @@ -138,10 +137,10 @@ match next index port(next, \Q) === port(chain.back(), \D) filter port(next, clk_port) == port(first, clk_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port) - filter !next->type.in(\FDRE) || !first->hasParam(\IS_C_INVERTED) || (next->hasParam(\IS_C_INVERTED) && param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()) - filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) - filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) - filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) + filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool() + filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() + filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() + filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) generate Cell *cell = module->addCell(NEW_ID, chain.back()->type); cell->setPort(\C, chain.back()->getPort(\C)); -- cgit v1.2.3 From 86b538bd02cb3e4c7e14be2c6d2210eb39463b0f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 10:11:09 -0700 Subject: More cleanup --- passes/pmgen/xilinx_srl.cc | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index b3bab6021..f66582025 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -36,8 +36,6 @@ void run_fixed(xilinx_srl_pm &pm) auto &ud = pm.ud_fixed; log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); - auto first_cell = ud.longest_chain.back(); - SigSpec initval; for (auto cell : ud.longest_chain) { log_debug(" %s\n", log_id(cell)); @@ -61,10 +59,10 @@ void run_fixed(xilinx_srl_pm &pm) } else log_abort(); - if (cell != first_cell) - pm.autoremove(cell); + pm.autoremove(cell); } + auto first_cell = ud.longest_chain.back(); auto last_cell = ud.longest_chain.front(); Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); pm.module->swap_names(c, first_cell); @@ -117,9 +115,6 @@ void run_variable(xilinx_srl_pm &pm) log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type)); - auto first_cell = ud.chain.back().first; - auto first_slice = ud.chain.back().second; - SigSpec initval; for (const auto &i : ud.chain) { auto cell = i.first; @@ -139,11 +134,13 @@ void run_variable(xilinx_srl_pm &pm) } else log_abort(); - if (cell != first_cell) - cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID); + cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID); } pm.autoremove(st.shiftx); + auto first_cell = ud.chain.back().first; + auto first_slice = ud.chain.back().second; + Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_)); pm.module->swap_names(c, first_cell); -- cgit v1.2.3 From 11e3eb1009360112acff5589cd3771a165278529 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 10:19:35 -0700 Subject: More cleanup --- passes/pmgen/xilinx_srl.pmg | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 8bdcb0bcd..45d44247a 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -13,9 +13,9 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->has_keep_attr() - select !first->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || !param(first, \IS_R_INVERTED).as_bool() - select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool() - select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0 + select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() + select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() + select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero() filter !non_first_cells.count(first) generate SigSpec C = module->addWire(NEW_ID); @@ -34,8 +34,10 @@ generate cell->setPort(\CE, module->addWire(NEW_ID)); if (r & 1) cell->setPort(\R, module->addWire(NEW_ID)); - else - cell->setPort(\R, State::S0); + else { + if (rng(2) == 0) + cell->setPort(\R, State::S0); + } break; case 2: case 3: @@ -82,9 +84,9 @@ arg en_port match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !first->has_keep_attr() - select !first->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || !param(first, \IS_R_INVERTED).as_bool() - select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool() - select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0 + select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() + select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() + select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero() endmatch code clk_port en_port @@ -105,7 +107,6 @@ match next select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 - select !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == State::S0 index next->type === first->type index port(next, \Q) === port(first, \D) filter port(next, clk_port) == port(first, clk_port) @@ -113,7 +114,7 @@ match next filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() - filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) + filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero() endmatch code @@ -140,14 +141,15 @@ match next filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() - filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) + filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero() generate Cell *cell = module->addCell(NEW_ID, chain.back()->type); cell->setPort(\C, chain.back()->getPort(\C)); cell->setPort(\D, module->addWire(NEW_ID)); cell->setPort(\Q, chain.back()->getPort(\D)); if (cell->type == \FDRE) { - cell->setPort(\R, chain.back()->getPort(\R)); + if (rng(2) == 0) + cell->setPort(\R, chain.back()->connections_.at(\R, State::S0)); cell->setPort(\CE, chain.back()->getPort(\CE)); } else if (cell->type.begins_with("$_DFFE_")) -- cgit v1.2.3 From 52c4655de32c027e0542834d030ac951be10c8eb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 11:06:11 -0700 Subject: No need to replace Q of slice since $shiftx is autoremove-d --- passes/pmgen/xilinx_srl.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index f66582025..87fcaa15a 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -134,7 +134,6 @@ void run_variable(xilinx_srl_pm &pm) } else log_abort(); - cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID); } pm.autoremove(st.shiftx); -- cgit v1.2.3 From 0af64df10cf817bf7776feda6dffd2a700a20550 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 15:31:55 -0700 Subject: Account for D port being a constant --- passes/pmgen/xilinx_srl.pmg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 45d44247a..b18119b87 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -105,7 +105,7 @@ endcode match next select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !next->has_keep_attr() - select !port(next, \D)[0].wire->get_bool_attribute(\keep) + select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === first->type index port(next, \Q) === port(first, \D) @@ -132,7 +132,7 @@ match next semioptional select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select !next->has_keep_attr() - select !port(next, \D)[0].wire->get_bool_attribute(\keep) + select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep) select nusers(port(next, \Q)) == 2 index next->type === chain.back()->type index port(next, \Q) === port(chain.back(), \D) @@ -201,7 +201,7 @@ endcode match first select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !first->has_keep_attr() - select !port(first, \Q)[0].wire->get_bool_attribute(\keep) + select port(first, \Q)[0].wire && !port(first, \Q)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(first, \Q)) select nusers(port(first, \Q)[idx]) <= 2 index port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1] @@ -272,7 +272,7 @@ match next semioptional select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe) select !next->has_keep_attr() - select !port(next, \D)[0].wire->get_bool_attribute(\keep) + select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(next, \Q)) select nusers(port(next, \Q)[idx]) <= 3 index next->type === chain.back().first->type -- cgit v1.2.3 From 4eb5847dbdbb4a4efcde20aa81455eed8196db56 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 18:10:33 -0700 Subject: Cleanup --- passes/pmgen/xilinx_srl.cc | 4 ---- 1 file changed, 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 87fcaa15a..3d264e8d4 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -24,11 +24,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -// for peepopt_pm -bool did_something; - #include "passes/pmgen/xilinx_srl_pm.h" -#include "passes/pmgen/peepopt_pm.h" void run_fixed(xilinx_srl_pm &pm) { -- cgit v1.2.3 From 14677610602ee18bcf1a41a0c54a626965e6bb06 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 10:33:28 -0700 Subject: Fix typo that's gone unnoticed for 5 months!?! --- passes/techmap/shregmap.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 5e298d8dd..02cc27ae2 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -346,7 +346,7 @@ struct ShregmapWorker IdString q_port = opts.ffcells.at(c1->type).second; auto c1_conn = c1->connections(); - auto c2_conn = c1->connections(); + auto c2_conn = c2->connections(); c1_conn.erase(d_port); c1_conn.erase(q_port); -- cgit v1.2.3 From 3e0f73c3df3119a839b326464a8399ce4256edc7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 12:12:59 -0700 Subject: abc9 to not call "clean" at end of run (often called outside) --- passes/techmap/abc9.cc | 3 --- 1 file changed, 3 deletions(-) (limited to 'passes') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 84cb2c04f..f2662e0cb 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1300,9 +1300,6 @@ struct Abc9Pass : public Pass { assign_map.clear(); - // The "clean" pass also contains a design->check() call - Pass::call(design, "clean"); - log_pop(); } } Abc9Pass; -- cgit v1.2.3 From 18cabe9370c46b72e9fb52eb9be5a7c7fb873274 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 17:24:03 -0700 Subject: Output has priority over input when stitching in abc9 --- passes/techmap/abc9.cc | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) (limited to 'passes') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f2662e0cb..6fdf987f0 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -694,30 +694,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module - for (auto &it : mapped_mod->wires_) { - RTLIL::Wire *w = it.second; - if (!w->port_input && !w->port_output) - continue; - RTLIL::Wire *wire = module->wire(w->name); + for (auto port : mapped_mod->ports) { + RTLIL::Wire *w = mapped_mod->wire(port); + RTLIL::Wire *wire = module->wire(port); log_assert(wire); - RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); + RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); - log_assert(w->port_input || w->port_output); RTLIL::SigSig conn; - if (w->port_input) { - conn.first = remap_wire; - conn.second = signal; - in_wires++; - module->connect(conn); - } if (w->port_output) { conn.first = signal; conn.second = remap_wire; out_wires++; module->connect(conn); } + else if (w->port_input) { + conn.first = remap_wire; + conn.second = signal; + in_wires++; + module->connect(conn); + } } for (auto &it : bit_users) -- cgit v1.2.3 From c1459bc748d0d2c47dcb2366e5a0893736d6d463 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 12:22:14 -0700 Subject: Do not restrict multiplier to unsigned --- passes/pmgen/ice40_dsp.cc | 5 ----- 1 file changed, 5 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 39d033a04..16bfe537f 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -64,11 +64,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm) bool mul_signed = st.mul->getParam("\\A_SIGNED").as_bool(); - if (mul_signed) { - log(" inference of signed iCE40 DSP arithmetic is currently not supported.\n"); - return; - } - log(" replacing $mul with SB_MAC16 cell.\n"); Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16"); -- cgit v1.2.3 From 17b77fd41197b64f79bbbb59088e9de623d84716 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 14:00:40 -0700 Subject: Missing dep for test_pmgen --- passes/pmgen/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index e73a7b1c9..4989c582a 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -4,7 +4,7 @@ # -------------------------------------- OBJS += passes/pmgen/test_pmgen.o -passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h +passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h $(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h)) # -------------------------------------- -- cgit v1.2.3 From fa5065e9b5ed58d774bfe4fc23de681314b50270 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 1 Sep 2019 11:00:09 +0200 Subject: Fix select command error msg, fixes issue #1081 --- passes/cmds/select.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 59d10a1b8..0f1f05ccb 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -664,7 +664,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else if (arg == "%D") { if (work_stack.size() < 2) - log_cmd_error("Must have at least two elements on the stack for operator %%d.\n"); + log_cmd_error("Must have at least two elements on the stack for operator %%D.\n"); select_op_diff(design, work_stack[work_stack.size()-1], work_stack[work_stack.size()-2]); work_stack[work_stack.size()-2] = work_stack[work_stack.size()-1]; work_stack.pop_back(); @@ -693,7 +693,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else if (arg == "%C") { if (work_stack.size() < 1) - log_cmd_error("Must have at least one element on the stack for operator %%M.\n"); + log_cmd_error("Must have at least one element on the stack for operator %%C.\n"); select_op_module_to_cells(design, work_stack[work_stack.size()-1]); } else if (arg == "%c") { -- cgit v1.2.3