From bbef0d2ac8a84299109d9bd93b5eb69a5500d594 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 12:29:26 -0700 Subject: Only display log message if did_something --- passes/pmgen/peepopt_dffmux.pmg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index 4fc8e3b4c..da3a66577 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -81,9 +81,9 @@ code did_something = true; mux->fixup_parameters(); dff->fixup_parameters(); + log("dffmux pattern in %s: dff=%s, mux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(mux), count); } - log("dffmux pattern in %s: dff=%s, mux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(mux), count); accept; } endcode -- cgit v1.2.3 From 4937917cd8fb351740ffd936ea8a227795872775 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 13:22:52 -0700 Subject: Cleanup --- passes/pmgen/peepopt_dffmux.pmg | 47 +++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 25 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index da3a66577..9b4fef76f 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -1,30 +1,27 @@ pattern dffmux -state muxAB +state cemuxAB match dff select dff->type == $dff select GetSize(port(dff, \D)) > 1 endmatch -match mux - select mux->type == $mux - select GetSize(port(mux, \Y)) > 1 +match cemux + select cemux->type == $mux + select GetSize(port(cemux, \Y)) > 1 + index port(cemux, \Y) === port(dff, \D) choice AB {\A, \B} - //select port(mux, AB)[GetSize(port(mux, \Y))-1].wire - index port(mux, \Y) === port(dff, \D) - define BA (AB == \A ? \B : \A) - index port(mux, BA) === port(dff, \Q) - set muxAB AB + index port(cemux, AB) === port(dff, \Q) + set cemuxAB AB endmatch code - SigSpec &D = mux->connections_.at(muxAB); + SigSpec &D = cemux->connections_.at(cemuxAB == \A ? \B : \A); SigSpec &Q = dff->connections_.at(\Q); int width = GetSize(D); - SigSpec AB = port(mux, muxAB); - if (AB[width-1] == AB[width-2]) { + if (D[width-1] == D[width-2]) { did_something = true; SigBit sign = D[width-1]; @@ -43,21 +40,21 @@ code } } - mux->connections_.at(\A).remove(i, width-i); - mux->connections_.at(\B).remove(i, width-i); - mux->connections_.at(\Y).remove(i, width-i); - mux->fixup_parameters(); + cemux->connections_.at(\A).remove(i, width-i); + cemux->connections_.at(\B).remove(i, width-i); + cemux->connections_.at(\Y).remove(i, width-i); + cemux->fixup_parameters(); dff->connections_.at(\D).remove(i, width-i); dff->connections_.at(\Q).remove(i, width-i); dff->fixup_parameters(); - log("dffmux pattern in %s: dff=%s, mux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(mux), width-i); + log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i); accept; } else { int count = 0; for (int i = width-1; i >= 0; i--) { - if (AB[i].wire) + if (D[i].wire) continue; Wire *w = Q[i].wire; auto it = w->attributes.find(\init); @@ -67,21 +64,21 @@ code else init = State::Sx; - if (init == State::Sx || init == AB[i].data) { + if (init == State::Sx || init == D[i].data) { count++; - module->connect(Q[i], AB[i]); - mux->connections_.at(\A).remove(i); - mux->connections_.at(\B).remove(i); - mux->connections_.at(\Y).remove(i); + module->connect(Q[i], D[i]); + cemux->connections_.at(\A).remove(i); + cemux->connections_.at(\B).remove(i); + cemux->connections_.at(\Y).remove(i); dff->connections_.at(\D).remove(i); dff->connections_.at(\Q).remove(i); } } if (count > 0) { did_something = true; - mux->fixup_parameters(); + cemux->fixup_parameters(); dff->fixup_parameters(); - log("dffmux pattern in %s: dff=%s, mux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(mux), count); + log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count); } accept; -- cgit v1.2.3 From bdb5e0f29c3e913fb4e701317105363064b9a7d3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 13:36:37 -0700 Subject: Cope with presence of reset muxes too --- passes/pmgen/peepopt_dffmux.pmg | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index 9b4fef76f..60a708616 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -1,16 +1,34 @@ pattern dffmux -state cemuxAB +state cemuxAB rstmuxBA +state sigD match dff select dff->type == $dff select GetSize(port(dff, \D)) > 1 endmatch +match rstmux + select rstmux->type == $mux + select GetSize(port(rstmux, \Y)) > 1 + index port(rstmux, \Y) === port(dff, \D) + choice BA {\B, \A} + select port(rstmux, BA).is_fully_const() + set rstmuxBA BA + optional +endmatch + +code sigD + if (rstmux) + sigD = port(rstmux, rstmuxBA == \B ? \A : \B); + else + sigD = port(dff, \D); +endcode + match cemux select cemux->type == $mux select GetSize(port(cemux, \Y)) > 1 - index port(cemux, \Y) === port(dff, \D) + index port(cemux, \Y) === sigD choice AB {\A, \B} index port(cemux, AB) === port(dff, \Q) set cemuxAB AB @@ -19,6 +37,9 @@ endmatch code SigSpec &D = cemux->connections_.at(cemuxAB == \A ? \B : \A); SigSpec &Q = dff->connections_.at(\Q); + Const rst; + if (rstmux) + rst = port(rstmux, rstmuxBA).as_const(); int width = GetSize(D); if (D[width-1] == D[width-2]) { @@ -30,12 +51,12 @@ code for (i = width-1; i >= 2; i--) { if (!is_signed) { module->connect(Q[i], sign); - if (D[i-1] != sign) + if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1])) break; } else { module->connect(Q[i], Q[i-1]); - if (D[i-2] != sign) + if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1])) break; } } -- cgit v1.2.3