From f4c62f33ac56bc5725c44ad822e75d2387f98061 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Mon, 12 Aug 2019 15:57:43 +0000 Subject: Add clock buffer insertion pass, improve iopadmap. A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. --- passes/techmap/Makefile.inc | 1 + passes/techmap/clkbufmap.cc | 299 ++++++++++++++++++++++++++++++++++++++++++++ passes/techmap/iopadmap.cc | 76 ++++++++--- 3 files changed, 356 insertions(+), 20 deletions(-) create mode 100644 passes/techmap/clkbufmap.cc (limited to 'passes') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 56f05eca4..631a80aa5 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -16,6 +16,7 @@ endif ifneq ($(SMALL),1) OBJS += passes/techmap/iopadmap.o +OBJS += passes/techmap/clkbufmap.o OBJS += passes/techmap/hilomap.o OBJS += passes/techmap/extract.o OBJS += passes/techmap/extract_fa.o diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc new file mode 100644 index 000000000..9ecc83071 --- /dev/null +++ b/passes/techmap/clkbufmap.cc @@ -0,0 +1,299 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +void split_portname_pair(std::string &port1, std::string &port2) +{ + size_t pos = port1.find_first_of(':'); + if (pos != std::string::npos) { + port2 = port1.substr(pos+1); + port1 = port1.substr(0, pos); + } +} + +std::vector split(std::string text, const char *delim) +{ + std::vector list; + char *p = strdup(text.c_str()); + char *t = strtok(p, delim); + while (t != NULL) { + list.push_back(t); + t = strtok(NULL, delim); + } + free(p); + return list; +} + +struct ClkbufmapPass : public Pass { + ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { } + void help() YS_OVERRIDE + { + log("\n"); + log(" clkbufmap [options] [selection]\n"); + log("\n"); + log("Inserts global buffers between nets connected to clock inputs and their\n"); + log("drivers.\n"); + log("\n"); + log(" -buf :\n"); + log(" Specifies the cell type to use for the global buffers\n"); + log(" and its port names. The first port will be connected to\n"); + log(" the clock network sinks, and the second will be connected\n"); + log(" to the actual clock source. This option is required.\n"); + log("\n"); + log(" -inpad :\n"); + log(" If specified, a PAD cell of the given type is inserted on\n"); + log(" clock nets that are also top module's inputs (in addition\n"); + log(" to the global buffer).\n"); + log("\n"); + } + + void module_queue(Design *design, Module *module, std::vector &modules_sorted, pool &modules_processed) { + if (modules_processed.count(module)) + return; + for (auto cell : module->cells()) { + Module *submodule = design->module(cell->type); + if (!submodule) + continue; + module_queue(design, submodule, modules_sorted, modules_processed); + } + modules_sorted.push_back(module); + modules_processed.insert(module); + } + + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n"); + + std::string buf_celltype, buf_portname, buf_portname2; + std::string inpad_celltype, inpad_portname, inpad_portname2; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + std::string arg = args[argidx]; + if (arg == "-buf" && argidx+2 < args.size()) { + buf_celltype = args[++argidx]; + buf_portname = args[++argidx]; + split_portname_pair(buf_portname, buf_portname2); + continue; + } + if (arg == "-inpad" && argidx+2 < args.size()) { + inpad_celltype = args[++argidx]; + inpad_portname = args[++argidx]; + split_portname_pair(inpad_portname, inpad_portname2); + continue; + } + break; + } + extra_args(args, argidx, design); + + if (buf_celltype.empty()) + log_error("The -buf option is required."); + + // Cell type, port name, bit index. + pool>> sink_ports; + pool>> buf_ports; + + // Process submodules before module using them. + std::vector modules_sorted; + pool modules_processed; + for (auto module : design->selected_modules()) + module_queue(design, module, modules_sorted, modules_processed); + + for (auto module : modules_sorted) + { + if (module->get_blackbox_attribute()) { + auto it = module->attributes.find("\\clkbuf_driver"); + if (it != module->attributes.end()) { + auto value = it->second.decode_string(); + for (auto name : split(value, ",")) { + auto wire = module->wire(RTLIL::escape_id(name)); + if (!wire) + log_error("Module %s does not have port %s.\n", log_id(module), log_id(name)); + for (int i = 0; i < GetSize(wire); i++) + buf_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i))); + } + } + it = module->attributes.find("\\clkbuf_sink"); + if (it != module->attributes.end()) { + auto value = it->second.decode_string(); + for (auto name : split(value, ",")) { + auto wire = module->wire(RTLIL::escape_id(name)); + if (!wire) + log_error("Module %s does not have port %s.\n", log_id(module), log_id(name)); + for (int i = 0; i < GetSize(wire); i++) + sink_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i))); + } + } + continue; + } + pool sink_wire_bits; + pool buf_wire_bits; + pool driven_wire_bits; + SigMap sigmap(module); + // bit -> (buffer, buffer's input) + dict> buffered_bits; + + // First, collect nets that could use a clock buffer. + for (auto cell : module->cells()) + for (auto port : cell->connections()) + for (int i = 0; i < port.second.size(); i++) + if (sink_ports.count(make_pair(cell->type, make_pair(port.first, i)))) + sink_wire_bits.insert(sigmap(port.second[i])); + + // Second, collect ones that already have a clock buffer. + for (auto cell : module->cells()) + for (auto port : cell->connections()) + for (int i = 0; i < port.second.size(); i++) + if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i)))) + buf_wire_bits.insert(sigmap(port.second[i])); + + // Collect all driven bits. + for (auto cell : module->cells()) + for (auto port : cell->connections()) + if (cell->output(port.first)) + for (int i = 0; i < port.second.size(); i++) + driven_wire_bits.insert(port.second[i]); + + // Insert buffers. + std::vector> input_queue; + for (auto wire : module->selected_wires()) + { + // Should not happen. + if (wire->port_input && wire->port_output) + continue; + if (wire->get_bool_attribute("\\clkbuf_inhibit")) + continue; + + pool input_bits; + + for (int i = 0; i < GetSize(wire); i++) + { + SigBit wire_bit(wire, i); + SigBit mapped_wire_bit = sigmap(wire_bit); + if (buf_wire_bits.count(mapped_wire_bit)) { + // Already buffered downstream. If this is an output, mark it. + if (wire->port_output) + buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); + } else if (!sink_wire_bits.count(mapped_wire_bit)) { + // Nothing to do. + } else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute("\\top"))) { + // Clock network not yet buffered, driven by one of + // our cells or a top-level input -- buffer it. + + log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i); + RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype)); + Wire *iwire = module->addWire(NEW_ID); + cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); + cell->setPort(RTLIL::escape_id(buf_portname2), iwire); + if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute("\\top")) { + log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i); + RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype)); + cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); + iwire = module->addWire(NEW_ID); + cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire); + } + buffered_bits[mapped_wire_bit] = make_pair(cell, iwire); + + if (wire->port_input) { + input_bits.insert(i); + } + } else if (wire->port_input) { + // A clock input in a submodule -- mark it, let higher level + // worry about it. + if (wire->port_input) + sink_ports.insert(make_pair(module->name, make_pair(wire->name, i))); + } + } + if (!input_bits.empty()) { + // This is an input port and some buffers were inserted -- we need + // to create a new input wire and transfer attributes. + Wire *new_wire = module->addWire(NEW_ID, wire); + + for (int i = 0; i < wire->width; i++) { + SigBit wire_bit(wire, i); + SigBit mapped_wire_bit = sigmap(wire_bit); + auto it = buffered_bits.find(mapped_wire_bit); + if (it != buffered_bits.end()) { + + module->connect(it->second.second, SigSpec(new_wire, i)); + } else { + module->connect(SigSpec(wire, i), SigSpec(new_wire, i)); + } + } + input_queue.push_back(make_pair(wire, new_wire)); + } + } + + // Mark any newly-buffered output ports as such. + for (auto wire : module->selected_wires()) { + if (wire->port_input || !wire->port_output) + continue; + for (int i = 0; i < GetSize(wire); i++) + { + SigBit wire_bit(wire, i); + SigBit mapped_wire_bit = sigmap(wire_bit); + if (buffered_bits.count(mapped_wire_bit)) + buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); + } + } + + // Reconnect the drivers to buffer inputs. + for (auto cell : module->cells()) + for (auto port : cell->connections()) { + if (!cell->output(port.first)) + continue; + SigSpec sig = port.second; + bool newsig = false; + for (auto &bit : sig) { + const auto it = buffered_bits.find(sigmap(bit)); + if (it == buffered_bits.end()) + continue; + // Avoid substituting buffer's own output pin. + if (cell == it->second.first) + continue; + bit = it->second.second; + newsig = true; + } + if (newsig) + cell->setPort(port.first, sig); + } + + // This has to be done last, to avoid upsetting sigmap before the port reconnections. + for (auto &it : input_queue) { + Wire *wire = it.first; + Wire *new_wire = it.second; + module->swap_names(new_wire, wire); + wire->attributes.clear(); + wire->port_id = 0; + wire->port_input = false; + wire->port_output = false; + } + + module->fixup_ports(); + } + } +} ClkbufmapPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index efcc082d5..e3d68ab0c 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -32,6 +32,19 @@ void split_portname_pair(std::string &port1, std::string &port2) } } +std::vector split(std::string text, const char *delim) +{ + std::vector list; + char *p = strdup(text.c_str()); + char *t = strtok(p, delim); + while (t != NULL) { + list.push_back(t); + t = strtok(NULL, delim); + } + free(p); + return list; +} + struct IopadmapPass : public Pass { IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { } void help() YS_OVERRIDE @@ -64,6 +77,11 @@ struct IopadmapPass : public Pass { log(" of the tristate driver and the 2nd portname is the internal output\n"); log(" buffering the external signal.\n"); log("\n"); + log(" -ignore [:]*\n"); + log(" Skips mapping inputs/outputs that are already connected to given\n"); + log(" ports of the given cell. Can be used multiple times. This is in\n"); + log(" addition to the cells specified as mapping targets.\n"); + log("\n"); log(" -widthparam \n"); log(" Use the specified parameter name to set the port width.\n"); log("\n"); @@ -88,6 +106,7 @@ struct IopadmapPass : public Pass { std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3; std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4; std::string widthparam, nameparam; + pool> ignore; bool flag_bits = false; size_t argidx; @@ -127,6 +146,18 @@ struct IopadmapPass : public Pass { split_portname_pair(tinoutpad_portname3, tinoutpad_portname4); continue; } + if (arg == "-ignore" && argidx+2 < args.size()) { + std::string ignore_celltype = args[++argidx]; + std::string ignore_portname = args[++argidx]; + std::string ignore_portname2; + while (!ignore_portname.empty()) { + split_portname_pair(ignore_portname, ignore_portname2); + ignore.insert(make_pair(RTLIL::escape_id(ignore_celltype), RTLIL::escape_id(ignore_portname))); + + ignore_portname = ignore_portname2; + } + continue; + } if (arg == "-widthparam" && argidx+1 < args.size()) { widthparam = args[++argidx]; continue; @@ -143,6 +174,28 @@ struct IopadmapPass : public Pass { } extra_args(args, argidx, design); + if (!inpad_portname2.empty()) + ignore.insert(make_pair(RTLIL::escape_id(inpad_celltype), RTLIL::escape_id(inpad_portname2))); + if (!outpad_portname2.empty()) + ignore.insert(make_pair(RTLIL::escape_id(outpad_celltype), RTLIL::escape_id(outpad_portname2))); + if (!inoutpad_portname2.empty()) + ignore.insert(make_pair(RTLIL::escape_id(inoutpad_celltype), RTLIL::escape_id(inoutpad_portname2))); + if (!toutpad_portname3.empty()) + ignore.insert(make_pair(RTLIL::escape_id(toutpad_celltype), RTLIL::escape_id(toutpad_portname3))); + if (!tinoutpad_portname4.empty()) + ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4))); + + for (auto module : design->modules()) + { + auto it = module->attributes.find("\\iopad_external_pin"); + if (it != module->attributes.end()) { + auto value = it->second.decode_string(); + for (auto name : split(value, ",")) { + ignore.insert(make_pair(module->name, RTLIL::escape_id(name))); + } + } + } + for (auto module : design->selected_modules()) { dict> skip_wires; @@ -150,28 +203,11 @@ struct IopadmapPass : public Pass { SigMap sigmap(module); for (auto cell : module->cells()) - { - if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2))) - for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2)))) - skip_wire_bits.insert(bit); - - if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2))) - for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2)))) - skip_wire_bits.insert(bit); - - if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2))) - for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2)))) + for (auto port : cell->connections()) + if (ignore.count(make_pair(cell->type, port.first))) + for (auto bit : sigmap(port.second)) skip_wire_bits.insert(bit); - if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3))) - for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3)))) - skip_wire_bits.insert(bit); - - if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4))) - for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4)))) - skip_wire_bits.insert(bit); - } - if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty()) { dict>> tbuf_bits; -- cgit v1.2.3 From c6d5b97b98e6edc395ee14ad60430f7ebc264f01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 13 Aug 2019 00:35:54 +0000 Subject: review fixes --- passes/techmap/clkbufmap.cc | 18 +++--------------- passes/techmap/iopadmap.cc | 15 +-------------- 2 files changed, 4 insertions(+), 29 deletions(-) (limited to 'passes') diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 9ecc83071..a2d10c48b 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2019 Marcin Kościelnicki * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,19 +33,6 @@ void split_portname_pair(std::string &port1, std::string &port2) } } -std::vector split(std::string text, const char *delim) -{ - std::vector list; - char *p = strdup(text.c_str()); - char *t = strtok(p, delim); - while (t != NULL) { - list.push_back(t); - t = strtok(NULL, delim); - } - free(p); - return list; -} - struct ClkbufmapPass : public Pass { ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { } void help() YS_OVERRIDE @@ -127,7 +115,7 @@ struct ClkbufmapPass : public Pass { auto it = module->attributes.find("\\clkbuf_driver"); if (it != module->attributes.end()) { auto value = it->second.decode_string(); - for (auto name : split(value, ",")) { + for (auto name : split_tokens(value, ",")) { auto wire = module->wire(RTLIL::escape_id(name)); if (!wire) log_error("Module %s does not have port %s.\n", log_id(module), log_id(name)); @@ -138,7 +126,7 @@ struct ClkbufmapPass : public Pass { it = module->attributes.find("\\clkbuf_sink"); if (it != module->attributes.end()) { auto value = it->second.decode_string(); - for (auto name : split(value, ",")) { + for (auto name : split_tokens(value, ",")) { auto wire = module->wire(RTLIL::escape_id(name)); if (!wire) log_error("Module %s does not have port %s.\n", log_id(module), log_id(name)); diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index e3d68ab0c..0fcb6b2ec 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -32,19 +32,6 @@ void split_portname_pair(std::string &port1, std::string &port2) } } -std::vector split(std::string text, const char *delim) -{ - std::vector list; - char *p = strdup(text.c_str()); - char *t = strtok(p, delim); - while (t != NULL) { - list.push_back(t); - t = strtok(NULL, delim); - } - free(p); - return list; -} - struct IopadmapPass : public Pass { IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { } void help() YS_OVERRIDE @@ -190,7 +177,7 @@ struct IopadmapPass : public Pass { auto it = module->attributes.find("\\iopad_external_pin"); if (it != module->attributes.end()) { auto value = it->second.decode_string(); - for (auto name : split(value, ",")) { + for (auto name : split_tokens(value, ",")) { ignore.insert(make_pair(module->name, RTLIL::escape_id(name))); } } -- cgit v1.2.3 From 3c75a72feb1cf83fa8fc138aa69155446b6b74f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 13 Aug 2019 19:36:59 +0000 Subject: move attributes to wires --- passes/techmap/clkbufmap.cc | 24 +++++------------------- passes/techmap/iopadmap.cc | 13 ++++--------- 2 files changed, 9 insertions(+), 28 deletions(-) (limited to 'passes') diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index a2d10c48b..6fac1b437 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -112,27 +112,13 @@ struct ClkbufmapPass : public Pass { for (auto module : modules_sorted) { if (module->get_blackbox_attribute()) { - auto it = module->attributes.find("\\clkbuf_driver"); - if (it != module->attributes.end()) { - auto value = it->second.decode_string(); - for (auto name : split_tokens(value, ",")) { - auto wire = module->wire(RTLIL::escape_id(name)); - if (!wire) - log_error("Module %s does not have port %s.\n", log_id(module), log_id(name)); + for (auto wire : module->wires()) { + if (wire->get_bool_attribute("\\clkbuf_driver")) for (int i = 0; i < GetSize(wire); i++) - buf_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i))); - } - } - it = module->attributes.find("\\clkbuf_sink"); - if (it != module->attributes.end()) { - auto value = it->second.decode_string(); - for (auto name : split_tokens(value, ",")) { - auto wire = module->wire(RTLIL::escape_id(name)); - if (!wire) - log_error("Module %s does not have port %s.\n", log_id(module), log_id(name)); + buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); + if (wire->get_bool_attribute("\\clkbuf_sink")) for (int i = 0; i < GetSize(wire); i++) - sink_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i))); - } + sink_ports.insert(make_pair(module->name, make_pair(wire->name, i))); } continue; } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 0fcb6b2ec..5fe965600 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -173,15 +173,10 @@ struct IopadmapPass : public Pass { ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4))); for (auto module : design->modules()) - { - auto it = module->attributes.find("\\iopad_external_pin"); - if (it != module->attributes.end()) { - auto value = it->second.decode_string(); - for (auto name : split_tokens(value, ",")) { - ignore.insert(make_pair(module->name, RTLIL::escape_id(name))); - } - } - } + if (module->get_blackbox_attribute()) + for (auto wire : module->wires()) + if (wire->get_bool_attribute("\\iopad_external_pin")) + ignore.insert(make_pair(module->name, wire->name)); for (auto module : design->selected_modules()) { -- cgit v1.2.3 From 51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:42:19 -0700 Subject: In sat: 'x' in init attr should not override constant --- passes/sat/sat.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index dd56d8c71..bcc690fa3 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,6 +268,8 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); + if (bit.is_fully_const() && rhs[i] == State::Sx) + rhs[i] = bit; if (!satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); -- cgit v1.2.3 From 4d89c3f468b6090dceabb304b9f56f3a6a597057 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 10:03:41 -0700 Subject: Review comment from @cliffordwolf --- passes/techmap/clkbufmap.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 6fac1b437..55341ead0 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -112,7 +112,8 @@ struct ClkbufmapPass : public Pass { for (auto module : modules_sorted) { if (module->get_blackbox_attribute()) { - for (auto wire : module->wires()) { + for (auto port : module->ports) { + auto wire = module->wire(port); if (wire->get_bool_attribute("\\clkbuf_driver")) for (int i = 0; i < GetSize(wire); i++) buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); -- cgit v1.2.3 From 619f2414e587a216edb68d39ce56e25e29f0502b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:14:42 -0700 Subject: clkbufmap to only check clkbuf_inhibit if no selection given --- passes/techmap/clkbufmap.cc | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 55341ead0..82b3dcdf7 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -37,11 +37,18 @@ struct ClkbufmapPass : public Pass { ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { } void help() YS_OVERRIDE { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" clkbufmap [options] [selection]\n"); log("\n"); - log("Inserts global buffers between nets connected to clock inputs and their\n"); - log("drivers.\n"); + log("Inserts global buffers between nets connected to clock inputs and their drivers.\n"); + log("\n"); + log("In the absence of any selection, all wires without the 'clkbuf_inhibit'\n"); + log("attribute will be considered for global buffer insertion.\n"); + log("Alternatively, to consider all wires without the 'buffer_type' attribute set to\n"); + log("'none' or 'bufr' one would specify:\n"); + log(" 'w:* a:buffer_type=none a:buffer_type=bufr %%u %%d'\n"); + log("as the selection.\n"); log("\n"); log(" -buf :\n"); log(" Specifies the cell type to use for the global buffers\n"); @@ -94,10 +101,16 @@ struct ClkbufmapPass : public Pass { } break; } - extra_args(args, argidx, design); + + bool select = false; + if (argidx < args.size()) { + if (args[argidx].compare(0, 1, "-") != 0) + select = true; + extra_args(args, argidx, design); + } if (buf_celltype.empty()) - log_error("The -buf option is required."); + log_error("The -buf option is required.\n"); // Cell type, port name, bit index. pool>> sink_ports; @@ -158,7 +171,7 @@ struct ClkbufmapPass : public Pass { // Should not happen. if (wire->port_input && wire->port_output) continue; - if (wire->get_bool_attribute("\\clkbuf_inhibit")) + if (!select && wire->get_bool_attribute("\\clkbuf_inhibit")) continue; pool input_bits; -- cgit v1.2.3 From 5fb4b12cb50b870b546d76f9c702678d8f0aa60a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 27 Aug 2019 17:26:47 +0200 Subject: improve clkbuf_inhibit propagation upwards through hierarchy --- passes/techmap/clkbufmap.cc | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 82b3dcdf7..246932d81 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -166,13 +166,24 @@ struct ClkbufmapPass : public Pass { // Insert buffers. std::vector> input_queue; - for (auto wire : module->selected_wires()) + // Copy current wire list, as we will be adding new ones during iteration. + std::vector wires(module->wires()); + for (auto wire : wires) { // Should not happen. if (wire->port_input && wire->port_output) continue; + bool process_wire = module->selected(wire); if (!select && wire->get_bool_attribute("\\clkbuf_inhibit")) + process_wire = false; + if (!process_wire) { + // This wire is supposed to be bypassed, so make sure we don't buffer it in + // some buffer higher up in the hierarchy. + if (wire->port_output) + for (int i = 0; i < GetSize(wire); i++) + buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); continue; + } pool input_bits; -- cgit v1.2.3 From 28133432bea4a3fa01cd2f5e82a52a853cfccb84 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 27 Aug 2019 09:24:59 -0700 Subject: Ignore all 1'bx in (* init *) --- passes/sat/sat.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index bcc690fa3..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,9 +268,7 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (bit.is_fully_const() && rhs[i] == State::Sx) - rhs[i] = bit; - if (!satgen.initial_state.check_all(bit)) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); -- cgit v1.2.3 From 0fda0e821cee249dd722c8b52e941c35bd9d8df0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 28 Aug 2019 10:03:27 +0200 Subject: Add "paramap" pass Signed-off-by: Clifford Wolf --- passes/techmap/attrmap.cc | 185 +++++++++++++++++++++++++++++----------------- 1 file changed, 118 insertions(+), 67 deletions(-) (limited to 'passes') diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index a38638e0b..3a2835733 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -143,6 +143,82 @@ void attrmap_apply(string objname, vector> &actio attributes.swap(new_attributes); } +void log_attrmap_paramap_options() +{ + log(" -tocase \n"); + log(" Match attribute names case-insensitively and set it to the specified\n"); + log(" name.\n"); + log("\n"); + log(" -rename \n"); + log(" Rename attributes as specified\n"); + log("\n"); + log(" -map = =\n"); + log(" Map key/value pairs as indicated.\n"); + log("\n"); + log(" -imap = =\n"); + log(" Like -map, but use case-insensitive match for when\n"); + log(" it is a string value.\n"); + log("\n"); + log(" -remove =\n"); + log(" Remove attributes matching this pattern.\n"); +} + +bool parse_attrmap_paramap_options(size_t &argidx, std::vector &args, vector> &actions) +{ + std::string arg = args[argidx]; + if (arg == "-tocase" && argidx+1 < args.size()) { + auto action = new AttrmapTocase; + action->name = args[++argidx]; + actions.push_back(std::unique_ptr(action)); + return true; + } + if (arg == "-rename" && argidx+2 < args.size()) { + auto action = new AttrmapRename; + action->old_name = args[++argidx]; + action->new_name = args[++argidx]; + actions.push_back(std::unique_ptr(action)); + return true; + } + if ((arg == "-map" || arg == "-imap") && argidx+2 < args.size()) { + string arg1 = args[++argidx]; + string arg2 = args[++argidx]; + string val1, val2; + size_t p = arg1.find("="); + if (p != string::npos) { + val1 = arg1.substr(p+1); + arg1 = arg1.substr(0, p); + } + p = arg2.find("="); + if (p != string::npos) { + val2 = arg2.substr(p+1); + arg2 = arg2.substr(0, p); + } + auto action = new AttrmapMap; + action->imap = (arg == "-map"); + action->old_name = arg1; + action->new_name = arg2; + action->old_value = val1; + action->new_value = val2; + actions.push_back(std::unique_ptr(action)); + return true; + } + if (arg == "-remove" && argidx+1 < args.size()) { + string arg1 = args[++argidx], val1; + size_t p = arg1.find("="); + if (p != string::npos) { + val1 = arg1.substr(p+1); + arg1 = arg1.substr(0, p); + } + auto action = new AttrmapRemove; + action->name = arg1; + action->has_value = (p != string::npos); + action->value = val1; + actions.push_back(std::unique_ptr(action)); + return true; + } + return false; +} + struct AttrmapPass : public Pass { AttrmapPass() : Pass("attrmap", "renaming attributes") { } void help() YS_OVERRIDE @@ -154,22 +230,7 @@ struct AttrmapPass : public Pass { log("This command renames attributes and/or mapps key/value pairs to\n"); log("other key/value pairs.\n"); log("\n"); - log(" -tocase \n"); - log(" Match attribute names case-insensitively and set it to the specified\n"); - log(" name.\n"); - log("\n"); - log(" -rename \n"); - log(" Rename attributes as specified\n"); - log("\n"); - log(" -map = =\n"); - log(" Map key/value pairs as indicated.\n"); - log("\n"); - log(" -imap = =\n"); - log(" Like -map, but use case-insensitive match for when\n"); - log(" it is a string value.\n"); - log("\n"); - log(" -remove =\n"); - log(" Remove attributes matching this pattern.\n"); + log_attrmap_paramap_options(); log("\n"); log(" -modattr\n"); log(" Operate on module attributes instead of attributes on wires and cells.\n"); @@ -190,58 +251,9 @@ struct AttrmapPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - std::string arg = args[argidx]; - if (arg == "-tocase" && argidx+1 < args.size()) { - auto action = new AttrmapTocase; - action->name = args[++argidx]; - actions.push_back(std::unique_ptr(action)); - continue; - } - if (arg == "-rename" && argidx+2 < args.size()) { - auto action = new AttrmapRename; - action->old_name = args[++argidx]; - action->new_name = args[++argidx]; - actions.push_back(std::unique_ptr(action)); + if (parse_attrmap_paramap_options(argidx, args, actions)) continue; - } - if ((arg == "-map" || arg == "-imap") && argidx+2 < args.size()) { - string arg1 = args[++argidx]; - string arg2 = args[++argidx]; - string val1, val2; - size_t p = arg1.find("="); - if (p != string::npos) { - val1 = arg1.substr(p+1); - arg1 = arg1.substr(0, p); - } - p = arg2.find("="); - if (p != string::npos) { - val2 = arg2.substr(p+1); - arg2 = arg2.substr(0, p); - } - auto action = new AttrmapMap; - action->imap = (arg == "-map"); - action->old_name = arg1; - action->new_name = arg2; - action->old_value = val1; - action->new_value = val2; - actions.push_back(std::unique_ptr(action)); - continue; - } - if (arg == "-remove" && argidx+1 < args.size()) { - string arg1 = args[++argidx], val1; - size_t p = arg1.find("="); - if (p != string::npos) { - val1 = arg1.substr(p+1); - arg1 = arg1.substr(0, p); - } - auto action = new AttrmapRemove; - action->name = arg1; - action->has_value = (p != string::npos); - action->value = val1; - actions.push_back(std::unique_ptr(action)); - continue; - } - if (arg == "-modattr") { + if (args[argidx] == "-modattr") { modattr_mode = true; continue; } @@ -287,4 +299,43 @@ struct AttrmapPass : public Pass { } } AttrmapPass; +struct ParamapPass : public Pass { + ParamapPass() : Pass("paramap", "renaming cell parameters") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" paramap [options] [selection]\n"); + log("\n"); + log("This command renames cell parameters and/or mapps key/value pairs to\n"); + log("other key/value pairs.\n"); + log("\n"); + log_attrmap_paramap_options(); + log("\n"); + log("For example, mapping Diamond-style ECP5 \"init\" attributes to Yosys-style:\n"); + log("\n"); + log(" paramap -tocase INIT t:LUT4\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing PARAMAP pass (move or copy cell parameters).\n"); + + vector> actions; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (parse_attrmap_paramap_options(argidx, args, actions)) + continue; + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + for (auto cell : module->selected_cells()) + attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->parameters); + } +} ParamapPass; + PRIVATE_NAMESPACE_END -- cgit v1.2.3 From 47ffbf554ef98a19222b42e48a9c58f3b55364fa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 28 Aug 2019 10:06:42 +0200 Subject: Fix typo Signed-off-by: Clifford Wolf --- passes/techmap/attrmap.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 3a2835733..5f30817d4 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -227,7 +227,7 @@ struct AttrmapPass : public Pass { log("\n"); log(" attrmap [options] [selection]\n"); log("\n"); - log("This command renames attributes and/or mapps key/value pairs to\n"); + log("This command renames attributes and/or maps key/value pairs to\n"); log("other key/value pairs.\n"); log("\n"); log_attrmap_paramap_options(); @@ -307,7 +307,7 @@ struct ParamapPass : public Pass { log("\n"); log(" paramap [options] [selection]\n"); log("\n"); - log("This command renames cell parameters and/or mapps key/value pairs to\n"); + log("This command renames cell parameters and/or maps key/value pairs to\n"); log("other key/value pairs.\n"); log("\n"); log_attrmap_paramap_options(); -- cgit v1.2.3