From 8f12c5b063a458ac5f751f54651baebd84006307 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 23 Jun 2020 23:16:43 +0200
Subject: simplemap: Fix $dffsre mapping.
---
passes/techmap/simplemap.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'passes')
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index c8388e2d7..b9d337da4 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -489,7 +489,7 @@ void simplemap_dffsre(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
- IdString gate_type = stringf("$_DFFSR_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol);
+ IdString gate_type = stringf("$_DFFSRE_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
--
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