From a39505e329cc05dbd4ad624a1cf0f6caf664fd9a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Sep 2019 12:59:10 -0700 Subject: equiv_opt to call async2sync when not -multiclock like SymbiYosys --- passes/equiv/equiv_opt.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index d4c7f7953..9fe3bbd57 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -156,6 +156,8 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); + else + run("async2sync", "(only without -multiclock)"); run("equiv_make gold gate equiv"); if (help_mode) run("equiv_induct [-undef] equiv"); -- cgit v1.2.3 From 3f70c1fd26eb109c2c4d899cce55f24bbf04acc1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 29 Sep 2019 13:22:11 +0200 Subject: Open aig frontend as binary file --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7eac08d17..7c764451f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -471,7 +471,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig"); - ifs.open(buffer); + ifs.open(buffer, std::ifstream::binary); if (ifs.fail()) log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); -- cgit v1.2.3 From 10e57f3880da8bfa373a3859a713509a549701c9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Sep 2019 14:58:23 +0200 Subject: Fix $dlatch handling in async2sync Signed-off-by: Clifford Wolf --- passes/sat/async2sync.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index 24ae6e448..740248545 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -198,6 +198,7 @@ struct Async2syncPass : public Pass { module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q); } + cell->setPort("\\D", sig_q); cell->setPort("\\Q", new_q); cell->unsetPort("\\EN"); cell->unsetParam("\\EN_POLARITY"); -- cgit v1.2.3 From a274b7cc86d4f64541d3d2903b4eeed4616ab1d8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 10:59:56 -0700 Subject: Update doc for equiv_opt --- passes/equiv/equiv_opt.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index 9fe3bbd57..4ab5b1a3e 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -32,7 +32,8 @@ struct EquivOptPass:public ScriptPass log("\n"); log(" equiv_opt [options] [command]\n"); log("\n"); - log("This command checks circuit equivalence before and after an optimization pass.\n"); + log("This command uses temporal induction to check circuit equivalence before and\n"); + log("after an optimization pass.\n"); log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); @@ -156,7 +157,7 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); - else + if (!multiclock || help_mode) run("async2sync", "(only without -multiclock)"); run("equiv_make gold gate equiv"); if (help_mode) -- cgit v1.2.3