From 84bf862f7c58c2b69babf043ff5032f924a3ee4d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 14 Aug 2015 10:56:05 +0200
Subject: Spell check (by Larry Doolittle)

---
 passes/cmds/check.cc          |  2 +-
 passes/cmds/connect.cc        |  2 +-
 passes/cmds/connwrappers.cc   |  4 ++--
 passes/cmds/design.cc         |  2 +-
 passes/cmds/select.cc         |  4 ++--
 passes/cmds/show.cc           | 14 +++++++-------
 passes/cmds/splice.cc         |  2 +-
 passes/cmds/write_file.cc     |  2 +-
 passes/equiv/equiv_make.cc    |  2 +-
 passes/fsm/fsm.cc             |  4 ++--
 passes/fsm/fsm_expand.cc      |  2 +-
 passes/hierarchy/hierarchy.cc |  2 +-
 passes/memory/memory_bram.cc  | 10 +++++-----
 passes/opt/opt_reduce.cc      |  2 +-
 passes/opt/share.cc           |  2 +-
 passes/sat/eval.cc            |  6 +++---
 passes/sat/expose.cc          |  4 ++--
 passes/sat/freduce.cc         | 10 +++++-----
 passes/sat/miter.cc           |  2 +-
 passes/sat/sat.cc             |  2 +-
 passes/techmap/abc.cc         |  4 ++--
 passes/techmap/dff2dffe.cc    |  2 +-
 passes/techmap/extract.cc     |  6 +++---
 passes/techmap/techmap.cc     | 16 ++++++++--------
 passes/tests/test_autotb.cc   |  2 +-
 25 files changed, 55 insertions(+), 55 deletions(-)

(limited to 'passes')

diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index fe74408d4..2ad848386 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -35,7 +35,7 @@ struct CheckPass : public Pass {
 		log("\n");
 		log("This pass identifies the following problems in the current design:\n");
 		log("\n");
-		log(" - combinatorical loops\n");
+		log(" - combinatorial loops\n");
 		log("\n");
 		log(" - two or more conflicting drivers for one wire\n");
 		log("\n");
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index e09d636fd..e0b1ce051 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -49,7 +49,7 @@ struct ConnectPass : public Pass {
 		log("\n");
 		log("    connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
 		log("\n");
-		log("Create a connection. This is equivialent to adding the statement 'assign\n");
+		log("Create a connection. This is equivalent to adding the statement 'assign\n");
 		log("<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing\n");
 		log("drivers for <lhs-expr> are unconnected. This can be overwritten by using\n");
 		log("the -nounset option.\n");
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 1c66fb81d..7828dce1d 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -158,8 +158,8 @@ struct ConnwrappersPass : public Pass {
 		log("\n");
 		log("Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports\n");
 		log("in wrapper cells with a (larger) constant port size. I.e. the upper bits\n");
-		log("of the wrapper outut are signed/unsigned bit extended. This command uses this\n");
-		log("knowlege to rewire the inputs of the driven cells to match the output of\n");
+		log("of the wrapper output are signed/unsigned bit extended. This command uses this\n");
+		log("knowledge to rewire the inputs of the driven cells to match the output of\n");
 		log("the driving cell.\n");
 		log("\n");
 		log("    -signed <cell_type> <port_name> <width_param>\n");
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 16a4e64ae..e900e7b9c 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -80,7 +80,7 @@ struct DesignPass : public Pass {
 		log("\n");
 		log("    design -copy-to <name> [-as <new_mod_name>] [selection]\n");
 		log("\n");
-		log("Copy modules from the current design into the soecified one.\n");
+		log("Copy modules from the current design into the specified one.\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index c9268165e..b4219db2c 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1078,7 +1078,7 @@ struct SelectPass : public Pass {
 		log("\n");
 		log("    %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
 		log("    %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
-		log("        simmilar to %%x, but only select input (%%ci) or output cones (%%co)\n");
+		log("        similar to %%x, but only select input (%%ci) or output cones (%%co)\n");
 		log("\n");
 		log("    %%xe[...] %%cie[...] %%coe\n");
 		log("        like %%x, %%ci, and %%co but only consider combinatorial cells\n");
@@ -1403,7 +1403,7 @@ struct CdPass : public Pass {
 		log("    cd <cellname>\n");
 		log("\n");
 		log("When no module with the specified name is found, but there is a cell\n");
-		log("with the specified name in the current module, then this is equivialent\n");
+		log("with the specified name in the current module, then this is equivalent\n");
 		log("to 'cd <celltype>'.\n");
 		log("\n");
 		log("    cd ..\n");
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 28e3decda..3035e7301 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -610,7 +610,7 @@ struct ShowPass : public Pass {
 		log("    -colors <seed>\n");
 		log("        Randomly assign colors to the wires. The integer argument is the seed\n");
 		log("        for the random number generator. Change the seed value if the colored\n");
-		log("        graph still is ambigous. A seed of zero deactivates the coloring.\n");
+		log("        graph still is ambiguous. A seed of zero deactivates the coloring.\n");
 		log("\n");
 		log("    -colorattr <attribute_name>\n");
 		log("        Use the specified attribute to assign colors. A unique color is\n");
@@ -620,7 +620,7 @@ struct ShowPass : public Pass {
 		log("        annotate busses with a label indicating the width of the bus.\n");
 		log("\n");
 		log("    -signed\n");
-		log("        mark ports (A, B) that are declarted as signed (using the [AB]_SIGNED\n");
+		log("        mark ports (A, B) that are declared as signed (using the [AB]_SIGNED\n");
 		log("        cell parameter) with an asterisk next to the port name.\n");
 		log("\n");
 		log("    -stretch\n");
@@ -634,7 +634,7 @@ struct ShowPass : public Pass {
 		log("        enumerate objects with internal ($-prefixed) names\n");
 		log("\n");
 		log("    -long\n");
-		log("        do not abbeviate objects with internal ($-prefixed) names\n");
+		log("        do not abbreviate objects with internal ($-prefixed) names\n");
 		log("\n");
 		log("    -notitle\n");
 		log("        do not add the module name as graph title to the dot file\n");
@@ -673,7 +673,7 @@ struct ShowPass : public Pass {
 		bool flag_stretch = false;
 		bool flag_pause = false;
 		bool flag_enum = false;
-		bool flag_abbeviate = true;
+		bool flag_abbreviate = true;
 		bool flag_notitle = false;
 		RTLIL::IdString colorattr;
 
@@ -743,12 +743,12 @@ struct ShowPass : public Pass {
 			}
 			if (arg == "-enum") {
 				flag_enum = true;
-				flag_abbeviate = false;
+				flag_abbreviate = false;
 				continue;
 			}
 			if (arg == "-long") {
 				flag_enum = false;
-				flag_abbeviate = false;
+				flag_abbreviate = false;
 				continue;
 			}
 			if (arg == "-notitle") {
@@ -796,7 +796,7 @@ struct ShowPass : public Pass {
 				delete lib;
 			log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
 		}
-		ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbeviate, flag_notitle, color_selections, label_selections, colorattr);
+		ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, color_selections, label_selections, colorattr);
 		fclose(f);
 
 		for (auto lib : libs)
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index e56699f40..4ce2ec11c 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -255,7 +255,7 @@ struct SplicePass : public Pass {
 		log("\n");
 		log("This command adds $slice and $concat cells to the design to make the splicing\n");
 		log("of multi-bit signals explicit. This for example is useful for coarse grain\n");
-		log("synthesis, where dedidacted hardware is needed to splice signals.\n");
+		log("synthesis, where dedicated hardware is needed to splice signals.\n");
 		log("\n");
 		log("    -sel_by_cell\n");
 		log("        only select the cell ports to rewire by the cell. if the selection\n");
diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc
index 25ec4acc2..b78265933 100644
--- a/passes/cmds/write_file.cc
+++ b/passes/cmds/write_file.cc
@@ -31,7 +31,7 @@ struct WriteFileFrontend : public Frontend {
 		log("\n");
 		log("    write_file [options] output_file [input_file]\n");
 		log("\n");
-		log("Write the text fron the input file to the output file.\n");
+		log("Write the text from the input file to the output file.\n");
 		log("\n");
 		log("    -a\n");
 		log("        Append to output file (instead of overwriting)\n");
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 1cc4c3a7c..c001fdbfe 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -407,7 +407,7 @@ struct EquivMakePass : public Pass {
 		log("        Do not match cells or signals that match the names in the file.\n");
 		log("\n");
 		log("    -encfile <file>\n");
-		log("        Match FSM encodings using the desiption from the file.\n");
+		log("        Match FSM encodings using the description from the file.\n");
 		log("        See 'help fsm_recode' for details.\n");
 		log("\n");
 		log("Note: The circuit created by this command is not a miter (with something like\n");
diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc
index 1ecf14a28..3f5564fc5 100644
--- a/passes/fsm/fsm.cc
+++ b/passes/fsm/fsm.cc
@@ -34,7 +34,7 @@ struct FsmPass : public Pass {
 		log("    fsm [options] [selection]\n");
 		log("\n");
 		log("This pass calls all the other fsm_* passes in a useful order. This performs\n");
-		log("FSM extraction and optimiziation. It also calls opt_clean as needed:\n");
+		log("FSM extraction and optimization. It also calls opt_clean as needed:\n");
 		log("\n");
 		log("    fsm_detect          unless got option -nodetect\n");
 		log("    fsm_extract\n");
@@ -59,7 +59,7 @@ struct FsmPass : public Pass {
 		log("    -expand, -norecode, -export, -nomap\n");
 		log("        enable or disable passes as indicated above\n");
 		log("\n");
-		log("    -encoding tye\n");
+		log("    -encoding type\n");
 		log("    -fm_set_fsm_file file\n");
 		log("    -encfile file\n");
 		log("        passed through to fsm_recode pass\n");
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 914dcf29c..43c9a792f 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -253,7 +253,7 @@ struct FsmExpandPass : public Pass {
 		log("\n");
 		log("The fsm_extract pass is conservative about the cells that belong to a finite\n");
 		log("state machine. This pass can be used to merge additional auxiliary gates into\n");
-		log("the finate state machine.\n");
+		log("the finite state machine.\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index bfa3890a2..598fe9396 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -388,7 +388,7 @@ struct HierarchyPass : public Pass {
 		log("\n");
 		log("Input ports are specified with the 'i' prefix, output ports with the 'o'\n");
 		log("prefix and inout ports with the 'io' prefix. The optional <num> specifies\n");
-		log("the position of the port in the parameter list (needed when instanciated\n");
+		log("the position of the port in the parameter list (needed when instantiated\n");
 		log("using positional arguments). When <num> is not specified, the <portname> can\n");
 		log("also contain wildcard characters.\n");
 		log("\n");
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 7d98a7c46..824d6a6e8 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -605,7 +605,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
 	mapped_wr_port:;
 	}
 
-	// houskeeping stuff for growing more read ports and restarting read port assignments
+	// housekeeping stuff for growing more read ports and restarting read port assignments
 
 	int grow_read_ports_cursor = -1;
 	bool try_growing_more_read_ports = false;
@@ -694,7 +694,7 @@ grow_read_ports:;
 						pi.make_transp = true;
 						enable_make_transp = true;
 					} else {
-						log("        Bram port %c%d.%d has incompatible read transparancy.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
+						log("        Bram port %c%d.%d has incompatible read transparency.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
 						goto skip_bram_rport;
 					}
 				}
@@ -1127,7 +1127,7 @@ struct MemoryBramPass : public Pass {
 		log("      ports  1 1         # number of ports in each group\n");
 		log("      wrmode 1 0         # set to '1' if this groups is write ports\n");
 		log("      enable 4 0         # number of enable bits (for write ports)\n");
-		log("      transp 0 2         # transparatent (for read ports)\n");
+		log("      transp 0 2         # transparent (for read ports)\n");
 		log("      clocks 1 2         # clock configuration\n");
 		log("      clkpol 2 2         # clock polarity configuration\n");
 		log("    endbram\n");
@@ -1145,7 +1145,7 @@ struct MemoryBramPass : public Pass {
 		log("greater than 1 share the same configuration bit.\n");
 		log("\n");
 		log("Using the same bram name in different bram blocks will create different variants\n");
-		log("of the bram. Verilog configration parameters for the bram are created as needed.\n");
+		log("of the bram. Verilog configuration parameters for the bram are created as needed.\n");
 		log("\n");
 		log("It is also possible to create variants by repeating statements in the bram block\n");
 		log("and appending '@<label>' to the individual statements.\n");
@@ -1178,7 +1178,7 @@ struct MemoryBramPass : public Pass {
 		log("    dcells  .......  number of cells in 'data-direction'\n");
 		log("    cells  ........  total number of cells (acells*dcells*dups)\n");
 		log("\n");
-		log("The interface for the created bram instances is dervived from the bram\n");
+		log("The interface for the created bram instances is derived from the bram\n");
 		log("description. Use 'techmap' to convert the created bram instances into\n");
 		log("instances of the actual bram cells of your target architecture.\n");
 		log("\n");
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index aec85b46e..98b7b2e15 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -284,7 +284,7 @@ struct OptReduceWorker
 			did_something = false;
 
 			// merge trees of reduce_* cells to one single cell and unify input vectors
-			// (only handle recduce_and and reduce_or for various reasons)
+			// (only handle reduce_and and reduce_or for various reasons)
 
 			const char *type_list[] = { "$reduce_or", "$reduce_and" };
 			for (auto type : type_list)
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index b1b441da7..2c39708bb 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -1393,7 +1393,7 @@ struct SharePass : public Pass {
 		log("\n");
 		log("  -fast\n");
 		log("    Only consider the simple part of the control logic in SAT solving, resulting\n");
-		log("    in much easier SAT problems at the cost of maybe missing some oportunities\n");
+		log("    in much easier SAT problems at the cost of maybe missing some opportunities\n");
 		log("    for resource sharing.\n");
 		log("\n");
 		log("  -limit N\n");
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index d97fa6f16..522664032 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -87,7 +87,7 @@ struct BruteForceEquivChecker
 	BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) :
 			mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
 	{
-		log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
+		log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
 		for (auto &w : mod1->wires_)
 		{
 			RTLIL::Wire *wire1 = w.second;
@@ -421,7 +421,7 @@ struct EvalPass : public Pass {
 					log_error("Can't find module `%s'!\n", mod2_name.c_str());
 				BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
 				if (checker.errors > 0)
-					log_cmd_error("Modules are not equivialent!\n");
+					log_cmd_error("Modules are not equivalent!\n");
 				log("Verified %s = %s (using brute-force check on %d cases).\n",
 						mod1_name.c_str(), mod2_name.c_str(), checker.counter);
 				return;
@@ -594,7 +594,7 @@ struct EvalPass : public Pass {
 			log("\n");
 			if (undef.size() > 0) {
 				undef.sort_and_unify();
-				log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef));
+				log("Assumed undef (x) value for the following signals: %s\n\n", log_signal(undef));
 			}
 		}
 	}
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 3d2bcf63a..ca784890b 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -237,8 +237,8 @@ struct ExposePass : public Pass {
 		log("        signal path at that wire.\n");
 		log("\n");
 		log("    -shared\n");
-		log("        only expose those signals that are shared ammong the selected modules.\n");
-		log("        this is useful for preparing modules for equivialence checking.\n");
+		log("        only expose those signals that are shared among the selected modules.\n");
+		log("        this is useful for preparing modules for equivalence checking.\n");
 		log("\n");
 		log("    -evert\n");
 		log("        also turn connections to instances of other modules to additional\n");
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index f9d3a82a5..e0d11243b 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -457,7 +457,7 @@ struct PerformReduction
 				out_depth[idx] = std::numeric_limits<int>::max();
 
 			if (verbose_level >= 1) {
-				log("%s    Found %d equivialent signals:", indt, int(bucket.size()));
+				log("%s    Found %d equivalent signals:", indt, int(bucket.size()));
 				for (int idx : bucket)
 					log("%s%s%s", idx == bucket.front() ? " " : ", ", out_inverted[idx] ? "~" : "", log_signal(out_bits[idx]));
 				log("\n");
@@ -506,7 +506,7 @@ struct PerformReduction
 				std::vector<RTLIL::SigBit> r_sigbits;
 				for (int idx : r)
 					r_sigbits.push_back(out_bits[idx]);
-				log("  Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(r_sigbits));
+				log("  Found group of %d equivalent signals: %s\n", int(r.size()), log_signal(r_sigbits));
 			}
 
 			std::vector<int> undef_slaves;
@@ -692,7 +692,7 @@ struct FreduceWorker
 		if (!dump_prefix.empty())
 			dump();
 
-		log("  Rewiring %d equivialent groups:\n", int(equiv.size()));
+		log("  Rewiring %d equivalent groups:\n", int(equiv.size()));
 		int rewired_sigbits = 0;
 		for (auto &grp : equiv)
 		{
@@ -766,7 +766,7 @@ struct FreducePass : public Pass {
 		log("    freduce [options] [selection]\n");
 		log("\n");
 		log("This pass performs functional reduction in the circuit. I.e. if two nodes are\n");
-		log("equivialent, they are merged to one node and one of the redundant drivers is\n");
+		log("equivalent, they are merged to one node and one of the redundant drivers is\n");
 		log("disconnected. A subsequent call to 'clean' will remove the redundant drivers.\n");
 		log("\n");
 		log("    -v, -vv\n");
@@ -784,7 +784,7 @@ struct FreducePass : public Pass {
 		log("        operation. this is mostly used for debugging the freduce command.\n");
 		log("\n");
 		log("This pass is undef-aware, i.e. it considers don't-care values for detecting\n");
-		log("equivialent nodes.\n");
+		log("equivalent nodes.\n");
 		log("\n");
 		log("All selected wires are considered for rewiring. The selected cells cover the\n");
 		log("circuit that is analyzed.\n");
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 24d7e3a08..682299ef2 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -340,7 +340,7 @@ struct MiterPass : public Pass {
 		log("\n");
 		log("    miter -equiv [options] gold_name gate_name miter_name\n");
 		log("\n");
-		log("Creates a miter circuit for equivialence checking. The gold- and gate- modules\n");
+		log("Creates a miter circuit for equivalence checking. The gold- and gate- modules\n");
 		log("must have the same interfaces. The miter circuit will have all inputs of the\n");
 		log("two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'\n");
 		log("output that goes high if an output mismatch between the two source modules is\n");
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 16ec88fe0..ed6526fba 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -1017,7 +1017,7 @@ struct SatPass : public Pass {
 		log("\n");
 		log("    -prove-x <signal> <value>\n");
 		log("        Like -prove, but an undef (x) bit in the lhs matches any value on\n");
-		log("        the right hand side. Useful for equivialence checking.\n");
+		log("        the right hand side. Useful for equivalence checking.\n");
 		log("\n");
 		log("    -prove-asserts\n");
 		log("        Prove that all asserts in the design hold.\n");
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index c19593f05..d1e629b5a 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1158,7 +1158,7 @@ struct AbcPass : public Pass {
 		log("        use the specified ABC script file instead of the default script.\n");
 		log("\n");
 		log("        if <file> starts with a plus sign (+), then the rest of the filename\n");
-		log("        string is interprated as the command string to be passed to ABC. the\n");
+		log("        string is interpreted as the command string to be passed to ABC. The\n");
 		log("        leading plus sign is removed and all commas (,) in the string are\n");
 		log("        replaced with blanks before the string is passed to ABC.\n");
 		log("\n");
@@ -1235,7 +1235,7 @@ struct AbcPass : public Pass {
 		log("\n");
 		log("    -keepff\n");
 		log("        set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
-		log("        them, for example for equivialence checking.)\n");
+		log("        them, for example for equivalence checking.)\n");
 		log("\n");
 		log("    -nocleanup\n");
 		log("        when this option is used, the temporary files created by this pass\n");
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index e587f827a..51bfaade3 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -273,7 +273,7 @@ struct Dff2dffePass : public Pass {
 		log("        <external_gate_type> is the cell type name for a cell with an\n");
 		log("        identical interface to the <internal_gate_type>, except it\n");
 		log("        also has an high-active enable port 'E'.\n");
-		log("          Usually <external_gate_type> is an intemediate cell type\n");
+		log("          Usually <external_gate_type> is an intermediate cell type\n");
 		log("        that is then translated to the final type using 'techmap'.\n");
 		log("\n");
 		log("    -direct-match <pattern>\n");
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index b670083bf..3c24524df 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -390,11 +390,11 @@ struct ExtractPass : public Pass {
 		log("        match. This option can be used multiple times.\n");
 		log("\n");
 		log("    -swap <needle_type> <port1>,<port2>[,...]\n");
-		log("        Register a set of swapable ports for a needle cell type.\n");
+		log("        Register a set of swappable ports for a needle cell type.\n");
 		log("        This option can be used multiple times.\n");
 		log("\n");
 		log("    -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]\n");
-		log("        Register a valid permutation of swapable ports for a needle\n");
+		log("        Register a valid permutation of swappable ports for a needle\n");
 		log("        cell type. This option can be used multiple times.\n");
 		log("\n");
 		log("    -cell_attr <attribute_name>\n");
@@ -409,7 +409,7 @@ struct ExtractPass : public Pass {
 		log("    -ignore_param <cell_type> <parameter_name>\n");
 		log("        Do not use this parameter when matching cells.\n");
 		log("\n");
-		log("This pass does not operate on modules with uprocessed processes in it.\n");
+		log("This pass does not operate on modules with unprocessed processes in it.\n");
 		log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
 		log("\n");
 		log("This pass can also be used for mining for frequent subcircuits. In this mode\n");
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1a16b6f45..8ba028310 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -850,7 +850,7 @@ struct TechmapPass : public Pass {
 		log("    techmap [-map filename] [selection]\n");
 		log("\n");
 		log("This pass implements a very simple technology mapper that replaces cells in\n");
-		log("the design with implementations given in form of a verilog or ilang source\n");
+		log("the design with implementations given in form of a Verilog or ilang source\n");
 		log("file.\n");
 		log("\n");
 		log("    -map filename\n");
@@ -871,7 +871,7 @@ struct TechmapPass : public Pass {
 		log("\n");
 		log("    -recursive\n");
 		log("        instead of the iterative breadth-first algorithm use a recursive\n");
-		log("        depth-first algorithm. both methods should yield equivialent results,\n");
+		log("        depth-first algorithm. both methods should yield equivalent results,\n");
 		log("        but may differ in performance.\n");
 		log("\n");
 		log("    -autoproc\n");
@@ -883,8 +883,8 @@ struct TechmapPass : public Pass {
 		log("        as final cell types by this mode.\n");
 		log("\n");
 		log("    -D <define>, -I <incdir>\n");
-		log("        this options are passed as-is to the verilog frontend for loading the\n");
-		log("        map file. Note that the verilog frontend is also called with the\n");
+		log("        this options are passed as-is to the Verilog frontend for loading the\n");
+		log("        map file. Note that the Verilog frontend is also called with the\n");
 		log("        '-ignore_redef' option set.\n");
 		log("\n");
 		log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
@@ -930,7 +930,7 @@ struct TechmapPass : public Pass {
 		log("        of constant inputs and shorted inputs at this point and import the\n");
 		log("        constant and connected bits into the map module. All further commands\n");
 		log("        are executed in this copy. This is a very convenient way of creating\n");
-		log("        optimizied specializations of techmap modules without using the special\n");
+		log("        optimized specializations of techmap modules without using the special\n");
 		log("        parameters described below.\n");
 		log("\n");
 		log("        A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
@@ -966,12 +966,12 @@ struct TechmapPass : public Pass {
 		log("constant value.\n");
 		log("\n");
 		log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
-		log("of the cell that is beeing replaced.\n");
+		log("of the cell that is being replaced.\n");
 		log("\n");
 		log("See 'help extract' for a pass that does the opposite thing.\n");
 		log("\n");
 		log("See 'help flatten' for a pass that does flatten the design (which is\n");
-		log("esentially techmap but using the design itself as map library).\n");
+		log("essentially techmap but using the design itself as map library).\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@@ -1099,7 +1099,7 @@ struct FlattenPass : public Pass {
 		log("    flatten [selection]\n");
 		log("\n");
 		log("This pass flattens the design by replacing cells by their implementation. This\n");
-		log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
+		log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
 		log("pass is using the current design as mapping library.\n");
 		log("\n");
 		log("Cells and/or modules with the 'keep_hiearchy' attribute set will not be\n");
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index 5d573ad62..659f0bb69 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -326,7 +326,7 @@ struct TestAutotbBackend : public Backend {
 		log("low in order to explore more inner states in a state machine.\n");
 		log("\n");
 		log("    -n <int>\n");
-		log("        number of iterations the test bench shuld run (default = 1000)\n");
+		log("        number of iterations the test bench should run (default = 1000)\n");
 		log("\n");
 	}
 	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
-- 
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