From ad69c668cedaab76f84c982411d7cddbd868cccf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 11 Jan 2019 14:02:16 +0100 Subject: Add mockup .pmg (pattern matcher generator) file Signed-off-by: Clifford Wolf --- passes/pmgen/ice40_dsp.pmg | 75 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 passes/pmgen/ice40_dsp.pmg (limited to 'passes') diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg new file mode 100644 index 000000000..5a0af3e04 --- /dev/null +++ b/passes/pmgen/ice40_dsp.pmg @@ -0,0 +1,75 @@ +state SigBit clock +state bool clock_pol, clock_vld +state SigSpec sigA, sigB, sigY + +match mul + select mul->type.in($mul) + select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10 + select GetSize(mul->getPort(\Y)) > 10 +endmatch + +match ffA + select ffA->type.in($dff) + filter port(ffA, \Q) === port(mul, \A) + optional +endmatch + +code sigA clock clock_pol clock_vld + sigA = port(mul, \A); + + if (ffA != nullptr) { + sigA = port(ffA, \D); + + clock = port(ffA, \CLK).as_bit(); + clock_pol = param(ffA, \CLK_POLARITY).as_bool(); + clock_vld = true; + } +endcode + +match ffB + select ffB->type.in($dff) + filter port(ffB, \Q) === port(mul, \B) + optional +endmatch + +code sigB clock clok_pol clock_vld + sigB = port(mul, \B); + + if (ffB != nullptr) { + sigB = port(ffB, \D); + SigBit c = port(ffB, \CLK).as_bit(); + bool cp = param(ffB, \CLK_POLARITY).as_bool(); + + if (clock_vld && (c != clock || cp != clock_pol)) + reject; + + clock = c; + clock_pol = cp; + clock_vld = true; + } +endcode + +match ffY + select ffY->type.in($dff) + filter port(ffY, \D) === port(mul, \Y) + optional +endmatch + +code sigY clock clok_pol clock_vld + sigY = port(mul, \Y); + + if (ffY != nullptr) { + sigY = port(ffY, \D); + SigBit c = port(ffY, \CLK).as_bit(); + bool cp = param(ffY, \CLK_POLARITY).as_bool(); + + if (clock_vld && (c != clock || cp != clock_pol)) + reject; + + clock = c; + clock_pol = cp; + clock_vld = true; + } + + accept; +endcode -- cgit v1.2.3 From b9545aa0e1260f3d7123ec63e9dcfb0e022e2ff3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 13 Jan 2019 10:57:11 +0100 Subject: Progress in pmgen Signed-off-by: Clifford Wolf --- passes/pmgen/.gitignore | 1 + passes/pmgen/Makefile.inc | 8 ++ passes/pmgen/ice40_dsp.cc | 65 +++++++++++ passes/pmgen/ice40_dsp.pmg | 19 ++-- passes/pmgen/pmgen.py | 262 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 347 insertions(+), 8 deletions(-) create mode 100644 passes/pmgen/.gitignore create mode 100644 passes/pmgen/Makefile.inc create mode 100644 passes/pmgen/ice40_dsp.cc create mode 100644 passes/pmgen/pmgen.py (limited to 'passes') diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore new file mode 100644 index 000000000..c9263057e --- /dev/null +++ b/passes/pmgen/.gitignore @@ -0,0 +1 @@ +/ice40_dsp_pm.h diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc new file mode 100644 index 000000000..33baaca30 --- /dev/null +++ b/passes/pmgen/Makefile.inc @@ -0,0 +1,8 @@ +OBJS += passes/pmgen/ice40_dsp.o + +passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h +EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h +.SECONDARY: passes/pmgen/ice40_dsp_pm.h + +passes/pmgen/ice40_dsp_pm.h: passes/pmgen/ice40_dsp.pmg passes/pmgen/pmgen.py + $(P) cd passes/pmgen && python3 pmgen.py ice40_dsp diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc new file mode 100644 index 000000000..0498f31b7 --- /dev/null +++ b/passes/pmgen/ice40_dsp.cc @@ -0,0 +1,65 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "passes/pmgen/ice40_dsp_pm.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +void ice40_dsp_accept(ice40_dsp_pm * /* pm */) +{ +} + +struct Ice40DspPass : public Pass { + Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ice40_dsp [options] [selection]\n"); + log("\n"); + log("Map multipliers and iCE40 DSP resources.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing ICE40_DSP pass (map multipliers).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // if (args[argidx] == "-singleton") { + // singleton_mode = true; + // continue; + // } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + ice40_dsp_pm pm(module); + pm.run(ice40_dsp_accept); + } + } +} Ice40DspPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 5a0af3e04..2b9bb8783 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -1,6 +1,6 @@ -state SigBit clock -state bool clock_pol, clock_vld -state SigSpec sigA, sigB, sigY +state clock +state clock_pol clock_vld +state sigA sigB sigY match mul select mul->type.in($mul) @@ -10,7 +10,8 @@ endmatch match ffA select ffA->type.in($dff) - filter port(ffA, \Q) === port(mul, \A) + select nusers(port(ffA, \Q)) == 2 + filter port(ffA, \Q) === port(mul, \A) optional endmatch @@ -28,11 +29,12 @@ endcode match ffB select ffB->type.in($dff) - filter port(ffB, \Q) === port(mul, \B) + select nusers(port(ffA, \Q)) == 2 + filter port(ffB, \Q) === port(mul, \B) optional endmatch -code sigB clock clok_pol clock_vld +code sigB clock clock_pol clock_vld sigB = port(mul, \B); if (ffB != nullptr) { @@ -51,11 +53,12 @@ endcode match ffY select ffY->type.in($dff) - filter port(ffY, \D) === port(mul, \Y) + select nusers(port(ffY, \D)) == 2 + filter port(ffY, \D) === port(mul, \Y) optional endmatch -code sigY clock clok_pol clock_vld +code sigY clock clock_pol clock_vld sigY = port(mul, \Y); if (ffY != nullptr) { diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py new file mode 100644 index 000000000..bf70a6dbd --- /dev/null +++ b/passes/pmgen/pmgen.py @@ -0,0 +1,262 @@ +#!/usr/bin/env python3 + +import re +import sys +import pprint + +pp = pprint.PrettyPrinter(indent=4) + +prefix = sys.argv[1] + +state_types = dict() +blocks = list() +ids = dict() + +def rewrite_cpp(s): + t = list() + i = 0 + while i < len(s): + if s[i] in ("'", '"') and i + 1 < len(s): + j = i + 1 + while j + 1 < len(s) and s[j] != s[i]: + if s[j] == '\\' and j + 1 < len(s): + j += 1 + j += 1 + t.append(s[i:j+1]) + i = j + 1 + continue + + if s[i] in ('$', '\\') and i + 1 < len(s): + j = i + 1 + while True: + if j == len(s): + j -= 1 + break + if ord('a') <= ord(s[j]) <= ord('z'): + j += 1 + continue + if ord('A') <= ord(s[j]) <= ord('Z'): + j += 1 + continue + if ord('0') <= ord(s[j]) <= ord('9'): + j += 1 + continue + if s[j] == '_': + j += 1 + continue + j -= 1 + break + + n = s[i:j+1] + i = j + 1 + + if n[0] == '$': + v = "id_d_" + n[1:] + else: + v = "id_b_" + n[1:] + + if v not in ids: + ids[v] = n + else: + assert ids[v] == n + + t.append(v) + continue + + if s[i] == "\t": + t.append(" ") + else: + t.append(s[i]) + + i += 1 + + return "".join(t) + +with open("%s.pmg" % prefix, "r") as f: + while True: + line = f.readline() + if line == "": break + line = line.strip() + + cmd = line.split() + if len(cmd) == 0: continue + cmd = cmd[0] + + if cmd == "state": + m = re.match(r"^state\s+<(.*?)>\s+(([A-Za-z_][A-Za-z_0-9]*\s+)*[A-Za-z_][A-Za-z_0-9]*)\s*$", line) + assert m + type_str = m.group(1) + states_str = m.group(2) + for s in re.split(r"\s+", states_str): + assert s not in state_types + state_types[s] = type_str + continue + + if cmd == "match": + block = dict() + block["type"] = "match" + + line = line.split() + assert len(line) == 2 + assert line[1] not in state_types + block["cell"] = line[1] + state_types[line[1]] = "Cell*"; + + block["select"] = list() + block["filter"] = list() + block["optional"] = False + + while True: + l = f.readline() + assert l != "" + a = l.split() + if len(a) == 0: continue + if a[0] == "endmatch": break + + if a[0] == "select": + b = l.lstrip()[6:] + block["select"].append(rewrite_cpp(b.strip())) + continue + + if a[0] == "filter": + m = re.match(r"^\s*filter\s+<(.*?)>\s+(.*?)\s*===\s*(.*?)\s*$", l) + assert m + block["filter"].append((m.group(1), rewrite_cpp(m.group(2)), rewrite_cpp(m.group(3)))) + continue + + if a[0] == "optional": + block["optional"] = True + continue + + assert False + + blocks.append(block) + + if cmd == "code": + block = dict() + block["type"] = "code" + block["code"] = list() + block["states"] = set() + + for s in line.split()[1:]: + assert s in state_types + block["states"].add(s) + + while True: + l = f.readline() + assert l != "" + a = l.split() + if len(a) == 0: continue + if a[0] == "endcode": break + + block["code"].append(rewrite_cpp(l.rstrip())) + + blocks.append(block) + +# pp.pprint(blocks) + +with open("%s_pm.h" % prefix, "w") as f: + print("// Generated by pmgen.py from {}.pgm".format(prefix), file=f) + print("#include \"kernel/yosys.h\"", file=f) + print("#include \"kernel/sigtools.h\"", file=f) + print("YOSYS_NAMESPACE_BEGIN", file=f) + print("struct {}_pm {{".format(prefix), file=f) + print(" Module *module;", file=f) + print(" SigMap sigmap;", file=f) + print(" std::function on_accept;".format(prefix), file=f) + print("", file=f) + + for index in range(len(blocks)): + block = blocks[index] + if block["type"] == "match": + index_types = list() + for filt in block["filter"]: + index_types.append(filt[0]) + print(" typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f) + print(" dict> index_{};".format(index, index), file=f) + print(" pool blacklist;", file=f) + print("", file=f) + + print(" struct state_t {", file=f) + + for s, t in sorted(state_types.items()): + print(" {} {};".format(t, s), file=f) + print(" } st;", file=f) + print("", file=f) + + for v, n in sorted(ids.items()): + if n[0] == "\\": + print(" IdString {}{{\"\\{}\"}};".format(v, n), file=f) + else: + print(" IdString {}{{\"{}\"}};".format(v, n), file=f) + print("", file=f) + + print(" {}_pm(Module *module) :".format(prefix), file=f) + print(" module(module), sigmap(module) {", file=f) + print(" }", file=f) + + print("", file=f) + print(" void run(std::function on_accept_f) {{".format(prefix), file=f) + print(" on_accept = on_accept_f;", file=f) + if len(blocks): + print(" block_0();", file=f) + print(" }", file=f) + + for index in range(len(blocks)): + block = blocks[index] + + print("", file=f) + print(" void block_{}() {{".format(index), file=f) + + const_st = set() + nonconst_st = set() + restore_st = set() + + for i in range(index): + if blocks[i]["type"] == "code": + for s in blocks[i]["states"]: + const_st.add(s) + elif blocks[i]["type"] == "match": + const_st.add(blocks[i]["cell"]) + else: + assert False + + if block["type"] == "code": + for s in block["states"]: + if s in const_st: + const_st.remove(s) + restore_st.add(s) + nonconst_st.add(s) + elif block["type"] == "match": + s = block["cell"] + assert s not in const_st + nonconst_st.add(s) + else: + assert False + + for s in sorted(const_st): + t = state_types[s] + if t.endswith("*"): + print(" {} const &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f) + else: + print(" const {} &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f) + + for s in sorted(nonconst_st): + t = state_types[s] + print(" {} &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f) + + if len(restore_st): + print("", file=f) + for s in sorted(restore_st): + t = state_types[s] + print(" {} backup_{} = st.{};".format(t, s, s), file=f) + + if len(restore_st): + print("", file=f) + for s in sorted(restore_st): + t = state_types[s] + print(" st.{} = backup_{};".format(s, s), file=f) + + print(" }", file=f) + + print("};\nYOSYS_NAMESPACE_END", file=f) -- cgit v1.2.3 From 1f8e76f993b602bb8b03af216615a248bbde3652 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 13 Jan 2019 12:53:13 +0100 Subject: Progress in pmgen Signed-off-by: Clifford Wolf --- passes/pmgen/ice40_dsp.cc | 11 +++- passes/pmgen/ice40_dsp.pmg | 6 +- passes/pmgen/pmgen.py | 161 ++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 157 insertions(+), 21 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 0498f31b7..049ef6c0e 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -24,8 +24,15 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -void ice40_dsp_accept(ice40_dsp_pm * /* pm */) +void ice40_dsp_accept(ice40_dsp_pm *pm) { + log("\n"); + log("mul: %s\n", pm->st.mul ? log_id(pm->st.mul) : "--"); + log("ffA: %s\n", pm->st.ffA ? log_id(pm->st.ffA) : "--"); + log("ffB: %s\n", pm->st.ffB ? log_id(pm->st.ffB) : "--"); + log("ffY: %s\n", pm->st.ffY ? log_id(pm->st.ffY) : "--"); + + pm->blacklist(pm->st.mul); } struct Ice40DspPass : public Pass { @@ -56,7 +63,7 @@ struct Ice40DspPass : public Pass { for (auto module : design->selected_modules()) { - ice40_dsp_pm pm(module); + ice40_dsp_pm pm(module, module->cells()); pm.run(ice40_dsp_accept); } } diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 2b9bb8783..a2937ddc6 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -10,7 +10,7 @@ endmatch match ffA select ffA->type.in($dff) - select nusers(port(ffA, \Q)) == 2 + // select nusers(port(ffA, \Q)) == 2 filter port(ffA, \Q) === port(mul, \A) optional endmatch @@ -29,7 +29,7 @@ endcode match ffB select ffB->type.in($dff) - select nusers(port(ffA, \Q)) == 2 + // select nusers(port(ffB, \Q)) == 2 filter port(ffB, \Q) === port(mul, \B) optional endmatch @@ -73,6 +73,4 @@ code sigY clock clock_pol clock_vld clock_pol = cp; clock_vld = true; } - - accept; endcode diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index bf70a6dbd..7d33c4fc9 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -79,7 +79,7 @@ with open("%s.pmg" % prefix, "r") as f: line = line.strip() cmd = line.split() - if len(cmd) == 0: continue + if len(cmd) == 0 or cmd[0].startswith("//"): continue cmd = cmd[0] if cmd == "state": @@ -110,7 +110,7 @@ with open("%s.pmg" % prefix, "r") as f: l = f.readline() assert l != "" a = l.split() - if len(a) == 0: continue + if len(a) == 0 or a[0].startswith("//"): continue if a[0] == "endmatch": break if a[0] == "select": @@ -153,13 +153,17 @@ with open("%s.pmg" % prefix, "r") as f: blocks.append(block) -# pp.pprint(blocks) - with open("%s_pm.h" % prefix, "w") as f: print("// Generated by pmgen.py from {}.pgm".format(prefix), file=f) + print("", file=f) + print("#include \"kernel/yosys.h\"", file=f) print("#include \"kernel/sigtools.h\"", file=f) + print("", file=f) + print("YOSYS_NAMESPACE_BEGIN", file=f) + print("", file=f) + print("struct {}_pm {{".format(prefix), file=f) print(" Module *module;", file=f) print(" SigMap sigmap;", file=f) @@ -174,7 +178,9 @@ with open("%s_pm.h" % prefix, "w") as f: index_types.append(filt[0]) print(" typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f) print(" dict> index_{};".format(index, index), file=f) - print(" pool blacklist;", file=f) + print(" dict> sigusers;", file=f) + print(" pool blacklist_cells;", file=f) + print(" int rollback;", file=f) print("", file=f) print(" struct state_t {", file=f) @@ -191,21 +197,89 @@ with open("%s_pm.h" % prefix, "w") as f: print(" IdString {}{{\"{}\"}};".format(v, n), file=f) print("", file=f) - print(" {}_pm(Module *module) :".format(prefix), file=f) - print(" module(module), sigmap(module) {", file=f) + print(" void add_siguser(const SigSpec &sig, Cell *cell) {", file=f) + print(" for (auto bit : sigmap(sig)) {", file=f) + print(" if (bit.wire == nullptr) continue;", file=f) + print(" if (sigusers.count(bit) == 0 && bit.wire->port_id)", file=f) + print(" sigusers[bit].insert(nullptr);", file=f) + print(" sigusers[bit].insert(cell);", file=f) + print(" }", file=f) + print(" }", file=f) + print("", file=f) + + print(" void blacklist(Cell *cell) {", file=f) + print(" blacklist_cells.insert(cell);", file=f) + print(" }", file=f) + print("", file=f) + + print(" void check_blacklist() {", file=f) + for index in range(len(blocks)): + block = blocks[index] + if block["type"] == "match": + print(" if (st.{} != nullptr && blacklist_cells.count(st.{})) {{".format(block["cell"], block["cell"]), file=f) + print(" rollback = {};".format(index+1), file=f) + print(" return;", file=f) + print(" }", file=f) + print(" rollback = 0;", file=f) + print(" }", file=f) + print("", file=f) + + print(" SigSpec port(Cell *cell, IdString portname) {", file=f) + print(" return sigmap(cell->getPort(portname));", file=f) print(" }", file=f) + print("", file=f) + + print(" Const param(Cell *cell, IdString paramname) {", file=f) + print(" return cell->getParam(paramname);", file=f) + print(" }", file=f) + print("", file=f) + print(" int nusers(const SigSpec &sig) {", file=f) + print(" pool users;", file=f) + print(" for (auto bit : sigmap(sig))", file=f) + print(" for (auto user : sigusers[bit])", file=f) + print(" users.insert(user);", file=f) + print(" return GetSize(users);", file=f) + print(" }", file=f) + print("", file=f) + + print(" {}_pm(Module *module, const vector &cells) :".format(prefix), file=f) + print(" module(module), sigmap(module) {", file=f) + print(" for (auto cell : cells) {", file=f) + print(" for (auto &conn : cell->connections())", file=f) + print(" add_siguser(conn.second, cell);", file=f) + + for index in range(len(blocks)): + block = blocks[index] + if block["type"] == "match": + print(" do {", file=f) + print(" Cell *{} = cell;".format(block["cell"]), file=f) + for expr in block["select"]: + print(" if (!({})) break;".format(expr), file=f) + print(" index_{}_key_type key;".format(index), file=f) + for field, filt in enumerate(block["filter"]): + print(" std::get<{}>(key) = {};".format(field, filt[1]), file=f) + print(" index_{}[key].push_back(cell);".format(index), file=f) + print(" } while (0);", file=f) + + print(" }", file=f) + print(" }", file=f) print("", file=f) + print(" void run(std::function on_accept_f) {{".format(prefix), file=f) print(" on_accept = on_accept_f;", file=f) - if len(blocks): - print(" block_0();", file=f) + print(" rollback = 0;", file=f) + print(" block_0();", file=f) print(" }", file=f) + print("", file=f) + + print("#define reject break", file=f) + print("#define accept do { on_accept(this); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f) + print("", file=f) for index in range(len(blocks)): block = blocks[index] - print("", file=f) print(" void block_{}() {{".format(index), file=f) const_st = set() @@ -251,12 +325,69 @@ with open("%s_pm.h" % prefix, "w") as f: t = state_types[s] print(" {} backup_{} = st.{};".format(t, s, s), file=f) - if len(restore_st): + if block["type"] == "code": print("", file=f) - for s in sorted(restore_st): - t = state_types[s] - print(" st.{} = backup_{};".format(s, s), file=f) + print(" do {", file=f) + for line in block["code"]: + print(" " + line, file=f) + + print("", file=f) + print(" block_{}();".format(index+1), file=f) + print("rollback_label: YS_ATTRIBUTE(unused);", file=f) + print(" } while (0);", file=f) + + if len(restore_st): + print("", file=f) + for s in sorted(restore_st): + t = state_types[s] + print(" st.{} = backup_{};".format(s, s), file=f) + + elif block["type"] == "match": + assert len(restore_st) == 0 + + print("", file=f) + print(" index_{}_key_type key;".format(index), file=f) + for field, filt in enumerate(block["filter"]): + print(" std::get<{}>(key) = {};".format(field, filt[2]), file=f) + print(" const vector &cells = index_{}[key];".format(index), file=f) + + print("", file=f) + print(" for (int idx = 0; idx < GetSize(cells); idx++) {", file=f) + print(" {} = cells[idx];".format(block["cell"]), file=f) + print(" block_{}();".format(index+1), file=f) + print(" if (rollback) {", file=f) + print(" if (rollback != {}) {{".format(index+1), file=f) + print(" {} = nullptr;".format(block["cell"]), file=f) + print(" return;", file=f) + print(" }", file=f) + print(" rollback = 0;", file=f) + print(" }", file=f) + print(" }", file=f) + + print("", file=f) + print(" {} = nullptr;".format(block["cell"]), file=f) + + if block["optional"]: + print(" block_{}();".format(index+1), file=f) + + else: + assert False + print(" }", file=f) + print("", file=f) + + print("#undef reject", file=f) + print("#undef accept", file=f) + print("", file=f) + + print(" void block_{}() {{".format(len(blocks)), file=f) + print(" on_accept(this);", file=f) + print(" check_blacklist();", file=f) + print(" }", file=f) + print("};", file=f) + + print("", file=f) + print("YOSYS_NAMESPACE_END", file=f) - print("};\nYOSYS_NAMESPACE_END", file=f) +# pp.pprint(blocks) -- cgit v1.2.3 From d45379936b82a26b713e40d92f3e73cf03bcf7cc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 13 Jan 2019 17:03:58 +0100 Subject: Progress in pmgen Signed-off-by: Clifford Wolf --- passes/pmgen/ice40_dsp.cc | 29 ++++++++++-------- passes/pmgen/ice40_dsp.pmg | 74 +++++++++++++++++++++++++++++++++++++++++----- passes/pmgen/pmgen.py | 72 +++++++++++++++++++++++++++++++++----------- 3 files changed, 139 insertions(+), 36 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 049ef6c0e..a8f63ebfe 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -24,17 +24,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -void ice40_dsp_accept(ice40_dsp_pm *pm) -{ - log("\n"); - log("mul: %s\n", pm->st.mul ? log_id(pm->st.mul) : "--"); - log("ffA: %s\n", pm->st.ffA ? log_id(pm->st.ffA) : "--"); - log("ffB: %s\n", pm->st.ffB ? log_id(pm->st.ffB) : "--"); - log("ffY: %s\n", pm->st.ffY ? log_id(pm->st.ffY) : "--"); - - pm->blacklist(pm->st.mul); -} - struct Ice40DspPass : public Pass { Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { } void help() YS_OVERRIDE @@ -64,7 +53,23 @@ struct Ice40DspPass : public Pass { for (auto module : design->selected_modules()) { ice40_dsp_pm pm(module, module->cells()); - pm.run(ice40_dsp_accept); + pm.match([&]() + { + log("\n"); + log("ffA: %s\n", log_id(pm.st.ffA, "--")); + log("ffB: %s\n", log_id(pm.st.ffB, "--")); + log("mul: %s\n", log_id(pm.st.mul, "--")); + log("ffY: %s\n", log_id(pm.st.ffY, "--")); + log("addAB: %s\n", log_id(pm.st.addAB, "--")); + log("muxAB: %s\n", log_id(pm.st.muxAB, "--")); + log("ffS: %s\n", log_id(pm.st.ffS, "--")); + + pm.blacklist(pm.st.mul); + pm.blacklist(pm.st.ffA); + pm.blacklist(pm.st.ffB); + pm.blacklist(pm.st.ffY); + pm.blacklist(pm.st.ffS); + }); } } } Ice40DspPass; diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index a2937ddc6..1370cb66a 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -1,6 +1,7 @@ state clock state clock_pol clock_vld -state sigA sigB sigY +state sigA sigB sigY sigS +state addAB muxAB match mul select mul->type.in($mul) @@ -11,14 +12,14 @@ endmatch match ffA select ffA->type.in($dff) // select nusers(port(ffA, \Q)) == 2 - filter port(ffA, \Q) === port(mul, \A) + index port(ffA, \Q) === port(mul, \A) optional endmatch code sigA clock clock_pol clock_vld sigA = port(mul, \A); - if (ffA != nullptr) { + if (ffA) { sigA = port(ffA, \D); clock = port(ffA, \CLK).as_bit(); @@ -30,14 +31,14 @@ endcode match ffB select ffB->type.in($dff) // select nusers(port(ffB, \Q)) == 2 - filter port(ffB, \Q) === port(mul, \B) + index port(ffB, \Q) === port(mul, \B) optional endmatch code sigB clock clock_pol clock_vld sigB = port(mul, \B); - if (ffB != nullptr) { + if (ffB) { sigB = port(ffB, \D); SigBit c = port(ffB, \CLK).as_bit(); bool cp = param(ffB, \CLK_POLARITY).as_bool(); @@ -54,14 +55,14 @@ endcode match ffY select ffY->type.in($dff) select nusers(port(ffY, \D)) == 2 - filter port(ffY, \D) === port(mul, \Y) + index port(ffY, \D) === port(mul, \Y) optional endmatch code sigY clock clock_pol clock_vld sigY = port(mul, \Y); - if (ffY != nullptr) { + if (ffY) { sigY = port(ffY, \D); SigBit c = port(ffY, \CLK).as_bit(); bool cp = param(ffY, \CLK_POLARITY).as_bool(); @@ -74,3 +75,62 @@ code sigY clock clock_pol clock_vld clock_vld = true; } endcode + +match addA + select addA->type.in($add, $sub) + select nusers(port(addA, \A)) == 2 + index port(addA, \A) === sigY + optional +endmatch + +match addB + if !addA + select addB->type.in($add, $sub) + select nusers(port(addB, \B)) == 2 + index port(addB, \B) === sigY + optional +endmatch + +code addAB sigS + if (addA) { + addAB = addA; + sigS = port(addA, \B); + } + if (addB) { + addAB = addB; + sigS = port(addB, \A); + } +endcode + +match muxA + if addAB + select muxA->type.in($mux) + select nusers(port(muxA, \A)) == 2 + index port(muxA, \A) === port(addAB, \Y) + optional +endmatch + +match muxB + if addAB + if !muxA + select muxB->type.in($mux) + select nusers(port(muxB, \B)) == 2 + index port(muxB, \B) === port(addAB, \Y) + optional +endmatch + +code muxAB + muxAB = addAB; + if (muxA) + muxAB = muxA; + if (muxB) + muxAB = muxB; +endcode + +match ffS + if muxAB + select ffS->type.in($dff) + select nusers(port(ffS, \D)) == 2 + index port(ffS, \D) === port(muxAB, \Y) + index port(ffS, \Q) === sigS +endmatch diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 7d33c4fc9..88d60d298 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -102,7 +102,9 @@ with open("%s.pmg" % prefix, "r") as f: block["cell"] = line[1] state_types[line[1]] = "Cell*"; + block["if"] = list() block["select"] = list() + block["index"] = list() block["filter"] = list() block["optional"] = False @@ -113,15 +115,25 @@ with open("%s.pmg" % prefix, "r") as f: if len(a) == 0 or a[0].startswith("//"): continue if a[0] == "endmatch": break + if a[0] == "if": + b = l.lstrip()[2:] + block["if"].append(rewrite_cpp(b.strip())) + continue + if a[0] == "select": b = l.lstrip()[6:] block["select"].append(rewrite_cpp(b.strip())) continue - if a[0] == "filter": - m = re.match(r"^\s*filter\s+<(.*?)>\s+(.*?)\s*===\s*(.*?)\s*$", l) + if a[0] == "index": + m = re.match(r"^\s*index\s+<(.*?)>\s+(.*?)\s*===\s*(.*?)\s*$", l) assert m - block["filter"].append((m.group(1), rewrite_cpp(m.group(2)), rewrite_cpp(m.group(3)))) + block["index"].append((m.group(1), rewrite_cpp(m.group(2)), rewrite_cpp(m.group(3)))) + continue + + if a[0] == "filter": + b = l.lstrip()[6:] + block["filter"].append(rewrite_cpp(b.strip())) continue if a[0] == "optional": @@ -167,15 +179,15 @@ with open("%s_pm.h" % prefix, "w") as f: print("struct {}_pm {{".format(prefix), file=f) print(" Module *module;", file=f) print(" SigMap sigmap;", file=f) - print(" std::function on_accept;".format(prefix), file=f) + print(" std::function on_accept;".format(prefix), file=f) print("", file=f) for index in range(len(blocks)): block = blocks[index] if block["type"] == "match": index_types = list() - for filt in block["filter"]: - index_types.append(filt[0]) + for entry in block["index"]: + index_types.append(entry[0]) print(" typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f) print(" dict> index_{};".format(index, index), file=f) print(" dict> sigusers;", file=f) @@ -208,7 +220,8 @@ with open("%s_pm.h" % prefix, "w") as f: print("", file=f) print(" void blacklist(Cell *cell) {", file=f) - print(" blacklist_cells.insert(cell);", file=f) + print(" if (cell != nullptr)", file=f) + print(" blacklist_cells.insert(cell);", file=f) print(" }", file=f) print("", file=f) @@ -248,6 +261,8 @@ with open("%s_pm.h" % prefix, "w") as f: print(" for (auto cell : cells) {", file=f) print(" for (auto &conn : cell->connections())", file=f) print(" add_siguser(conn.second, cell);", file=f) + print(" }", file=f) + print(" for (auto cell : cells) {", file=f) for index in range(len(blocks)): block = blocks[index] @@ -257,8 +272,8 @@ with open("%s_pm.h" % prefix, "w") as f: for expr in block["select"]: print(" if (!({})) break;".format(expr), file=f) print(" index_{}_key_type key;".format(index), file=f) - for field, filt in enumerate(block["filter"]): - print(" std::get<{}>(key) = {};".format(field, filt[1]), file=f) + for field, entry in enumerate(block["index"]): + print(" std::get<{}>(key) = {};".format(field, entry[1]), file=f) print(" index_{}[key].push_back(cell);".format(index), file=f) print(" } while (0);", file=f) @@ -266,15 +281,20 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print(" void run(std::function on_accept_f) {{".format(prefix), file=f) + print(" void match(std::function on_accept_f) {{".format(prefix), file=f) print(" on_accept = on_accept_f;", file=f) print(" rollback = 0;", file=f) + for s, t in sorted(state_types.items()): + if t.endswith("*"): + print(" st.{} = nullptr;".format(s), file=f) + else: + print(" st.{} = {}();".format(s, t), file=f) print(" block_0();", file=f) print(" }", file=f) print("", file=f) print("#define reject break", file=f) - print("#define accept do { on_accept(this); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f) + print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f) print("", file=f) for index in range(len(blocks)): @@ -323,7 +343,7 @@ with open("%s_pm.h" % prefix, "w") as f: print("", file=f) for s in sorted(restore_st): t = state_types[s] - print(" {} backup_{} = st.{};".format(t, s, s), file=f) + print(" {} backup_{} = {};".format(t, s, s), file=f) if block["type"] == "code": print("", file=f) @@ -336,24 +356,42 @@ with open("%s_pm.h" % prefix, "w") as f: print("rollback_label: YS_ATTRIBUTE(unused);", file=f) print(" } while (0);", file=f) - if len(restore_st): + if len(restore_st) or len(nonconst_st): print("", file=f) for s in sorted(restore_st): t = state_types[s] - print(" st.{} = backup_{};".format(s, s), file=f) + print(" {} = backup_{};".format(s, s), file=f) + for s in sorted(nonconst_st): + if s not in restore_st: + t = state_types[s] + if t.endswith("*"): + print(" {} = nullptr;".format(s), file=f) + else: + print(" {} = {}();".format(s, t), file=f) elif block["type"] == "match": assert len(restore_st) == 0 + if len(block["if"]): + for expr in block["if"]: + print("", file=f) + print(" if (!({})) {{".format(expr), file=f) + print(" {} = nullptr;".format(block["cell"]), file=f) + print(" block_{}();".format(index+1), file=f) + print(" return;", file=f) + print(" }", file=f) + print("", file=f) print(" index_{}_key_type key;".format(index), file=f) - for field, filt in enumerate(block["filter"]): - print(" std::get<{}>(key) = {};".format(field, filt[2]), file=f) + for field, entry in enumerate(block["index"]): + print(" std::get<{}>(key) = {};".format(field, entry[2]), file=f) print(" const vector &cells = index_{}[key];".format(index), file=f) print("", file=f) print(" for (int idx = 0; idx < GetSize(cells); idx++) {", file=f) print(" {} = cells[idx];".format(block["cell"]), file=f) + for expr in block["filter"]: + print(" if (!({})) continue;".format(expr), file=f) print(" block_{}();".format(index+1), file=f) print(" if (rollback) {", file=f) print(" if (rollback != {}) {{".format(index+1), file=f) @@ -382,7 +420,7 @@ with open("%s_pm.h" % prefix, "w") as f: print("", file=f) print(" void block_{}() {{".format(len(blocks)), file=f) - print(" on_accept(this);", file=f) + print(" on_accept();", file=f) print(" check_blacklist();", file=f) print(" }", file=f) print("};", file=f) -- cgit v1.2.3 From 55ac03038270f4a70da5e579dd317487e20fe6cf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 13 Jan 2019 17:15:40 +0100 Subject: Fix pmgen "reject" statement Signed-off-by: Clifford Wolf --- passes/pmgen/pmgen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 88d60d298..6486278d4 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -293,7 +293,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print("#define reject break", file=f) + print("#define reject do { check_blacklist(); goto rollback_label; } while(0)", file=f) print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f) print("", file=f) -- cgit v1.2.3 From 5216735210f1b081f84c8ec110acb1cf9c3a0555 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 14 Jan 2019 13:29:27 +0100 Subject: Progress in pmgen, add pmgen README Signed-off-by: Clifford Wolf --- passes/pmgen/README.md | 224 ++++++++++++++++++++++++++++++++++++++++++++++ passes/pmgen/ice40_dsp.cc | 4 +- passes/pmgen/pmgen.py | 46 +++++++--- 3 files changed, 260 insertions(+), 14 deletions(-) create mode 100644 passes/pmgen/README.md (limited to 'passes') diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md new file mode 100644 index 000000000..27e54b43e --- /dev/null +++ b/passes/pmgen/README.md @@ -0,0 +1,224 @@ +Pattern Matcher Generator +========================= + +The program `pmgen.py` reads a `.pmg` (Pattern Matcher Generator) file and +writes a header-only C++ library that implements that pattern matcher. + +The "patterns" in this context are subgraphs in a Yosys RTLIL netlist. + +The algorithm used in the generated pattern matcher is a simple recursive +search with backtracking. It is left to the author of the `.pmg` file to +determine an efficient cell order for the search that allows for maximum +use of indices and early backtracking. + + +API of Generated Matcher +======================== + +When `pmgen.py` reads a `foobar.pmg` file, it writes `foobar_pm.h` containing +a class `foobar_pm`. That class is instanciated with an RTLIL module and a +list of cells from that module: + + foobar_pm pm(module, module->selected_cells()); + +The caller must make sure that none of the cells in the 2nd argument are +deleted for as long as the patter matcher instance is used. + +At any time it is possible to disable cells, preventing them from showing +up in any future matches: + + pm.blacklist(some_cell); + +The `.run(callback_function)` method searches for all matches and calls the +callback function for each found match: + + pm.run([&](){ + log("found matching 'foo' cell: %s\n", log_id(pm.st.foo)); + log(" with 'bar' cell: %s\n", log_id(pm.st.bar)); + }); + +The `.pmg` file declares matcher state variables that are accessible via the +`.st.` members. (The `.st` member is of type `foobar_pm::state_t`.) + +Similarly the `.pmg` file declares user data variables that become members of +`.ud`, a struct of type `foobar_pm::udata_t`. + + +The .pmg File Format +==================== + +The `.pmg` file format is a simple line-based file format. For the most part +lines consist of whitespace-separated tokens. + +Lines in `.pmg` files starting with `//` are comments. + +Declaring state variables +------------------------- + +One or more state variables can be declared using the `state` statement, +followed by a C++ type in angle brackets, followed by a whitespace separated +list of variable names. For example: + + state flag1 flag2 happy big + state sigA sigB sigY + +State variables are automatically managed by the generated backtracking algorithm +and saved and restored as needed. + +They are atomatically initialzed to the default constructed value of their type +when `.run(callback_function)` is called. + +Declaring udata variables +------------------------- + +Udata (user-data) variables can be used for example to configure the matcher or +the callback function used to perform actions on found matches. + +There is no automatic management of udata variables. For this reason it is +recommended that the user-supplied matcher code treats them as read-only +variables. + +They are declared like state variables, just using the `udata` statement: + + udata min_data_width max_data_width + udata data_port_name + +They are atomatically initialzed to the default constructed value of their type +when ther pattern matcher object is constructed. + +Embedded C++ code +----------------- + +Many statements in a `.pmg` file contain C++ code. However, there are some +slight additions to regular C++/Yosys/RTLIL code that make it a bit easier to +write matchers: + +- Identifiers starting with a dollar sign or backslash are automatically + converted to special IdString variables that are initialized when the + matcher object is constructed. + +- The `port(, )` function is a handy alias for + `sigmap(->getPort())`. + +- Similarly `param(, )` looks up a parameter on a cell. + +- The function `nusers()` returns the number of different cells + connected to any of the given signal bits, plus one if any of the signal + bits is also a primary input or primary output. + +- In `code..endcode` blocks there exist `accept`, `reject`, and `branch` + statements. + +- In `index` statements there is a special `===` operator for the index + lookup. + +Matching cells +-------------- + +Cells are matched using `match..endmatch` blocks. For example: + + match mul + if ff + select mul->type == $mul + select nusers(port(mul, \Y) == 2 + index port(mul, \Y) === port(ff, \D) + filter some_weird_function(mul) < other_weird_function(ff) + optional + endmatch + +A `match` block starts with `match ` and implicitly generates +a state variable `` of type `RTLIL::Cell*`. + +All statements in the match block are optional. (An empty match block +would simply match each and every cell in the module.) + +The `if ` statement makes the match block conditional. If +`` evaluates to `false` then the match block will be ignored +and the corresponding state variable is set to `nullptr`. In our example +we only try to match the `mul` cell if the `ff` state variable points +to a cell. (Presumably `ff` is provided by a prior `match` block.) + +The `select` lines are evaluated once for each cell when the matcher is +initialized. A `match` block will only consider cells for which all `select` +expressions evaluated to `true`. Note that the state variable corresponding to +the match (in the example `mul`) is the only state variable that may be used +`select` lines. + +Index lines are using the `index expr1 === expr2` syntax. `expr1` is +evaluated during matcher initialization and the same restrictions apply as for +`select` expressions. `expr2` is evaluated when the match is calulated. It is a +function of any state variables assigned to by previous blocks. Both expression +are converted to the given type and compared for equality. Only cells for which +all `index` statements in the block pass are considered by the match. + +Note that `select` and `index` are fast operations. Thus `select` and `index` +should be used whenever possible to create efficient matchers. + +Finally, `filter ` narrows down the remaining list of cells. For +performance reasons `filter` statements should only be used for things that +can't be done using `select` and `index`. + +The `optional` statement marks optional matches. I.e. the matcher will also +explore the case where `mul` is set to `nullptr`. Without the `optional` +statement a match may only be assigned nullptr when one of the `if` expressions +evaluates to `false`. + +Additional code +--------------- + +Interleaved with `match..endmatch` blocks there may be `code..endcode` blocks. +Such a block starts with the keyword `code` followed by a list of state variables +that the block may modify. For example: + + code addAB sigS + if (addA) { + addAB = addA; + sigS = port(addA, \B); + } + if (addB) { + addAB = addB; + sigS = port(addB, \A); + } + endcode + +The special keyword `reject` can be used to reject the current state and +backtrack. For example: + + code + if (ffA && ffB) { + if (port(ffA, \CLK) != port(ffB, \CLK)) + reject; + if (param(ffA, \CLK_POLARITY) != param(ffB, \CLK_POLARITY)) + reject; + } + endcode + +Similarly, the special keyword `accept` can be used to accept the current +state. (`accept` will not backtrack. This means it continues with the current +branch and may accept a larger match later.) + +The special keyword `branch` can be used to explore different cases. Note that +each code block has an implicit `branch` at the end. So most use-cases of the +`branch` keyword need to end the block with `reject` to avoid the implicit +branch at the end. For example: + + state mode + + code mode + for (mode = 0; mode < 8; mode++) + branch; + reject; + endcode + +But in some cases it is more natural to utilize the implicit branch statement: + + state portAB + + code portAB + portAB = \A; + branch; + portAB = \B; + endcode + +There is an implicit `code..endcode` block at the end of each `.pgm` file +that just accepts everything that gets all the way there. diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index a8f63ebfe..78b5bad33 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -52,8 +52,8 @@ struct Ice40DspPass : public Pass { for (auto module : design->selected_modules()) { - ice40_dsp_pm pm(module, module->cells()); - pm.match([&]() + ice40_dsp_pm pm(module, module->selected_cells()); + pm.run([&]() { log("\n"); log("ffA: %s\n", log_id(pm.st.ffA, "--")); diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 6486278d4..885f6db1c 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -9,6 +9,7 @@ pp = pprint.PrettyPrinter(indent=4) prefix = sys.argv[1] state_types = dict() +udata_types = dict() blocks = list() ids = dict() @@ -92,6 +93,16 @@ with open("%s.pmg" % prefix, "r") as f: state_types[s] = type_str continue + if cmd == "udata": + m = re.match(r"^udata\s+<(.*?)>\s+(([A-Za-z_][A-Za-z_0-9]*\s+)*[A-Za-z_][A-Za-z_0-9]*)\s*$", line) + assert m + type_str = m.group(1) + udatas_str = m.group(2) + for s in re.split(r"\s+", udatas_str): + assert s not in udata_types + udata_types[s] = type_str + continue + if cmd == "match": block = dict() block["type"] = "match" @@ -196,12 +207,17 @@ with open("%s_pm.h" % prefix, "w") as f: print("", file=f) print(" struct state_t {", file=f) - for s, t in sorted(state_types.items()): print(" {} {};".format(t, s), file=f) print(" } st;", file=f) print("", file=f) + print(" struct udata_t {", file=f) + for s, t in sorted(udata_types.items()): + print(" {} {};".format(t, s), file=f) + print(" } ud;", file=f) + print("", file=f) + for v, n in sorted(ids.items()): if n[0] == "\\": print(" IdString {}{{\"\\{}\"}};".format(v, n), file=f) @@ -258,7 +274,12 @@ with open("%s_pm.h" % prefix, "w") as f: print(" {}_pm(Module *module, const vector &cells) :".format(prefix), file=f) print(" module(module), sigmap(module) {", file=f) - print(" for (auto cell : cells) {", file=f) + for s, t in sorted(udata_types.items()): + if t.endswith("*"): + print(" ud.{} = nullptr;".format(s), file=f) + else: + print(" ud.{} = {}();".format(s, t), file=f) + print(" for (auto cell : module->cells()) {", file=f) print(" for (auto &conn : cell->connections())", file=f) print(" add_siguser(conn.second, cell);", file=f) print(" }", file=f) @@ -281,7 +302,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print(" void match(std::function on_accept_f) {{".format(prefix), file=f) + print(" void run(std::function on_accept_f) {{".format(prefix), file=f) print(" on_accept = on_accept_f;", file=f) print(" rollback = 0;", file=f) for s, t in sorted(state_types.items()): @@ -293,10 +314,6 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print("#define reject do { check_blacklist(); goto rollback_label; } while(0)", file=f) - print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f) - print("", file=f) - for index in range(len(blocks)): block = blocks[index] @@ -348,13 +365,22 @@ with open("%s_pm.h" % prefix, "w") as f: if block["type"] == "code": print("", file=f) print(" do {", file=f) + print("#define reject do { check_blacklist(); goto rollback_label; } while(0)", file=f) + print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f) + print("#define branch do {{ block_{}(); }} while(0)".format(index+1), file=f) + for line in block["code"]: print(" " + line, file=f) print("", file=f) print(" block_{}();".format(index+1), file=f) - print("rollback_label: YS_ATTRIBUTE(unused);", file=f) + print("#undef reject", file=f) + print("#undef accept", file=f) + print("#undef branch", file=f) print(" } while (0);", file=f) + print("", file=f) + print("rollback_label:", file=f) + print(" YS_ATTRIBUTE(unused);", file=f) if len(restore_st) or len(nonconst_st): print("", file=f) @@ -415,10 +441,6 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print("#undef reject", file=f) - print("#undef accept", file=f) - print("", file=f) - print(" void block_{}() {{".format(len(blocks)), file=f) print(" on_accept();", file=f) print(" check_blacklist();", file=f) -- cgit v1.2.3 From 8ddec5d882c6834cb6b3415e05a2a88d416cabff Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 14 Jan 2019 13:42:42 +0100 Subject: Progress in pmgen Signed-off-by: Clifford Wolf --- passes/pmgen/pmgen.py | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 885f6db1c..a59cf5a81 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -203,6 +203,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" dict> index_{};".format(index, index), file=f) print(" dict> sigusers;", file=f) print(" pool blacklist_cells;", file=f) + print(" bool blacklist_dirty;", file=f) print(" int rollback;", file=f) print("", file=f) @@ -236,12 +237,17 @@ with open("%s_pm.h" % prefix, "w") as f: print("", file=f) print(" void blacklist(Cell *cell) {", file=f) - print(" if (cell != nullptr)", file=f) - print(" blacklist_cells.insert(cell);", file=f) + print(" if (cell != nullptr) {", file=f) + print(" if (blacklist_cells.insert(cell).second)", file=f) + print(" blacklist_dirty = true;", file=f) + print(" }", file=f) print(" }", file=f) print("", file=f) print(" void check_blacklist() {", file=f) + print(" if (!blacklist_dirty)", file=f) + print(" return;", file=f) + print(" blacklist_dirty = false;", file=f) for index in range(len(blocks)): block = blocks[index] if block["type"] == "match": @@ -305,6 +311,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" void run(std::function on_accept_f) {{".format(prefix), file=f) print(" on_accept = on_accept_f;", file=f) print(" rollback = 0;", file=f) + print(" blacklist_dirty = false;", file=f) for s, t in sorted(state_types.items()): if t.endswith("*"): print(" st.{} = nullptr;".format(s), file=f) @@ -367,7 +374,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" do {", file=f) print("#define reject do { check_blacklist(); goto rollback_label; } while(0)", file=f) print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f) - print("#define branch do {{ block_{}(); }} while(0)".format(index+1), file=f) + print("#define branch do {{ block_{}(); if (rollback) goto rollback_label; }} while(0)".format(index+1), file=f) for line in block["code"]: print(" " + line, file=f) @@ -416,6 +423,7 @@ with open("%s_pm.h" % prefix, "w") as f: print("", file=f) print(" for (int idx = 0; idx < GetSize(cells); idx++) {", file=f) print(" {} = cells[idx];".format(block["cell"]), file=f) + print(" if (blacklist_cells.count({})) continue;".format(block["cell"]), file=f) for expr in block["filter"]: print(" if (!({})) continue;".format(expr), file=f) print(" block_{}();".format(index+1), file=f) -- cgit v1.2.3 From 8524a479b15ff89db48872c57103c60be77142af Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 4 Dec 2018 14:17:47 +0000 Subject: abc: Preserve naming through ABC using 'dress' command Signed-off-by: David Shah --- passes/techmap/abc.cc | 80 ++++++++++++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 29 deletions(-) (limited to 'passes') diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index d2d15a4a9..d3bdd555b 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -329,6 +329,18 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) std::string remap_name(RTLIL::IdString abc_name) { + std::string abc_sname = abc_name.substr(1); + if (abc_sname.substr(0, 5) == "ys__n") { + int sid = std::stoi(abc_sname.substr(5)); + bool inv = abc_sname.back() == 'v'; + for (auto sig : signal_list) { + if (sig.id == sid) { + std::stringstream sstr; + sstr << "$abc$" << map_autoidx << "$" << log_signal(sig.bit) << (inv ? "_inv" : ""); + return sstr.str(); + } + } + } std::stringstream sstr; sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1); return sstr.str(); @@ -353,12 +365,12 @@ void dump_loop_graph(FILE *f, int &nr, std::map> &edges, std: } for (auto n : nodes) - fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit), + fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit), n, in_counts[n], workpool.count(n) ? ", shape=box" : ""); for (auto &e : edges) for (auto n : e.second) - fprintf(f, " n%d -> n%d;\n", e.first, n); + fprintf(f, " ys__n%d -> ys__n%d;\n", e.first, n); fprintf(f, "}\n"); } @@ -624,7 +636,7 @@ struct abc_output_filter void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, - const std::vector &cells, bool show_tempdir, bool sop_mode) + const std::vector &cells, bool show_tempdir, bool sop_mode, bool abc_dress) { module = current_module; map_autoidx = autoidx++; @@ -728,7 +740,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3); - + if (abc_dress) + abc_script += "; dress"; abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str()); abc_script = add_echos_to_abc_cmd(abc_script); @@ -784,7 +797,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin for (auto &si : signal_list) { if (!si.is_port || si.type != G(NONE)) continue; - fprintf(f, " n%d", si.id); + fprintf(f, " ys__n%d", si.id); pi_map[count_input++] = log_signal(si.bit); } if (count_input == 0) @@ -796,17 +809,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin for (auto &si : signal_list) { if (!si.is_port || si.type == G(NONE)) continue; - fprintf(f, " n%d", si.id); + fprintf(f, " ys__n%d", si.id); po_map[count_output++] = log_signal(si.bit); } fprintf(f, "\n"); for (auto &si : signal_list) - fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit)); + fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit)); for (auto &si : signal_list) { if (si.bit.wire == NULL) { - fprintf(f, ".names n%d\n", si.id); + fprintf(f, ".names ys__n%d\n", si.id); if (si.bit == RTLIL::State::S1) fprintf(f, "1\n"); } @@ -815,68 +828,68 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin int count_gates = 0; for (auto &si : signal_list) { if (si.type == G(BUF)) { - fprintf(f, ".names n%d n%d\n", si.in1, si.id); + fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id); fprintf(f, "1 1\n"); } else if (si.type == G(NOT)) { - fprintf(f, ".names n%d n%d\n", si.in1, si.id); + fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id); fprintf(f, "0 1\n"); } else if (si.type == G(AND)) { - fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id); fprintf(f, "11 1\n"); } else if (si.type == G(NAND)) { - fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id); fprintf(f, "0- 1\n"); fprintf(f, "-0 1\n"); } else if (si.type == G(OR)) { - fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id); fprintf(f, "-1 1\n"); fprintf(f, "1- 1\n"); } else if (si.type == G(NOR)) { - fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id); fprintf(f, "00 1\n"); } else if (si.type == G(XOR)) { - fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id); fprintf(f, "01 1\n"); fprintf(f, "10 1\n"); } else if (si.type == G(XNOR)) { - fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id); fprintf(f, "00 1\n"); fprintf(f, "11 1\n"); } else if (si.type == G(ANDNOT)) { - fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id); fprintf(f, "10 1\n"); } else if (si.type == G(ORNOT)) { - fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id); fprintf(f, "1- 1\n"); fprintf(f, "-0 1\n"); } else if (si.type == G(MUX)) { - fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id); fprintf(f, "1-0 1\n"); fprintf(f, "-11 1\n"); } else if (si.type == G(AOI3)) { - fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id); fprintf(f, "-00 1\n"); fprintf(f, "0-0 1\n"); } else if (si.type == G(OAI3)) { - fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id); fprintf(f, "00- 1\n"); fprintf(f, "--0 1\n"); } else if (si.type == G(AOI4)) { - fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id); fprintf(f, "-0-0 1\n"); fprintf(f, "-00- 1\n"); fprintf(f, "0--0 1\n"); fprintf(f, "0-0- 1\n"); } else if (si.type == G(OAI4)) { - fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id); + fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id); fprintf(f, "00-- 1\n"); fprintf(f, "--00 1\n"); } else if (si.type == G(FF)) { if (si.init == State::S0 || si.init == State::S1) { - fprintf(f, ".latch n%d n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0); + fprintf(f, ".latch ys__n%d ys__n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0); recover_init = true; } else - fprintf(f, ".latch n%d n%d 2\n", si.in1, si.id); + fprintf(f, ".latch ys__n%d ys__n%d 2\n", si.in1, si.id); } else if (si.type != G(NONE)) log_abort(); if (si.type != G(NONE)) @@ -889,7 +902,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", count_gates, GetSize(signal_list), count_input, count_output); log_push(); - if (count_output > 0) { log_header(design, "Executing ABC.\n"); @@ -1213,7 +1225,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin for (auto &si : signal_list) if (si.is_port) { char buffer[100]; - snprintf(buffer, 100, "\\n%d", si.id); + snprintf(buffer, 100, "\\ys__n%d", si.id); RTLIL::SigSig conn; if (si.type != G(NONE)) { conn.first = si.bit; @@ -1407,6 +1419,11 @@ struct AbcPass : public Pass { log(" this attribute is a unique integer for each ABC process started. This\n"); log(" is useful for debugging the partitioning of clock domains.\n"); log("\n"); + log(" -dress\n"); + log(" run the 'dress' command after all other ABC commands. This aims to\n"); + log(" preserve naming by an equivalence check between the original and post-ABC\n"); + log(" netlists (experimental).\n"); + log("\n"); log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n"); log("loaded into ABC before the ABC script is executed.\n"); log("\n"); @@ -1441,6 +1458,7 @@ struct AbcPass : public Pass { std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; + bool abc_dress = false; vector lut_costs; markgroups = false; @@ -1555,6 +1573,10 @@ struct AbcPass : public Pass { map_mux16 = true; continue; } + if (arg == "-dress") { + abc_dress = true; + continue; + } if (arg == "-g" && argidx+1 < args.size()) { for (auto g : split_tokens(args[++argidx], ",")) { vector gate_list; @@ -1704,7 +1726,7 @@ struct AbcPass : public Pass { if (!dff_mode || !clk_str.empty()) { abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, - delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode); + delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress); continue; } @@ -1849,7 +1871,7 @@ struct AbcPass : public Pass { en_polarity = std::get<2>(it.first); en_sig = assign_map(std::get<3>(it.first)); abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", - keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode); + keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress); assign_map.set(mod); } } -- cgit v1.2.3 From 58c22dae31cd65010bd525ad7b4241709e773314 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 16 Dec 2018 17:44:37 +0000 Subject: abc: Improved recovered netnames, also preserve src on nets with dress Signed-off-by: David Shah --- passes/techmap/abc.cc | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index d3bdd555b..21b70f492 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -327,16 +327,22 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) } } -std::string remap_name(RTLIL::IdString abc_name) +std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr) { std::string abc_sname = abc_name.substr(1); if (abc_sname.substr(0, 5) == "ys__n") { int sid = std::stoi(abc_sname.substr(5)); bool inv = abc_sname.back() == 'v'; for (auto sig : signal_list) { - if (sig.id == sid) { + if (sig.id == sid && sig.bit.wire != nullptr) { std::stringstream sstr; - sstr << "$abc$" << map_autoidx << "$" << log_signal(sig.bit) << (inv ? "_inv" : ""); + sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1); + if (sig.bit.wire->width != 1) + sstr << "[" << sig.bit.offset << "]"; + if (inv) + sstr << "_inv"; + if (orig_wire != nullptr) + *orig_wire = sig.bit.wire; return sstr.str(); } } @@ -1000,7 +1006,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin log_error("ABC output file does not contain a module `netlist'.\n"); for (auto &it : mapped_mod->wires_) { RTLIL::Wire *w = it.second; - RTLIL::Wire *wire = module->addWire(remap_name(w->name)); + RTLIL::Wire *orig_wire = nullptr; + RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire)); + if (orig_wire != nullptr && orig_wire->attributes.count("\\src")) + wire->attributes["\\src"] = orig_wire->attributes["\\src"]; if (markgroups) wire->attributes["\\abcgroup"] = map_autoidx; design->select(module, wire); } -- cgit v1.2.3 From 5c504c5ae676488f7e0b53f827f189fa7cacb2c8 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Fri, 15 Feb 2019 11:31:37 -0800 Subject: Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code). --- passes/hierarchy/hierarchy.cc | 50 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 0e28dbca2..332ebdfbb 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -140,6 +140,23 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, } } +// Return the "basic" type for an array item. +std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) { + std::string basicType = celltype; + if (celltype.substr(0, 7) == "$array:") { + int pos_idx = celltype.find_first_of(':'); + int pos_num = celltype.find_first_of(':', pos_idx + 1); + int pos_type = celltype.find_first_of(':', pos_num + 1); + basicType = celltype.substr(pos_type + 1); + if (pos != nullptr) { + pos[0] = pos_idx; + pos[1] = pos_num; + pos[2] = pos_type; + } + } + return basicType; +} + bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, bool flag_simcheck, std::vector &libdirs) { bool did_something = false; @@ -178,9 +195,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check std::vector connections_to_add_signal; if (cell->type.substr(0, 7) == "$array:") { - int pos_idx = cell->type.str().find_first_of(':'); - int pos_num = cell->type.str().find_first_of(':', pos_idx + 1); - int pos_type = cell->type.str().find_first_of(':', pos_num + 1); + int pos[3]; + basic_cell_type(cell->type.str(), pos); + int pos_idx = pos[0]; + int pos_num = pos[1]; + int pos_type = pos[2]; int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str()); int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str()); array_cells[cell] = std::pair(idx, num); @@ -439,10 +458,7 @@ void hierarchy_worker(RTLIL::Design *design, std::setcells()) { std::string celltype = cell->type.str(); if (celltype.substr(0, 7) == "$array:") { - int pos_idx = celltype.find_first_of(':'); - int pos_num = celltype.find_first_of(':', pos_idx + 1); - int pos_type = celltype.find_first_of(':', pos_num + 1); - celltype = celltype.substr(pos_type + 1); + celltype = basic_cell_type(celltype); } if (design->module(celltype)) hierarchy_worker(design, used, design->module(celltype), indent+4); @@ -502,9 +518,23 @@ int find_top_mod_score(Design *design, Module *module, dict &db) if (db.count(module) == 0) { int score = 0; db[module] = 0; - for (auto cell : module->cells()) - if (design->module(cell->type)) - score = max(score, find_top_mod_score(design, design->module(cell->type), db) + 1); + for (auto cell : module->cells()) { + std::string celltype = cell->type.str(); + // Is this an array instance + if (celltype.substr(0, 7) == "$array:") { + celltype = basic_cell_type(celltype); + // Is this cell is a module instance? + if (celltype[0] != '$') { + auto instModule = design->module(celltype); + // If there is no instance for this, issue a warning. + if (instModule == NULL) { + log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str()); + } + if (instModule != NULL) + score = max(score, find_top_mod_score(design, instModule, db) + 1); + } + } + } db[module] = score; } return db.at(module); -- cgit v1.2.3 From 5a853ed46cd3a41df9da4c8206f9416748788487 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 17 Feb 2019 15:35:48 +0100 Subject: Add actual DSP inference to ice40_dsp pass Signed-off-by: Clifford Wolf --- passes/pmgen/ice40_dsp.cc | 197 ++++++++++++++++++++++++++++++++++++++++----- passes/pmgen/ice40_dsp.pmg | 18 ++++- passes/pmgen/pmgen.py | 23 +++++- 3 files changed, 214 insertions(+), 24 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 78b5bad33..7463d598f 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -24,6 +24,180 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +void create_ice40_dsp(ice40_dsp_pm &pm) +{ +#if 0 + log("\n"); + log("ffA: %s\n", log_id(pm.st.ffA, "--")); + log("ffB: %s\n", log_id(pm.st.ffB, "--")); + log("mul: %s\n", log_id(pm.st.mul, "--")); + log("ffY: %s\n", log_id(pm.st.ffY, "--")); + log("addAB: %s\n", log_id(pm.st.addAB, "--")); + log("muxAB: %s\n", log_id(pm.st.muxAB, "--")); + log("ffS: %s\n", log_id(pm.st.ffS, "--")); +#endif + + log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(pm.st.mul)); + + if (GetSize(pm.st.sigA) > 16) { + log(" input A (%s) is too large (%d > 16).\n", log_signal(pm.st.sigA), GetSize(pm.st.sigA)); + return; + } + + if (GetSize(pm.st.sigB) > 16) { + log(" input B (%s) is too large (%d > 16).\n", log_signal(pm.st.sigB), GetSize(pm.st.sigB)); + return; + } + + if (GetSize(pm.st.sigS) > 32) { + log(" accumulator (%s) is too large (%d > 32).\n", log_signal(pm.st.sigS), GetSize(pm.st.sigS)); + return; + } + + if (GetSize(pm.st.sigY) > 32) { + log(" output (%s) is too large (%d > 32).\n", log_signal(pm.st.sigY), GetSize(pm.st.sigY)); + return; + } + + log(" replacing $mul with SB_MAC16 cell.\n"); + + bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool(); + + Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16"); + pm.module->swap_names(cell, pm.st.mul); + + // SB_MAC16 Input Interface + + SigSpec A = pm.st.sigA; + A.extend_u0(16, mul_signed); + + SigSpec B = pm.st.sigB; + B.extend_u0(16, mul_signed); + + SigSpec CD; + if (pm.st.muxA) + CD = pm.st.muxA->getPort("\\B"); + if (pm.st.muxB) + CD = pm.st.muxB->getPort("\\A"); + CD.extend_u0(32, mul_signed); + + cell->setPort("\\A", A); + cell->setPort("\\B", B); + cell->setPort("\\C", CD.extract(0, 16)); + cell->setPort("\\D", CD.extract(16, 16)); + + cell->setParam("\\A_REG", pm.st.ffA ? State::S0 : State::S1); + cell->setParam("\\B_REG", pm.st.ffB ? State::S0 : State::S1); + + cell->setPort("\\AHOLD", State::S0); + cell->setPort("\\BHOLD", State::S0); + cell->setPort("\\CHOLD", State::S0); + cell->setPort("\\DHOLD", State::S0); + + cell->setPort("\\IRSTTOP", State::S0); + cell->setPort("\\IRSTBOT", State::S0); + + if (pm.st.clock_vld) + { + cell->setPort("\\CLK", pm.st.clock); + cell->setPort("\\CE", State::S1); + cell->setParam("\\NEG_TRIGGER", pm.st.clock_pol ? State::S0 : State::S1); + + log(" clock: %s (%s)", log_signal(pm.st.clock), pm.st.clock_pol ? "posedge" : "negedge"); + + if (pm.st.ffA) + log(" ffA:%s", log_id(pm.st.ffA)); + + if (pm.st.ffB) + log(" ffB:%s", log_id(pm.st.ffB)); + + if (pm.st.ffY) + log(" ffY:%s", log_id(pm.st.ffY)); + + if (pm.st.ffS) + log(" ffS:%s", log_id(pm.st.ffS)); + + log("\n"); + } + else + { + cell->setPort("\\CLK", State::S0); + cell->setPort("\\CE", State::S0); + cell->setParam("\\NEG_TRIGGER", State::S0); + } + + // SB_MAC16 Cascade Interface + + cell->setPort("\\SIGNEXTIN", State::Sx); + cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID)); + + cell->setPort("\\CI", State::Sx); + cell->setPort("\\CO", pm.module->addWire(NEW_ID)); + + cell->setPort("\\ACCUMCI", State::Sx); + cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID)); + + // SB_MAC16 Output Interface + + SigSpec O = pm.st.ffS ? pm.st.sigS : pm.st.sigY; + if (GetSize(O) < 32) + O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); + + cell->setPort("\\O", O); + + if (pm.st.addAB) { + log(" accumulator %s (%s)\n", log_id(pm.st.addAB), log_id(pm.st.addAB->type)); + cell->setPort("\\ADDSUBTOP", pm.st.addAB->type == "$add" ? State::S0 : State::S1); + cell->setPort("\\ADDSUBBOT", pm.st.addAB->type == "$add" ? State::S0 : State::S1); + } else { + cell->setPort("\\ADDSUBTOP", State::S0); + cell->setPort("\\ADDSUBBOT", State::S0); + } + + cell->setPort("\\ORTSTOP", State::S0); + cell->setPort("\\ORTSBOT", State::S0); + + cell->setPort("\\OHOLDTOP", State::S0); + cell->setPort("\\OHOLDBOT", State::S0); + + SigSpec acc_reset = State::S0; + if (pm.st.muxA) + acc_reset = pm.st.muxA->getPort("\\S"); + if (pm.st.muxB) + acc_reset = pm.module->Not(NEW_ID, pm.st.muxB->getPort("\\S")); + + cell->setPort("\\OLOADTOP", acc_reset); + cell->setPort("\\OLOADBOT", acc_reset); + + // SB_MAC16 Remaining Parameters + + cell->setParam("\\C_REG", State::S0); + cell->setParam("\\D_REG", State::S0); + + cell->setParam("\\TOP_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0); + cell->setParam("\\BOT_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0); + cell->setParam("\\PIPELINE_16X16_MULT_REG1", pm.st.ffY ? State::S1 : State::S0); + cell->setParam("\\PIPELINE_16X16_MULT_REG2", State::S0); + + cell->setParam("\\TOPOUTPUT_SELECT", Const(pm.st.ffS ? 1 : 3, 2)); + cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2)); + cell->setParam("\\TOPADDSUB_UPPERINPUT", State::S0); + cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2)); + + cell->setParam("\\BOTOUTPUT_SELECT", Const(pm.st.ffS ? 1 : 3, 2)); + cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2)); + cell->setParam("\\BOTADDSUB_UPPERINPUT", State::S0); + cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2)); + + cell->setParam("\\MODE_8x8", State::S0); + cell->setParam("\\A_SIGNED", mul_signed ? State::S1 : State::S0); + cell->setParam("\\B_SIGNED", mul_signed ? State::S1 : State::S0); + + pm.autoremove(pm.st.mul); + pm.autoremove(pm.st.ffY); + pm.autoremove(pm.st.ffS); +} + struct Ice40DspPass : public Pass { Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { } void help() YS_OVERRIDE @@ -32,7 +206,7 @@ struct Ice40DspPass : public Pass { log("\n"); log(" ice40_dsp [options] [selection]\n"); log("\n"); - log("Map multipliers and iCE40 DSP resources.\n"); + log("Map multipliers and multiply-accumulate blocks to iCE40 DSP resources.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -51,26 +225,7 @@ struct Ice40DspPass : public Pass { extra_args(args, argidx, design); for (auto module : design->selected_modules()) - { - ice40_dsp_pm pm(module, module->selected_cells()); - pm.run([&]() - { - log("\n"); - log("ffA: %s\n", log_id(pm.st.ffA, "--")); - log("ffB: %s\n", log_id(pm.st.ffB, "--")); - log("mul: %s\n", log_id(pm.st.mul, "--")); - log("ffY: %s\n", log_id(pm.st.ffY, "--")); - log("addAB: %s\n", log_id(pm.st.addAB, "--")); - log("muxAB: %s\n", log_id(pm.st.muxAB, "--")); - log("ffS: %s\n", log_id(pm.st.ffS, "--")); - - pm.blacklist(pm.st.mul); - pm.blacklist(pm.st.ffA); - pm.blacklist(pm.st.ffB); - pm.blacklist(pm.st.ffY); - pm.blacklist(pm.st.ffS); - }); - } + ice40_dsp_pm(module, module->selected_cells()).run(create_ice40_dsp); } } Ice40DspPass; diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 1370cb66a..58e1ce0e0 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -63,7 +63,7 @@ code sigY clock clock_pol clock_vld sigY = port(mul, \Y); if (ffY) { - sigY = port(ffY, \D); + sigY = port(ffY, \Q); SigBit c = port(ffY, \CLK).as_bit(); bool cp = param(ffY, \CLK_POLARITY).as_bool(); @@ -77,7 +77,7 @@ code sigY clock clock_pol clock_vld endcode match addA - select addA->type.in($add, $sub) + select addA->type.in($add) select nusers(port(addA, \A)) == 2 index port(addA, \A) === sigY optional @@ -134,3 +134,17 @@ match ffS index port(ffS, \D) === port(muxAB, \Y) index port(ffS, \Q) === sigS endmatch + +code clock clock_pol clock_vld + if (ffS) { + SigBit c = port(ffS, \CLK).as_bit(); + bool cp = param(ffS, \CLK_POLARITY).as_bool(); + + if (clock_vld && (c != clock || cp != clock_pol)) + reject; + + clock = c; + clock_pol = cp; + clock_vld = true; + } +endcode diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index a59cf5a81..e688a4567 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -203,6 +203,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" dict> index_{};".format(index, index), file=f) print(" dict> sigusers;", file=f) print(" pool blacklist_cells;", file=f) + print(" pool autoremove_cells;", file=f) print(" bool blacklist_dirty;", file=f) print(" int rollback;", file=f) print("", file=f) @@ -244,6 +245,15 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) + print(" void autoremove(Cell *cell) {", file=f) + print(" if (cell != nullptr) {", file=f) + print(" if (blacklist_cells.insert(cell).second)", file=f) + print(" blacklist_dirty = true;", file=f) + print(" autoremove_cells.insert(cell);", file=f) + print(" }", file=f) + print(" }", file=f) + print("", file=f) + print(" void check_blacklist() {", file=f) print(" if (!blacklist_dirty)", file=f) print(" return;", file=f) @@ -308,7 +318,13 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print(" void run(std::function on_accept_f) {{".format(prefix), file=f) + print(" ~{}_pm() {{".format(prefix), file=f) + print(" for (auto cell : autoremove_cells)", file=f) + print(" module->remove(cell);", file=f) + print(" }", file=f) + print("", file=f) + + print(" void run(std::function on_accept_f) {", file=f) print(" on_accept = on_accept_f;", file=f) print(" rollback = 0;", file=f) print(" blacklist_dirty = false;", file=f) @@ -321,6 +337,11 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) + print(" void run(std::function on_accept_f) {{".format(prefix), file=f) + print(" run([&](){on_accept_f(*this);});", file=f) + print(" }", file=f) + print("", file=f) + for index in range(len(blocks)): block = blocks[index] -- cgit v1.2.3 From 5c4a72c43ef61420b4b099d87949b0fdba0f4b55 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 19 Feb 2019 14:35:15 -0800 Subject: Fix normal (non-array) hierarchy -auto-top. Add simple test. --- passes/hierarchy/hierarchy.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 332ebdfbb..f112e969e 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -523,15 +523,15 @@ int find_top_mod_score(Design *design, Module *module, dict &db) // Is this an array instance if (celltype.substr(0, 7) == "$array:") { celltype = basic_cell_type(celltype); - // Is this cell is a module instance? - if (celltype[0] != '$') { - auto instModule = design->module(celltype); - // If there is no instance for this, issue a warning. - if (instModule == NULL) { - log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str()); - } - if (instModule != NULL) - score = max(score, find_top_mod_score(design, instModule, db) + 1); + } + // Is this cell a module instance? + if (celltype[0] != '$') { + auto instModule = design->module(celltype); + // If there is no instance for this, issue a warning. + if (instModule == NULL) { + log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str()); + } else { + score = max(score, find_top_mod_score(design, instModule, db) + 1); } } } -- cgit v1.2.3 From dca65d83a0037539464d303ea8751a3e06a92e03 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 20 Feb 2019 11:18:19 +0100 Subject: Detect and reject cases that do not map well to iCE40 DSPs (yet) Signed-off-by: Clifford Wolf --- passes/pmgen/ice40_dsp.cc | 9 +++++++-- passes/pmgen/ice40_dsp.pmg | 10 ++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 7463d598f..8c50a9393 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -59,10 +59,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm) return; } - log(" replacing $mul with SB_MAC16 cell.\n"); - bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool(); + if (mul_signed) { + log(" inference of signed iCE40 DSP arithmetic is currently not supported.\n"); + return; + } + + log(" replacing $mul with SB_MAC16 cell.\n"); + Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16"); pm.module->swap_names(cell, pm.st.mul); diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 58e1ce0e0..96c62e313 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -100,6 +100,16 @@ code addAB sigS addAB = addB; sigS = port(addB, \A); } + if (addAB) { + int natural_mul_width = GetSize(sigA) + GetSize(sigB); + int actual_mul_width = GetSize(sigY); + int actual_acc_width = GetSize(sigS); + + if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) + reject; + if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool())) + reject; + } endcode match muxA -- cgit v1.2.3 From 246391200e3e0d47ee571d4d77dd0744dba0e164 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 20 Feb 2019 16:36:42 +0100 Subject: Add FF support to wreduce Signed-off-by: Clifford Wolf --- passes/opt/wreduce.cc | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 8063b86a6..3aa916ec2 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -38,7 +38,8 @@ struct WreduceConfig "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", "$add", "$sub", "$mul", // "$div", "$mod", "$pow", - "$mux", "$pmux" + "$mux", "$pmux", + "$dff", "$adff" }); } }; @@ -134,6 +135,71 @@ struct WreduceWorker module->connect(sig_y.extract(n_kept, n_removed), sig_removed); } + void run_cell_dff(Cell *cell) + { + // Reduce size of FF if inputs are just sign/zero extended or output bit is not used + + SigSpec sig_d = mi.sigmap(cell->getPort("\\D")); + SigSpec sig_q = mi.sigmap(cell->getPort("\\Q")); + + int width_before = GetSize(sig_q); + + if (width_before == 0) + return; + + bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0; + bool sign_ext = !zero_ext; + + for (int i = GetSize(sig_q)-1; i >= 0; i--) + { + if (zero_ext && sig_d[i] == State::S0) { + module->connect(sig_q[i], State::S0); + sig_d.remove(i); + sig_q.remove(i); + continue; + } + + if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1]) { + module->connect(sig_q[i], sig_q[i-1]); + sig_d.remove(i); + sig_q.remove(i); + continue; + } + + auto info = mi.query(sig_q[i]); + if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) { + sig_d.remove(i); + sig_q.remove(i); + zero_ext = false; + sign_ext = false; + continue; + } + + break; + } + + if (width_before == GetSize(sig_q)) + return; + + if (GetSize(sig_q) == 0) { + log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + return; + } + + log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before, + log_id(module), log_id(cell), log_id(cell->type)); + + for (auto bit : sig_d) + work_queue_bits.insert(bit); + + for (auto bit : sig_q) + work_queue_bits.insert(bit); + + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); + cell->fixup_parameters(); + } + void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something) { port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); @@ -176,6 +242,9 @@ struct WreduceWorker if (cell->type.in("$mux", "$pmux")) return run_cell_mux(cell); + if (cell->type.in("$dff", "$adff")) + return run_cell_dff(cell); + SigSpec sig = mi.sigmap(cell->getPort("\\Y")); if (sig.has_const()) -- cgit v1.2.3 From 218e9051bbdbbd00620a21e6918e6a4b9bc07867 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 20 Feb 2019 16:42:27 +0100 Subject: Add "synth_ice40 -dsp" Signed-off-by: Clifford Wolf --- passes/pmgen/ice40_dsp.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 8c50a9393..3e342453d 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -159,8 +159,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setPort("\\ADDSUBBOT", State::S0); } - cell->setPort("\\ORTSTOP", State::S0); - cell->setPort("\\ORTSBOT", State::S0); + cell->setPort("\\ORSTTOP", State::S0); + cell->setPort("\\ORSTBOT", State::S0); cell->setPort("\\OHOLDTOP", State::S0); cell->setPort("\\OHOLDBOT", State::S0); @@ -181,8 +181,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setParam("\\TOP_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0); cell->setParam("\\BOT_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0); - cell->setParam("\\PIPELINE_16X16_MULT_REG1", pm.st.ffY ? State::S1 : State::S0); - cell->setParam("\\PIPELINE_16X16_MULT_REG2", State::S0); + cell->setParam("\\PIPELINE_16x16_MULT_REG1", pm.st.ffY ? State::S1 : State::S0); + cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0); cell->setParam("\\TOPOUTPUT_SELECT", Const(pm.st.ffS ? 1 : 3, 2)); cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2)); -- cgit v1.2.3 From 2fe1c830eb8aea783c75529b42cab04208cea690 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Feb 2019 13:28:46 +0100 Subject: Bugfix in ice40_dsp Signed-off-by: Clifford Wolf --- passes/pmgen/ice40_dsp.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 3e342453d..3a054a463 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -91,8 +91,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setPort("\\C", CD.extract(0, 16)); cell->setPort("\\D", CD.extract(16, 16)); - cell->setParam("\\A_REG", pm.st.ffA ? State::S0 : State::S1); - cell->setParam("\\B_REG", pm.st.ffB ? State::S0 : State::S1); + cell->setParam("\\A_REG", pm.st.ffA ? State::S1 : State::S0); + cell->setParam("\\B_REG", pm.st.ffB ? State::S1 : State::S0); cell->setPort("\\AHOLD", State::S0); cell->setPort("\\BHOLD", State::S0); -- cgit v1.2.3 From 2da4c9c8f0a849434f657ac4a56de11d35e1c41e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Feb 2019 13:48:23 +0100 Subject: Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816 Signed-off-by: Clifford Wolf --- passes/opt/opt_rmdff.cc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 5880254c1..e8570f0eb 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -174,8 +174,6 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } else { @@ -186,11 +184,12 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } + + return true; } - else + + if (!hasreset) { IdString new_type; @@ -207,8 +206,10 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetPort("\\S"); cell->unsetPort("\\R"); - return did_something; + return true; } + + return did_something; } bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) -- cgit v1.2.3 From 893194689daee52ea870fef839c237c61e14c6c9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Feb 2019 18:50:02 +0100 Subject: Fix typo in passes/pmgen/README.md Signed-off-by: Clifford Wolf --- passes/pmgen/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 27e54b43e..a1007dc62 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -65,7 +65,7 @@ list of variable names. For example: State variables are automatically managed by the generated backtracking algorithm and saved and restored as needed. -They are atomatically initialzed to the default constructed value of their type +They are automatically initialized to the default constructed value of their type when `.run(callback_function)` is called. Declaring udata variables -- cgit v1.2.3 From 4c82ddf39412fa7f90d71f259d578f98e732c865 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 21 Feb 2019 10:16:38 -0800 Subject: Add -params mode to force undef parameters in selected cells. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- passes/cmds/setundef.cc | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'passes') diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 56ef2d125..aea3165e4 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -143,6 +143,9 @@ struct SetundefPass : public Pass { log(" -init\n"); log(" also create/update init values for flip-flops\n"); log("\n"); + log(" -params\n"); + log(" replace undef in cell parameters\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { @@ -150,6 +153,7 @@ struct SetundefPass : public Pass { bool undriven_mode = false; bool expose_mode = false; bool init_mode = false; + bool params_mode = false; SetundefWorker worker; log_header(design, "Executing SETUNDEF pass (replace undef values with defined constants).\n"); @@ -199,6 +203,10 @@ struct SetundefPass : public Pass { init_mode = true; continue; } + if (args[argidx] == "-params") { + params_mode = true; + continue; + } if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; worker.next_bit_mode = MODE_RANDOM; @@ -228,6 +236,27 @@ struct SetundefPass : public Pass { for (auto module : design->selected_modules()) { + if (params_mode) + { + for (auto *cell : module->cells()) + { + // Only modify selected cells. + if (!design->selected(module, it)) { + continue; + } + + for (auto ¶meter : cell->parameters) + { + for (auto &bit : parameter.second.bits) { + if (bit > RTLIL::State::S1) + { + bit = worker.next_bit(); + } + } + } + } + } + if (undriven_mode) { if (!module->processes.empty()) -- cgit v1.2.3 From d55790909c3b4244889d092c8eae630c7efd1aee Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Feb 2019 19:27:23 +0100 Subject: Hotfix for 4c82ddf Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'passes') diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index aea3165e4..f6949c820 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -238,20 +238,11 @@ struct SetundefPass : public Pass { { if (params_mode) { - for (auto *cell : module->cells()) - { - // Only modify selected cells. - if (!design->selected(module, it)) { - continue; - } - - for (auto ¶meter : cell->parameters) - { + for (auto *cell : module->selected_cells()) { + for (auto ¶meter : cell->parameters) { for (auto &bit : parameter.second.bits) { if (bit > RTLIL::State::S1) - { bit = worker.next_bit(); - } } } } -- cgit v1.2.3 From 25680f6a078bb32f157bd580705656496717bafb Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 22 Feb 2019 10:28:28 -0800 Subject: Fix WREDUCE on FF not fixing ARST_VALUE parameter. Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- passes/opt/wreduce.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'passes') diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 3aa916ec2..c550b402e 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -195,6 +195,19 @@ struct WreduceWorker for (auto bit : sig_q) work_queue_bits.insert(bit); + // Narrow ARST_VALUE parameter to new size. + // + // Note: This works because earlier loop only removes signals from + // the upper bits of the DFF. + if(cell->parameters.count("\\ARST_VALUE") > 0) { + RTLIL::Const old_arst_value = cell->parameters.at("\\ARST_VALUE"); + std::vector new_arst_value(GetSize(sig_q)); + for(int i = 0; i < GetSize(sig_q); ++i) { + new_arst_value[i] = old_arst_value[i]; + } + cell->parameters["\\ARST_VALUE"] = RTLIL::Const(new_arst_value); + } + cell->setPort("\\D", sig_d); cell->setPort("\\Q", sig_q); cell->fixup_parameters(); -- cgit v1.2.3 From 71bcc4c644b0dafa760ff8b6d7bd1109836be621 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Fri, 22 Feb 2019 16:06:10 -0800 Subject: Address requested changes - don't require non-$ name. Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types. --- passes/hierarchy/hierarchy.cc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index f112e969e..cb54ffa58 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -525,14 +525,14 @@ int find_top_mod_score(Design *design, Module *module, dict &db) celltype = basic_cell_type(celltype); } // Is this cell a module instance? - if (celltype[0] != '$') { - auto instModule = design->module(celltype); - // If there is no instance for this, issue a warning. - if (instModule == NULL) { + auto instModule = design->module(celltype); + // If there is no instance for this, issue a warning. + if (instModule == NULL) { + // but only if we're sure it is a reference to a module. + if (celltype[0] != '$') log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str()); - } else { - score = max(score, find_top_mod_score(design, instModule, db) + 1); - } + } else { + score = max(score, find_top_mod_score(design, instModule, db) + 1); } } db[module] = score; -- cgit v1.2.3 From cd722f26a5437e145c02c49b5736bd03b13927da Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Feb 2019 20:34:23 +0100 Subject: Cleanups in ARST handling in wreduce Signed-off-by: Clifford Wolf --- passes/opt/wreduce.cc | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index c550b402e..09983bc67 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -196,16 +196,10 @@ struct WreduceWorker work_queue_bits.insert(bit); // Narrow ARST_VALUE parameter to new size. - // - // Note: This works because earlier loop only removes signals from - // the upper bits of the DFF. - if(cell->parameters.count("\\ARST_VALUE") > 0) { - RTLIL::Const old_arst_value = cell->parameters.at("\\ARST_VALUE"); - std::vector new_arst_value(GetSize(sig_q)); - for(int i = 0; i < GetSize(sig_q); ++i) { - new_arst_value[i] = old_arst_value[i]; - } - cell->parameters["\\ARST_VALUE"] = RTLIL::Const(new_arst_value); + if (cell->parameters.count("\\ARST_VALUE")) { + Const arst_value = cell->getParam("\\ARST_VALUE"); + arst_value.bits.resize(GetSize(sig_q)); + cell->setParam("\\ARST_VALUE", arst_value); } cell->setPort("\\D", sig_d); -- cgit v1.2.3 From c258b99040c8414952a3aceae874dc47563540dc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Feb 2019 20:41:36 +0100 Subject: Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check Signed-off-by: Clifford Wolf --- passes/hierarchy/hierarchy.cc | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index cb54ffa58..2d8edebb5 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -527,11 +527,7 @@ int find_top_mod_score(Design *design, Module *module, dict &db) // Is this cell a module instance? auto instModule = design->module(celltype); // If there is no instance for this, issue a warning. - if (instModule == NULL) { - // but only if we're sure it is a reference to a module. - if (celltype[0] != '$') - log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str()); - } else { + if (instModule != nullptr) { score = max(score, find_top_mod_score(design, instModule, db) + 1); } } -- cgit v1.2.3