From 661fa5ff92f19675cfd87754a99d0c5c42c9df13 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 2 Nov 2022 17:45:46 +0100 Subject: simplemap: Map `$xnor` to `$_XNOR_` cells The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of the `$_XNOR_` cell. --- passes/techmap/simplemap.cc | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'passes') diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f75b82919..baae8c6af 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -61,25 +61,11 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool()); - if (cell->type == ID($xnor)) - { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y)); - - for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - gate->setPort(ID::A, sig_t[i]); - gate->setPort(ID::Y, sig_y[i]); - } - - sig_y = sig_t; - } - IdString gate_type; if (cell->type == ID($and)) gate_type = ID($_AND_); if (cell->type == ID($or)) gate_type = ID($_OR_); if (cell->type == ID($xor)) gate_type = ID($_XOR_); - if (cell->type == ID($xnor)) gate_type = ID($_XOR_); + if (cell->type == ID($xnor)) gate_type = ID($_XNOR_); log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { -- cgit v1.2.3