From f2f19df2d4387ae70f5b063f2bd6e7cbdaa1ce75 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Sep 2019 17:44:01 -0700 Subject: Add -select option to aigmap --- passes/techmap/aigmap.cc | 46 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 1d5e1286b..2ecb2f35a 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -27,6 +27,7 @@ struct AigmapPass : public Pass { AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { } void help() YS_OVERRIDE { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" aigmap [options] [selection]\n"); log("\n"); @@ -36,10 +37,15 @@ struct AigmapPass : public Pass { log(" -nand\n"); log(" Enable creation of $_NAND_ cells\n"); log("\n"); + log(" -select\n"); + log(" Overwrite replaced cells in the current selection with new $_AND_,\n"); + log(" $_NOT_, and $_NAND_, cells\n"); + + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - bool nand_mode = false; + bool nand_mode = false, select_mode = false; log_header(design, "Executing AIGMAP pass (map logic to AIG).\n"); @@ -50,6 +56,10 @@ struct AigmapPass : public Pass { nand_mode = true; continue; } + if (args[argidx] == "-select") { + select_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -62,6 +72,7 @@ struct AigmapPass : public Pass { dict stat_not_replaced; int orig_num_cells = GetSize(module->cells()); + pool new_sel; for (auto cell : module->selected_cells()) { Aig aig(cell); @@ -75,6 +86,8 @@ struct AigmapPass : public Pass { if (aig.name.empty()) { not_replaced_count++; stat_not_replaced[cell->type]++; + if (select_mode) + new_sel.insert(cell->name); continue; } @@ -95,19 +108,33 @@ struct AigmapPass : public Pass { SigBit A = sigs.at(node.left_parent); SigBit B = sigs.at(node.right_parent); if (nand_mode && node.inverter) { - bit = module->NandGate(NEW_ID, A, B); + bit = module->addWire(NEW_ID); + auto gate = module->addNandGate(NEW_ID, A, B, bit); + if (select_mode) + new_sel.insert(gate->name); + goto skip_inverter; } else { pair key(node.left_parent, node.right_parent); if (and_cache.count(key)) bit = and_cache.at(key); - else - bit = module->AndGate(NEW_ID, A, B); + else { + bit = module->addWire(NEW_ID); + auto gate = module->addAndGate(NEW_ID, A, B, bit); + if (select_mode) + new_sel.insert(gate->name); + } } } - if (node.inverter) - bit = module->NotGate(NEW_ID, bit); + if (node.inverter) { + SigBit new_bit = module->addWire(NEW_ID); + auto gate = module->addNotGate(NEW_ID, bit, new_bit); + bit = new_bit; + if (select_mode) + new_sel.insert(gate->name); + + } skip_inverter: for (auto &op : node.outports) @@ -142,6 +169,13 @@ struct AigmapPass : public Pass { for (auto cell : replaced_cells) module->remove(cell); + + if (select_mode) { + log_assert(!design->selection_stack.empty()); + RTLIL::Selection& sel = design->selection_stack.back(); + sel.selected_members[module->name] = std::move(new_sel); + } + } } } AigmapPass; -- cgit v1.2.3 From edc378072301dba7ee79dd1d64a825faf72a1d62 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 17:20:12 -0700 Subject: techmap wires named _TECHMAP_REPLACE_. to create alias --- passes/techmap/techmap.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 08a1af2d5..8f8cff9fa 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -257,6 +257,12 @@ struct TechmapWorker w->add_strpool_attribute(ID(src), extra_src_attrs); } design->select(module, w); + + if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) { + IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_")); + Wire *replace_w = module->addWire(replace_name, it.second); + module->connect(replace_w, w); + } } SigMap tpl_sigmap(tpl); @@ -1198,6 +1204,10 @@ struct TechmapPass : public Pass { log("\n"); log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n"); log("and attributes of the cell that is being replaced.\n"); + log("A wire with a name of the form `_TECHMAP_REPLACE_.` in the map file will\n"); + log("cause a new wire alias to be created with its name set to the original but with\n"); + log("its `_TECHMAP_REPLACE_' prefix to be substituted with the name of the cell being\n"); + log("replaced.\n"); log("\n"); log("See 'help extract' for a pass that does the opposite thing.\n"); log("\n"); -- cgit v1.2.3 From 45e4c040d7bafed59ef46f5cf92e7a2adb802bdc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 2 Oct 2019 13:35:03 +0200 Subject: Add "check -mapped" Signed-off-by: Clifford Wolf --- passes/cmds/check.cc | 56 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 21 deletions(-) (limited to 'passes') diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 64697c134..87dc34209 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -47,6 +47,9 @@ struct CheckPass : public Pass { log("When called with -initdrv then this command also checks for wires which have\n"); log("the 'init' attribute set and aren't driven by a FF cell type.\n"); log("\n"); + log("When called with -mapped then this command also checks for internal cells\n"); + log("that have not been mapped to cells of the target architecture.\n"); + log("\n"); log("When called with -assert then the command will produce an error if any\n"); log("problems are found in the current design.\n"); log("\n"); @@ -56,6 +59,7 @@ struct CheckPass : public Pass { int counter = 0; bool noinit = false; bool initdrv = false; + bool mapped = false; bool assert_mode = false; size_t argidx; @@ -68,6 +72,10 @@ struct CheckPass : public Pass { initdrv = true; continue; } + if (args[argidx] == "-mapped") { + mapped = true; + continue; + } if (args[argidx] == "-assert") { assert_mode = true; continue; @@ -135,29 +143,35 @@ struct CheckPass : public Pass { TopoSort topo; for (auto cell : module->cells()) - for (auto &conn : cell->connections()) { - SigSpec sig = sigmap(conn.second); - bool logic_cell = yosys_celltypes.cell_evaluable(cell->type); - if (cell->input(conn.first)) - for (auto bit : sig) - if (bit.wire) { + { + if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) { + log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type)); + counter++; + } + for (auto &conn : cell->connections()) { + SigSpec sig = sigmap(conn.second); + bool logic_cell = yosys_celltypes.cell_evaluable(cell->type); + if (cell->input(conn.first)) + for (auto bit : sig) + if (bit.wire) { + if (logic_cell) + topo.edge(stringf("wire %s", log_signal(bit)), + stringf("cell %s (%s)", log_id(cell), log_id(cell->type))); + used_wires.insert(bit); + } + if (cell->output(conn.first)) + for (int i = 0; i < GetSize(sig); i++) { if (logic_cell) - topo.edge(stringf("wire %s", log_signal(bit)), - stringf("cell %s (%s)", log_id(cell), log_id(cell->type))); - used_wires.insert(bit); + topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)), + stringf("wire %s", log_signal(sig[i]))); + if (sig[i].wire) + wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)", + log_id(conn.first), i, log_id(cell), log_id(cell->type))); } - if (cell->output(conn.first)) - for (int i = 0; i < GetSize(sig); i++) { - if (logic_cell) - topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)), - stringf("wire %s", log_signal(sig[i]))); - if (sig[i].wire) - wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)", - log_id(conn.first), i, log_id(cell), log_id(cell->type))); - } - if (!cell->input(conn.first) && cell->output(conn.first)) - for (auto bit : sig) - if (bit.wire) wire_drivers_count[bit]++; + if (!cell->input(conn.first) && cell->output(conn.first)) + for (auto bit : sig) + if (bit.wire) wire_drivers_count[bit]++; + } } pool init_bits; -- cgit v1.2.3 From 265a655ef906fa0fc9ae30c1315db312e13ebd18 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 12:43:35 -0700 Subject: Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf --- passes/techmap/techmap.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 8f8cff9fa..0c57733d4 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -384,6 +384,8 @@ struct TechmapWorker if (techmap_replace_cell) c_name = orig_cell_name; + else if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) + c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_")); else apply_prefix(cell->name, c_name); @@ -1204,10 +1206,12 @@ struct TechmapPass : public Pass { log("\n"); log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n"); log("and attributes of the cell that is being replaced.\n"); - log("A wire with a name of the form `_TECHMAP_REPLACE_.` in the map file will\n"); - log("cause a new wire alias to be created with its name set to the original but with\n"); - log("its `_TECHMAP_REPLACE_' prefix to be substituted with the name of the cell being\n"); - log("replaced.\n"); + log("A cell with a name of the form `_TECHMAP_REPLACE_.` in the map file will\n"); + log("be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name\n"); + log("of the cell being replaced.\n"); + log("Similarly, a wire named in the form `_TECHMAP_REPLACE_.` will cause a\n"); + log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n"); + log("prefix also substituted.\n"); log("\n"); log("See 'help extract' for a pass that does the opposite thing.\n"); log("\n"); -- cgit v1.2.3 From 3e27b2846bc7d4178f436035d5007ac598bc194d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 3 Oct 2019 11:49:56 +0200 Subject: Add "check -allow-tbuf" Signed-off-by: Clifford Wolf --- passes/cmds/check.cc | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 87dc34209..820ecac7b 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -41,17 +41,24 @@ struct CheckPass : public Pass { log("\n"); log(" - used wires that do not have a driver\n"); log("\n"); - log("When called with -noinit then this command also checks for wires which have\n"); - log("the 'init' attribute set.\n"); + log("Options:\n"); log("\n"); - log("When called with -initdrv then this command also checks for wires which have\n"); - log("the 'init' attribute set and aren't driven by a FF cell type.\n"); + log(" -noinit\n"); + log(" Also check for wires which have the 'init' attribute set.\n"); log("\n"); - log("When called with -mapped then this command also checks for internal cells\n"); - log("that have not been mapped to cells of the target architecture.\n"); + log(" -initdrv\n"); + log(" Also check for wires that have the 'init' attribute set and are not\n"); + log(" driven by an FF cell type.\n"); log("\n"); - log("When called with -assert then the command will produce an error if any\n"); - log("problems are found in the current design.\n"); + log(" -mapped\n"); + log(" Also check for internal cells that have not been mapped to cells of the\n"); + log(" target architecture.\n"); + log("\n"); + log(" -allow-tbuf\n"); + log(" Modify the -mapped behavior to still allow $_TBUF_ cells.\n"); + log("\n"); + log(" -assert\n"); + log(" Produce a runtime error if any problems are found in the current design.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -60,6 +67,7 @@ struct CheckPass : public Pass { bool noinit = false; bool initdrv = false; bool mapped = false; + bool allow_tbuf = false; bool assert_mode = false; size_t argidx; @@ -76,6 +84,10 @@ struct CheckPass : public Pass { mapped = true; continue; } + if (args[argidx] == "-allow-tbuf") { + allow_tbuf = true; + continue; + } if (args[argidx] == "-assert") { assert_mode = true; continue; @@ -145,8 +157,10 @@ struct CheckPass : public Pass { for (auto cell : module->cells()) { if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) { + if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed; log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type)); counter++; + cell_allowed:; } for (auto &conn : cell->connections()) { SigSpec sig = sigmap(conn.second); -- cgit v1.2.3