From 7f5c73d58fd732a96e480083896cd73c722849ba Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Tue, 17 Mar 2020 18:44:06 +0100 Subject: Add N:* to select language, fix some old code Signed-off-by: Claire Wolf --- passes/cmds/select.cc | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 1657ef818..4dcf76480 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -764,10 +764,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else { size_t pos = arg.find('/'); if (pos == std::string::npos) { - if (arg.find(':') == std::string::npos || arg.compare(0, 1, "A") == 0) - arg_mod = arg; - else - arg_mod = "*", arg_memb = arg; + arg_mod = arg; } else { arg_mod = arg.substr(0, pos); arg_memb = arg.substr(pos+1); @@ -789,6 +786,10 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (!match_attr(mod->attributes, arg_mod.substr(2))) continue; } else + if (arg_mod.compare(0, 2, "N:") == 0) { + if (!match_ids(mod->name, arg_mod.substr(2))) + continue; + } else if (!match_ids(mod->name, arg_mod)) continue; @@ -1074,6 +1075,10 @@ struct SelectPass : public Pass { log(" all modules with an attribute matching the given pattern\n"); log(" in addition to = also <, <=, >=, and > are supported\n"); log("\n"); + log(" N:\n"); + log(" all modules with a name matching the given pattern\n"); + log(" (i.e. 'N:' is optional as it is the default matching rule)\n"); + log("\n"); log("An can be an object name, wildcard expression, or one of\n"); log("the following:\n"); log("\n"); -- cgit v1.2.3 From 5026f36250b7043195566b33fa0fae60746c4d97 Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Thu, 12 Mar 2020 17:00:21 +0000 Subject: Warn on empty selection for `add` command. --- passes/cmds/add.cc | 4 ++++ passes/cmds/select.cc | 42 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 40 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 7b76f3d4a..c49b8bf5d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -206,6 +206,7 @@ struct AddPass : public Pass { extra_args(args, argidx, design); + bool selected_anything = false; for (auto module : design->modules()) { log_assert(module != nullptr); @@ -214,11 +215,14 @@ struct AddPass : public Pass { if (module->get_bool_attribute("\\blackbox")) continue; + selected_anything = true; if (is_formal_celltype(command)) add_formal(module, command, arg_name, enable_name); else if (command == "wire") add_wire(design, module, arg_name, arg_width, arg_flag_input, arg_flag_output, arg_flag_global); } + if (!selected_anything) + log_warning("No modules selected, or only blackboxes. Nothing was added.\n"); } } AddPass; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 4dcf76480..42938b6ba 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -628,6 +628,10 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se static void select_stmt(RTLIL::Design *design, std::string arg) { std::string arg_mod, arg_memb; + std::unordered_map arg_mod_found; + std::unordered_map arg_memb_found; + auto isalpha = [](const char &x) { return ((x >= 'a' && x <= 'z') || (x >= 'A' && x <= 'Z')); }; + bool prefixed = GetSize(arg) >= 2 && isalpha(arg[0]) && arg[1] == ':'; if (arg.size() == 0) return; @@ -758,16 +762,20 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (!design->selected_active_module.empty()) { arg_mod = design->selected_active_module; arg_memb = arg; + if (!prefixed) arg_memb_found[arg_memb] = false; } else - if (GetSize(arg) >= 2 && arg[0] >= 'a' && arg[0] <= 'z' && arg[1] == ':') { + if (prefixed && arg[0] >= 'a' && arg[0] <= 'z') { arg_mod = "*", arg_memb = arg; } else { size_t pos = arg.find('/'); if (pos == std::string::npos) { arg_mod = arg; + if (!prefixed) arg_mod_found[arg_mod] = false; } else { arg_mod = arg.substr(0, pos); + if (!prefixed) arg_mod_found[arg_mod] = false; arg_memb = arg.substr(pos+1); + if (!prefixed) arg_memb_found[arg_memb] = false; } } @@ -792,6 +800,8 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else if (!match_ids(mod->name, arg_mod)) continue; + else + arg_mod_found[arg_mod] = true; if (arg_memb == "") { sel.selected_modules.insert(mod->name); @@ -840,7 +850,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.compare(0, 2, "c:") ==0) { + if (arg_memb.compare(0, 2, "c:") == 0) { for (auto cell : mod->cells()) if (match_ids(cell->name, arg_memb.substr(2))) sel.selected_members[mod->name].insert(cell->name); @@ -874,24 +884,44 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (match_attr(cell->parameters, arg_memb.substr(2))) sel.selected_members[mod->name].insert(cell->name); } else { + std::string orig_arg_memb = arg_memb; if (arg_memb.compare(0, 2, "n:") == 0) arg_memb = arg_memb.substr(2); for (auto wire : mod->wires()) - if (match_ids(wire->name, arg_memb)) + if (match_ids(wire->name, arg_memb)) { sel.selected_members[mod->name].insert(wire->name); + arg_memb_found[orig_arg_memb] = true; + } for (auto &it : mod->memories) - if (match_ids(it.first, arg_memb)) + if (match_ids(it.first, arg_memb)) { sel.selected_members[mod->name].insert(it.first); + arg_memb_found[orig_arg_memb] = true; + } for (auto cell : mod->cells()) - if (match_ids(cell->name, arg_memb)) + if (match_ids(cell->name, arg_memb)) { sel.selected_members[mod->name].insert(cell->name); + arg_memb_found[orig_arg_memb] = true; + } for (auto &it : mod->processes) - if (match_ids(it.first, arg_memb)) + if (match_ids(it.first, arg_memb)) { sel.selected_members[mod->name].insert(it.first); + arg_memb_found[orig_arg_memb] = true; + } } } select_filter_active_mod(design, work_stack.back()); + + for (auto &it : arg_mod_found) { + if (it.second == false) { + log_warning("Selection \"%s\" did not match any module.\n", it.first.c_str()); + } + } + for (auto &it : arg_memb_found) { + if (it.second == false) { + log_warning("Selection \"%s\" did not match any object.\n", it.first.c_str()); + } + } } static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel) -- cgit v1.2.3 From ca4e5dd56e1f007fa13c791ab179236103187c6f Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Mon, 23 Mar 2020 06:31:41 +0000 Subject: Suppress warnings for empty `select` arguments when `-count` or `-assert-*` options are set. --- passes/cmds/select.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 42938b6ba..fc693d20e 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -625,7 +625,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se } } -static void select_stmt(RTLIL::Design *design, std::string arg) +static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_empty_warning = false) { std::string arg_mod, arg_memb; std::unordered_map arg_mod_found; @@ -913,12 +913,12 @@ static void select_stmt(RTLIL::Design *design, std::string arg) select_filter_active_mod(design, work_stack.back()); for (auto &it : arg_mod_found) { - if (it.second == false) { + if (it.second == false && !disable_empty_warning) { log_warning("Selection \"%s\" did not match any module.\n", it.first.c_str()); } } for (auto &it : arg_memb_found) { - if (it.second == false) { + if (it.second == false && !disable_empty_warning) { log_warning("Selection \"%s\" did not match any object.\n", it.first.c_str()); } } @@ -1311,7 +1311,8 @@ struct SelectPass : public Pass { } if (arg.size() > 0 && arg[0] == '-') log_cmd_error("Unknown option %s.\n", arg.c_str()); - select_stmt(design, arg); + bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_count != -1) || (assert_max != -1) || (assert_min != -1); + select_stmt(design, arg, disable_empty_warning); sel_str += " " + arg; } -- cgit v1.2.3 From 0da65d498b9f18ce0c09eedc19f16db2390e6dcb Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Mon, 23 Mar 2020 17:50:11 +0000 Subject: Do not warn on empty selection with prefixed `arg_memb`. Co-Authored-By: N. Engelhardt --- passes/cmds/select.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index fc693d20e..b64b077e4 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -775,7 +775,8 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp arg_mod = arg.substr(0, pos); if (!prefixed) arg_mod_found[arg_mod] = false; arg_memb = arg.substr(pos+1); - if (!prefixed) arg_memb_found[arg_memb] = false; + bool arg_memb_prefixed = GetSize(arg_memb) >= 2 && isalpha(arg_memb[0]) && arg_memb[1] == ':'; + if (!arg_memb_prefixed) arg_memb_found[arg_memb] = false; } } -- cgit v1.2.3