From 1b96d29174d7c56a14031bc117a7da5fa5192c81 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 17:02:20 -0700 Subject: No need to punch ports at all --- passes/techmap/abc9.cc | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'passes') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index ce057566c..777ec6ac8 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1121,19 +1121,6 @@ struct Abc9Pass : public Pass { Pass::call_on_module(design, derived_module, "proc"); SigMap derived_sigmap(derived_module); - Wire *currQ = derived_module->wire("\\$currQ"); - if (currQ == NULL) - log_error("'\\$currQ' is not a wire present in module '%s'.\n", log_id(cell->type)); - log_assert(!currQ->port_output); - if (!currQ->port_input) { - currQ->port_input = true; - derived_module->ports.push_back(currQ->name); - currQ->port_id = GetSize(derived_module->ports); -#ifndef NDEBUG - derived_module->check(); -#endif - } - SigSpec pattern; SigSpec with; for (auto &conn : cell->connections()) { -- cgit v1.2.3