From 14412e6c957a34381c33740426b35f7b90a446be Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Aug 2014 00:45:25 +0200
Subject: Preparations for RTLIL::IdString redesign: cleanup of existing code

---
 passes/abc/abc.cc     | 2 +-
 passes/cmds/delete.cc | 6 +++---
 passes/cmds/design.cc | 2 +-
 passes/cmds/select.cc | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'passes')

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 4b2e82ca7..196643578 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -193,7 +193,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 	}
 }
 
-static std::string remap_name(std::string abc_name)
+static std::string remap_name(RTLIL::IdString abc_name)
 {
 	std::stringstream sstr;
 	sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 67b4d939f..2a91bc9ea 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -64,7 +64,7 @@ struct DeletePass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		std::vector<std::string> delete_mods;
+		std::vector<RTLIL::IdString> delete_mods;
 
 		for (auto &mod_it : design->modules_)
 		{
@@ -92,8 +92,8 @@ struct DeletePass : public Pass {
 
 			std::set<RTLIL::Wire*> delete_wires;
 			std::set<RTLIL::Cell*> delete_cells;
-			std::set<std::string> delete_procs;
-			std::set<std::string> delete_mems;
+			std::set<RTLIL::IdString> delete_procs;
+			std::set<RTLIL::IdString> delete_mems;
 
 			for (auto &it : module->wires_)
 				if (design->selected(module, it.second))
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 41548f621..260e7b5d9 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -192,7 +192,7 @@ struct DesignPass : public Pass {
 
 			for (auto mod : copy_src_modules)
 			{
-				std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name);
+				std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name);
 
 				if (copy_to_design->modules_.count(trg_name))
 					delete copy_to_design->modules_.at(trg_name);
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index bbfa396ba..35ca2f474 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -547,7 +547,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
 		return;
 	}
 
-	std::vector<std::string> del_list;
+	std::vector<RTLIL::IdString> del_list;
 	for (auto mod_name : sel.selected_modules)
 		if (mod_name != design->selected_active_module)
 			del_list.push_back(mod_name);
@@ -1322,7 +1322,7 @@ struct CdPass : public Pass {
 template<typename T>
 static int log_matches(const char *title, std::string pattern, T list)
 {
-	std::vector<std::string> matches;
+	std::vector<RTLIL::IdString> matches;
 
 	for (auto &it : list)
 		if (pattern.empty() || match_ids(it.first, pattern))
-- 
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