From da487c4f31fd2d97c0d7110010e7379e5445ceb0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 09:08:18 -0700 Subject: For now, short $_DFF_[NP]_ from ff_map.v at re-integration --- passes/techmap/abc9.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f7f2e862a..69b0c1192 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -511,6 +511,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // Remove all AND, NOT, and ABC box instances // in preparation for stitching mapped_mod in + // Short $_DFF_[NP]_ cells used by ABC (FIXME) dict erased_boxes; for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { RTLIL::Cell* cell = it->second; @@ -518,6 +519,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri it = module->cells_.erase(it); continue; } + else if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { + SigBit D = cell->getPort("\\D"); + SigBit Q = cell->getPort("\\Q"); + module->connect(Q, D); + it = module->cells_.erase(it); + continue; + } RTLIL::Module* box_module = design->module(cell->type); if (box_module && box_module->attributes.count("\\abc_box_id")) { erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters))); -- cgit v1.2.3 From ac18a76bebad001fc3e617a7cefebe13610abcb8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 09:34:48 -0700 Subject: Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues --- passes/techmap/abc9.cc | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 69b0c1192..4bb4058b1 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -242,7 +242,7 @@ struct abc_output_filter }; void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, - bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, + bool cleanup, vector lut_costs, bool retime_mode, std::string clk_str, bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, bool show_tempdir, std::string box_file, std::string lut_file, std::string wire_delay) @@ -285,7 +285,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0)); } - if (dff_mode && clk_sig.empty()) + if (retime_mode && clk_sig.empty()) log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); std::string tempdir_name = "/tmp/yosys-abc-XXXXXX"; @@ -359,7 +359,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri fprintf(f, "%s\n", abc_script.c_str()); fclose(f); - if (dff_mode || !clk_str.empty()) + if (retime_mode || !clk_str.empty()) { if (clk_sig.size() == 0) log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching"); @@ -511,7 +511,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // Remove all AND, NOT, and ABC box instances // in preparation for stitching mapped_mod in - // Short $_DFF_[NP]_ cells used by ABC (FIXME) + // Short $_FF_ cells used by ABC (FIXME) dict erased_boxes; for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { RTLIL::Cell* cell = it->second; @@ -519,7 +519,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri it = module->cells_.erase(it); continue; } - else if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { + else if (cell->type.in("$_FF_")) { SigBit D = cell->getPort("\\D"); SigBit Q = cell->getPort("\\Q"); module->connect(Q, D); @@ -842,7 +842,7 @@ struct Abc9Pass : public Pass { #endif std::string script_file, clk_str, box_file, lut_file; std::string delay_target, lutin_shared = "-S 1", wire_delay; - bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; + bool fast_mode = false, retime_mode = false, keepff = false, cleanup = true; bool show_tempdir = false; vector lut_costs; markgroups = false; @@ -933,13 +933,13 @@ struct Abc9Pass : public Pass { fast_mode = true; continue; } - //if (arg == "-dff") { - // dff_mode = true; - // continue; - //} + if (arg == "-retime") { + retime_mode = true; + continue; + } //if (arg == "-clk" && argidx+1 < args.size()) { // clk_str = args[++argidx]; - // dff_mode = true; + // retime_mode = true; // continue; //} //if (arg == "-keepff") { @@ -1003,8 +1003,8 @@ struct Abc9Pass : public Pass { } } - if (!dff_mode || !clk_str.empty()) { - abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff, + if (!retime_mode || !clk_str.empty()) { + abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, retime_mode, clk_str, keepff, delay_target, lutin_shared, fast_mode, show_tempdir, box_file, lut_file, wire_delay); continue; -- cgit v1.2.3 From a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 09:46:35 -0700 Subject: Fix initialisation of flops --- passes/techmap/abc9.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4bb4058b1..51bea4d57 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -520,8 +520,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri continue; } else if (cell->type.in("$_FF_")) { - SigBit D = cell->getPort("\\D"); - SigBit Q = cell->getPort("\\Q"); + RTLIL::Wire *D = cell->getPort("\\D").as_wire(); + RTLIL::Wire *Q = cell->getPort("\\Q").as_wire(); + Q->attributes.swap(D->attributes); module->connect(Q, D); it = module->cells_.erase(it); continue; -- cgit v1.2.3 From c2f3f116d041b97b0d8b6ed28c87810bf6c2630e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 18:16:14 -0700 Subject: Use $__ABC_FF_ instead of $_FF_ --- passes/techmap/abc9.cc | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 51bea4d57..cedbc9273 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -399,6 +399,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", // count_gates, GetSize(signal_list), count_input, count_output); +#if 0 + Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.xaig", tempdir_name.c_str())); +#endif Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); std::string buffer; @@ -513,25 +516,22 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // in preparation for stitching mapped_mod in // Short $_FF_ cells used by ABC (FIXME) dict erased_boxes; + std::vector abc_dff; for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { RTLIL::Cell* cell = it->second; if (cell->type.in("$_AND_", "$_NOT_")) { it = module->cells_.erase(it); continue; } - else if (cell->type.in("$_FF_")) { - RTLIL::Wire *D = cell->getPort("\\D").as_wire(); - RTLIL::Wire *Q = cell->getPort("\\Q").as_wire(); - Q->attributes.swap(D->attributes); - module->connect(Q, D); - it = module->cells_.erase(it); - continue; - } - RTLIL::Module* box_module = design->module(cell->type); - if (box_module && box_module->attributes.count("\\abc_box_id")) { - erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters))); - it = module->cells_.erase(it); - continue; + if (cell->type.in("$__ABC_FF_")) + abc_dff.emplace_back(cell); + else { + RTLIL::Module* box_module = design->module(cell->type); + if (box_module && box_module->attributes.count("\\abc_box_id")) { + erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters))); + it = module->cells_.erase(it); + continue; + } } ++it; } @@ -671,6 +671,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module + // TODO: iterate using ports for (auto &it : mapped_mod->wires_) { RTLIL::Wire *w = it.second; if (!w->port_input && !w->port_output) @@ -697,6 +698,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } + for (auto cell : abc_dff) { + RTLIL::SigBit D = cell->getPort("\\D"); + RTLIL::SigBit Q = cell->getPort("\\Q"); + module->connect(Q, D); + module->remove(cell); + } + //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); -- cgit v1.2.3 From cdfb634977b3ee005c5635f7902ea21dd45f7311 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 18:18:56 -0700 Subject: Cleanup --- passes/techmap/abc9.cc | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index cedbc9273..e13cd0eef 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -671,26 +671,23 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module - // TODO: iterate using ports - for (auto &it : mapped_mod->wires_) { - RTLIL::Wire *w = it.second; - if (!w->port_input && !w->port_output) - continue; - RTLIL::Wire *wire = module->wire(w->name); + for (auto port_name : mapped_mod->ports) { + RTLIL::Wire *port = mapped_mod->wire(port_name); + log_assert(port); + RTLIL::Wire *wire = module->wire(port->name); log_assert(wire); - RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); + RTLIL::Wire *remap_wire = module->wire(remap_name(port->name)); RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); - log_assert(w->port_input || w->port_output); RTLIL::SigSig conn; - if (w->port_input) { + if (port->port_input) { conn.first = remap_wire; conn.second = signal; in_wires++; module->connect(conn); } - if (w->port_output) { + if (port->port_output) { conn.first = signal; conn.second = remap_wire; out_wires++; -- cgit v1.2.3 From 2309459605b262040f7bea84e6d935d2838686d5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 19:36:55 -0700 Subject: Do not treat $__ABC_FF_ as a user cell --- passes/techmap/abc9.cc | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index e13cd0eef..decf5a6aa 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -512,26 +512,18 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } - // Remove all AND, NOT, and ABC box instances - // in preparation for stitching mapped_mod in - // Short $_FF_ cells used by ABC (FIXME) dict erased_boxes; - std::vector abc_dff; for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { RTLIL::Cell* cell = it->second; - if (cell->type.in("$_AND_", "$_NOT_")) { + if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) { it = module->cells_.erase(it); continue; } - if (cell->type.in("$__ABC_FF_")) - abc_dff.emplace_back(cell); - else { - RTLIL::Module* box_module = design->module(cell->type); - if (box_module && box_module->attributes.count("\\abc_box_id")) { - erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters))); - it = module->cells_.erase(it); - continue; - } + RTLIL::Module* box_module = design->module(cell->type); + if (box_module && box_module->attributes.count("\\abc_box_id")) { + erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters))); + it = module->cells_.erase(it); + continue; } ++it; } @@ -695,13 +687,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } - for (auto cell : abc_dff) { - RTLIL::SigBit D = cell->getPort("\\D"); - RTLIL::SigBit Q = cell->getPort("\\Q"); - module->connect(Q, D); - module->remove(cell); - } - //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); -- cgit v1.2.3 From 416312b9ed027b062c4e043b6265b73b25eb299a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 22:44:45 -0700 Subject: abc9 to recover_init by default --- passes/techmap/abc9.cc | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index decf5a6aa..aea5e478d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -67,7 +67,6 @@ SigMap assign_map; RTLIL::Module *module; std::map signal_map; std::map signal_init; -bool recover_init; bool clk_polarity, en_polarity; RTLIL::SigSpec clk_sig, en_sig; @@ -253,7 +252,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri signal_map.clear(); pi_map.clear(); po_map.clear(); - recover_init = false; if (clk_str != "$") { @@ -510,6 +508,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (int i = 0; i < GetSize(wire); i++) output_bits.insert({wire, i}); } + + auto jt = w->attributes.find("\\init"); + if (jt != w->attributes.end()) { + auto r = remap_wire->attributes.insert(std::make_pair("\\init", jt->second)); + log_assert(r.second); + } } dict erased_boxes; @@ -649,15 +653,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri module->connect(conn); } - if (recover_init) - for (auto wire : mapped_mod->wires()) { - if (wire->attributes.count("\\init")) { - Wire *w = module->wires_[remap_name(wire->name)]; - log_assert(w->attributes.count("\\init") == 0); - w->attributes["\\init"] = wire->attributes.at("\\init"); - } - } - for (auto &it : cell_stats) log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); int in_wires = 0, out_wires = 0; -- cgit v1.2.3 From 3ed95dae8d7661256003f5294f6aa7168b87c5a8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 22:48:16 -0700 Subject: Cleanup --- passes/techmap/abc9.cc | 47 +++++++---------------------------------------- 1 file changed, 7 insertions(+), 40 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index aea5e478d..4e7bdfa8f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -65,12 +65,9 @@ bool markgroups; int map_autoidx; SigMap assign_map; RTLIL::Module *module; -std::map signal_map; -std::map signal_init; bool clk_polarity, en_polarity; RTLIL::SigSpec clk_sig, en_sig; -dict pi_map, po_map; std::string remap_name(RTLIL::IdString abc_name) { @@ -227,13 +224,13 @@ struct abc_output_filter void next_line(const std::string &line) { - int pi, po; - if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) { - log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n", - pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???", - po, po_map.count(po) ? po_map.at(po).c_str() : "???"); - return; - } + //int pi, po; + //if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) { + // log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n", + // pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???", + // po, po_map.count(po) ? po_map.at(po).c_str() : "???"); + // return; + //} for (char ch : line) next_char(ch); @@ -249,10 +246,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri module = current_module; map_autoidx = autoidx++; - signal_map.clear(); - pi_map.clear(); - po_map.clear(); - if (clk_str != "$") { clk_polarity = true; @@ -816,10 +809,6 @@ struct Abc9Pass : public Pass { log_push(); assign_map.clear(); - signal_map.clear(); - signal_init.clear(); - pi_map.clear(); - po_map.clear(); #ifdef ABCEXTERNAL std::string exe_file = ABCEXTERNAL; @@ -970,24 +959,6 @@ struct Abc9Pass : public Pass { } assign_map.set(mod); - signal_init.clear(); - - for (Wire *wire : mod->wires()) - if (wire->attributes.count("\\init")) { - SigSpec initsig = assign_map(wire); - Const initval = wire->attributes.at("\\init"); - for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) - switch (initval[i]) { - case State::S0: - signal_init[initsig[i]] = State::S0; - break; - case State::S1: - signal_init[initsig[i]] = State::S0; - break; - default: - break; - } - } if (!retime_mode || !clk_str.empty()) { abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, retime_mode, clk_str, keepff, @@ -1146,10 +1117,6 @@ struct Abc9Pass : public Pass { Pass::call(design, "clean"); assign_map.clear(); - signal_map.clear(); - signal_init.clear(); - pi_map.clear(); - po_map.clear(); log_pop(); } -- cgit v1.2.3 From d80678e581899315791706ee1703bf700b0f9c15 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 17 Jun 2019 15:10:33 -0700 Subject: Cleanup --- passes/techmap/abc9.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 776bceb3b..f56350b1d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -527,7 +527,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } RTLIL::Module* box_module = design->module(cell->type); if (box_module && box_module->attributes.count("\\abc_box_id")) - boxes.emplace_back(it->second); + boxes.emplace_back(cell); ++it; } @@ -629,8 +629,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } - for (auto cell : boxes) - module->remove(cell); + for (auto cell : boxes) + module->remove(cell); // Copy connections (and rename) from mapped_mod to module for (auto conn : mapped_mod->connections()) { -- cgit v1.2.3 From ef757002dbc8280a65d25618e57b20d3dbadd64a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 10:55:24 -0700 Subject: Also remove $__ABC_FF_ --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 2eee43739..30df8e3ef 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -566,7 +566,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri vector boxes; for (const auto &it : module->cells_) { auto cell = it.second; - if (cell->type.in("$_AND_", "$_NOT_")) { + if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) { module->remove(cell); continue; } -- cgit v1.2.3 From 71acd3ddcfc9083f23ee624de1c16be6b8dbe4d6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 18:57:44 -0700 Subject: Remove -retime from abc9, revert to abc behav with separate clock/en domains --- passes/techmap/abc9.cc | 90 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 61 insertions(+), 29 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 30df8e3ef..6e57ab7f3 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -285,7 +285,7 @@ struct abc_output_filter }; void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, - bool cleanup, vector lut_costs, bool retime_mode, std::string clk_str, + bool cleanup, vector lut_costs, bool /*retime_mode*/, std::string clk_str, bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, bool show_tempdir, std::string box_file, std::string lut_file, std::string wire_delay) @@ -323,8 +323,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0)); } - if (retime_mode && clk_sig.empty()) - log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); + //if (retime_mode && clk_sig.empty()) + // log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); std::string tempdir_name = "/tmp/yosys-abc-XXXXXX"; if (!cleanup) @@ -397,7 +397,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri fprintf(f, "%s\n", abc_script.c_str()); fclose(f); - if (retime_mode || !clk_str.empty()) + if (/*retime_mode ||*/ !clk_str.empty()) { if (clk_sig.size() == 0) log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching"); @@ -874,7 +874,7 @@ struct Abc9Pass : public Pass { #endif std::string script_file, clk_str, box_file, lut_file; std::string delay_target, lutin_shared = "-S 1", wire_delay; - bool fast_mode = false, retime_mode = false, keepff = false, cleanup = true; + bool fast_mode = false, /*retime_mode = false,*/ keepff = false, cleanup = true; bool show_tempdir = false; vector lut_costs; markgroups = false; @@ -965,10 +965,10 @@ struct Abc9Pass : public Pass { fast_mode = true; continue; } - if (arg == "-retime") { - retime_mode = true; - continue; - } + //if (arg == "-retime") { + // retime_mode = true; + // continue; + //} //if (arg == "-clk" && argidx+1 < args.size()) { // clk_str = args[++argidx]; // retime_mode = true; @@ -1017,13 +1017,6 @@ struct Abc9Pass : public Pass { assign_map.set(mod); - if (!retime_mode || !clk_str.empty()) { - abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, retime_mode, clk_str, keepff, - delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, wire_delay); - continue; - } - CellTypes ct(design); std::vector all_cells = mod->selected_cells(); @@ -1040,8 +1033,10 @@ struct Abc9Pass : public Pass { std::map> cell_to_bit, cell_to_bit_up, cell_to_bit_down; std::map> bit_to_cell, bit_to_cell_up, bit_to_cell_down; - for (auto cell : all_cells) - { + pool seen_cells; + dict> flop_data; + + for (auto cell : all_cells) { clkdomain_t key; for (auto &conn : cell->connections()) @@ -1061,19 +1056,56 @@ struct Abc9Pass : public Pass { } } - if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") - { - key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); + decltype(flop_data)::iterator it; + if (seen_cells.insert(cell->type).second) { + RTLIL::Module* inst_module = design->module(cell->type); + if (!inst_module) + continue; + + if (!inst_module->attributes.count("\\abc_flop")) + continue; + + IdString abc_flop_clk, abc_flop_en; + for (auto port_name : inst_module->ports) { + auto wire = inst_module->wire(port_name); + log_assert(wire); + if (wire->attributes.count("\\abc_flop_clk")) { + if (abc_flop_clk != IdString()) + log_error("More than one port has the 'abc_flop_clk' attribute set on module '%s'.\n", log_id(cell->type)); + abc_flop_clk = port_name; + } + if (wire->attributes.count("\\abc_flop_en")) { + if (abc_flop_en != IdString()) + log_error("More than one port has the 'abc_flop_en' attribute set on module '%s'.\n", log_id(cell->type)); + abc_flop_en = port_name; + } + } + + if (abc_flop_clk == IdString()) + log_error("'abc_flop_clk' attribute not found on any ports on module '%s'.\n", log_id(cell->type)); + if (abc_flop_en == IdString()) + log_error("'abc_flop_en' attribute not found on any ports on module '%s'.\n", log_id(cell->type)); + it = flop_data.insert(std::make_pair(cell->type, std::make_pair(abc_flop_clk, abc_flop_en))).first; } - else - if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") - { - bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"; - bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"; - key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); + else { + it = flop_data.find(cell->type); + if (it == flop_data.end()) + continue; } - else - continue; + + auto jt = cell->parameters.find("\\$abc_flop_clk_pol"); + if (jt == cell->parameters.end()) + log_error("'$abc_flop_clk_pol' parameter not found on module '%s'.\n", log_id(cell->type)); + cell->parameters.erase(jt); + bool this_clk_pol = jt->second.as_bool(); + jt = cell->parameters.find("\\$abc_flop_en_pol"); + if (jt == cell->parameters.end()) + log_error("'$abc_flop_en_pol' parameter not found on module '%s'.\n", log_id(cell->type)); + bool this_en_pol = jt->second.as_bool(); + cell->parameters.erase(jt); + + const auto &data = it->second; + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.first)), this_en_pol, assign_map(cell->getPort(data.second))); unassigned_cells.erase(cell); expand_queue.insert(cell); -- cgit v1.2.3 From 9f608d6be30c9302c0e3810525457e39f57b0334 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 20:25:59 -0700 Subject: write_verilog with *.v extension --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 6e57ab7f3..330361f65 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -435,7 +435,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // count_gates, GetSize(signal_list), count_input, count_output); #if 0 - Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.xaig", tempdir_name.c_str())); + Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.v", tempdir_name.c_str())); #endif Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); -- cgit v1.2.3 From 33862d04451ba58ce2b51c1e11abf86b65c3f018 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 09:22:52 -0700 Subject: WIP for fixing partitioning, temporarily do not partition --- passes/techmap/abc9.cc | 46 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 12 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 330361f65..4347c3789 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -86,7 +86,7 @@ void handle_loops(RTLIL::Design *design) // cell in the component, and select (and mark) all its output // wires pool ids_seen; - for (auto cell : module->cells()) { + for (auto cell : module->selected_cells()) { auto it = cell->attributes.find("\\abc_scc_id"); if (it != cell->attributes.end()) { auto r = ids_seen.insert(it->second); @@ -423,10 +423,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (count_output) { - design->selection_stack.emplace_back(false); - RTLIL::Selection& sel = design->selection_stack.back(); - sel.select(module); - Pass::call(design, "aigmap"); handle_loops(design); @@ -457,8 +453,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri design->remove(design->module("$__abc9__")); #endif - design->selection_stack.pop_back(); - // Now 'unexpose' those wires by undoing // the expose operation -- remove them from PO/PI // and re-connecting them back together @@ -477,7 +471,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } module->fixup_ports(); - log_header(design, "Executing ABC9.\n"); if (!lut_costs.empty()) { @@ -564,8 +557,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri dict abc_box; vector boxes; - for (const auto &it : module->cells_) { - auto cell = it.second; + for (auto cell : module->selected_cells()) { if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) { module->remove(cell); continue; @@ -663,6 +655,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (existing_cell) { cell->parameters = existing_cell->parameters; cell->attributes = existing_cell->attributes; + + auto it = cell->parameters.find("\\$abc_flop_clk_pol"); + if (it != cell->parameters.end()) + cell->parameters.erase(it); + it = cell->parameters.find("\\$abc_flop_en_pol"); + if (it != cell->parameters.end()) + cell->parameters.erase(it); } else { cell->parameters = c->parameters; @@ -1017,6 +1016,20 @@ struct Abc9Pass : public Pass { assign_map.set(mod); + if (true || /*!dff_mode ||*/ !clk_str.empty()) { + + design->selection_stack.emplace_back(false); + RTLIL::Selection& sel = design->selection_stack.back(); + sel.select(mod); + + abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, false, clk_str, keepff, + delay_target, lutin_shared, fast_mode, show_tempdir, + box_file, lut_file, wire_delay); + + design->selection_stack.pop_back(); + continue; + } + CellTypes ct(design); std::vector all_cells = mod->selected_cells(); @@ -1096,13 +1109,11 @@ struct Abc9Pass : public Pass { auto jt = cell->parameters.find("\\$abc_flop_clk_pol"); if (jt == cell->parameters.end()) log_error("'$abc_flop_clk_pol' parameter not found on module '%s'.\n", log_id(cell->type)); - cell->parameters.erase(jt); bool this_clk_pol = jt->second.as_bool(); jt = cell->parameters.find("\\$abc_flop_en_pol"); if (jt == cell->parameters.end()) log_error("'$abc_flop_en_pol' parameter not found on module '%s'.\n", log_id(cell->type)); bool this_en_pol = jt->second.as_bool(); - cell->parameters.erase(jt); const auto &data = it->second; key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.first)), this_en_pol, assign_map(cell->getPort(data.second))); @@ -1191,16 +1202,27 @@ struct Abc9Pass : public Pass { std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)), std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first))); + design->selection_stack.emplace_back(false); + RTLIL::Selection& sel = design->selection_stack.back(); + for (auto &it : assigned_cells) { clk_polarity = std::get<0>(it.first); clk_sig = assign_map(std::get<1>(it.first)); en_polarity = std::get<2>(it.first); en_sig = assign_map(std::get<3>(it.first)); + + pool assigned_names; + for (auto i : it.second) + assigned_names.insert(i->name); + sel.selected_members[mod->name] = std::move(assigned_names); + abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, lutin_shared, fast_mode, show_tempdir, box_file, lut_file, wire_delay); assign_map.set(mod); } + + design->selection_stack.pop_back(); } Pass::call(design, "clean"); -- cgit v1.2.3 From 0c3ed73dade2488d0add1a3e6e82b148171f2d66 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 09:55:14 -0700 Subject: Count $_NOT_ cells turned into $luts --- passes/techmap/abc9.cc | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4347c3789..53b0b8bbe 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -584,7 +584,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_assert(wire); module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1); } - else if (!lut_costs.empty() || !lut_file.empty()) { + else { RTLIL::Cell* driving_lut = nullptr; // ABC can return NOT gates that drive POs if (!a_bit.wire->port_input) { @@ -622,12 +622,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), driver_lut); } - } - else { - cell = module->addCell(remap_name(c->name), "$_NOT_"); - cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset)); - cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset)); - cell_stats[RTLIL::unescape_id(c->type)]++; + cell_stats["$lut"]++; } if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx; continue; -- cgit v1.2.3 From 237d8651a5b91bf4fa1de69d0930fdcbba049e40 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 09:58:00 -0700 Subject: Error out if abc9 not called with -lut or -luts --- passes/techmap/abc9.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 53b0b8bbe..b9eb71cf1 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -999,6 +999,9 @@ struct Abc9Pass : public Pass { } extra_args(args, argidx, design); + if (lut_costs.empty() && lut_file.empty()) + log_cmd_error("abc9 must be called with '-lut' or '-luts'\n"); + for (auto mod : design->selected_modules()) { if (mod->attributes.count("\\abc_box_id")) -- cgit v1.2.3 From 9bfe924e17a87fac8a35fcb7ff5e067f6c520e07 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 09:40:01 -0700 Subject: Set abc_flop and use it in toposort --- passes/techmap/abc9.cc | 82 +++++++++++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 31 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 50a6e0fe5..df62b4fa5 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -443,6 +443,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri design->remove(design->module(ID($__abc9__))); #endif + design->selection_stack.pop_back(); + // Now 'unexpose' those wires by undoing // the expose operation -- remove them from PO/PI // and re-connecting them back together @@ -568,19 +570,17 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri dict> bit2sinks; std::map cell_stats; - for (auto c : mapped_mod->cells()) + for (auto mapped_cell : mapped_mod->cells()) { - toposort.node(c->name); + toposort.node(mapped_cell->name); RTLIL::Cell *cell = nullptr; - if (c->type == ID($_NOT_)) { - RTLIL::SigBit a_bit = c->getPort(ID(A)); - RTLIL::SigBit y_bit = c->getPort(ID(Y)); - bit_users[a_bit].insert(c->name); - bit_drivers[y_bit].insert(c->name); + if (mapped_cell->type == ID($_NOT_)) { + RTLIL::SigBit a_bit = mapped_cell->getPort(ID(A)); + RTLIL::SigBit y_bit = mapped_cell->getPort(ID(Y)); if (!a_bit.wire) { - c->setPort(ID(Y), module->addWire(NEW_ID)); + mapped_cell->setPort(ID(Y), module->addWire(NEW_ID)); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); log_assert(wire); module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1); @@ -604,38 +604,40 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (!driving_lut) { // If a driver couldn't be found (could be from PI or box CI) // then implement using a LUT - cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())), + cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())), RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::Const::from_string("01")); bit2sinks[cell->getPort(ID(A))].push_back(cell); cell_stats[ID($lut)]++; + bit_users[a_bit].insert(mapped_cell->name); + bit_drivers[y_bit].insert(mapped_cell->name); } else - not2drivers[c] = driving_lut; + not2drivers[mapped_cell] = driving_lut; continue; } if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; continue; } - cell_stats[c->type]++; + cell_stats[mapped_cell->type]++; RTLIL::Cell *existing_cell = nullptr; - if (c->type == ID($lut)) { - if (GetSize(c->getPort(ID(A))) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) { - SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID(A)).as_wire()->name)); - SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID(Y)).as_wire()->name)); + if (mapped_cell->type == ID($lut)) { + if (GetSize(mapped_cell->getPort(ID(A))) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) { + SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID(A)).as_wire()->name)); + SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID(Y)).as_wire()->name)); module->connect(my_y, my_a); - if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) mapped_cell->attributes[ID(abcgroup)] = map_autoidx; log_abort(); continue; } - cell = module->addCell(remap_name(c->name), c->type); + cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); } else { - existing_cell = module->cell(c->name); + existing_cell = module->cell(mapped_cell->name); log_assert(existing_cell); - cell = module->addCell(remap_name(c->name), c->type); + cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); module->swap_names(cell, existing_cell); } @@ -652,10 +654,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri cell->parameters.erase(it); } else { - cell->parameters = c->parameters; - cell->attributes = c->attributes; + cell->parameters = mapped_cell->parameters; + cell->attributes = mapped_cell->attributes; } - for (auto &conn : c->connections()) { + + auto abc_flop = mapped_cell->attributes.count("\\abc_flop"); + for (auto &conn : mapped_cell->connections()) { RTLIL::SigSpec newsig; for (auto c : conn.second.chunks()) { if (c.width == 0) @@ -667,15 +671,17 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } cell->setPort(conn.first, newsig); - if (cell->input(conn.first)) { - for (auto i : newsig) - bit2sinks[i].push_back(cell); - for (auto i : conn.second) - bit_users[i].insert(c->name); + if (!abc_flop) { + if (cell->input(conn.first)) { + for (auto i : newsig) + bit2sinks[i].push_back(cell); + for (auto i : conn.second) + bit_users[i].insert(mapped_cell->name); + } + if (cell->output(conn.first)) + for (auto i : conn.second) + bit_drivers[i].insert(mapped_cell->name); } - if (cell->output(conn.first)) - for (auto i : conn.second) - bit_drivers[i].insert(c->name); } } @@ -701,7 +707,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } for (auto &it : cell_stats) - log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); + log("ABC RESULTS: %15s cells: %8d\n", log_id(it.first), it.second); int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module @@ -734,7 +740,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (auto driver_cell : bit_drivers.at(it.first)) for (auto user_cell : it.second) toposort.edge(driver_cell, user_cell); +#if 0 + toposort.analyze_loops = true; +#endif bool no_loops = toposort.sort(); +#if 0 + unsigned i = 0; + for (auto &it : toposort.loops) { + log(" loop %d\n", i++); + for (auto cell_name : it) { + auto cell = mapped_mod->cell(cell_name); + log_assert(cell); + log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str()); + } + } +#endif log_assert(no_loops); for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) { -- cgit v1.2.3 From e301440a0bae76dcff159c77274c91aad40021c0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 09:51:49 -0700 Subject: Use attributes instead of params --- passes/techmap/abc9.cc | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index df62b4fa5..d52be1836 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -646,12 +646,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri cell->parameters = existing_cell->parameters; cell->attributes = existing_cell->attributes; - auto it = cell->parameters.find("\\$abc_flop_clk_pol"); - if (it != cell->parameters.end()) - cell->parameters.erase(it); - it = cell->parameters.find("\\$abc_flop_en_pol"); - if (it != cell->parameters.end()) - cell->parameters.erase(it); + cell->attributes.erase("\\abc_flop_clk_pol"); + cell->attributes.erase("\\abc_flop_en_pol"); } else { cell->parameters = mapped_cell->parameters; @@ -1265,14 +1261,32 @@ struct Abc9Pass : public Pass { continue; } - auto jt = cell->parameters.find("\\$abc_flop_clk_pol"); + auto jt = cell->attributes.find("\\abc_flop_clk_pol"); if (jt == cell->parameters.end()) - log_error("'$abc_flop_clk_pol' parameter not found on module '%s'.\n", log_id(cell->type)); - bool this_clk_pol = jt->second.as_bool(); + log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(cell->type)); + bool this_clk_pol; + if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) { + auto param = jt->second.decode_string(); + auto kt = cell->parameters.find(param); + if (kt == cell->parameters.end()) + log_error("'abc_flop_clk_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type)); + this_clk_pol = kt->second.as_bool(); + } + else + this_clk_pol = jt->second.as_bool(); jt = cell->parameters.find("\\$abc_flop_en_pol"); if (jt == cell->parameters.end()) - log_error("'$abc_flop_en_pol' parameter not found on module '%s'.\n", log_id(cell->type)); - bool this_en_pol = jt->second.as_bool(); + log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(cell->type)); + bool this_en_pol; + if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) { + auto param = jt->second.decode_string(); + auto kt = cell->parameters.find(param); + if (kt == cell->parameters.end()) + log_error("'abc_flop_en_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type)); + this_en_pol = kt->second.as_bool(); + } + else + this_en_pol = jt->second.as_bool(); const auto &data = it->second; key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.first)), this_en_pol, assign_map(cell->getPort(data.second))); -- cgit v1.2.3 From ba2261e21a18b969473f228b5f55bd5612558ed8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 11:18:33 -0700 Subject: Move from cell attr to module attr --- passes/techmap/abc9.cc | 88 ++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 64 insertions(+), 24 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 398df190c..be2a8d50b 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1202,7 +1202,15 @@ struct Abc9Pass : public Pass { std::map> bit_to_cell, bit_to_cell_up, bit_to_cell_down; pool seen_cells; - dict> flop_data; + struct flop_data_t { + IdString clk_port; + IdString clk_pol_param; + bool clk_pol; + IdString en_port; + IdString en_pol_param; + bool en_pol; + }; + dict flop_data; for (auto cell : all_cells) { clkdomain_t key; @@ -1253,7 +1261,40 @@ struct Abc9Pass : public Pass { log_error("'abc_flop_clk' attribute not found on any ports on module '%s'.\n", log_id(cell->type)); if (abc_flop_en == IdString()) log_error("'abc_flop_en' attribute not found on any ports on module '%s'.\n", log_id(cell->type)); - it = flop_data.insert(std::make_pair(cell->type, std::make_pair(abc_flop_clk, abc_flop_en))).first; + + auto jt = inst_module->attributes.find("\\abc_flop_clk_pol"); + if (jt == inst_module->attributes.end()) + log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(inst_module)); + IdString abc_flop_clk_pol_param; + bool abc_flop_clk_pol; + if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) { + auto param = jt->second.decode_string(); + abc_flop_clk_pol = (param[0] == '!'); + if (abc_flop_clk_pol) + abc_flop_clk_pol_param = RTLIL::escape_id(param.substr(1)); + else + abc_flop_clk_pol_param = RTLIL::escape_id(param); + } + else + abc_flop_clk_pol = !jt->second.as_bool(); + jt = inst_module->attributes.find("\\abc_flop_en_pol"); + if (jt == inst_module->attributes.end()) + log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(inst_module)); + IdString abc_flop_en_pol_param; + bool abc_flop_en_pol; + if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) { + auto param = jt->second.decode_string(); + abc_flop_en_pol = (param[0] == '!'); + if (abc_flop_en_pol) + abc_flop_en_pol_param = RTLIL::escape_id(param.substr(1)); + else + abc_flop_en_pol_param = RTLIL::escape_id(param); + } + else + abc_flop_en_pol = !jt->second.as_bool(); + + it = flop_data.insert(std::make_pair(cell->type, flop_data_t{abc_flop_clk, abc_flop_clk_pol_param, abc_flop_clk_pol, + abc_flop_en, abc_flop_en_pol_param, abc_flop_en_pol})).first; } else { it = flop_data.find(cell->type); @@ -1261,35 +1302,34 @@ struct Abc9Pass : public Pass { continue; } - auto jt = cell->attributes.find("\\abc_flop_clk_pol"); - if (jt == cell->parameters.end()) - log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(cell->type)); + const auto &data = it->second; + bool this_clk_pol; - if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) { - auto param = jt->second.decode_string(); - auto kt = cell->parameters.find(param); - if (kt == cell->parameters.end()) + if (data.clk_pol_param == IdString()) + this_clk_pol = data.clk_pol; + else { + auto param = data.clk_pol_param; + auto jt = cell->parameters.find(param); + if (jt == cell->parameters.end()) log_error("'abc_flop_clk_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type)); - this_clk_pol = kt->second.as_bool(); - } - else this_clk_pol = jt->second.as_bool(); - jt = cell->parameters.find("\\$abc_flop_en_pol"); - if (jt == cell->parameters.end()) - log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(cell->type)); + if (data.clk_pol) + this_clk_pol = !this_clk_pol; + } bool this_en_pol; - if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) { - auto param = jt->second.decode_string(); - auto kt = cell->parameters.find(param); - if (kt == cell->parameters.end()) + if (data.en_pol_param == IdString()) + this_en_pol = data.en_pol; + else { + auto param = data.en_pol_param; + auto jt = cell->parameters.find(param); + if (jt == cell->parameters.end()) log_error("'abc_flop_en_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type)); - this_en_pol = kt->second.as_bool(); - } - else this_en_pol = jt->second.as_bool(); + if (data.en_pol) + this_en_pol = !this_en_pol; + } - const auto &data = it->second; - key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.first)), this_en_pol, assign_map(cell->getPort(data.second))); + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.clk_port)), this_en_pol, assign_map(cell->getPort(data.en_port))); unassigned_cells.erase(cell); expand_queue.insert(cell); -- cgit v1.2.3 From 91687d3feae8df0e315232d3989a445e7d452d1f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 12:33:24 -0700 Subject: Add (* abc_arrival *) attribute --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index be2a8d50b..9156381fa 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -965,7 +965,7 @@ struct Abc9Pass : public Pass { vector lut_costs; markgroups = false; -#if 0 +#if 1 cleanup = false; show_tempdir = true; #endif -- cgit v1.2.3 From e29df7d5fa507657994e974630e89511a205ff1e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 12:44:43 -0700 Subject: Remove debug --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 9156381fa..be2a8d50b 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -965,7 +965,7 @@ struct Abc9Pass : public Pass { vector lut_costs; markgroups = false; -#if 1 +#if 0 cleanup = false; show_tempdir = true; #endif -- cgit v1.2.3 From 505d062daf0e2600dacf04cf18d97b279bd58d72 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 13:33:31 -0700 Subject: Fix use of {CLK,EN}_POLARITY, also add a FIXME --- passes/techmap/abc9.cc | 78 +++++++++----------------------------------------- 1 file changed, 13 insertions(+), 65 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 576fb8542..c7dc67c62 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -645,9 +645,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (existing_cell) { cell->parameters = existing_cell->parameters; cell->attributes = existing_cell->attributes; - - cell->attributes.erase("\\abc_flop_clk_pol"); - cell->attributes.erase("\\abc_flop_en_pol"); } else { cell->parameters = mapped_cell->parameters; @@ -1204,11 +1201,7 @@ struct Abc9Pass : public Pass { pool seen_cells; struct flop_data_t { IdString clk_port; - IdString clk_pol_param; - bool clk_pol; IdString en_port; - IdString en_pol_param; - bool en_pol; }; dict flop_data; @@ -1262,39 +1255,7 @@ struct Abc9Pass : public Pass { if (abc_flop_en == IdString()) log_error("'abc_flop_en' attribute not found on any ports on module '%s'.\n", log_id(cell->type)); - auto jt = inst_module->attributes.find("\\abc_flop_clk_pol"); - if (jt == inst_module->attributes.end()) - log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(inst_module)); - IdString abc_flop_clk_pol_param; - bool abc_flop_clk_pol; - if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) { - auto param = jt->second.decode_string(); - abc_flop_clk_pol = (param[0] == '!'); - if (abc_flop_clk_pol) - abc_flop_clk_pol_param = RTLIL::escape_id(param.substr(1)); - else - abc_flop_clk_pol_param = RTLIL::escape_id(param); - } - else - abc_flop_clk_pol = !jt->second.as_bool(); - jt = inst_module->attributes.find("\\abc_flop_en_pol"); - if (jt == inst_module->attributes.end()) - log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(inst_module)); - IdString abc_flop_en_pol_param; - bool abc_flop_en_pol; - if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) { - auto param = jt->second.decode_string(); - abc_flop_en_pol = (param[0] == '!'); - if (abc_flop_en_pol) - abc_flop_en_pol_param = RTLIL::escape_id(param.substr(1)); - else - abc_flop_en_pol_param = RTLIL::escape_id(param); - } - else - abc_flop_en_pol = !jt->second.as_bool(); - - it = flop_data.insert(std::make_pair(cell->type, flop_data_t{abc_flop_clk, abc_flop_clk_pol_param, abc_flop_clk_pol, - abc_flop_en, abc_flop_en_pol_param, abc_flop_en_pol})).first; + it = flop_data.insert(std::make_pair(cell->type, flop_data_t{abc_flop_clk, abc_flop_en})).first; } else { it = flop_data.find(cell->type); @@ -1304,30 +1265,15 @@ struct Abc9Pass : public Pass { const auto &data = it->second; - bool this_clk_pol; - if (data.clk_pol_param == IdString()) - this_clk_pol = data.clk_pol; - else { - auto param = data.clk_pol_param; - auto jt = cell->parameters.find(param); - if (jt == cell->parameters.end()) - log_error("'abc_flop_clk_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type)); - this_clk_pol = jt->second.as_bool(); - if (data.clk_pol) - this_clk_pol = !this_clk_pol; - } - bool this_en_pol; - if (data.en_pol_param == IdString()) - this_en_pol = data.en_pol; - else { - auto param = data.en_pol_param; - auto jt = cell->parameters.find(param); - if (jt == cell->parameters.end()) - log_error("'abc_flop_en_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type)); - this_en_pol = jt->second.as_bool(); - if (data.en_pol) - this_en_pol = !this_en_pol; - } + auto jt = cell->parameters.find("\\CLK_POLARITY"); + if (jt == cell->parameters.end()) + log_error("'CLK_POLARITY' is not a parameter on module '%s'.\n", log_id(cell->type)); + bool this_clk_pol = jt->second.as_bool(); + + jt = cell->parameters.find("\\EN_POLARITY"); + if (jt == cell->parameters.end()) + log_error("'EN_POLARITY' is not a parameter on module '%s'.\n", log_id(cell->type)); + bool this_en_pol = jt->second.as_bool(); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.clk_port)), this_en_pol, assign_map(cell->getPort(data.en_port))); @@ -1416,9 +1362,10 @@ struct Abc9Pass : public Pass { std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first))); design->selection_stack.emplace_back(false); - RTLIL::Selection& sel = design->selection_stack.back(); for (auto &it : assigned_cells) { + // FIXME: abc9_module calls below can delete cells, + // leaving a dangling pointer here... clk_polarity = std::get<0>(it.first); clk_sig = assign_map(std::get<1>(it.first)); en_polarity = std::get<2>(it.first); @@ -1427,6 +1374,7 @@ struct Abc9Pass : public Pass { pool assigned_names; for (auto i : it.second) assigned_names.insert(i->name); + RTLIL::Selection& sel = design->selection_stack.back(); sel.selected_members[mod->name] = std::move(assigned_names); abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$", -- cgit v1.2.3 From fad15d276dd9746b41a2d3e1592285ad4362fe21 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:08:58 -0700 Subject: retime_mode -> dff_mode --- passes/techmap/abc9.cc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index c7dc67c62..29929f80b 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -269,7 +269,7 @@ struct abc_output_filter }; void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, - bool cleanup, vector lut_costs, bool /*retime_mode*/, std::string clk_str, + bool cleanup, vector lut_costs, bool /*dff_mode*/, std::string clk_str, bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, bool show_tempdir, std::string box_file, std::string lut_file, std::string wire_delay, const dict &box_lookup, @@ -309,7 +309,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0)); } - //if (retime_mode && clk_sig.empty()) + //if (dff_mode && clk_sig.empty()) // log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); std::string tempdir_name = "/tmp/yosys-abc-XXXXXX"; @@ -383,7 +383,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri fprintf(f, "%s\n", abc_script.c_str()); fclose(f); - if (/*retime_mode ||*/ !clk_str.empty()) + if (/*dff_mode ||*/ !clk_str.empty()) { if (clk_sig.size() == 0) log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching"); @@ -957,7 +957,7 @@ struct Abc9Pass : public Pass { #endif std::string script_file, clk_str, box_file, lut_file; std::string delay_target, lutin_shared = "-S 1", wire_delay; - bool fast_mode = false, /*retime_mode = false,*/ keepff = false, cleanup = true; + bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false; vector lut_costs; markgroups = false; @@ -1049,12 +1049,12 @@ struct Abc9Pass : public Pass { continue; } //if (arg == "-retime") { - // retime_mode = true; + // dff_mode = true; // continue; //} //if (arg == "-clk" && argidx+1 < args.size()) { // clk_str = args[++argidx]; - // retime_mode = true; + // dff_mode = true; // continue; //} //if (arg == "-keepff") { @@ -1169,7 +1169,7 @@ struct Abc9Pass : public Pass { assign_map.set(mod); - if (true || /*!dff_mode ||*/ !clk_str.empty()) { + if (!dff_mode || !clk_str.empty()) { design->selection_stack.emplace_back(false); RTLIL::Selection& sel = design->selection_stack.back(); -- cgit v1.2.3 From 091bf4a18b2f4bf84fe62b61577c88d961468b3c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:16:37 -0700 Subject: Remove sequential extension --- passes/techmap/abc9.cc | 88 ++++++++++++-------------------------------------- 1 file changed, 20 insertions(+), 68 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 29929f80b..919c4ce53 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -551,7 +551,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri dict abc_box; vector boxes; for (auto cell : module->selected_cells()) { - if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC_FF_))) { + if (cell->type.in(ID($_AND_), ID($_NOT_))) { module->remove(cell); continue; } @@ -651,7 +651,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri cell->attributes = mapped_cell->attributes; } - auto abc_flop = mapped_cell->attributes.count("\\abc_flop"); for (auto &conn : mapped_cell->connections()) { RTLIL::SigSpec newsig; for (auto c : conn.second.chunks()) { @@ -664,17 +663,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } cell->setPort(conn.first, newsig); - if (!abc_flop) { - if (cell->input(conn.first)) { - for (auto i : newsig) - bit2sinks[i].push_back(cell); - for (auto i : conn.second) - bit_users[i].insert(mapped_cell->name); - } - if (cell->output(conn.first)) - for (auto i : conn.second) - bit_drivers[i].insert(mapped_cell->name); + if (cell->input(conn.first)) { + for (auto i : newsig) + bit2sinks[i].push_back(cell); + for (auto i : conn.second) + bit_users[i].insert(mapped_cell->name); } + if (cell->output(conn.first)) + for (auto i : conn.second) + bit_drivers[i].insert(mapped_cell->name); } } @@ -1170,7 +1167,6 @@ struct Abc9Pass : public Pass { assign_map.set(mod); if (!dff_mode || !clk_str.empty()) { - design->selection_stack.emplace_back(false); RTLIL::Selection& sel = design->selection_stack.back(); sel.select(mod); @@ -1198,13 +1194,6 @@ struct Abc9Pass : public Pass { std::map> cell_to_bit, cell_to_bit_up, cell_to_bit_down; std::map> bit_to_cell, bit_to_cell_up, bit_to_cell_down; - pool seen_cells; - struct flop_data_t { - IdString clk_port; - IdString en_port; - }; - dict flop_data; - for (auto cell : all_cells) { clkdomain_t key; @@ -1225,57 +1214,20 @@ struct Abc9Pass : public Pass { } } - decltype(flop_data)::iterator it; - if (seen_cells.insert(cell->type).second) { - RTLIL::Module* inst_module = design->module(cell->type); - if (!inst_module) - continue; - - if (!inst_module->attributes.count("\\abc_flop")) - continue; - - IdString abc_flop_clk, abc_flop_en; - for (auto port_name : inst_module->ports) { - auto wire = inst_module->wire(port_name); - log_assert(wire); - if (wire->attributes.count("\\abc_flop_clk")) { - if (abc_flop_clk != IdString()) - log_error("More than one port has the 'abc_flop_clk' attribute set on module '%s'.\n", log_id(cell->type)); - abc_flop_clk = port_name; - } - if (wire->attributes.count("\\abc_flop_en")) { - if (abc_flop_en != IdString()) - log_error("More than one port has the 'abc_flop_en' attribute set on module '%s'.\n", log_id(cell->type)); - abc_flop_en = port_name; - } - } - - if (abc_flop_clk == IdString()) - log_error("'abc_flop_clk' attribute not found on any ports on module '%s'.\n", log_id(cell->type)); - if (abc_flop_en == IdString()) - log_error("'abc_flop_en' attribute not found on any ports on module '%s'.\n", log_id(cell->type)); - - it = flop_data.insert(std::make_pair(cell->type, flop_data_t{abc_flop_clk, abc_flop_en})).first; + if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) + { + key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec()); } - else { - it = flop_data.find(cell->type); - if (it == flop_data.end()) - continue; + else + if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) + { + bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_)); + bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)); + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E)))); } + else + continue; - const auto &data = it->second; - - auto jt = cell->parameters.find("\\CLK_POLARITY"); - if (jt == cell->parameters.end()) - log_error("'CLK_POLARITY' is not a parameter on module '%s'.\n", log_id(cell->type)); - bool this_clk_pol = jt->second.as_bool(); - - jt = cell->parameters.find("\\EN_POLARITY"); - if (jt == cell->parameters.end()) - log_error("'EN_POLARITY' is not a parameter on module '%s'.\n", log_id(cell->type)); - bool this_en_pol = jt->second.as_bool(); - - key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.clk_port)), this_en_pol, assign_map(cell->getPort(data.en_port))); unassigned_cells.erase(cell); expand_queue.insert(cell); -- cgit v1.2.3 From 57493e328ad69b749619bc692130e28ab5c212ee Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 19:48:16 -0700 Subject: techmap -max_iter to apply to each module individually --- passes/techmap/techmap.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index b271c8781..a6c1214a7 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -943,7 +943,8 @@ struct TechmapPass : public Pass { log(" instead of inlining them.\n"); log("\n"); log(" -max_iter \n"); - log(" only run the specified number of iterations.\n"); + log(" only run the specified number of iterations for each module.\n"); + log(" default: unlimited\n"); log("\n"); log(" -recursive\n"); log(" instead of the iterative breadth-first algorithm use a recursive\n"); @@ -1157,15 +1158,16 @@ struct TechmapPass : public Pass { RTLIL::Module *module = *worker.module_queue.begin(); worker.module_queue.erase(module); + int module_max_iter = max_iter; bool did_something = true; std::set handled_cells; while (did_something) { did_something = false; - if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) - did_something = true; + if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) + did_something = true; if (did_something) module->check(); - if (max_iter > 0 && --max_iter == 0) + if (module_max_iter > 0 && --module_max_iter == 0) break; } } -- cgit v1.2.3 From 48c424e45bceec55b71dd64c987b2c7eafe7a113 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 13:46:05 -0700 Subject: Cleanup --- passes/techmap/abc9.cc | 189 +++++++++++++++---------------------------------- 1 file changed, 59 insertions(+), 130 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 919c4ce53..968c68b70 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -76,8 +76,7 @@ inline std::string remap_name(RTLIL::IdString abc_name) return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1); } -void handle_loops(RTLIL::Design *design, - const dict> &scc_break_inputs) +void handle_loops(RTLIL::Design *design) { Pass::call(design, "scc -set_attr abc_scc_id {}"); @@ -85,7 +84,7 @@ void handle_loops(RTLIL::Design *design, // cell in the component, and select (and mark) all its output // wires pool ids_seen; - for (auto cell : module->selected_cells()) { + for (auto cell : module->cells()) { auto it = cell->attributes.find(ID(abc_scc_id)); if (it != cell->attributes.end()) { auto r = ids_seen.insert(it->second); @@ -114,30 +113,6 @@ void handle_loops(RTLIL::Design *design, } cell->attributes.erase(it); } - - auto jt = scc_break_inputs.find(cell->type); - if (jt != scc_break_inputs.end()) - for (auto port_name : jt->second) { - RTLIL::SigSpec sig; - auto &rhs = cell->connections_.at(port_name); - for (auto b : rhs) { - Wire *w = b.wire; - if (!w) continue; - w->port_output = true; - w->set_bool_attribute(ID(abc_scc_break)); - w = module->wire(stringf("%s.abci", w->name.c_str())); - if (!w) { - w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire)); - w->port_input = true; - } - else { - log_assert(b.offset < GetSize(w)); - log_assert(w->port_input); - } - sig.append(RTLIL::SigBit(w, b.offset)); - } - rhs = sig; - } } module->fixup_ports(); @@ -269,11 +244,10 @@ struct abc_output_filter }; void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, - bool cleanup, vector lut_costs, bool /*dff_mode*/, std::string clk_str, + bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, bool show_tempdir, std::string box_file, std::string lut_file, - std::string wire_delay, const dict &box_lookup, - const dict> &scc_break_inputs + std::string wire_delay, const dict &box_lookup ) { module = current_module; @@ -309,8 +283,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0)); } - //if (dff_mode && clk_sig.empty()) - // log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); + if (dff_mode && clk_sig.empty()) + log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); std::string tempdir_name = "/tmp/yosys-abc-XXXXXX"; if (!cleanup) @@ -383,7 +357,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri fprintf(f, "%s\n", abc_script.c_str()); fclose(f); - if (/*dff_mode ||*/ !clk_str.empty()) + if (dff_mode || !clk_str.empty()) { if (clk_sig.size() == 0) log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching"); @@ -413,16 +387,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Selection& sel = design->selection_stack.back(); sel.select(module); - handle_loops(design, scc_break_inputs); + handle_loops(design); Pass::call(design, "aigmap"); //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", // count_gates, GetSize(signal_list), count_input, count_output); -#if 0 - Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.v", tempdir_name.c_str())); -#endif Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); std::string buffer; @@ -531,12 +502,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (int i = 0; i < GetSize(w); i++) output_bits.insert({wire, i}); } - - auto jt = w->attributes.find("\\init"); - if (jt != w->attributes.end()) { - auto r = remap_wire->attributes.insert(std::make_pair("\\init", jt->second)); - log_assert(r.second); - } } for (auto &it : module->connections_) { @@ -550,7 +515,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri dict abc_box; vector boxes; - for (auto cell : module->selected_cells()) { + for (const auto &it : module->cells_) { + auto cell = it.second; if (cell->type.in(ID($_AND_), ID($_NOT_))) { module->remove(cell); continue; @@ -570,23 +536,25 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri dict> bit2sinks; std::map cell_stats; - for (auto mapped_cell : mapped_mod->cells()) + for (auto c : mapped_mod->cells()) { - toposort.node(mapped_cell->name); + toposort.node(c->name); RTLIL::Cell *cell = nullptr; - if (mapped_cell->type == ID($_NOT_)) { - RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A); - RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y); + if (c->type == ID($_NOT_)) { + RTLIL::SigBit a_bit = c->getPort(ID::A); + RTLIL::SigBit y_bit = c->getPort(ID::Y); + bit_users[a_bit].insert(c->name); + bit_drivers[y_bit].insert(c->name); if (!a_bit.wire) { - mapped_cell->setPort(ID::Y, module->addWire(NEW_ID)); + c->setPort(ID::Y, module->addWire(NEW_ID)); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); log_assert(wire); module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1); } - else { - RTLIL::Cell* driving_lut = nullptr; + else if (!lut_costs.empty() || !lut_file.empty()) { + RTLIL::Cell* driver_lut = nullptr; // ABC can return NOT gates that drive POs if (!a_bit.wire->port_input) { // If it's not a NOT gate that that comes from a PI directly, @@ -598,46 +566,46 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri driver_name = stringf("%s$lut", a_bit.wire->name.c_str()); else driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset); - driving_lut = mapped_mod->cell(driver_name); + driver_lut = mapped_mod->cell(driver_name); } - if (!driving_lut) { + if (!driver_lut) { // If a driver couldn't be found (could be from PI or box CI) // then implement using a LUT - cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())), + cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())), RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::Const::from_string("01")); bit2sinks[cell->getPort(ID::A)].push_back(cell); cell_stats[ID($lut)]++; - bit_users[a_bit].insert(mapped_cell->name); - bit_drivers[y_bit].insert(mapped_cell->name); } else - not2drivers[mapped_cell] = driving_lut; + not2drivers[c] = driver_lut; continue; } + else + log_abort(); if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; continue; } - cell_stats[mapped_cell->type]++; + cell_stats[c->type]++; RTLIL::Cell *existing_cell = nullptr; - if (mapped_cell->type == ID($lut)) { - if (GetSize(mapped_cell->getPort(ID::A)) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) { - SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name)); - SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name)); + if (c->type == ID($lut)) { + if (GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) { + SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID::A).as_wire()->name)); + SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID::Y).as_wire()->name)); module->connect(my_y, my_a); - if (markgroups) mapped_cell->attributes[ID(abcgroup)] = map_autoidx; + if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx; log_abort(); continue; } - cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); + cell = module->addCell(remap_name(c->name), c->type); } else { - existing_cell = module->cell(mapped_cell->name); + existing_cell = module->cell(c->name); log_assert(existing_cell); - cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); + cell = module->addCell(remap_name(c->name), c->type); module->swap_names(cell, existing_cell); } @@ -647,11 +615,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri cell->attributes = existing_cell->attributes; } else { - cell->parameters = mapped_cell->parameters; - cell->attributes = mapped_cell->attributes; + cell->parameters = c->parameters; + cell->attributes = c->attributes; } - - for (auto &conn : mapped_cell->connections()) { + for (auto &conn : c->connections()) { RTLIL::SigSpec newsig; for (auto c : conn.second.chunks()) { if (c.width == 0) @@ -667,11 +634,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (auto i : newsig) bit2sinks[i].push_back(cell); for (auto i : conn.second) - bit_users[i].insert(mapped_cell->name); + bit_users[i].insert(c->name); } if (cell->output(conn.first)) for (auto i : conn.second) - bit_drivers[i].insert(mapped_cell->name); + bit_drivers[i].insert(c->name); } } @@ -697,27 +664,29 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } for (auto &it : cell_stats) - log("ABC RESULTS: %15s cells: %8d\n", log_id(it.first), it.second); + log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module - for (auto port_name : mapped_mod->ports) { - RTLIL::Wire *port = mapped_mod->wire(port_name); - log_assert(port); - RTLIL::Wire *wire = module->wire(port->name); + for (auto &it : mapped_mod->wires_) { + RTLIL::Wire *w = it.second; + if (!w->port_input && !w->port_output) + continue; + RTLIL::Wire *wire = module->wire(w->name); log_assert(wire); - RTLIL::Wire *remap_wire = module->wire(remap_name(port->name)); + RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); + log_assert(w->port_input || w->port_output); RTLIL::SigSig conn; - if (port->port_input) { + if (w->port_input) { conn.first = remap_wire; conn.second = signal; in_wires++; module->connect(conn); } - if (port->port_output) { + if (w->port_output) { conn.first = signal; conn.second = remap_wire; out_wires++; @@ -730,21 +699,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (auto driver_cell : bit_drivers.at(it.first)) for (auto user_cell : it.second) toposort.edge(driver_cell, user_cell); -#if 0 - toposort.analyze_loops = true; -#endif bool no_loops YS_ATTRIBUTE(unused) = toposort.sort(); -#if 0 - unsigned i = 0; - for (auto &it : toposort.loops) { - log(" loop %d\n", i++); - for (auto cell_name : it) { - auto cell = mapped_mod->cell(cell_name); - log_assert(cell); - log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str()); - } - } -#endif log_assert(no_loops); for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) { @@ -1045,7 +1000,7 @@ struct Abc9Pass : public Pass { fast_mode = true; continue; } - //if (arg == "-retime") { + //if (arg == "-dff") { // dff_mode = true; // continue; //} @@ -1085,11 +1040,7 @@ struct Abc9Pass : public Pass { } extra_args(args, argidx, design); - if (lut_costs.empty() && lut_file.empty()) - log_cmd_error("abc9 must be called with '-lut' or '-luts'\n"); - dict box_lookup; - dict> scc_break_inputs; for (auto m : design->modules()) { auto it = m->attributes.find(ID(abc_box_id)); if (it == m->attributes.end()) @@ -1107,17 +1058,13 @@ struct Abc9Pass : public Pass { for (auto p : m->ports) { auto w = m->wire(p); log_assert(w); - if (w->port_input) { - if (w->attributes.count(ID(abc_scc_break))) - scc_break_inputs[m->name].insert(p); - if (w->attributes.count(ID(abc_carry))) { + if (w->attributes.count(ID(abc_carry))) { + if (w->port_input) { if (carry_in) log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m)); carry_in = w; } - } - if (w->port_output) { - if (w->attributes.count(ID(abc_carry))) { + else if (w->port_output) { if (carry_out) log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m)); carry_out = w; @@ -1167,14 +1114,9 @@ struct Abc9Pass : public Pass { assign_map.set(mod); if (!dff_mode || !clk_str.empty()) { - design->selection_stack.emplace_back(false); - RTLIL::Selection& sel = design->selection_stack.back(); - sel.select(mod); - - abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, false, clk_str, keepff, + abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, wire_delay, box_lookup, scc_break_inputs); - design->selection_stack.pop_back(); + box_file, lut_file, wire_delay, box_lookup); continue; } @@ -1194,7 +1136,8 @@ struct Abc9Pass : public Pass { std::map> cell_to_bit, cell_to_bit_up, cell_to_bit_down; std::map> bit_to_cell, bit_to_cell_up, bit_to_cell_down; - for (auto cell : all_cells) { + for (auto cell : all_cells) + { clkdomain_t key; for (auto &conn : cell->connections()) @@ -1228,7 +1171,6 @@ struct Abc9Pass : public Pass { else continue; - unassigned_cells.erase(cell); expand_queue.insert(cell); expand_queue_up.insert(cell); @@ -1313,29 +1255,16 @@ struct Abc9Pass : public Pass { std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)), std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first))); - design->selection_stack.emplace_back(false); - for (auto &it : assigned_cells) { - // FIXME: abc9_module calls below can delete cells, - // leaving a dangling pointer here... clk_polarity = std::get<0>(it.first); clk_sig = assign_map(std::get<1>(it.first)); en_polarity = std::get<2>(it.first); en_sig = assign_map(std::get<3>(it.first)); - - pool assigned_names; - for (auto i : it.second) - assigned_names.insert(i->name); - RTLIL::Selection& sel = design->selection_stack.back(); - sel.selected_members[mod->name] = std::move(assigned_names); - abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, wire_delay, box_lookup, scc_break_inputs); + box_file, lut_file, wire_delay, box_lookup); assign_map.set(mod); } - - design->selection_stack.pop_back(); } assign_map.clear(); -- cgit v1.2.3 From c4e53108230c246ecf1b014b11c240b71ed39a8a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 20:58:55 -0700 Subject: Use a dummy box file if none specified --- passes/techmap/abc9.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 968c68b70..11fe9c4a5 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1027,9 +1027,6 @@ struct Abc9Pass : public Pass { } if (arg == "-box" && argidx+1 < args.size()) { box_file = args[++argidx]; - rewrite_filename(box_file); - if (!box_file.empty() && !is_absolute_path(box_file)) - box_file = std::string(pwd) + "/" + box_file; continue; } if (arg == "-W" && argidx+1 < args.size()) { @@ -1040,6 +1037,14 @@ struct Abc9Pass : public Pass { } extra_args(args, argidx, design); + // ABC expects a box file for XAIG + if (box_file.empty()) + box_file = "+/dummy.box"; + + rewrite_filename(box_file); + if (!box_file.empty() && !is_absolute_path(box_file)) + box_file = std::string(pwd) + "/" + box_file; + dict box_lookup; for (auto m : design->modules()) { auto it = m->attributes.find(ID(abc_box_id)); -- cgit v1.2.3 From 694a8f75cf7a8bcf86a421ca6c9fe3560b1e2a0f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Aug 2019 00:55:43 +0200 Subject: Add flatten handling of pre-existing wires as created by interfaces, fixes #1145 Signed-off-by: Clifford Wolf --- passes/techmap/techmap.cc | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c4496f76f..cb01cadb1 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -211,14 +211,26 @@ struct TechmapWorker positional_ports[stringf("$%d", it.second->port_id)] = it.first; IdString w_name = it.second->name; apply_prefix(cell->name, w_name); - RTLIL::Wire *w = module->addWire(w_name, it.second); - w->port_input = false; - w->port_output = false; - w->port_id = 0; - if (it.second->get_bool_attribute(ID(_techmap_special_))) - w->attributes.clear(); - if (w->attributes.count(ID(src))) - w->add_strpool_attribute(ID(src), extra_src_attrs); + RTLIL::Wire *w = module->wire(w_name); + if (w != nullptr) { + if (!flatten_mode) + log_error("Signal %s.%s conflicts with %s.%s (via %s.%s).\n", log_id(module), log_id(w), + log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); + if (GetSize(w) < GetSize(it.second)) { + log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), + log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); + w->width = GetSize(it.second); + } + } else { + w = module->addWire(w_name, it.second); + w->port_input = false; + w->port_output = false; + w->port_id = 0; + if (it.second->get_bool_attribute(ID(_techmap_special_))) + w->attributes.clear(); + if (w->attributes.count(ID(src))) + w->add_strpool_attribute(ID(src), extra_src_attrs); + } design->select(module, w); } -- cgit v1.2.3 From 30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 5 Sep 2019 13:51:53 +0200 Subject: Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220 Signed-off-by: Clifford Wolf --- passes/techmap/techmap.cc | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index cb01cadb1..5ce1bf7d6 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -205,6 +205,7 @@ struct TechmapWorker } std::map positional_ports; + dict temp_renamed_wires; for (auto &it : tpl->wires_) { if (it.second->port_id > 0) @@ -213,15 +214,20 @@ struct TechmapWorker apply_prefix(cell->name, w_name); RTLIL::Wire *w = module->wire(w_name); if (w != nullptr) { - if (!flatten_mode) - log_error("Signal %s.%s conflicts with %s.%s (via %s.%s).\n", log_id(module), log_id(w), - log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); - if (GetSize(w) < GetSize(it.second)) { - log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), - log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); - w->width = GetSize(it.second); + if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) { + temp_renamed_wires[w] = w->name; + module->rename(w, NEW_ID); + w = nullptr; + } else { + w->attributes.erase(ID(hierconn)); + if (GetSize(w) < GetSize(it.second)) { + log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), + log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); + w->width = GetSize(it.second); + } } - } else { + } + if (w == nullptr) { w = module->addWire(w_name, it.second); w->port_input = false; w->port_output = false; @@ -392,6 +398,16 @@ struct TechmapWorker } module->remove(cell); + + for (auto &it : temp_renamed_wires) + { + Wire *w = it.first; + IdString name = it.second; + IdString altname = module->uniquify(name); + Wire *other_w = module->wire(name); + module->rename(other_w, altname); + module->rename(w, name); + } } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set &handled_cells, -- cgit v1.2.3 From a82e8df7d37c02258d36223bb16833331dc8808e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Fri, 16 Aug 2019 03:14:03 +0000 Subject: techmap: Add support for extracting init values of ports --- passes/techmap/techmap.cc | 71 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) (limited to 'passes/techmap') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 5ce1bf7d6..51a65aea6 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -424,6 +424,18 @@ struct TechmapWorker SigMap sigmap(module); + dict init_bits; + pool remove_init_bits; + + for (auto wire : module->wires()) { + if (wire->attributes.count("\\init")) { + Const value = wire->attributes.at("\\init"); + for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) + if (value[i] != State::Sx) + init_bits[sigmap(SigBit(wire, i))] = value[i]; + } + } + TopoSort> cells; std::map> cell_to_inbit; std::map> outbit_to_cell; @@ -661,6 +673,17 @@ struct TechmapWorker bit = RTLIL::SigBit(RTLIL::State::Sx); parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const(); } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) { + auto sig = sigmap(conn.second); + RTLIL::Const value(State::Sx, sig.size()); + for (int i = 0; i < sig.size(); i++) { + auto it = init_bits.find(sig[i]); + if (it != init_bits.end()) { + value[i] = it->second; + } + } + parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value; + } } int unique_bit_id_counter = 0; @@ -861,12 +884,25 @@ struct TechmapWorker TechmapWires twd = techmap_find_special_wires(tpl); for (auto &it : twd) { - if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_") + if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_") log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str()); if (techmap_do_cache[tpl]) for (auto &it2 : it.second) if (!it2.value.is_fully_const()) log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value)); + if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache[tpl]) { + for (auto &it2 : it.second) { + auto val = it2.value.as_const(); + auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1)); + auto it = cell->connections().find(wirename); + if (it != cell->connections().end()) { + auto sig = sigmap(it->second); + for (int i = 0; i < sig.size(); i++) + if (val[i] == State::S1) + remove_init_bits.insert(sig[i]); + } + } + } techmap_wire_names.erase(it.first); } @@ -935,6 +971,25 @@ struct TechmapWorker handled_cells.insert(cell); } + if (!remove_init_bits.empty()) { + for (auto wire : module->wires()) + if (wire->attributes.count("\\init")) { + Const &value = wire->attributes.at("\\init"); + bool do_cleanup = true; + for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) { + SigBit bit = sigmap(SigBit(wire, i)); + if (remove_init_bits.count(bit)) + value[i] = State::Sx; + else if (value[i] != State::Sx) + do_cleanup = false; + } + if (do_cleanup) { + log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire)); + wire->attributes.erase("\\init"); + } + } + } + if (log_continue) { log_header(design, "Continuing TECHMAP pass.\n"); log_continue = false; @@ -1047,6 +1102,13 @@ struct TechmapPass : public Pass { log("\n"); log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n"); log("\n"); + log(" _TECHMAP_REMOVEINIT__\n"); + log(" When this wire is set to a constant value, the init attribute of the wire(s)\n"); + log(" connected to this port will be consumed. This wire must have the same\n"); + log(" width as the given port, and for every bit that is set to 1 in the value,\n"); + log(" the corresponding init attribute bit will be changed to 1'bx. If all\n"); + log(" bits of an init attribute are left as x, it will be removed.\n"); + log("\n"); log("In addition to this special wires, techmap also supports special parameters in\n"); log("modules in the map file:\n"); log("\n"); @@ -1060,6 +1122,13 @@ struct TechmapPass : public Pass { log(" former has a 1-bit for each constant input bit and the latter has the\n"); log(" value for this bit. The unused bits of the latter are set to undef (x).\n"); log("\n"); + log(" _TECHMAP_WIREINIT__\n"); + log(" When a parameter with this name exists, it will be set to the initial\n"); + log(" value of the wire(s) connected to the given port, as specified by the init\n"); + log(" attribute. If the attribute doesn't exist, x will be filled for the\n"); + log(" missing bits. To remove the init attribute bits used, use the\n"); + log(" _TECHMAP_REMOVEINIT_*_ wires.\n"); + log("\n"); log(" _TECHMAP_BITS_CONNMAP_\n"); log(" _TECHMAP_CONNMAP__\n"); log(" For an N-bit port, the _TECHMAP_CONNMAP__ parameter, if it\n"); -- cgit v1.2.3 From f72765090cd001ff4dc54d5a9c01a2d4b3339865 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 10 Sep 2019 16:31:50 +0000 Subject: Add -match-init option to dff2dffs. --- passes/techmap/dff2dffs.cc | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc index 0ea033513..3fa1ed5cf 100644 --- a/passes/techmap/dff2dffs.cc +++ b/passes/techmap/dff2dffs.cc @@ -34,11 +34,16 @@ struct Dff2dffsPass : public Pass { log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n"); log("dff2dffe for SR over CE priority.\n"); log("\n"); + log(" -match-init\n"); + log(" Disallow merging synchronous set/reset that has polarity opposite of the\n"); + log(" output wire's init attribute (if any).\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n"); + bool match_init = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -46,6 +51,10 @@ struct Dff2dffsPass : public Pass { // singleton_mode = true; // continue; // } + if (args[argidx] == "-match-init") { + match_init = true; + continue; + } break; } extra_args(args, argidx, design); @@ -96,9 +105,6 @@ struct Dff2dffsPass : public Pass { SigBit bit_b = sigmap(mux_cell->getPort(ID::B)); SigBit bit_s = sigmap(mux_cell->getPort(ID(S))); - log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell), - log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type)); - SigBit sr_val, sr_sig; bool invert_sr; sr_sig = bit_s; @@ -113,6 +119,23 @@ struct Dff2dffsPass : public Pass { invert_sr = false; } + if (match_init) { + SigBit bit_q = cell->getPort(ID(Q)); + if (bit_q.wire) { + auto it = bit_q.wire->attributes.find(ID(init)); + if (it != bit_q.wire->attributes.end()) { + auto init_val = it->second[bit_q.offset]; + if (init_val == State::S1 && sr_val != State::S1) + continue; + if (init_val == State::S0 && sr_val != State::S0) + continue; + } + } + } + + log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell), + log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type)); + if (sr_val == State::S1) { if (cell->type == ID($_DFF_N_)) { if (invert_sr) cell->type = ID($__DFFS_NN1_); -- cgit v1.2.3 From 9a73adde5016346078f336c296c2a54f44210246 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 16:18:05 -0700 Subject: Explicitly order function arguments --- passes/techmap/alumacc.cc | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 5b168d524..034731b87 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -48,14 +48,25 @@ struct AlumaccWorker RTLIL::SigSpec cached_cf, cached_of, cached_sf; RTLIL::SigSpec get_lt() { - if (GetSize(cached_lt) == 0) - cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf(); + if (GetSize(cached_lt) == 0) { + if (is_signed) { + get_of(); + get_sf(); + cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf); + } + else + cached_lt = get_cf(); + } return cached_lt; } RTLIL::SigSpec get_gt() { - if (GetSize(cached_gt) == 0) - cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute()); + if (GetSize(cached_gt) == 0) { + get_lt(); + get_eq(); + SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq); + cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute()); + } return cached_gt; } -- cgit v1.2.3 From c9f9518de4af34b2539d230c0894b04d174b755d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 28 Aug 2019 14:58:14 +0000 Subject: Added extractinv pass --- passes/techmap/Makefile.inc | 1 + passes/techmap/extractinv.cc | 123 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 passes/techmap/extractinv.cc (limited to 'passes/techmap') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 631a80aa5..cd357d72a 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -40,6 +40,7 @@ OBJS += passes/techmap/attrmap.o OBJS += passes/techmap/zinit.o OBJS += passes/techmap/dff2dffs.o OBJS += passes/techmap/flowmap.o +OBJS += passes/techmap/extractinv.o endif GENFILES += passes/techmap/techmap.inc diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc new file mode 100644 index 000000000..dda71f12a --- /dev/null +++ b/passes/techmap/extractinv.cc @@ -0,0 +1,123 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2019 Marcin Kościelnicki + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +void split_portname_pair(std::string &port1, std::string &port2) +{ + size_t pos = port1.find_first_of(':'); + if (pos != std::string::npos) { + port2 = port1.substr(pos+1); + port1 = port1.substr(0, pos); + } +} + +struct ExtractinvPass : public Pass { + ExtractinvPass() : Pass("extractinv", "extract explicit inverter cells for invertible cell pins") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" extractinv [options] [selection]\n"); + log("\n"); + log("Searches the design for all cells with invertible pins controlled by a cell\n"); + log("parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.\n"); + log("If the parameter was set to 1, inserts an explicit inverter cell in front of\n"); + log("the pin instead. Normally used for output to ISE, which does not support the\n"); + log("inversion parameters.\n"); + log("\n"); + log("To mark a cell port as invertible, use (* invertible_pin = \"param_name\" *)\n"); + log("on the wire in the blackbox module. The parameter value should have\n"); + log("the same width as the port, and will be effectively XORed with it.\n"); + log("\n"); + log(" -inv :\n"); + log(" Specifies the cell type to use for the inverters and its port names.\n"); + log(" This option is required.\n"); + log("\n"); + } + + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n"); + + std::string inv_celltype, inv_portname, inv_portname2; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + std::string arg = args[argidx]; + if (arg == "-inv" && argidx+2 < args.size()) { + inv_celltype = args[++argidx]; + inv_portname = args[++argidx]; + split_portname_pair(inv_portname, inv_portname2); + continue; + } + break; + } + extra_args(args, argidx, design); + + if (inv_celltype.empty()) + log_error("The -inv option is required.\n"); + + for (auto module : design->selected_modules()) + { + for (auto cell : module->selected_cells()) + for (auto port : cell->connections()) { + auto cell_module = design->module(cell->type); + if (!cell_module) + continue; + auto cell_wire = cell_module->wire(port.first); + if (!cell_wire) + continue; + auto it = cell_wire->attributes.find("\\invertible_pin"); + if (it == cell_wire->attributes.end()) + continue; + IdString param_name = RTLIL::escape_id(it->second.decode_string()); + auto it2 = cell->parameters.find(param_name); + // Inversion not used -- skip. + if (it2 == cell->parameters.end()) + continue; + SigSpec sig = port.second; + if (it2->second.size() != sig.size()) + log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name)); + RTLIL::Const invmask = it2->second; + cell->parameters.erase(param_name); + if (invmask.is_fully_zero()) + continue; + Wire *iwire = module->addWire(NEW_ID, sig.size()); + for (int i = 0; i < sig.size(); i++) + if (invmask[i] == State::S1) { + RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype)); + icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i)); + icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]); + log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i); + sig[i] = SigBit(iwire, i); + } + cell->setPort(port.first, sig); + } + } + } +} ExtractinvPass; + +PRIVATE_NAMESPACE_END -- cgit v1.2.3 From b76fac3ac3a815568827a03b201f386b2577e010 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 19 Sep 2019 19:26:09 +0200 Subject: Add techmap_autopurge attribute, fixes #1381 Signed-off-by: Clifford Wolf --- passes/techmap/techmap.cc | 54 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 49 insertions(+), 5 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 51a65aea6..cf40b2f17 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -206,10 +206,27 @@ struct TechmapWorker std::map positional_ports; dict temp_renamed_wires; + pool autopurge_tpl_bits; - for (auto &it : tpl->wires_) { + for (auto &it : tpl->wires_) + { if (it.second->port_id > 0) - positional_ports[stringf("$%d", it.second->port_id)] = it.first; + { + IdString posportname = stringf("$%d", it.second->port_id); + positional_ports[posportname] = it.first; + + if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) && + (!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) && + (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) + { + if (sigmaps.count(tpl) == 0) + sigmaps[tpl].set(tpl); + + for (auto bit : sigmaps.at(tpl)(it.second)) + if (bit.wire != nullptr) + autopurge_tpl_bits.insert(it.second); + } + } IdString w_name = it.second->name; apply_prefix(cell->name, w_name); RTLIL::Wire *w = module->wire(w_name); @@ -232,6 +249,8 @@ struct TechmapWorker w->port_input = false; w->port_output = false; w->port_id = 0; + if (!flatten_mode) + w->attributes.erase(ID(techmap_autopurge)); if (it.second->get_bool_attribute(ID(_techmap_special_))) w->attributes.clear(); if (w->attributes.count(ID(src))) @@ -362,11 +381,31 @@ struct TechmapWorker if (!flatten_mode && c->type.begins_with("\\$")) c->type = c->type.substr(1); - for (auto &it2 : c->connections_) { - apply_prefix(cell->name, it2.second, module); - port_signal_map.apply(it2.second); + vector autopurge_ports; + + for (auto &it2 : c->connections_) + { + bool autopurge = false; + if (!autopurge_tpl_bits.empty()) { + autopurge = GetSize(it2.second) != 0; + for (auto &bit : sigmaps.at(tpl)(it2.second)) + if (!autopurge_tpl_bits.count(bit)) { + autopurge = false; + break; + } + } + + if (autopurge) { + autopurge_ports.push_back(it2.first); + } else { + apply_prefix(cell->name, it2.second, module); + port_signal_map.apply(it2.second); + } } + for (auto &it2 : autopurge_ports) + c->unsetPort(it2); + if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) { IdString memid = c->getParam(ID(MEMID)).decode_string(); log_assert(memory_renames.count(memid) != 0); @@ -1064,6 +1103,11 @@ struct TechmapPass : public Pass { log("will create a wrapper for the cell and then run the command string that the\n"); log("attribute is set to on the wrapper module.\n"); log("\n"); + log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n"); + log("set, and that port is not connected in the instantiation that is mapped, then\n"); + log("then a cell port connected only to such wires will be omitted in the mapped\n"); + log("version of the circuit.\n"); + log("\n"); log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n"); log("or *._TECHMAP_* are special wires that are used to pass instructions from\n"); log("the mapping module to the techmap command. At the moment the following special\n"); -- cgit v1.2.3 From 567e5f0aa7816bf92e0f1cb885af6fa333863163 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 17:42:36 -0700 Subject: Fix first testcase in #1391 --- passes/techmap/abc9.cc | 2 +- passes/techmap/techmap.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7eac08d17..7715fb291 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -30,7 +30,7 @@ "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\ "&mfs; &ps -l" #else -#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l" +#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v -w; &mfs; &ps -l" #endif diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index cf40b2f17..3cc3edbcb 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -224,7 +224,7 @@ struct TechmapWorker for (auto bit : sigmaps.at(tpl)(it.second)) if (bit.wire != nullptr) - autopurge_tpl_bits.insert(it.second); + autopurge_tpl_bits.insert(bit); } } IdString w_name = it.second->name; -- cgit v1.2.3 From 72ce06909e87d1697ed5eac62d91db00a751a34b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 17:48:37 -0700 Subject: Trim mismatched connection to be same (smallest) size --- passes/techmap/techmap.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'passes/techmap') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 3cc3edbcb..1d0362ad6 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -359,6 +359,12 @@ struct TechmapWorker for (auto &attr : w->attributes) { if (attr.first == ID(src)) continue; + auto lhs = GetSize(extra_connect.first); + auto rhs = GetSize(extra_connect.second); + if (lhs > rhs) + extra_connect.first.remove(rhs, lhs-rhs); + else if (rhs > lhs) + extra_connect.second.remove(lhs, rhs-lhs); module->connect(extra_connect); break; } -- cgit v1.2.3 From ec08a031b548749bc3177ed3fdddcaf463043d26 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 17:52:23 -0700 Subject: Revert abc9.cc --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7715fb291..7eac08d17 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -30,7 +30,7 @@ "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\ "&mfs; &ps -l" #else -#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v -w; &mfs; &ps -l" +#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l" #endif -- cgit v1.2.3 From 44374b1b2b0dbc455c9e43d713e133d7d78a5e1a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 21:58:40 -0700 Subject: "abc_padding" attr for blackbox outputs that were padded, remove them later --- passes/techmap/abc9.cc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7eac08d17..aa473e67d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -606,7 +606,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri existing_cell = module->cell(c->name); log_assert(existing_cell); cell = module->addCell(remap_name(c->name), c->type); - module->swap_names(cell, existing_cell); } if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; @@ -642,8 +641,22 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } - for (auto cell : boxes) - module->remove(cell); + for (auto existing_cell : boxes) { + Cell *cell = module->cell(remap_name(existing_cell->name)); + if (cell) { + for (auto &conn : existing_cell->connections()) { + if (!conn.second.is_wire()) + continue; + Wire *wire = conn.second.as_wire(); + if (!wire->get_bool_attribute(ID(abc_padding))) + continue; + cell->unsetPort(conn.first); + log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second)); + } + module->swap_names(cell, existing_cell); + } + module->remove(existing_cell); + } // Copy connections (and rename) from mapped_mod to module for (auto conn : mapped_mod->connections()) { -- cgit v1.2.3 From fd0e3a2c43d96ba31beede9865d5000230029994 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Fri, 27 Sep 2019 11:03:04 +0200 Subject: Fix _TECHMAP_REMOVEINIT_ handling. Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396. --- passes/techmap/techmap.cc | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 1d0362ad6..08a1af2d5 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -935,19 +935,6 @@ struct TechmapWorker for (auto &it2 : it.second) if (!it2.value.is_fully_const()) log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value)); - if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache[tpl]) { - for (auto &it2 : it.second) { - auto val = it2.value.as_const(); - auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1)); - auto it = cell->connections().find(wirename); - if (it != cell->connections().end()) { - auto sig = sigmap(it->second); - for (int i = 0; i < sig.size(); i++) - if (val[i] == State::S1) - remove_init_bits.insert(sig[i]); - } - } - } techmap_wire_names.erase(it.first); } @@ -973,6 +960,23 @@ struct TechmapWorker mkdebug.off(); } + TechmapWires twd = techmap_find_special_wires(tpl); + for (auto &it : twd) { + if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") { + for (auto &it2 : it.second) { + auto val = it2.value.as_const(); + auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1)); + auto it = cell->connections().find(wirename); + if (it != cell->connections().end()) { + auto sig = sigmap(it->second); + for (int i = 0; i < sig.size(); i++) + if (val[i] == State::S1) + remove_init_bits.insert(sig[i]); + } + } + } + } + if (extern_mode && !in_recursion) { std::string m_name = stringf("$extern:%s", log_id(tpl)); -- cgit v1.2.3 From 3f70c1fd26eb109c2c4d899cce55f24bbf04acc1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 29 Sep 2019 13:22:11 +0200 Subject: Open aig frontend as binary file --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7eac08d17..7c764451f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -471,7 +471,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig"); - ifs.open(buffer); + ifs.open(buffer, std::ifstream::binary); if (ifs.fail()) log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); -- cgit v1.2.3