From 9dcf204dece518a48192a90ea962a9d630283e11 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 18 Feb 2020 08:41:48 -0800 Subject: TimingInfo: index by (port_name,offset) --- passes/techmap/abc9_ops.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index f7097fadb..e5de2bcc4 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -473,11 +473,11 @@ void prep_lut(RTLIL::Design *design, int maxlut) auto &t = timing.setup_module(module); - SigBit o; + TimingInfo::NameBit o; std::vector specify; for (const auto &i : t.comb) { auto &d = i.first.second; - if (o == SigBit()) + if (o == TimingInfo::NameBit()) o = d; else if (o != d) log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module)); @@ -581,7 +581,8 @@ void prep_box(RTLIL::Design *design, bool dff_mode) first = false; else ss << " "; - auto it = t.find(wire); + log_assert(GetSize(wire) == 1); + auto it = t.find(SigBit(wire,0)); if (it == t.end()) // Assume that no setup time means zero ss << 0; -- cgit v1.2.3