From a63e2508fcca395e795029d5c57c59acc63a9959 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 12:52:03 -0800
Subject: Add RTLIL::constpad, init by yosys_setup(); use for abc9

---
 passes/techmap/abc9.cc | 34 +++++++++-------------------------
 1 file changed, 9 insertions(+), 25 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 8cb34e523..486b9313b 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -22,20 +22,6 @@
 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
 // http://www.eecs.berkeley.edu/~alanmi/abc/
 
-#if 0
-// Based on &flow3 - better QoR but more experimental
-#define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
-						"&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
-						"&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
-						"&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
-						"&mfs; &ps -l"
-#else
-#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
-#endif
-
-
-#define ABC_FAST_COMMAND_LUT "&st; &if {W} {D}"
-
 #include "kernel/register.h"
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
@@ -292,7 +278,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		} else
 			abc9_script += stringf("source %s", script_file.c_str());
 	} else if (!lut_costs.empty() || !lut_file.empty()) {
-		abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
+		abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast")
+			: RTLIL::constpad.at("abc9.script.default");
 	} else
 		log_abort();
 
@@ -305,11 +292,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 	for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
 		abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
 
+	for (size_t pos = abc9_script.find("{C}"); pos != std::string::npos; pos = abc9_script.find("{C}", pos))
+		abc9_script = abc9_script.substr(0, pos) + design->scratchpad_get_string("abc9.if.C", "") + abc9_script.substr(pos+3);
+
 	if (nomfs)
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
 			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
 
-	abc9_script += stringf("; &write -n %s/output.aig", tempdir_name.c_str());
+	abc9_script += stringf("&ps -l; &write -n %s/output.aig", tempdir_name.c_str());
 	abc9_script = add_echos_to_abc9_cmd(abc9_script);
 
 	for (size_t i = 0; i+1 < abc9_script.size(); i++)
@@ -758,18 +748,15 @@ struct Abc9Pass : public Pass {
 		log("\n");
 		log("        if no -script parameter is given, the following scripts are used:\n");
 		log("\n");
-		log("        for -lut/-luts (only one LUT size):\n");
-		log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
-		log("\n");
-		log("        for -lut/-luts (different LUT sizes):\n");
-		log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
+		log("        for -lut/-luts:\n");
+		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default")).c_str());
 		log("\n");
 		log("    -fast\n");
 		log("        use different default scripts that are slightly faster (at the cost\n");
 		log("        of output quality):\n");
 		log("\n");
 		log("        for -lut/-luts:\n");
-		log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
+		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast")).c_str());
 		log("\n");
 		log("    -D <picoseconds>\n");
 		log("        set delay target. the string {D} in the default scripts above is\n");
@@ -883,9 +870,6 @@ struct Abc9Pass : public Pass {
 			}
 			if (arg == "-script" && argidx+1 < args.size()) {
 				script_file = args[++argidx];
-				rewrite_filename(script_file);
-				if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
-					script_file = std::string(pwd) + "/" + script_file;
 				continue;
 			}
 			if (arg == "-D" && argidx+1 < args.size()) {
-- 
cgit v1.2.3


From e230fd8afef6483d546cb38616e63b05d4d9b42a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 13:08:59 -0800
Subject: Fix {C} substitution

---
 passes/techmap/abc9.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 486b9313b..d03c24fdb 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -292,8 +292,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 	for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
 		abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
 
+	std::string C;
+	if (design->scratchpad.count("abc9.if.C"))
+		C = "-C " + design->scratchpad_get_string("abc9.if.C");
 	for (size_t pos = abc9_script.find("{C}"); pos != std::string::npos; pos = abc9_script.find("{C}", pos))
-		abc9_script = abc9_script.substr(0, pos) + design->scratchpad_get_string("abc9.if.C", "") + abc9_script.substr(pos+3);
+		abc9_script = abc9_script.substr(0, pos) + C + abc9_script.substr(pos+3);
 
 	if (nomfs)
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
-- 
cgit v1.2.3


From 050f03f15b01855d9c3bd6e98c4c47ebab607d57 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 8 Jan 2020 10:55:44 -0800
Subject: abc9: add time as last script command

---
 passes/techmap/abc9.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index d03c24fdb..652ccafaf 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -302,7 +302,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
 			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
 
-	abc9_script += stringf("&ps -l; &write -n %s/output.aig", tempdir_name.c_str());
+	abc9_script += stringf("&ps -l; &write -n %s/output.aig; time", tempdir_name.c_str());
 	abc9_script = add_echos_to_abc9_cmd(abc9_script);
 
 	for (size_t i = 0; i+1 < abc9_script.size(); i++)
-- 
cgit v1.2.3


From 0696b7bc9e4bd86eadd0e0b92696392cc5dc6172 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 8 Jan 2020 12:11:55 -0800
Subject: abc9: if -script value is a file, then source it, otherwise commands

---
 passes/techmap/abc9.cc | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 652ccafaf..5bcbb1611 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -267,16 +267,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 	abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
 
 	if (!script_file.empty()) {
-		if (script_file[0] == '+') {
-			for (size_t i = 1; i < script_file.size(); i++)
-				if (script_file[i] == '\'')
-					abc9_script += "'\\''";
-				else if (script_file[i] == ',')
-					abc9_script += " ";
-				else
-					abc9_script += script_file[i];
-		} else
+		if (check_file_exists(script_file))
 			abc9_script += stringf("source %s", script_file.c_str());
+		else {
+			if (script_file[0] == '+') {
+				for (size_t i = 1; i < script_file.size(); i++)
+					if (script_file[i] == '\'')
+						abc9_script += "'\\''";
+					else if (script_file[i] == ',')
+						abc9_script += " ";
+					else
+						abc9_script += script_file[i];
+			}
+			else
+				abc9_script += script_file;
+		}
 	} else if (!lut_costs.empty() || !lut_file.empty()) {
 		abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast")
 			: RTLIL::constpad.at("abc9.script.default");
@@ -302,7 +307,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
 			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
 
-	abc9_script += stringf("&ps -l; &write -n %s/output.aig; time", tempdir_name.c_str());
+	abc9_script += stringf("; &ps -l; &write -n %s/output.aig; time", tempdir_name.c_str());
 	abc9_script = add_echos_to_abc9_cmd(abc9_script);
 
 	for (size_t i = 0; i+1 < abc9_script.size(); i++)
@@ -924,7 +929,7 @@ struct Abc9Pass : public Pass {
 		extra_args(args, argidx, design);
 
 		rewrite_filename(script_file);
-		if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
+		if (!script_file.empty() && !is_absolute_path(script_file) && check_file_exists(script_file))
 			script_file = std::string(pwd) + "/" + script_file;
 
 		// handle -lut / -luts args
-- 
cgit v1.2.3


From 589ffead5cca63a55506eb3b291ffd025f0f9c0f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 8 Jan 2020 12:13:06 -0800
Subject: scratchpad entry abc9.if.R to &if -R

---
 passes/techmap/abc9.cc | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 5bcbb1611..3fdcc0e5c 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -303,6 +303,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 	for (size_t pos = abc9_script.find("{C}"); pos != std::string::npos; pos = abc9_script.find("{C}", pos))
 		abc9_script = abc9_script.substr(0, pos) + C + abc9_script.substr(pos+3);
 
+	std::string R;
+	if (design->scratchpad.count("abc9.if.R"))
+		C = "-C " + design->scratchpad_get_string("abc9.if.R");
+	for (size_t pos = abc9_script.find("{R}"); pos != std::string::npos; pos = abc9_script.find("{R}", pos))
+		abc9_script = abc9_script.substr(0, pos) + C + abc9_script.substr(pos+3);
+
 	if (nomfs)
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
 			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
-- 
cgit v1.2.3


From 67c9c41f7e566f5604a3e38e7ad402d6b5c80fd8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 17:10:54 -0800
Subject: Move abc9.* constpad entries to Abc9Pass::on_register()

---
 passes/techmap/abc9.cc | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3fdcc0e5c..3f05494c7 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -735,6 +735,43 @@ clone_lut:
 
 struct Abc9Pass : public Pass {
 	Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
+	void on_register() YS_OVERRIDE
+	{
+		RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
+		RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
+		RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
+		// Based on ABC's &flow
+		RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
+			/* Round 1 */ \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			"&st; &dsdb;" \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			"&st; &syn2 -m -R 10; &dsdb;" \
+			"&blut -a -K 6;" \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			/* Round 2 */ \
+			"&st; &sopb;" \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			"&st; &dsdb;" \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			"&st; &syn2 -m -R 10; &dsdb;" \
+			"&blut -a -K 6;" \
+			"&unmap; &if {C} {W} {D} {R} -v; &mfs";
+		// Based on ABC's &flow2
+		RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
+			/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+			/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+			"&load; &st; &sopb -R 10 -C 4; " \
+			/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+			/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
+			"&load";
+		// Based on ABC's &flow3
+		RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
+			"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
+			"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
+			"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
+			"&mfs";
+	}
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-- 
cgit v1.2.3


From ef3e84aac97565caff1f7d9bbce459d1592318ad Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 17:11:09 -0800
Subject: Revert "abc9: if -script value is a file, then source it, otherwise
 commands"

This reverts commit 0696b7bc9e4bd86eadd0e0b92696392cc5dc6172.
---
 passes/techmap/abc9.cc | 27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3f05494c7..e8988f699 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -267,21 +267,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 	abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
 
 	if (!script_file.empty()) {
-		if (check_file_exists(script_file))
+		if (script_file[0] == '+') {
+			for (size_t i = 1; i < script_file.size(); i++)
+				if (script_file[i] == '\'')
+					abc9_script += "'\\''";
+				else if (script_file[i] == ',')
+					abc9_script += " ";
+				else
+					abc9_script += script_file[i];
+		} else
 			abc9_script += stringf("source %s", script_file.c_str());
-		else {
-			if (script_file[0] == '+') {
-				for (size_t i = 1; i < script_file.size(); i++)
-					if (script_file[i] == '\'')
-						abc9_script += "'\\''";
-					else if (script_file[i] == ',')
-						abc9_script += " ";
-					else
-						abc9_script += script_file[i];
-			}
-			else
-				abc9_script += script_file;
-		}
 	} else if (!lut_costs.empty() || !lut_file.empty()) {
 		abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast")
 			: RTLIL::constpad.at("abc9.script.default");
@@ -313,7 +308,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
 			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
 
-	abc9_script += stringf("; &ps -l; &write -n %s/output.aig; time", tempdir_name.c_str());
+	abc9_script += stringf("&ps -l; &write -n %s/output.aig; time", tempdir_name.c_str());
 	abc9_script = add_echos_to_abc9_cmd(abc9_script);
 
 	for (size_t i = 0; i+1 < abc9_script.size(); i++)
@@ -972,7 +967,7 @@ struct Abc9Pass : public Pass {
 		extra_args(args, argidx, design);
 
 		rewrite_filename(script_file);
-		if (!script_file.empty() && !is_absolute_path(script_file) && check_file_exists(script_file))
+		if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
 			script_file = std::string(pwd) + "/" + script_file;
 
 		// handle -lut / -luts args
-- 
cgit v1.2.3


From ca70f9650336b4e58a13ab119e098f6494549f27 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 17:17:47 -0800
Subject: abc9.script.* constpad entries to start with '+'

---
 passes/techmap/abc9.cc | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index e8988f699..7039d4dd8 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -278,8 +278,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		} else
 			abc9_script += stringf("source %s", script_file.c_str());
 	} else if (!lut_costs.empty() || !lut_file.empty()) {
-		abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast")
-			: RTLIL::constpad.at("abc9.script.default");
+		abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)
+			: RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos);
 	} else
 		log_abort();
 
@@ -732,11 +732,11 @@ struct Abc9Pass : public Pass {
 	Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
 	void on_register() YS_OVERRIDE
 	{
-		RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
-		RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
-		RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
+		RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
+		RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
+		RTLIL::constpad["abc9.script.default.fast"] = "+&if {C} {W} {D} {R}";
 		// Based on ABC's &flow
-		RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
+		RTLIL::constpad["abc9.script.flow"] = "+&scorr; &sweep;" \
 			/* Round 1 */ \
 			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
 			"&st; &dsdb;" \
@@ -753,7 +753,7 @@ struct Abc9Pass : public Pass {
 			"&blut -a -K 6;" \
 			"&unmap; &if {C} {W} {D} {R} -v; &mfs";
 		// Based on ABC's &flow2
-		RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
+		RTLIL::constpad["abc9.script.flow2"] = "+&scorr; &sweep;" \
 			/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
 			/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
 			"&load; &st; &sopb -R 10 -C 4; " \
@@ -761,7 +761,7 @@ struct Abc9Pass : public Pass {
 			/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
 			"&load";
 		// Based on ABC's &flow3
-		RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
+		RTLIL::constpad["abc9.script.flow3"] = "+&scorr; &sweep;" \
 			"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
 			"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
 			"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
-- 
cgit v1.2.3


From 32946a402de068ba052e0af9564959cf746fbf91 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 17:35:13 -0800
Subject: abc9: start post-fix with semicolon

---
 passes/techmap/abc9.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 7039d4dd8..fb0c547a3 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -308,7 +308,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
 			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
 
-	abc9_script += stringf("&ps -l; &write -n %s/output.aig; time", tempdir_name.c_str());
+	abc9_script += stringf("; &ps -l; &write -n %s/output.aig; time", tempdir_name.c_str());
 	abc9_script = add_echos_to_abc9_cmd(abc9_script);
 
 	for (size_t i = 0; i+1 < abc9_script.size(); i++)
-- 
cgit v1.2.3


From 8b6309747b302f11046be029d5f224ba891d0461 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 17:49:56 -0800
Subject: Add '-v' to &if for abc9.script.default.fast

---
 passes/techmap/abc9.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index fb0c547a3..aed662fc5 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -734,7 +734,7 @@ struct Abc9Pass : public Pass {
 	{
 		RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
 		RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
-		RTLIL::constpad["abc9.script.default.fast"] = "+&if {C} {W} {D} {R}";
+		RTLIL::constpad["abc9.script.default.fast"] = "+&if {C} {W} {D} {R} -v";
 		// Based on ABC's &flow
 		RTLIL::constpad["abc9.script.flow"] = "+&scorr; &sweep;" \
 			/* Round 1 */ \
-- 
cgit v1.2.3


From e378902f939c24cb8f6cbff29c3f508a4655f3ab Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 18:16:58 -0800
Subject: Tune abc9.script.flow

---
 passes/techmap/abc9.cc | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index aed662fc5..b828404bc 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -737,21 +737,29 @@ struct Abc9Pass : public Pass {
 		RTLIL::constpad["abc9.script.default.fast"] = "+&if {C} {W} {D} {R} -v";
 		// Based on ABC's &flow
 		RTLIL::constpad["abc9.script.flow"] = "+&scorr; &sweep;" \
+			"&dch -C 500;" \
 			/* Round 1 */ \
-			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
 			"&st; &dsdb;" \
-			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
 			"&st; &syn2 -m -R 10; &dsdb;" \
 			"&blut -a -K 6;" \
-			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
 			/* Round 2 */ \
 			"&st; &sopb;" \
-			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
 			"&st; &dsdb;" \
-			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
 			"&st; &syn2 -m -R 10; &dsdb;" \
 			"&blut -a -K 6;" \
-			"&unmap; &if {C} {W} {D} {R} -v; &mfs";
+			/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
+			/* Round 3 */ \
+			/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
+			"&st; &dsdb;" \
+			/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
+			"&st; &syn2 -m -R 10; &dsdb;" \
+			"&blut -a -K 6;" \
+			/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;";
 		// Based on ABC's &flow2
 		RTLIL::constpad["abc9.script.flow2"] = "+&scorr; &sweep;" \
 			/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-- 
cgit v1.2.3


From d1f8371481b787b3cc6948a7165b7c191e4b4c64 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 10 Jan 2020 10:00:09 -0800
Subject: abc9: fix typos

---
 passes/techmap/abc9.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index b828404bc..22f5a1f3a 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -300,9 +300,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 
 	std::string R;
 	if (design->scratchpad.count("abc9.if.R"))
-		C = "-C " + design->scratchpad_get_string("abc9.if.R");
+		R = "-R " + design->scratchpad_get_string("abc9.if.R");
 	for (size_t pos = abc9_script.find("{R}"); pos != std::string::npos; pos = abc9_script.find("{R}", pos))
-		abc9_script = abc9_script.substr(0, pos) + C + abc9_script.substr(pos+3);
+		abc9_script = abc9_script.substr(0, pos) + R + abc9_script.substr(pos+3);
 
 	if (nomfs)
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
@@ -803,14 +803,14 @@ struct Abc9Pass : public Pass {
 		log("        if no -script parameter is given, the following scripts are used:\n");
 		log("\n");
 		log("        for -lut/-luts:\n");
-		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default")).c_str());
+		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default")).c_str()+1);
 		log("\n");
 		log("    -fast\n");
 		log("        use different default scripts that are slightly faster (at the cost\n");
 		log("        of output quality):\n");
 		log("\n");
 		log("        for -lut/-luts:\n");
-		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast")).c_str());
+		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast")).c_str()+1);
 		log("\n");
 		log("    -D <picoseconds>\n");
 		log("        set delay target. the string {D} in the default scripts above is\n");
-- 
cgit v1.2.3


From 291530c59f639609bc7534e561f28c9fb4081e19 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 10 Jan 2020 15:04:13 -0800
Subject: abc9: add abc9.verify and abc9.debug options

---
 passes/techmap/abc9.cc | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 22f5a1f3a..3ce435dd0 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -308,7 +308,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
 			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
 
-	abc9_script += stringf("; &ps -l; &write -n %s/output.aig; time", tempdir_name.c_str());
+	abc9_script += stringf("; &ps -l; &write -n %s/output.aig;", tempdir_name.c_str());
+	if (design->scratchpad_get_bool("abc9.debug")) {
+		if (dff_mode)
+			abc9_script += "verify -s;";
+		else
+			abc9_script += "verify;";
+	}
+	abc9_script += "time";
 	abc9_script = add_echos_to_abc9_cmd(abc9_script);
 
 	for (size_t i = 0; i+1 < abc9_script.size(); i++)
@@ -910,6 +917,11 @@ struct Abc9Pass : public Pass {
 		}
 		nomfs = design->scratchpad_get_bool("abc9.nomfs", nomfs);
 
+		if (design->scratchpad_get_bool("abc9.debug")) {
+			cleanup = false;
+			show_tempdir = true;
+		}
+
 		size_t argidx;
 		char pwd [PATH_MAX];
 		if (!getcwd(pwd, sizeof(pwd))) {
-- 
cgit v1.2.3


From ed2aeb498eb7bbe028ece4adf96b94bacd0b3ef0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 10 Jan 2020 15:09:42 -0800
Subject: Copy-pasta

---
 passes/techmap/abc9.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3ce435dd0..387d9b644 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -309,7 +309,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
 
 	abc9_script += stringf("; &ps -l; &write -n %s/output.aig;", tempdir_name.c_str());
-	if (design->scratchpad_get_bool("abc9.debug")) {
+	if (design->scratchpad_get_bool("abc9.verify")) {
 		if (dff_mode)
 			abc9_script += "verify -s;";
 		else
-- 
cgit v1.2.3


From c8206823141aa54b6151c57548fdb73211157451 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 11 Jan 2020 12:11:35 -0800
Subject: abc9: fix help message, found by @nakengelhardt

---
 passes/techmap/abc9.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 387d9b644..ec80e098f 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -810,14 +810,14 @@ struct Abc9Pass : public Pass {
 		log("        if no -script parameter is given, the following scripts are used:\n");
 		log("\n");
 		log("        for -lut/-luts:\n");
-		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default")).c_str()+1);
+		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str());
 		log("\n");
 		log("    -fast\n");
 		log("        use different default scripts that are slightly faster (at the cost\n");
 		log("        of output quality):\n");
 		log("\n");
 		log("        for -lut/-luts:\n");
-		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast")).c_str()+1);
+		log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
 		log("\n");
 		log("    -D <picoseconds>\n");
 		log("        set delay target. the string {D} in the default scripts above is\n");
-- 
cgit v1.2.3


From 556ed0e18ac00e4ec19e127f33ccf3550be78186 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 11 Jan 2020 17:05:30 -0800
Subject: MIssed this merge conflict

---
 passes/techmap/abc9.cc | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index bd4e506ac..8a6195741 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -304,10 +304,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 	for (size_t pos = abc9_script.find("{R}"); pos != std::string::npos; pos = abc9_script.find("{R}", pos))
 		abc9_script = abc9_script.substr(0, pos) + R + abc9_script.substr(pos+3);
 
-	if (nomfs)
-		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
-			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
-
 	abc9_script += stringf("; &ps -l; &write -n %s/output.aig;", tempdir_name.c_str());
 	if (design->scratchpad_get_bool("abc9.verify")) {
 		if (dff_mode)
-- 
cgit v1.2.3


From 808b388e34f3cededd450de35555476874cf2799 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 09:43:57 -0800
Subject: abc9: log which module is being operated on

---
 passes/techmap/abc9.cc     | 4 +++-
 passes/techmap/abc9_exe.cc | 4 ----
 2 files changed, 3 insertions(+), 5 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2ded1c162..2e3df773e 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -276,9 +276,11 @@ struct Abc9Pass : public ScriptPass
 					run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
 
 					int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
-					log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
+
+					log("Extracted %d AND gates and %d wires from module `%s' to a netlist network with %d inputs and %d outputs.\n",
 							active_design->scratchpad_get_int("write_xaiger.num_ands"),
 							active_design->scratchpad_get_int("write_xaiger.num_wires"),
+							log_id(mod),
 							active_design->scratchpad_get_int("write_xaiger.num_inputs"),
 							num_outputs);
 					if (num_outputs) {
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc
index c1687ef97..a2acfac91 100644
--- a/passes/techmap/abc9_exe.cc
+++ b/passes/techmap/abc9_exe.cc
@@ -168,10 +168,6 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
 		std::string wire_delay, std::string tempdir_name
 )
 {
-	//FIXME:
-	//log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
-	//		module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
-
 	std::string abc9_script;
 
 	if (!lut_costs.empty())
-- 
cgit v1.2.3


From 766e16b525d5ab23e451be1e4183cf82560dc8da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 17:34:37 -0800
Subject: read_aiger: make $and/$not/$lut the prefix not suffix

---
 passes/techmap/abc9.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 8a6195741..1f6cdaa22 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -348,7 +348,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
 		log_assert(!design->module(ID($__abc9__)));
 		{
-			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, /*buffer.c_str()*/ "" /* map_filename */, true /* wideports */);
+			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
 			reader.parse_xaiger();
 		}
 		ifs.close();
@@ -472,16 +472,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 						// (TODO: Optimise by not cloning unless will increase depth)
 						RTLIL::IdString driver_name;
 						if (GetSize(a_bit.wire) == 1)
-							driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
+							driver_name = stringf("$lut%s", a_bit.wire->name.c_str());
 						else
-							driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
+							driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset);
 						driver_lut = mapped_mod->cell(driver_name);
 					}
 
 					if (!driver_lut) {
 						// If a driver couldn't be found (could be from PI or box CI)
 						// then implement using a LUT
-						cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
+						cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())),
 								RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
 								RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
 								RTLIL::Const::from_string("01"));
-- 
cgit v1.2.3


From a6d4ea74634826741f09793c36d596f2fa239f62 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 19:21:11 -0800
Subject: abc9: respect (* keep *) on cells

---
 passes/techmap/abc9_ops.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index cc22fd474..9cc58c99d 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -489,6 +489,8 @@ void reintegrate(RTLIL::Module *module)
 
 	std::vector<Cell*> boxes;
 	for (auto cell : module->cells().to_vector()) {
+		if (cell->has_keep_attr())
+			continue;
 		if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
 			module->remove(cell);
 		else if (cell->attributes.erase("\\abc9_box_seq"))
-- 
cgit v1.2.3


From a2c4d98da70744253ccbe253083ef9df5fa39305 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 19:22:23 -0800
Subject: abc9: add -run option

---
 passes/techmap/abc9.cc | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2e3df773e..2627ab9ca 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -91,6 +91,11 @@ struct Abc9Pass : public ScriptPass
 		log("tool [1] for technology mapping of the current design to a target FPGA\n");
 		log("architecture. Only fully-selected modules are supported.\n");
 		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
 		log("    -exe <command>\n");
 #ifdef ABCEXTERNAL
 		log("        use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
@@ -210,13 +215,21 @@ struct Abc9Pass : public ScriptPass
 			}
 			if (arg == "-dff") {
 				dff_mode = true;
-                exe_cmd << " " << arg;
+				exe_cmd << " " << arg;
 				continue;
 			}
 			if (arg == "-nocleanup") {
 				cleanup = false;
 				continue;
 			}
+			if (arg == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
-- 
cgit v1.2.3


From 2c65e1abacc4401c4fd3e9b48f52c4de120bc511 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 21:45:27 -0800
Subject: abc9: break SCC by setting (* keep *) on output wires

---
 passes/techmap/abc9.cc     |  2 +-
 passes/techmap/abc9_ops.cc | 29 ++++-------------------------
 2 files changed, 5 insertions(+), 26 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2627ab9ca..dad40be63 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -298,7 +298,7 @@ struct Abc9Pass : public ScriptPass
 							num_outputs);
 					if (num_outputs) {
 						run(stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str()));
-						run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod->name), tempdir_name.c_str(), tempdir_name.c_str()));
+						run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
 						run("abc9_ops -reintegrate");
 					}
 					else
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 9cc58c99d..4da10d94b 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -53,30 +53,7 @@ void break_scc(RTLIL::Module *module)
 			if (cell->output(c.first)) {
 				SigBit b = c.second.as_bit();
 				Wire *w = b.wire;
-				if (w->port_input) {
-					// In this case, hopefully the loop break has been already created
-					// Get the non-prefixed wire
-					Wire *wo = module->wire(stringf("%s.abco", b.wire->name.c_str()));
-					log_assert(wo != nullptr);
-					log_assert(wo->port_output);
-					log_assert(b.offset < GetSize(wo));
-					c.second = RTLIL::SigBit(wo, b.offset);
-				}
-				else {
-					// Create a new output/input loop break
-					w->port_input = true;
-					w = module->wire(stringf("%s.abco", w->name.c_str()));
-					if (!w) {
-						w = module->addWire(stringf("%s.abco", b.wire->name.c_str()), GetSize(b.wire));
-						w->port_output = true;
-					}
-					else {
-						log_assert(w->port_input);
-						log_assert(b.offset < GetSize(w));
-					}
-					w->set_bool_attribute(ID(abc9_scc_break));
-					c.second = RTLIL::SigBit(w, b.offset);
-				}
+				w->set_bool_attribute(ID::keep);
 			}
 		}
 	}
@@ -586,7 +563,9 @@ void reintegrate(RTLIL::Module *module)
 				}
 				if (cell->output(mapped_conn.first))
 					for (auto i : mapped_conn.second)
-						bit_drivers[i].insert(mapped_cell->name);
+						// Ignore inouts for topo ordering
+						if (i.wire && !(i.wire->port_input && i.wire->port_output))
+							bit_drivers[i].insert(mapped_cell->name);
 			}
 		}
 		else {
-- 
cgit v1.2.3


From b678b15c6d0d14580ca18e89f86926eabf8fead0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 23:33:37 -0800
Subject: abc9_ops: ignore inouts of all cell outputs for topo ordering

---
 passes/techmap/abc9_ops.cc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 4da10d94b..d7ebfdf3f 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -488,7 +488,9 @@ void reintegrate(RTLIL::Module *module)
 			RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
 			RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
 			bit_users[a_bit].insert(mapped_cell->name);
-			bit_drivers[y_bit].insert(mapped_cell->name);
+			// Ignore inouts for topo ordering
+			if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
+				bit_drivers[y_bit].insert(mapped_cell->name);
 
 			if (!a_bit.wire) {
 				mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
@@ -598,7 +600,9 @@ void reintegrate(RTLIL::Module *module)
 				for (const auto &i : inputs)
 					bit_users[i].insert(mapped_cell->name);
 				for (const auto &i : outputs)
-					bit_drivers[i].insert(mapped_cell->name);
+					// Ignore inouts for topo ordering
+					if (i.wire && !(i.wire->port_input && i.wire->port_output))
+						bit_drivers[i].insert(mapped_cell->name);
 			}
 
 			int input_count = 0, output_count = 0;
-- 
cgit v1.2.3


From 531fddf797a79b46df3e462112ca68ff50e6a18e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 23:42:27 -0800
Subject: abc9_ops: -break_scc -> -mark_scc using (* keep *), remove
 -unbreak_scc

---
 passes/techmap/abc9.cc     |  7 ++----
 passes/techmap/abc9_ops.cc | 59 ++++++++++++++--------------------------------
 2 files changed, 20 insertions(+), 46 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index dad40be63..c7fe05795 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -244,9 +244,9 @@ struct Abc9Pass : public ScriptPass
 		if (check_label("pre")) {
 			run("scc -set_attr abc9_scc_id {}");
 			if (help_mode)
-				run("abc9_ops -break_scc -prep_holes [-dff]", "(option for -dff)");
+				run("abc9_ops -mark_scc -prep_holes [-dff]", "(option for -dff)");
 			else
-				run("abc9_ops -break_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
+				run("abc9_ops -mark_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
 			run("select -set abc9_holes A:abc9_holes");
 			run("flatten -wb @abc9_holes");
 			run("techmap @abc9_holes");
@@ -315,9 +315,6 @@ struct Abc9Pass : public ScriptPass
 				active_design->selection_stack.pop_back();
 			}
 		}
-
-		if (check_label("post"))
-			run("abc9_ops -unbreak_scc");
 	}
 } Abc9Pass;
 
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index d7ebfdf3f..c7236486f 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -33,7 +33,7 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
 	return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
 }
 
-void break_scc(RTLIL::Module *module)
+void mark_scc(RTLIL::Module *module)
 {
 	// For every unique SCC found, (arbitrarily) find the first
 	//   cell in the component, and convert all wires driven by
@@ -44,7 +44,8 @@ void break_scc(RTLIL::Module *module)
 		auto it = cell->attributes.find(ID(abc9_scc_id));
 		if (it == cell->attributes.end())
 			continue;
-		auto r = ids_seen.insert(it->second);
+		auto id = it->second;
+		auto r = ids_seen.insert(id);
 		cell->attributes.erase(it);
 		if (!r.second)
 			continue;
@@ -54,6 +55,7 @@ void break_scc(RTLIL::Module *module)
 				SigBit b = c.second.as_bit();
 				Wire *w = b.wire;
 				w->set_bool_attribute(ID::keep);
+				w->attributes[ID(abc9_scc_id)] = id.as_int();
 			}
 		}
 	}
@@ -61,28 +63,6 @@ void break_scc(RTLIL::Module *module)
 	module->fixup_ports();
 }
 
-void unbreak_scc(RTLIL::Module *module)
-{
-	// Now 'unexpose' those wires by undoing
-	// the expose operation -- remove them from PO/PI
-	// and re-connecting them back together
-	for (auto wire : module->wires()) {
-		auto it = wire->attributes.find(ID(abc9_scc_break));
-		if (it != wire->attributes.end()) {
-			wire->attributes.erase(it);
-			log_assert(wire->port_output);
-			wire->port_output = false;
-			std::string name = wire->name.str();
-			RTLIL::Wire *i_wire = module->wire(name.substr(0, GetSize(name) - 5));
-			log_assert(i_wire);
-			log_assert(i_wire->port_input);
-			i_wire->port_input = false;
-			module->connect(i_wire, wire);
-		}
-	}
-	module->fixup_ports();
-}
-
 void prep_dff(RTLIL::Module *module)
 {
 	auto design = module->design;
@@ -676,21 +656,25 @@ void reintegrate(RTLIL::Module *module)
 
 	// Stitch in mapped_mod's inputs/outputs into module
 	for (auto port : mapped_mod->ports) {
-		RTLIL::Wire *w = mapped_mod->wire(port);
+		RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
 		RTLIL::Wire *wire = module->wire(port);
 		log_assert(wire);
+		if (wire->attributes.erase(ID(abc9_scc_id))) {
+			auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
+			log_assert(r);
+		}
 		RTLIL::Wire *remap_wire = module->wire(remap_name(port));
 		RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
 		log_assert(GetSize(signal) >= GetSize(remap_wire));
 
 		RTLIL::SigSig conn;
-		if (w->port_output) {
+		if (mapped_wire->port_output) {
 			conn.first = signal;
 			conn.second = remap_wire;
 			out_wires++;
 			module->connect(conn);
 		}
-		else if (w->port_input) {
+		else if (mapped_wire->port_input) {
 			conn.first = remap_wire;
 			conn.second = signal;
 			in_wires++;
@@ -791,8 +775,7 @@ struct Abc9OpsPass : public Pass {
 	{
 		log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
 
-		bool break_scc_mode = false;
-		bool unbreak_scc_mode = false;
+		bool mark_scc_mode = false;
 		bool prep_dff_mode = false;
 		bool prep_holes_mode = false;
 		bool reintegrate_mode = false;
@@ -801,12 +784,8 @@ struct Abc9OpsPass : public Pass {
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
-			if (arg == "-break_scc") {
-				break_scc_mode = true;
-				continue;
-			}
-			if (arg == "-unbreak_scc") {
-				unbreak_scc_mode = true;
+			if (arg == "-mark_scc") {
+				mark_scc_mode = true;
 				continue;
 			}
 			if (arg == "-prep_dff") {
@@ -829,8 +808,8 @@ struct Abc9OpsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (!(break_scc_mode || unbreak_scc_mode || prep_dff_mode || reintegrate_mode))
-			log_cmd_error("At least one of -{,un}break_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
+		if (!(mark_scc_mode || prep_dff_mode || reintegrate_mode))
+			log_cmd_error("At least one of -mark_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
 
 		if (dff_mode && !prep_holes_mode)
 			log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
@@ -847,10 +826,8 @@ struct Abc9OpsPass : public Pass {
 			if (!design->selected_whole_module(mod))
 				log_error("Can't handle partially selected module %s!\n", log_id(mod));
 
-			if (break_scc_mode)
-				break_scc(mod);
-			if (unbreak_scc_mode)
-				unbreak_scc(mod);
+			if (mark_scc_mode)
+				mark_scc(mod);
 			if (prep_dff_mode)
 				prep_dff(mod);
 			if (prep_holes_mode)
-- 
cgit v1.2.3


From 468386d67d902722562e9a0412a76fca79ec4fa2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 12:25:45 -0800
Subject: abc9_ops: -prep_holes -> -prep_xaiger, move padding to write_xaiger

---
 passes/techmap/abc9.cc     |   4 +-
 passes/techmap/abc9_ops.cc | 173 +++++++++++++++++++--------------------------
 2 files changed, 73 insertions(+), 104 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index c7fe05795..6a296bfe7 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -244,9 +244,9 @@ struct Abc9Pass : public ScriptPass
 		if (check_label("pre")) {
 			run("scc -set_attr abc9_scc_id {}");
 			if (help_mode)
-				run("abc9_ops -mark_scc -prep_holes [-dff]", "(option for -dff)");
+				run("abc9_ops -mark_scc -prep_xaiger [-dff]", "(option for -dff)");
 			else
-				run("abc9_ops -mark_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
+				run("abc9_ops -mark_scc -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
 			run("select -set abc9_holes A:abc9_holes");
 			run("flatten -wb @abc9_holes");
 			run("techmap @abc9_holes");
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index cc82a72cf..405f3e267 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -143,7 +143,7 @@ void prep_dff(RTLIL::Module *module)
 	}
 }
 
-void prep_holes(RTLIL::Module *module, bool dff)
+void prep_xaiger(RTLIL::Module *module, bool dff)
 {
 	auto design = module->design;
 	log_assert(design);
@@ -152,7 +152,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
 
 	dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 	TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
-	bool abc9_box_seen = false;
+	dict<IdString, std::vector<IdString>> box_ports;
 
 	for (auto cell : module->cells()) {
 		if (cell->type == "$__ABC9_FF_")
@@ -165,7 +165,40 @@ void prep_holes(RTLIL::Module *module, bool dff)
 			abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
 			if (abc9_flop && !dff)
 				continue;
-			abc9_box_seen = abc9_box;
+
+			auto r = box_ports.insert(cell->type);
+			if (r.second) {
+				// Make carry in the last PI, and carry out the last PO
+				//   since ABC requires it this way
+				IdString carry_in, carry_out;
+				for (const auto &port_name : inst_module->ports) {
+					auto w = inst_module->wire(port_name);
+					log_assert(w);
+					if (w->get_bool_attribute("\\abc9_carry")) {
+						if (w->port_input) {
+							if (carry_in != IdString())
+								log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(inst_module));
+							carry_in = port_name;
+						}
+						if (w->port_output) {
+							if (carry_out != IdString())
+								log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(inst_module));
+							carry_out = port_name;
+						}
+					}
+					else
+						r.first->second.push_back(port_name);
+				}
+
+				if (carry_in != IdString() && carry_out == IdString())
+					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(inst_module));
+				if (carry_in == IdString() && carry_out != IdString())
+					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(inst_module));
+				if (carry_in != IdString()) {
+					r.first->second.push_back(carry_in);
+					r.first->second.push_back(carry_out);
+				}
+			}
 		}
 		else if (!yosys_celltypes.cell_known(cell->type))
 			continue;
@@ -183,7 +216,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
 		toposort.node(cell->name);
 	}
 
-	if (!abc9_box_seen)
+	if (box_ports.empty())
 		return;
 
 	for (auto &it : bit_users)
@@ -211,7 +244,13 @@ void prep_holes(RTLIL::Module *module, bool dff)
 
 	log_assert(no_loops);
 
-	vector<Cell*> box_list;
+	RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
+	log_assert(holes_module);
+	holes_module->set_bool_attribute("\\abc9_holes");
+
+	dict<IdString, Cell*> cell_cache;
+
+	int port_id = 1, box_count = 0;
 	for (auto cell_name : toposort.sorted) {
 		RTLIL::Cell *cell = module->cell(cell_name);
 		log_assert(cell);
@@ -220,62 +259,10 @@ void prep_holes(RTLIL::Module *module, bool dff)
 		if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
 			continue;
 
-		bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
-
-		// Fully pad all unused input connections of this box cell with S0
-		// Fully pad all undriven output connections of this box cell with anonymous wires
-		for (const auto &port_name : box_module->ports) {
-			RTLIL::Wire* w = box_module->wire(port_name);
-			log_assert(w);
-			auto it = cell->connections_.find(port_name);
-			if (w->port_input) {
-				RTLIL::SigSpec rhs;
-				if (it != cell->connections_.end()) {
-					if (GetSize(it->second) < GetSize(w))
-						it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
-					rhs = it->second;
-				}
-				else {
-					rhs = RTLIL::SigSpec(State::S0, GetSize(w));
-					cell->setPort(port_name, rhs);
-				}
-			}
-			if (w->port_output) {
-				RTLIL::SigSpec rhs;
-				auto it = cell->connections_.find(w->name);
-				if (it != cell->connections_.end()) {
-					if (GetSize(it->second) < GetSize(w))
-						it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
-					rhs = it->second;
-				}
-				else {
-					Wire *wire = module->addWire(NEW_ID, GetSize(w));
-					if (blackbox)
-						wire->set_bool_attribute(ID(abc9_padding));
-					rhs = wire;
-					cell->setPort(port_name, rhs);
-				}
-			}
-		}
-
-		cell->attributes["\\abc9_box_seq"] = box_list.size();
-		box_list.emplace_back(cell);
-	}
-	log_assert(!box_list.empty());
-
-	RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
-	log_assert(holes_module);
-	holes_module->set_bool_attribute("\\abc9_holes");
+		cell->attributes["\\abc9_box_seq"] = box_count++;
 
-	dict<IdString, Cell*> cell_cache;
-	dict<IdString, std::vector<IdString>> box_ports;
-
-	int port_id = 1;
-	for (auto cell : box_list) {
-		RTLIL::Module* orig_box_module = design->module(cell->type);
-		log_assert(orig_box_module);
-		IdString derived_name = orig_box_module->derive(design, cell->parameters);
-		RTLIL::Module* box_module = design->module(derived_name);
+		IdString derived_name = box_module->derive(design, cell->parameters);
+		box_module = design->module(derived_name);
 
 		auto r = cell_cache.insert(derived_name);
 		auto &holes_cell = r.first->second;
@@ -283,40 +270,6 @@ void prep_holes(RTLIL::Module *module, bool dff)
 			if (box_module->has_processes())
 				Pass::call_on_module(design, box_module, "proc");
 
-			auto r2 = box_ports.insert(cell->type);
-			if (r2.second) {
-				// Make carry in the last PI, and carry out the last PO
-				//   since ABC requires it this way
-				IdString carry_in, carry_out;
-				for (const auto &port_name : box_module->ports) {
-					auto w = box_module->wire(port_name);
-					log_assert(w);
-					if (w->get_bool_attribute("\\abc9_carry")) {
-						if (w->port_input) {
-							if (carry_in != IdString())
-								log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
-							carry_in = port_name;
-						}
-						if (w->port_output) {
-							if (carry_out != IdString())
-								log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
-							carry_out = port_name;
-						}
-					}
-					else
-						r2.first->second.push_back(port_name);
-				}
-
-				if (carry_in != IdString() && carry_out == IdString())
-					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
-				if (carry_in == IdString() && carry_out != IdString())
-					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
-				if (carry_in != IdString()) {
-					r2.first->second.push_back(carry_in);
-					r2.first->second.push_back(carry_out);
-				}
-			}
-
 			if (box_module->get_bool_attribute("\\whitebox")) {
 				holes_cell = holes_module->addCell(cell->name, derived_name);
 
@@ -770,6 +723,22 @@ struct Abc9OpsPass : public Pass {
 		log("\n");
 		log("    abc9_ops [options] [selection]\n");
 		log("\n");
+		log("This pass contains a set of supporting operations for use during ABC technology\n");
+		log("mapping, and is expected to be called in conjunction with other operations from\n");
+		log("the `abc9' script pass. Only fully-selected modules are supported.\n");
+		log("\n");
+		log("    -mark_scc\n");
+		log("        for an arbitrarily chosen cell in each unique SCC of each selected module\n");
+		log("        (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
+		log("        wires driven by this cell's outputs with a (* keep *) attribute in order\n");
+		log("        to break the SCC. this temporary attribute will be removed on -reintegrate.\n");
+		log("\n");
+		log("    -prep_xaiger\n");
+		log("        prepare the design for XAIGER output. this includes computing the\n");
+		log("        topological ordering of ABC9 boxes, as well as preparing the\n");
+		log("        '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
+		log("        whiteboxes.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -777,7 +746,7 @@ struct Abc9OpsPass : public Pass {
 
 		bool mark_scc_mode = false;
 		bool prep_dff_mode = false;
-		bool prep_holes_mode = false;
+		bool prep_xaiger_mode = false;
 		bool reintegrate_mode = false;
 		bool dff_mode = false;
 
@@ -792,8 +761,8 @@ struct Abc9OpsPass : public Pass {
 				prep_dff_mode = true;
 				continue;
 			}
-			if (arg == "-prep_holes") {
-				prep_holes_mode = true;
+			if (arg == "-prep_xaiger") {
+				prep_xaiger_mode = true;
 				continue;
 			}
 			if (arg == "-reintegrate") {
@@ -809,10 +778,10 @@ struct Abc9OpsPass : public Pass {
 		extra_args(args, argidx, design);
 
 		if (!(mark_scc_mode || prep_dff_mode || reintegrate_mode))
-			log_cmd_error("At least one of -mark_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
+			log_cmd_error("At least one of -mark_scc, -prep_{xaiger,dff}, -reintegrate must be specified.\n");
 
-		if (dff_mode && !prep_holes_mode)
-			log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
+		if (dff_mode && !prep_xaiger_mode)
+			log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
 
 		for (auto mod : design->selected_modules()) {
 			if (mod->get_bool_attribute("\\abc9_holes"))
@@ -830,8 +799,8 @@ struct Abc9OpsPass : public Pass {
 				mark_scc(mod);
 			if (prep_dff_mode)
 				prep_dff(mod);
-			if (prep_holes_mode)
-				prep_holes(mod, dff_mode);
+			if (prep_xaiger_mode)
+				prep_xaiger(mod, dff_mode);
 			if (reintegrate_mode)
 				reintegrate(mod);
 		}
-- 
cgit v1.2.3


From 654247abe9078566f93960a135ce08b0cfc96442 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 12:40:36 -0800
Subject: abc9_ops/write_xaiger: update doc

---
 passes/techmap/abc9_ops.cc | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'passes/techmap')

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 405f3e267..463941b0b 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -739,6 +739,19 @@ struct Abc9OpsPass : public Pass {
 		log("        '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
 		log("        whiteboxes.\n");
 		log("\n");
+		log("    -dff\n");
+		log("        consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
+		log("        during -prep_xaiger.\n");
+		log("\n");
+		log("    -prep_dff\n");
+		log("        compute the clock domain and initial value of each flop in the design.\n");
+		log("        process the '$holes' module to support clock-enable functionality.\n");
+		log("\n");
+		log("    -reintegrate\n");
+		log("        for each selected module, re-intergrate the module '<module-name>$abc9'\n");
+		log("        by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
+		log("        inputs and outputs.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-- 
cgit v1.2.3