From 72787f52fc31954e4b7dc3dc34d86705fc4e9dd1 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Tue, 8 Jun 2021 00:39:36 +0200
Subject: Fixing old e-mail addresses and deadnames

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
---
 passes/techmap/simplemap.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/techmap/simplemap.cc')

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index b9d337da4..b65224c71 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
-- 
cgit v1.2.3


From f9aad606ca9c8f875ce3c3091daf465b73d3f513 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 2 Oct 2021 00:42:36 +0200
Subject: simplemap: refactor to use FfData.

---
 passes/techmap/simplemap.cc | 300 +++-----------------------------------------
 1 file changed, 19 insertions(+), 281 deletions(-)

(limited to 'passes/techmap/simplemap.cc')

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index b65224c71..69f9da075 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -19,6 +19,7 @@
 
 #include "simplemap.h"
 #include "kernel/sigtools.h"
+#include "kernel/ff.h"
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -367,276 +368,13 @@ void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
 	module->connect(RTLIL::SigSig(sig_y, sig_ab));
 }
 
-void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
-	char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
-
-	RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
-	RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::S, sig_s[i]);
-		gate->setPort(ID::R, sig_r[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
 void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type = ID($_FF_);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
-
-	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type = stringf("$_DFF_%c_", clk_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::C, sig_clk);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
-	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
-
-	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
-	RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::C, sig_clk);
-		gate->setPort(ID::E, sig_en);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
-	char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
-	char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
-
-	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
-	RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
-	RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::C, sig_clk);
-		gate->setPort(ID::S, sig_s[i]);
-		gate->setPort(ID::R, sig_r[i]);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_dffsre(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
-	char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
-	char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
-	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
-
-	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
-	RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
-	RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
-	RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type = stringf("$_DFFSRE_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::C, sig_clk);
-		gate->setPort(ID::S, sig_s[i]);
-		gate->setPort(ID::R, sig_r[i]);
-		gate->setPort(ID::E, sig_e);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_adff_sdff(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	bool is_async = cell->type == ID($adff);
-	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
-	char rst_pol = cell->parameters.at(is_async ? ID::ARST_POLARITY : ID::SRST_POLARITY).as_bool() ? 'P' : 'N';
-	const char *type = is_async ? "DFF" : "SDFF";
-
-	std::vector<RTLIL::State> rst_val = cell->parameters.at(is_async ? ID::ARST_VALUE : ID::SRST_VALUE).bits;
-	while (int(rst_val.size()) < width)
-		rst_val.push_back(RTLIL::State::S0);
-
-	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
-	RTLIL::SigSpec sig_rst = cell->getPort(is_async ? ID::ARST : ID::SRST);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type_0 = stringf("$_%s_%c%c0_", type, clk_pol, rst_pol);
-	IdString gate_type_1 = stringf("$_%s_%c%c1_", type, clk_pol, rst_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::C, sig_clk);
-		gate->setPort(ID::R, sig_rst);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_adffe_sdffe_sdffce(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	bool is_async = cell->type == ID($adffe);
-	char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
-	char rst_pol = cell->parameters.at(is_async ? ID::ARST_POLARITY : ID::SRST_POLARITY).as_bool() ? 'P' : 'N';
-	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
-	const char *type = is_async ? "DFFE" : cell->type == ID($sdffe) ? "SDFFE" : "SDFFCE";
-
-	std::vector<RTLIL::State> rst_val = cell->parameters.at(is_async ? ID::ARST_VALUE : ID::SRST_VALUE).bits;
-	while (int(rst_val.size()) < width)
-		rst_val.push_back(RTLIL::State::S0);
-
-	RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
-	RTLIL::SigSpec sig_rst = cell->getPort(is_async ? ID::ARST : ID::SRST);
-	RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type_0 = stringf("$_%s_%c%c0%c_", type, clk_pol, rst_pol, en_pol);
-	IdString gate_type_1 = stringf("$_%s_%c%c1%c_", type, clk_pol, rst_pol, en_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::C, sig_clk);
-		gate->setPort(ID::R, sig_rst);
-		gate->setPort(ID::E, sig_e);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
-
-	RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type = stringf("$_DLATCH_%c_", en_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::E, sig_en);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_adlatch(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
-	char rst_pol = cell->parameters.at(ID::ARST_POLARITY).as_bool() ? 'P' : 'N';
-
-	std::vector<RTLIL::State> rst_val = cell->parameters.at(ID::ARST_VALUE).bits;
-	while (int(rst_val.size()) < width)
-		rst_val.push_back(RTLIL::State::S0);
-
-	RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
-	RTLIL::SigSpec sig_rst = cell->getPort(ID::ARST);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type_0 = stringf("$_DLATCH_%c%c0_", en_pol, rst_pol);
-	IdString gate_type_1 = stringf("$_DLATCH_%c%c1_", en_pol, rst_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::E, sig_en);
-		gate->setPort(ID::R, sig_rst);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
-	}
-}
-
-void simplemap_dlatchsr(RTLIL::Module *module, RTLIL::Cell *cell)
-{
-	int width = cell->parameters.at(ID::WIDTH).as_int();
-	char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
-	char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
-	char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
-
-	RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
-	RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
-	RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
-	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
-	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
-
-	IdString gate_type = stringf("$_DLATCHSR_%c%c%c_", en_pol, set_pol, clr_pol);
-
-	for (int i = 0; i < width; i++) {
-		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
-		gate->setPort(ID::E, sig_en);
-		gate->setPort(ID::S, sig_s[i]);
-		gate->setPort(ID::R, sig_r[i]);
-		gate->setPort(ID::D, sig_d[i]);
-		gate->setPort(ID::Q, sig_q[i]);
+	FfData ff(nullptr, cell);
+	for (int i = 0; i < ff.width; i++) {
+		FfData fff = ff.slice({i});
+		fff.is_fine = true;
+		fff.emit(module, NEW_ID);
 	}
 }
 
@@ -666,20 +404,20 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
 	mappers[ID($sop)]         = simplemap_sop;
 	mappers[ID($slice)]       = simplemap_slice;
 	mappers[ID($concat)]      = simplemap_concat;
-	mappers[ID($sr)]          = simplemap_sr;
+	mappers[ID($sr)]          = simplemap_ff;
 	mappers[ID($ff)]          = simplemap_ff;
-	mappers[ID($dff)]         = simplemap_dff;
-	mappers[ID($dffe)]        = simplemap_dffe;
-	mappers[ID($dffsr)]       = simplemap_dffsr;
-	mappers[ID($dffsre)]      = simplemap_dffsre;
-	mappers[ID($adff)]        = simplemap_adff_sdff;
-	mappers[ID($sdff)]        = simplemap_adff_sdff;
-	mappers[ID($adffe)]       = simplemap_adffe_sdffe_sdffce;
-	mappers[ID($sdffe)]       = simplemap_adffe_sdffe_sdffce;
-	mappers[ID($sdffce)]      = simplemap_adffe_sdffe_sdffce;
-	mappers[ID($dlatch)]      = simplemap_dlatch;
-	mappers[ID($adlatch)]     = simplemap_adlatch;
-	mappers[ID($dlatchsr)]    = simplemap_dlatchsr;
+	mappers[ID($dff)]         = simplemap_ff;
+	mappers[ID($dffe)]        = simplemap_ff;
+	mappers[ID($dffsr)]       = simplemap_ff;
+	mappers[ID($dffsre)]      = simplemap_ff;
+	mappers[ID($adff)]        = simplemap_ff;
+	mappers[ID($sdff)]        = simplemap_ff;
+	mappers[ID($adffe)]       = simplemap_ff;
+	mappers[ID($sdffe)]       = simplemap_ff;
+	mappers[ID($sdffce)]      = simplemap_ff;
+	mappers[ID($dlatch)]      = simplemap_ff;
+	mappers[ID($adlatch)]     = simplemap_ff;
+	mappers[ID($dlatchsr)]    = simplemap_ff;
 }
 
 void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
-- 
cgit v1.2.3


From e7d89e653c9d295d3cc9547b83660658e4d1c95b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 2 Oct 2021 01:23:43 +0200
Subject: Hook up $aldff support in various passes.

---
 passes/techmap/simplemap.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'passes/techmap/simplemap.cc')

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 69f9da075..04d7ec874 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -415,6 +415,8 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
 	mappers[ID($adffe)]       = simplemap_ff;
 	mappers[ID($sdffe)]       = simplemap_ff;
 	mappers[ID($sdffce)]      = simplemap_ff;
+	mappers[ID($aldff)]       = simplemap_ff;
+	mappers[ID($aldffe)]      = simplemap_ff;
 	mappers[ID($dlatch)]      = simplemap_ff;
 	mappers[ID($adlatch)]     = simplemap_ff;
 	mappers[ID($dlatchsr)]    = simplemap_ff;
@@ -450,7 +452,7 @@ struct SimplemapPass : public Pass {
 		log("  $not, $pos, $and, $or, $xor, $xnor\n");
 		log("  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
 		log("  $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
-		log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
+		log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
-- 
cgit v1.2.3


From 4e70c3077562e511d6f840c91dd30ade87d66517 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Wed, 6 Oct 2021 22:16:55 +0200
Subject: FfData: some refactoring.

- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
---
 passes/techmap/simplemap.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/techmap/simplemap.cc')

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 04d7ec874..68f44cf6d 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -368,13 +368,13 @@ void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
 	module->connect(RTLIL::SigSig(sig_y, sig_ab));
 }
 
-void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
+void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell)
 {
 	FfData ff(nullptr, cell);
 	for (int i = 0; i < ff.width; i++) {
 		FfData fff = ff.slice({i});
 		fff.is_fine = true;
-		fff.emit(module, NEW_ID);
+		fff.emit();
 	}
 }
 
-- 
cgit v1.2.3


From 93508d58dafbbffcedffa70b21a197b6fca8bb30 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Mon, 24 Jan 2022 16:02:29 +0100
Subject: Add $bmux and $demux cells.

---
 passes/techmap/simplemap.cc | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

(limited to 'passes/techmap/simplemap.cc')

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 68f44cf6d..7d8dba439 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -299,6 +299,30 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 }
 
+void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	SigSpec sel = cell->getPort(ID::S);
+	SigSpec data = cell->getPort(ID::A);
+	int width = GetSize(cell->getPort(ID::Y));
+
+	for (int idx = 0; idx < GetSize(sel); idx++) {
+		SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
+		for (int i = 0; i < GetSize(new_data); i += width) {
+			for (int k = 0; k < width; k++) {
+				RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
+				gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+				gate->setPort(ID::A, data[i*2+k]);
+				gate->setPort(ID::B, data[i*2+width+k]);
+				gate->setPort(ID::S, sel[idx]);
+				gate->setPort(ID::Y, new_data[i+k]);
+			}
+		}
+		data = new_data;
+	}
+
+	module->connect(cell->getPort(ID::Y), data);
+}
+
 void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	SigSpec lut_ctrl = cell->getPort(ID::A);
@@ -306,7 +330,6 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
 	lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
 
 	for (int idx = 0; GetSize(lut_data) > 1; idx++) {
-		SigSpec sig_s = lut_ctrl[idx];
 		SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
 		for (int i = 0; i < GetSize(lut_data); i += 2) {
 			RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
@@ -400,6 +423,7 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
 	mappers[ID($nex)]         = simplemap_eqne;
 	mappers[ID($mux)]         = simplemap_mux;
 	mappers[ID($tribuf)]      = simplemap_tribuf;
+	mappers[ID($bmux)]        = simplemap_bmux;
 	mappers[ID($lut)]         = simplemap_lut;
 	mappers[ID($sop)]         = simplemap_sop;
 	mappers[ID($slice)]       = simplemap_slice;
-- 
cgit v1.2.3