From 00e7dec7f54eb2e4f18112e5c0007a55287fdf8e Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 26 Aug 2020 17:29:32 +0000
Subject: Replace "ILANG" with "RTLIL" everywhere.

The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
---
 passes/techmap/extract.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'passes/techmap/extract.cc')

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 7278cb680..f5966fac0 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -354,7 +354,7 @@ struct ExtractPass : public Pass {
 		log("\n");
 		log("This pass looks for subcircuits that are isomorphic to any of the modules\n");
 		log("in the given map file and replaces them with instances of this modules. The\n");
-		log("map file can be a Verilog source file (*.v) or an ilang file (*.il).\n");
+		log("map file can be a Verilog source file (*.v) or an RTLIL source file (*.il).\n");
 		log("\n");
 		log("    -map <map_file>\n");
 		log("        use the modules in this file as reference. This option can be used\n");
@@ -409,7 +409,7 @@ struct ExtractPass : public Pass {
 		log("the following options are to be used instead of the -map option.\n");
 		log("\n");
 		log("    -mine <out_file>\n");
-		log("        mine for frequent subcircuits and write them to the given ilang file\n");
+		log("        mine for frequent subcircuits and write them to the given RTLIL file\n");
 		log("\n");
 		log("    -mine_cells_span <min> <max>\n");
 		log("        only mine for subcircuits with the specified number of cells\n");
@@ -578,7 +578,7 @@ struct ExtractPass : public Pass {
 		}
 
 		if (map_filenames.empty() && mine_outfile.empty())
-			log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n");
+			log_cmd_error("Missing option -map <verilog_or_rtlil_file> or -mine <output_rtlil_file>.\n");
 
 		RTLIL::Design *map = nullptr;
 
@@ -606,7 +606,7 @@ struct ExtractPass : public Pass {
 						delete map;
 						log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
 					}
-					Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog"));
+					Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
 					f.close();
 
 					if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) {
@@ -744,7 +744,7 @@ struct ExtractPass : public Pass {
 			f.open(mine_outfile.c_str(), std::ofstream::trunc);
 			if (f.fail())
 				log_error("Can't open output file `%s'.\n", mine_outfile.c_str());
-			Backend::backend_call(map, &f, mine_outfile, "ilang");
+			Backend::backend_call(map, &f, mine_outfile, "rtlil");
 			f.close();
 		}
 
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