From ccfc00705a1658260e792e9604ae5319ec7b7c2a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 26 Jan 2022 09:26:19 +0100
Subject: Add ability to write to FST file

---
 passes/sat/sim.cc | 120 +++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 109 insertions(+), 11 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 4e158da62..ba7519be5 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -21,6 +21,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
 #include "kernel/mem.h"
+#include "libs/fst/fstapi.h"
 
 #include <ctime>
 
@@ -92,6 +93,7 @@ struct SimInstance
 	std::vector<Mem> memories;
 
 	dict<Wire*, pair<int, Const>> vcd_database;
+	dict<Wire*, pair<fstHandle, Const>> fst_database;
 
 	SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
 			shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
@@ -616,12 +618,60 @@ struct SimInstance
 		for (auto child : children)
 			child.second->write_vcd_step(f);
 	}
+
+	void write_fst_header(struct fstContext *f)
+	{
+		fstWriterSetScope(f, FST_ST_VCD_MODULE, stringf("%s",log_id(name())).c_str(), nullptr);
+		for (auto wire : module->wires())
+		{
+			if (shared->hide_internal && wire->name[0] == '$')
+				continue;
+
+			fstHandle id = fstWriterCreateVar(f, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
+												stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
+			fst_database[wire] = make_pair(id, Const());
+		}
+
+		for (auto child : children)
+			child.second->write_fst_header(f);
+
+		fstWriterSetUpscope(f);
+	}
+
+	void write_fst_step(struct fstContext *f)
+	{
+		for (auto &it : fst_database)
+		{
+			Wire *wire = it.first;
+			Const value = get_state(wire);
+			fstHandle id = it.second.first;
+
+			if (it.second.second == value)
+				continue;
+
+			it.second.second = value;
+			std::stringstream ss;
+			for (int i = GetSize(value)-1; i >= 0; i--) {
+				switch (value[i]) {
+					case State::S0: ss << "0"; break;
+					case State::S1: ss << "1"; break;
+					case State::Sx: ss << "x"; break;
+					default: ss << "z";
+				}
+			}
+			fstWriterEmitValueChange(f, id, ss.str().c_str());
+		}
+
+		for (auto child : children)
+			child.second->write_fst_step(f);
+	}
 };
 
 struct SimWorker : SimShared
 {
 	SimInstance *top = nullptr;
 	std::ofstream vcdfile;
+	struct fstContext *fstfile = nullptr;
 	pool<IdString> clock, clockn, reset, resetn;
 	std::string timescale;
 
@@ -632,9 +682,6 @@ struct SimWorker : SimShared
 
 	void write_vcd_header()
 	{
-		if (!vcdfile.is_open())
-			return;
-
 		vcdfile << stringf("$version %s $end\n", yosys_version_str);
 
 		std::time_t t = std::time(nullptr);
@@ -654,13 +701,53 @@ struct SimWorker : SimShared
 
 	void write_vcd_step(int t)
 	{
-		if (!vcdfile.is_open())
-			return;
-
 		vcdfile << stringf("#%d\n", t);
 		top->write_vcd_step(vcdfile);
 	}
 
+	void write_fst_header()
+	{
+		std::time_t t = std::time(nullptr);
+	    fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
+	    fstWriterSetVersion(fstfile, yosys_version_str);
+		if (!timescale.empty())
+	    	fstWriterSetTimescaleFromString(fstfile, timescale.c_str());
+
+		fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
+		fstWriterSetRepackOnClose(fstfile, 1);
+	   
+		top->write_fst_header(fstfile);
+	}
+
+	void write_fst_step(int t)
+	{
+		fstWriterEmitTimeChange(fstfile, t);
+
+		top->write_fst_step(fstfile);
+	}
+
+	void write_output_header()
+	{
+		if (vcdfile.is_open())
+			write_vcd_header();
+		if (fstfile)
+			write_fst_header();
+	}
+
+	void write_output_step(int t)
+	{
+		if (vcdfile.is_open())
+			write_vcd_step(t);
+		if (fstfile)
+			write_fst_step(t);
+	}
+
+	void write_output_end()
+	{
+		if (fstfile)
+			fstWriterClose(fstfile);
+	}
+
 	void update()
 	{
 		while (1)
@@ -714,8 +801,8 @@ struct SimWorker : SimShared
 
 		update();
 
-		write_vcd_header();
-		write_vcd_step(0);
+		write_output_header();
+		write_output_step(0);
 
 		for (int cycle = 0; cycle < numcycles; cycle++)
 		{
@@ -726,7 +813,7 @@ struct SimWorker : SimShared
 			set_inports(clockn, State::S1);
 
 			update();
-			write_vcd_step(10*cycle + 5);
+			write_output_step(10*cycle + 5);
 
 			if (debug)
 				log("\n===== %d =====\n", 10*cycle + 10);
@@ -742,10 +829,12 @@ struct SimWorker : SimShared
 			}
 
 			update();
-			write_vcd_step(10*cycle + 10);
+			write_output_step(10*cycle + 10);
 		}
 
-		write_vcd_step(10*numcycles + 2);
+		write_output_step(10*numcycles + 2);
+
+		write_output_end();
 
 		if (writeback) {
 			pool<Module*> wbmods;
@@ -767,6 +856,9 @@ struct SimPass : public Pass {
 		log("    -vcd <filename>\n");
 		log("        write the simulation results to the given VCD file\n");
 		log("\n");
+		log("    -fst <filename>\n");
+		log("        write the simulation results to the given FST file\n");
+		log("\n");
 		log("    -clock <portname>\n");
 		log("        name of top-level clock input\n");
 		log("\n");
@@ -816,6 +908,12 @@ struct SimPass : public Pass {
 				worker.vcdfile.open(vcd_filename.c_str());
 				continue;
 			}
+			if (args[argidx] == "-fst" && argidx+1 < args.size()) {
+				std::string fst_filename = args[++argidx];
+				rewrite_filename(fst_filename);
+				worker.fstfile = (struct fstContext *)fstWriterCreate(fst_filename.c_str(),1);
+				continue;
+			}
 			if (args[argidx] == "-n" && argidx+1 < args.size()) {
 				numcycles = atoi(args[++argidx].c_str());
 				continue;
-- 
cgit v1.2.3


From 9a8939f0a4584c13bfceb978120cc8605ede03ee Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 26 Jan 2022 15:50:38 +0100
Subject: Read fst and use data to set inputs

---
 passes/sat/sim.cc | 102 ++++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 92 insertions(+), 10 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index ba7519be5..99ea701d9 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -21,7 +21,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
 #include "kernel/mem.h"
-#include "libs/fst/fstapi.h"
+#include "kernel/fstdata.h"
 
 #include <ctime>
 
@@ -35,6 +35,7 @@ struct SimShared
 	bool writeback = false;
 	bool zinit = false;
 	int rstlen = 1;
+	FstData *fst = nullptr;
 };
 
 void zinit(State &v)
@@ -52,7 +53,8 @@ void zinit(Const &v)
 struct SimInstance
 {
 	SimShared *shared;
-
+	
+	std::string scope;
 	Module *module;
 	Cell *instance;
 
@@ -95,8 +97,8 @@ struct SimInstance
 	dict<Wire*, pair<int, Const>> vcd_database;
 	dict<Wire*, pair<fstHandle, Const>> fst_database;
 
-	SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
-			shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
+	SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
+			shared(shared), scope(scope), module(module), instance(instance), parent(parent), sigmap(module)
 	{
 		log_assert(module);
 
@@ -146,7 +148,7 @@ struct SimInstance
 			Module *mod = module->design->module(cell->type);
 
 			if (mod != nullptr) {
-				dirty_children.insert(new SimInstance(shared, mod, cell, this));
+				dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(module->name), mod, cell, this));
 			}
 
 			for (auto &port : cell->connections()) {
@@ -674,6 +676,8 @@ struct SimWorker : SimShared
 	struct fstContext *fstfile = nullptr;
 	pool<IdString> clock, clockn, reset, resetn;
 	std::string timescale;
+	std::string sim_filename;
+	std::string scope;
 
 	~SimWorker()
 	{
@@ -708,10 +712,10 @@ struct SimWorker : SimShared
 	void write_fst_header()
 	{
 		std::time_t t = std::time(nullptr);
-	    fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
-	    fstWriterSetVersion(fstfile, yosys_version_str);
+		fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
+		fstWriterSetVersion(fstfile, yosys_version_str);
 		if (!timescale.empty())
-	    	fstWriterSetTimescaleFromString(fstfile, timescale.c_str());
+			fstWriterSetTimescaleFromString(fstfile, timescale.c_str());
 
 		fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
 		fstWriterSetRepackOnClose(fstfile, 1);
@@ -786,7 +790,7 @@ struct SimWorker : SimShared
 	void run(Module *topmod, int numcycles)
 	{
 		log_assert(top == nullptr);
-		top = new SimInstance(this, topmod);
+		top = new SimInstance(this, scope, topmod);
 
 		if (debug)
 			log("\n===== 0 =====\n");
@@ -841,6 +845,65 @@ struct SimWorker : SimShared
 			top->writeback(wbmods);
 		}
 	}
+
+	void run_cosim(Module *topmod, int numcycles)
+	{
+		log_assert(top == nullptr);
+		top = new SimInstance(this, scope, topmod);
+
+		fst = new FstData(sim_filename);
+
+		std::vector<fstHandle> fst_clock;
+
+		for (auto portname : clock)
+		{
+			Wire *w = topmod->wire(portname);
+			if (!w)
+				log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
+			if (!w->port_input)
+				log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
+			fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
+			if (id==0)
+				log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
+			fst_clock.push_back(id);
+		}
+		for (auto portname : clockn)
+		{
+			Wire *w = topmod->wire(portname);
+			if (!w)
+				log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
+			if (!w->port_input)
+				log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
+			fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
+			if (id==0)
+				log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
+			fst_clock.push_back(id);
+		}
+		if (fst_clock.size()==0)
+			log_error("No clock signals defined for input file\n");
+
+		SigMap sigmap(topmod);
+		log ("Get inputs\n");
+		std::map<Wire*,fstHandle> inputs;
+
+		for (auto wire : topmod->wires()) {
+			if (wire->port_input) {
+				fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
+				log("Input %s\n",log_id(wire));
+				inputs[wire] = id;
+			}
+		}
+
+		fst->reconstruct(fst_clock);
+		auto edges = fst->edges(fst_clock.back(), true, true);
+		fst->reconstructAllAtTimes(edges);
+		for(auto &time : edges) {
+			for(auto &item : inputs) {
+				std::string v = fst->valueAt(item.second, time);
+				top->set_state(item.first, Const::from_string(v));
+			}
+			update();
+		}
 };
 
 struct SimPass : public Pass {
@@ -889,6 +952,12 @@ struct SimPass : public Pass {
 		log("    -w\n");
 		log("        writeback mode: use final simulation state as new init state\n");
 		log("\n");
+		log("    -r\n");
+		log("        read simulation results file (file formats supported: FST)\n");
+		log("\n");
+		log("    -scope\n");
+		log("        scope of simulation top model\n");
+		log("\n");
 		log("    -d\n");
 		log("        enable debug output\n");
 		log("\n");
@@ -958,6 +1027,16 @@ struct SimPass : public Pass {
 				worker.zinit = true;
 				continue;
 			}
+			if (args[argidx] == "-r" && argidx+1 < args.size()) {
+				std::string sim_filename = args[++argidx];
+				rewrite_filename(sim_filename);
+				worker.sim_filename = sim_filename;
+				continue;
+			}
+			if (args[argidx] == "-scope" && argidx+1 < args.size()) {
+				worker.scope = args[++argidx];
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -976,7 +1055,10 @@ struct SimPass : public Pass {
 			top_mod = mods.front();
 		}
 
-		worker.run(top_mod, numcycles);
+		if (worker.sim_filename.empty())
+			worker.run(top_mod, numcycles);
+		else
+			worker.run_cosim(top_mod, numcycles);
 	}
 } SimPass;
 
-- 
cgit v1.2.3


From be7be63fece641db3e3fa1bd28f10603d07732bf Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 26 Jan 2022 15:51:43 +0100
Subject: Check if stimulated

---
 passes/sat/sim.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 99ea701d9..605dc8e1e 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -903,7 +903,21 @@ struct SimWorker : SimShared
 				top->set_state(item.first, Const::from_string(v));
 			}
 			update();
+
+			/*Wire *wire = topmod->wire("\\cnt");
+			Const value = top->get_state(wire);
+			std::stringstream ss;
+			for (int i = GetSize(value)-1; i >= 0; i--) {
+				switch (value[i]) {
+					case State::S0: ss << "0"; break;
+					case State::S1: ss << "1"; break;
+					case State::Sx: ss << "x"; break;
+					default: ss << "z";
+				}
+			}
+			log("%s\n",ss.str().c_str());*/
 		}
+	}
 };
 
 struct SimPass : public Pass {
-- 
cgit v1.2.3


From 40018e191b7f5e233b2da4eab823f37d51a07778 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 26 Jan 2022 16:52:36 +0100
Subject: Display values of outputs

---
 passes/sat/sim.cc | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 605dc8e1e..8cabcfbb4 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -885,6 +885,7 @@ struct SimWorker : SimShared
 		SigMap sigmap(topmod);
 		log ("Get inputs\n");
 		std::map<Wire*,fstHandle> inputs;
+		std::map<Wire*,fstHandle> outputs;
 
 		for (auto wire : topmod->wires()) {
 			if (wire->port_input) {
@@ -892,6 +893,11 @@ struct SimWorker : SimShared
 				log("Input %s\n",log_id(wire));
 				inputs[wire] = id;
 			}
+			if (wire->port_output) {
+				fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
+				log("Output %s %d\n",log_id(wire), id);
+				outputs[wire] = id;
+			}
 		}
 
 		fst->reconstruct(fst_clock);
@@ -903,19 +909,11 @@ struct SimWorker : SimShared
 				top->set_state(item.first, Const::from_string(v));
 			}
 			update();
-
-			/*Wire *wire = topmod->wire("\\cnt");
-			Const value = top->get_state(wire);
-			std::stringstream ss;
-			for (int i = GetSize(value)-1; i >= 0; i--) {
-				switch (value[i]) {
-					case State::S0: ss << "0"; break;
-					case State::S1: ss << "1"; break;
-					case State::Sx: ss << "x"; break;
-					default: ss << "z";
-				}
+			for(auto &item : outputs) {
+				Const fst_val = Const::from_string(fst->valueAt(item.second, time));
+				Const sim_val = top->get_state(item.first);
+				log("%s %s\n", log_signal(fst_val), log_signal(sim_val));
 			}
-			log("%s\n",ss.str().c_str());*/
 		}
 	}
 };
-- 
cgit v1.2.3


From 3e35de2be108b7d8b24808aa55a0f0f9f8570705 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 28 Jan 2022 10:18:02 +0100
Subject: Add more options and time handling

---
 passes/sat/sim.cc | 105 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 103 insertions(+), 2 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 8cabcfbb4..d6f5f3a81 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -28,6 +28,41 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+enum class SimulationMode {
+	cmp,
+	gold,
+	gate,
+};
+
+static const std::map<std::string, int> g_units =
+{
+	{ "",    -9 }, // default is ns
+	{ "s",    0 },
+	{ "ms",  -3 },
+	{ "us",  -6 },
+	{ "ns",  -9 },
+	{ "ps", -12 },
+	{ "fs", -15 },
+	{ "as", -18 },
+	{ "zs", -21 },
+};
+
+static double stringToTime(std::string str)
+{
+	if (str=="END") return -1;
+
+	char *endptr;
+	long value = strtol(str.c_str(), &endptr, 10);
+
+	if (g_units.find(endptr)==g_units.end())
+		log_error("Cannot parse '%s', bad unit '%s'\n", str.c_str(), endptr);
+
+	if (value < 0)
+		log_error("Time value '%s' must be positive\n", str.c_str());
+
+	return value * pow(10.0, g_units.at(endptr));
+}
+
 struct SimShared
 {
 	bool debug = false;
@@ -36,6 +71,9 @@ struct SimShared
 	bool zinit = false;
 	int rstlen = 1;
 	FstData *fst = nullptr;
+	double start_time = 0;
+	double stop_time = -1;
+	SimulationMode sim_mode = SimulationMode::cmp;
 };
 
 void zinit(State &v)
@@ -900,10 +938,38 @@ struct SimWorker : SimShared
 			}
 		}
 
+		uint64_t startCount = 0;
+		uint64_t stopCount = 0;
+		if (start_time==0) {
+			if (start_time < fst->getStartTime())
+				log_warning("Start time is before simulation file start time\n");
+			startCount = fst->getStartTime();
+		} else if (start_time==-1) 
+			startCount = fst->getEndTime();
+		else {
+			startCount = start_time / fst->getTimescale();
+			if (startCount > fst->getEndTime()) {
+				startCount = fst->getEndTime();
+				log_warning("Start time is after simulation file end time\n");
+			}
+		}
+		if (stop_time==0) {
+			if (stop_time < fst->getStartTime())
+				log_warning("Stop time is before simulation file start time\n");
+			stopCount = fst->getStartTime();
+		} else if (stop_time==-1) 
+			stopCount = fst->getEndTime();
+		else {
+			stopCount = stop_time / fst->getTimescale();
+			if (stopCount > fst->getEndTime()) {
+				stopCount = fst->getEndTime();
+				log_warning("Stop time is after simulation file end time\n");
+			}
+		}
 		fst->reconstruct(fst_clock);
 		auto edges = fst->edges(fst_clock.back(), true, true);
 		fst->reconstructAllAtTimes(edges);
-		for(auto &time : edges) {
+/*		for(auto &time : edges) {
 			for(auto &item : inputs) {
 				std::string v = fst->valueAt(item.second, time);
 				top->set_state(item.first, Const::from_string(v));
@@ -914,7 +980,7 @@ struct SimWorker : SimShared
 				Const sim_val = top->get_state(item.first);
 				log("%s %s\n", log_signal(fst_val), log_signal(sim_val));
 			}
-		}
+		}*/
 	}
 };
 
@@ -970,6 +1036,21 @@ struct SimPass : public Pass {
 		log("    -scope\n");
 		log("        scope of simulation top model\n");
 		log("\n");
+		log("    -start <time>\n");
+		log("        start co-simulation in arbitary time (default 0)\n");
+		log("\n");
+		log("    -stop <time>\n");
+		log("        stop co-simulation in arbitary time (default END)\n");
+		log("\n");
+		log("    -sim-cmp\n");
+		log("        co-simulation expect exact match (default)\n");
+		log("\n");
+		log("    -sim-gold\n");
+		log("        co-simulation, x in simulation can match any value in FST\n");
+		log("\n");
+		log("    -sim-gate\n");
+		log("        co-simulation, x in FST can match any value in simulation\n");
+		log("\n");
 		log("    -d\n");
 		log("        enable debug output\n");
 		log("\n");
@@ -1049,6 +1130,26 @@ struct SimPass : public Pass {
 				worker.scope = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-start" && argidx+1 < args.size()) {
+				worker.start_time = stringToTime(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-stop" && argidx+1 < args.size()) {
+				worker.stop_time = stringToTime(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-sim-cmp") {
+				worker.sim_mode = SimulationMode::cmp;
+				continue;
+			}
+			if (args[argidx] == "-sim-gold") {
+				worker.sim_mode = SimulationMode::gold;
+				continue;
+			}
+			if (args[argidx] == "-sim-gate") {
+				worker.sim_mode = SimulationMode::gate;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
-- 
cgit v1.2.3


From 4f75a2ca1b4a71ad335124b45d36eed9c8d619c8 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 28 Jan 2022 12:50:41 +0100
Subject: Do actual compare

---
 passes/sat/sim.cc | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index d6f5f3a81..e9e114047 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -966,21 +966,32 @@ struct SimWorker : SimShared
 				log_warning("Stop time is after simulation file end time\n");
 			}
 		}
-		fst->reconstruct(fst_clock);
-		auto edges = fst->edges(fst_clock.back(), true, true);
+		auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
 		fst->reconstructAllAtTimes(edges);
-/*		for(auto &time : edges) {
+		for(auto &time : edges) {
 			for(auto &item : inputs) {
 				std::string v = fst->valueAt(item.second, time);
 				top->set_state(item.first, Const::from_string(v));
 			}
 			update();
+			bool status = true;
 			for(auto &item : outputs) {
 				Const fst_val = Const::from_string(fst->valueAt(item.second, time));
 				Const sim_val = top->get_state(item.first);
-				log("%s %s\n", log_signal(fst_val), log_signal(sim_val));
+				if (sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
+					// TODO: check bit by bit
+				} else if (sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
+					// TODO: check bit by bit
+				} else {
+					if (fst_val!=sim_val) {
+						status = false;
+						log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+					}
+				}
 			}
-		}*/
+			if (!status)
+				log_error("Signal difference at %zu\n", time);
+		}
 	}
 };
 
-- 
cgit v1.2.3


From 81b76155d63919bed356876616b5d12a85d805dd Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 28 Jan 2022 13:24:38 +0100
Subject: recursive check

---
 passes/sat/sim.cc | 60 +++++++++++++++++++++++++++++++------------------------
 1 file changed, 34 insertions(+), 26 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index e9e114047..0b9a282e1 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -134,6 +134,7 @@ struct SimInstance
 
 	dict<Wire*, pair<int, Const>> vcd_database;
 	dict<Wire*, pair<fstHandle, Const>> fst_database;
+	dict<Wire*, fstHandle> fst_handles;
 
 	SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
 			shared(shared), scope(scope), module(module), instance(instance), parent(parent), sigmap(module)
@@ -158,6 +159,11 @@ struct SimInstance
 				}
 			}
 
+			if (shared->fst) {
+				fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
+				fst_handles[wire] = id;
+			}
+
 			if (wire->attributes.count(ID::init)) {
 				Const initval = wire->attributes.at(ID::init);
 				for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
@@ -705,6 +711,29 @@ struct SimInstance
 		for (auto child : children)
 			child.second->write_fst_step(f);
 	}
+
+	bool checkSignals(uint64_t time)
+	{
+		bool retVal = false;
+		for(auto &item : fst_handles) {
+			if (item.second==0) continue; // Ignore signals not found
+			Const fst_val = Const::from_string(shared->fst->valueAt(item.second, time));
+			Const sim_val = get_state(item.first);
+			if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
+				// TODO: check bit by bit
+			} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
+				// TODO: check bit by bit
+			} else {
+				if (fst_val!=sim_val) {
+					retVal = true;
+					log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+				}
+			}
+		}
+		for (auto child : children)
+			retVal |= child.second->checkSignals(time);
+		return retVal;
+	}
 };
 
 struct SimWorker : SimShared
@@ -887,10 +916,10 @@ struct SimWorker : SimShared
 	void run_cosim(Module *topmod, int numcycles)
 	{
 		log_assert(top == nullptr);
-		top = new SimInstance(this, scope, topmod);
-
 		fst = new FstData(sim_filename);
 
+		top = new SimInstance(this, scope, topmod);
+
 		std::vector<fstHandle> fst_clock;
 
 		for (auto portname : clock)
@@ -921,21 +950,13 @@ struct SimWorker : SimShared
 			log_error("No clock signals defined for input file\n");
 
 		SigMap sigmap(topmod);
-		log ("Get inputs\n");
 		std::map<Wire*,fstHandle> inputs;
-		std::map<Wire*,fstHandle> outputs;
 
 		for (auto wire : topmod->wires()) {
 			if (wire->port_input) {
 				fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
-				log("Input %s\n",log_id(wire));
 				inputs[wire] = id;
 			}
-			if (wire->port_output) {
-				fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
-				log("Output %s %d\n",log_id(wire), id);
-				outputs[wire] = id;
-			}
 		}
 
 		uint64_t startCount = 0;
@@ -974,22 +995,9 @@ struct SimWorker : SimShared
 				top->set_state(item.first, Const::from_string(v));
 			}
 			update();
-			bool status = true;
-			for(auto &item : outputs) {
-				Const fst_val = Const::from_string(fst->valueAt(item.second, time));
-				Const sim_val = top->get_state(item.first);
-				if (sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
-					// TODO: check bit by bit
-				} else if (sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
-					// TODO: check bit by bit
-				} else {
-					if (fst_val!=sim_val) {
-						status = false;
-						log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
-					}
-				}
-			}
-			if (!status)
+			
+			bool status = top->checkSignals(time);
+			if (status)
 				log_error("Signal difference at %zu\n", time);
 		}
 	}
-- 
cgit v1.2.3


From cb12b7c4d8153896b1f798994aed2aa97a41f011 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 28 Jan 2022 14:20:16 +0100
Subject: ignore not found private signals

---
 passes/sat/sim.cc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 0b9a282e1..65f952915 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -161,6 +161,8 @@ struct SimInstance
 
 			if (shared->fst) {
 				fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
+				if (id==0 && wire->name.isPublic())
+					log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str());
 				fst_handles[wire] = id;
 			}
 
@@ -728,6 +730,7 @@ struct SimInstance
 					retVal = true;
 					log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 				}
+				//log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 			}
 		}
 		for (auto child : children)
-- 
cgit v1.2.3


From ecbba625c4d981ce714434aad51d23a158aabb8a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 28 Jan 2022 15:59:13 +0100
Subject: set initial state, only flip-flops

---
 passes/sat/sim.cc | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 65f952915..d0e0b526c 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -714,6 +714,28 @@ struct SimInstance
 			child.second->write_fst_step(f);
 	}
 
+	void setInitState(uint64_t time)
+	{
+		for (auto &it : ff_database)
+		{
+			Cell *cell = it.first;
+			
+			SigSpec qsig = cell->getPort(ID::Q);
+			if (qsig.is_wire()) {
+				IdString name = qsig.as_wire()->name;
+				fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
+				if (id==0 && name.isPublic())
+					log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
+				if (id!=0) {
+					Const fst_val = Const::from_string(shared->fst->valueAt(id, time));
+					set_state(qsig, fst_val);
+				}
+			}
+		}
+		for (auto child : children)
+			child.second->setInitState(time);
+	}
+
 	bool checkSignals(uint64_t time)
 	{
 		bool retVal = false;
@@ -730,8 +752,8 @@ struct SimInstance
 					retVal = true;
 					log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 				}
-				//log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 			}
+			//log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 		}
 		for (auto child : children)
 			retVal |= child.second->checkSignals(time);
@@ -992,11 +1014,16 @@ struct SimWorker : SimShared
 		}
 		auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
 		fst->reconstructAllAtTimes(edges);
+		bool initial = false;
 		for(auto &time : edges) {
 			for(auto &item : inputs) {
 				std::string v = fst->valueAt(item.second, time);
 				top->set_state(item.first, Const::from_string(v));
 			}
+			if (!initial) {
+				top->setInitState(time);
+				initial = true;
+			}
 			update();
 			
 			bool status = top->checkSignals(time);
-- 
cgit v1.2.3


From f04d1398e569d6371a6f31c34ff145096d4a96c9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 28 Jan 2022 19:41:43 +0100
Subject: check if stop before start

---
 passes/sat/sim.cc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index d0e0b526c..3cf5967cc 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1012,6 +1012,9 @@ struct SimWorker : SimShared
 				log_warning("Stop time is after simulation file end time\n");
 			}
 		}
+		if (stopCount<startCount) {
+			log_error("Stop time is before start time\n");
+		}
 		auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
 		fst->reconstructAllAtTimes(edges);
 		bool initial = false;
-- 
cgit v1.2.3


From 190e44f0dac1a9c7f2dbf0c3069cd1d646806aaa Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 08:56:29 +0100
Subject: Fix scope

---
 passes/sat/sim.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 3cf5967cc..bea8f12b4 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -194,7 +194,7 @@ struct SimInstance
 			Module *mod = module->design->module(cell->type);
 
 			if (mod != nullptr) {
-				dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(module->name), mod, cell, this));
+				dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
 			}
 
 			for (auto &port : cell->connections()) {
-- 
cgit v1.2.3


From cbadfa02689ddbd5e9e75324aeb15b2c797d8cc4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 09:19:34 +0100
Subject: Updating initial state and checks

---
 passes/sat/sim.cc | 43 ++++++++++++++++++++++++++++---------------
 1 file changed, 28 insertions(+), 15 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index bea8f12b4..e67f8246b 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1016,22 +1016,35 @@ struct SimWorker : SimShared
 			log_error("Stop time is before start time\n");
 		}
 		auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
-		fst->reconstructAllAtTimes(edges);
-		bool initial = false;
-		for(auto &time : edges) {
-			for(auto &item : inputs) {
-				std::string v = fst->valueAt(item.second, time);
-				top->set_state(item.first, Const::from_string(v));
-			}
-			if (!initial) {
-				top->setInitState(time);
-				initial = true;
+		
+		if ((startCount == stopCount) && writeback) {
+			log("Update initial state with values from %zu\n",startCount);
+			if (edges.empty())
+				edges.push_back(startCount);
+			fst->reconstructAllAtTimes(edges);
+			top->setInitState(startCount);
+			pool<Module*> wbmods;
+			top->writeback(wbmods);
+		} else {
+			if (edges.empty())
+				log_error("No clock edges found in given time range\n");
+			fst->reconstructAllAtTimes(edges);
+			bool initial = false;
+			for(auto &time : edges) {
+				for(auto &item : inputs) {
+					std::string v = fst->valueAt(item.second, time);
+					top->set_state(item.first, Const::from_string(v));
+				}
+				if (!initial) {
+					top->setInitState(time);
+					initial = true;
+				}
+				update();
+
+				bool status = top->checkSignals(time);
+				if (status)
+					log_error("Signal difference at %zu\n", time);
 			}
-			update();
-			
-			bool status = top->checkSignals(time);
-			if (status)
-				log_error("Signal difference at %zu\n", time);
 		}
 	}
 };
-- 
cgit v1.2.3


From a6959d30df067c27da75d12bc0bd5233eb91d3ca Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 09:38:25 +0100
Subject: Use edges when explicit

---
 passes/sat/sim.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index e67f8246b..ff815b69a 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -74,6 +74,7 @@ struct SimShared
 	double start_time = 0;
 	double stop_time = -1;
 	SimulationMode sim_mode = SimulationMode::cmp;
+	bool cycles_set = false;
 };
 
 void zinit(State &v)
@@ -1016,7 +1017,9 @@ struct SimWorker : SimShared
 			log_error("Stop time is before start time\n");
 		}
 		auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
-		
+		if (cycles_set && ((size_t)(numcycles *2) < edges.size()))
+			edges.erase(edges.begin() + (numcycles*2), edges.end());
+
 		if ((startCount == stopCount) && writeback) {
 			log("Update initial state with values from %zu\n",startCount);
 			if (edges.empty())
@@ -1143,6 +1146,7 @@ struct SimPass : public Pass {
 			}
 			if (args[argidx] == "-n" && argidx+1 < args.size()) {
 				numcycles = atoi(args[++argidx].c_str());
+				worker.cycles_set = true;
 				continue;
 			}
 			if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {
-- 
cgit v1.2.3


From 543feb75cb3765746ea865c11aa6ceccaf0adeac Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 10:52:47 +0100
Subject: Display simulation time data

---
 passes/sat/sim.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index ff815b69a..05fe11201 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1033,7 +1033,9 @@ struct SimWorker : SimShared
 				log_error("No clock edges found in given time range\n");
 			fst->reconstructAllAtTimes(edges);
 			bool initial = false;
+			int cycle = 0;
 			for(auto &time : edges) {
+				log("Simulating cycle %d [%zu %s].\n", cycle+1, time, fst->getTimescaleString());
 				for(auto &item : inputs) {
 					std::string v = fst->valueAt(item.second, time);
 					top->set_state(item.first, Const::from_string(v));
@@ -1046,7 +1048,8 @@ struct SimWorker : SimShared
 
 				bool status = top->checkSignals(time);
 				if (status)
-					log_error("Signal difference at %zu\n", time);
+					log_error("Signal difference\n");
+				cycle++;
 			}
 		}
 	}
-- 
cgit v1.2.3


From 6513300db7648fcdf62b59bddd2aad9812829c02 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 11:41:52 +0100
Subject: message update

---
 passes/sat/sim.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 05fe11201..e6de1b134 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1035,7 +1035,7 @@ struct SimWorker : SimShared
 			bool initial = false;
 			int cycle = 0;
 			for(auto &time : edges) {
-				log("Simulating cycle %d [%zu %s].\n", cycle+1, time, fst->getTimescaleString());
+				log("Co-simulating cycle %d [%zu %s].\n", cycle+1, time, fst->getTimescaleString());
 				for(auto &item : inputs) {
 					std::string v = fst->valueAt(item.second, time);
 					top->set_state(item.first, Const::from_string(v));
-- 
cgit v1.2.3


From 26de52fa094f90d5ce7a2766df5a53e6188b4d13 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 12:00:15 +0100
Subject: Cleanup

---
 passes/sat/sim.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index e6de1b134..f08a3eb1f 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1021,7 +1021,7 @@ struct SimWorker : SimShared
 			edges.erase(edges.begin() + (numcycles*2), edges.end());
 
 		if ((startCount == stopCount) && writeback) {
-			log("Update initial state with values from %zu\n",startCount);
+			log("Update initial state with values from [%zu%s]\n", startCount, fst->getTimescaleString());
 			if (edges.empty())
 				edges.push_back(startCount);
 			fst->reconstructAllAtTimes(edges);
@@ -1035,7 +1035,7 @@ struct SimWorker : SimShared
 			bool initial = false;
 			int cycle = 0;
 			for(auto &time : edges) {
-				log("Co-simulating cycle %d [%zu %s].\n", cycle+1, time, fst->getTimescaleString());
+				log("Co-simulating cycle %d [%zu%s].\n", cycle+1, time, fst->getTimescaleString());
 				for(auto &item : inputs) {
 					std::string v = fst->valueAt(item.second, time);
 					top->set_state(item.first, Const::from_string(v));
-- 
cgit v1.2.3


From eabd0ff11560e2d22d007a61010ac9231b413d37 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 13:41:02 +0100
Subject: Compare bits when not all are defined

---
 passes/sat/sim.cc | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index f08a3eb1f..34a56ff40 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -744,14 +744,28 @@ struct SimInstance
 			if (item.second==0) continue; // Ignore signals not found
 			Const fst_val = Const::from_string(shared->fst->valueAt(item.second, time));
 			Const sim_val = get_state(item.first);
+			if (sim_val.size()!=fst_val.size())
+				log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
 			if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
-				// TODO: check bit by bit
+				for(int i=0;i<fst_val.size();i++) {
+					if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
+						log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+						retVal = true;
+						break;
+					}
+				}
 			} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
-				// TODO: check bit by bit
+				for(int i=0;i<sim_val.size();i++) {
+					if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
+						log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+						retVal = true;
+						break;
+					}
+				}
 			} else {
 				if (fst_val!=sim_val) {
+					log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 					retVal = true;
-					log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 				}
 			}
 			//log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
-- 
cgit v1.2.3


From 1b5ff92e6240c1a12cb3f28adb1b5d0dda77b6e7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 13:45:28 +0100
Subject: Cleanup

---
 passes/sat/sim.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 34a56ff40..050fc8d5a 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -768,7 +768,6 @@ struct SimInstance
 					retVal = true;
 				}
 			}
-			//log("signal: %s fst: %s  sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 		}
 		for (auto child : children)
 			retVal |= child.second->checkSignals(time);
@@ -1048,6 +1047,7 @@ struct SimWorker : SimShared
 			fst->reconstructAllAtTimes(edges);
 			bool initial = false;
 			int cycle = 0;
+			log("Co-simulation from %zu%s to %zu%s\n", startCount, fst->getTimescaleString(), stopCount, fst->getTimescaleString());
 			for(auto &time : edges) {
 				log("Co-simulating cycle %d [%zu%s].\n", cycle+1, time, fst->getTimescaleString());
 				for(auto &item : inputs) {
-- 
cgit v1.2.3


From 8ba2000a50dcfedbcda57cfebabbfb39caabcfb9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 17:41:50 +0100
Subject: error when no signal found

---
 passes/sat/sim.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 050fc8d5a..c6fc1518f 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -994,6 +994,8 @@ struct SimWorker : SimShared
 		for (auto wire : topmod->wires()) {
 			if (wire->port_input) {
 				fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
+				if (id==0)
+					log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
 				inputs[wire] = id;
 			}
 		}
-- 
cgit v1.2.3


From 820b2fdd65c4022b555b440beabc65b123421090 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 2 Feb 2022 09:37:32 +0100
Subject: added stimulus mode and param check

---
 passes/sat/sim.cc | 36 +++++++++++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 5 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index c6fc1518f..bb1b1dfa3 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -29,6 +29,7 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 enum class SimulationMode {
+	sim,
 	cmp,
 	gold,
 	gate,
@@ -73,7 +74,7 @@ struct SimShared
 	FstData *fst = nullptr;
 	double start_time = 0;
 	double stop_time = -1;
-	SimulationMode sim_mode = SimulationMode::cmp;
+	SimulationMode sim_mode = SimulationMode::sim;
 	bool cycles_set = false;
 };
 
@@ -746,7 +747,9 @@ struct SimInstance
 			Const sim_val = get_state(item.first);
 			if (sim_val.size()!=fst_val.size())
 				log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
-			if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
+			if (shared->sim_mode == SimulationMode::sim) {
+				// No checks performed when using stimulus
+			} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
 				for(int i=0;i<fst_val.size();i++) {
 					if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
 						log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
@@ -1109,10 +1112,10 @@ struct SimPass : public Pass {
 		log("        include the specified timescale declaration in the vcd\n");
 		log("\n");
 		log("    -n <integer>\n");
-		log("        number of cycles to simulate (default: 20)\n");
+		log("        number of clock cycles to simulate (default: 20)\n");
 		log("\n");
 		log("    -a\n");
-		log("        include all nets in VCD output, not just those with public names\n");
+		log("        use all nets in VCD/FST operations, not just those with public names\n");
 		log("\n");
 		log("    -w\n");
 		log("        writeback mode: use final simulation state as new init state\n");
@@ -1123,14 +1126,20 @@ struct SimPass : public Pass {
 		log("    -scope\n");
 		log("        scope of simulation top model\n");
 		log("\n");
+		log("    -at <time>\n");
+		log("        sets start and stop time\n");
+		log("\n");
 		log("    -start <time>\n");
 		log("        start co-simulation in arbitary time (default 0)\n");
 		log("\n");
 		log("    -stop <time>\n");
 		log("        stop co-simulation in arbitary time (default END)\n");
 		log("\n");
+		log("    -sim\n");
+		log("        simulation with stimulus from FST (default)\n");
+		log("\n");
 		log("    -sim-cmp\n");
-		log("        co-simulation expect exact match (default)\n");
+		log("        co-simulation expect exact match\n");
 		log("\n");
 		log("    -sim-gold\n");
 		log("        co-simulation, x in simulation can match any value in FST\n");
@@ -1146,6 +1155,7 @@ struct SimPass : public Pass {
 	{
 		SimWorker worker;
 		int numcycles = 20;
+		bool start_set = false, stop_set = false, at_set = false;
 
 		log_header(design, "Executing SIM pass (simulate the circuit).\n");
 
@@ -1220,10 +1230,22 @@ struct SimPass : public Pass {
 			}
 			if (args[argidx] == "-start" && argidx+1 < args.size()) {
 				worker.start_time = stringToTime(args[++argidx]);
+				start_set = true;
 				continue;
 			}
 			if (args[argidx] == "-stop" && argidx+1 < args.size()) {
 				worker.stop_time = stringToTime(args[++argidx]);
+				stop_set = true;
+				continue;
+			}
+			if (args[argidx] == "-at" && argidx+1 < args.size()) {
+				worker.start_time = stringToTime(args[++argidx]);
+				worker.stop_time = worker.start_time;
+				at_set = true;
+				continue;
+			}
+			if (args[argidx] == "-sim") {
+				worker.sim_mode = SimulationMode::sim;
 				continue;
 			}
 			if (args[argidx] == "-sim-cmp") {
@@ -1241,6 +1263,10 @@ struct SimPass : public Pass {
 			break;
 		}
 		extra_args(args, argidx, design);
+		if (at_set && (start_set || stop_set || worker.cycles_set))
+			log_error("'at' option can only be defined separate of 'start','stop' and 'n'\n");
+		if (stop_set && worker.cycles_set)
+			log_error("'stop' and 'n' can only be used exclusively'\n");
 
 		Module *top_mod = nullptr;
 
-- 
cgit v1.2.3


From 169ffcd2fbd037aa1d827515af5a95a28299b832 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 2 Feb 2022 10:08:23 +0100
Subject: unify cycles counting and cleanup

---
 passes/sat/sim.cc | 71 +++++++++++++++++++++++++++----------------------------
 1 file changed, 35 insertions(+), 36 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index bb1b1dfa3..3c8d03cba 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -921,7 +921,8 @@ struct SimWorker : SimShared
 		{
 			if (debug)
 				log("\n===== %d =====\n", 10*cycle + 5);
-
+			else
+				log("Simulating cycle %d.\n", (cycle*2)+1);
 			set_inports(clock, State::S0);
 			set_inports(clockn, State::S1);
 
@@ -931,7 +932,7 @@ struct SimWorker : SimShared
 			if (debug)
 				log("\n===== %d =====\n", 10*cycle + 10);
 			else
-				log("Simulating cycle %d.\n", cycle+1);
+				log("Simulating cycle %d.\n", (cycle*2)+2);
 
 			set_inports(clock, State::S1);
 			set_inports(clockn, State::S0);
@@ -1034,42 +1035,40 @@ struct SimWorker : SimShared
 		if (stopCount<startCount) {
 			log_error("Stop time is before start time\n");
 		}
-		auto edges = fst->getAllEdges(fst_clock, startCount, stopCount);
-		if (cycles_set && ((size_t)(numcycles *2) < edges.size()))
-			edges.erase(edges.begin() + (numcycles*2), edges.end());
-
-		if ((startCount == stopCount) && writeback) {
-			log("Update initial state with values from [%zu%s]\n", startCount, fst->getTimescaleString());
-			if (edges.empty())
-				edges.push_back(startCount);
-			fst->reconstructAllAtTimes(edges);
-			top->setInitState(startCount);
+		auto samples = fst->getAllEdges(fst_clock, startCount, stopCount);
+
+		// Limit to number of cycles if provided
+		if (cycles_set && ((size_t)(numcycles *2) < samples.size()))
+			samples.erase(samples.begin() + (numcycles*2), samples.end());
+
+		// Add setup time (start time)
+		if (samples.empty() || samples.front()!=startCount)
+			samples.insert(samples.begin(), startCount);
+
+		fst->reconstructAllAtTimes(samples);
+		bool initial = true;
+		int cycle = 0;
+		log("Co-simulation from %zu%s to %zu%s\n", startCount, fst->getTimescaleString(), stopCount, fst->getTimescaleString());
+		for(auto &time : samples) {
+			log("Co-simulating cycle %d [%zu%s].\n", cycle, time, fst->getTimescaleString());
+			for(auto &item : inputs) {
+				std::string v = fst->valueAt(item.second, time);
+				top->set_state(item.first, Const::from_string(v));
+			}
+			if (initial) {
+				top->setInitState(time);
+				initial = false;
+			}
+			update();
+
+			bool status = top->checkSignals(time);
+			if (status)
+				log_error("Signal difference\n");
+			cycle++;
+		}
+		if (writeback) {
 			pool<Module*> wbmods;
 			top->writeback(wbmods);
-		} else {
-			if (edges.empty())
-				log_error("No clock edges found in given time range\n");
-			fst->reconstructAllAtTimes(edges);
-			bool initial = false;
-			int cycle = 0;
-			log("Co-simulation from %zu%s to %zu%s\n", startCount, fst->getTimescaleString(), stopCount, fst->getTimescaleString());
-			for(auto &time : edges) {
-				log("Co-simulating cycle %d [%zu%s].\n", cycle+1, time, fst->getTimescaleString());
-				for(auto &item : inputs) {
-					std::string v = fst->valueAt(item.second, time);
-					top->set_state(item.first, Const::from_string(v));
-				}
-				if (!initial) {
-					top->setInitState(time);
-					initial = true;
-				}
-				update();
-
-				bool status = top->checkSignals(time);
-				if (status)
-					log_error("Signal difference\n");
-				cycle++;
-			}
 		}
 	}
 };
-- 
cgit v1.2.3


From 990aee5531f41fdf01887870047eb924f12618b9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 2 Feb 2022 10:15:22 +0100
Subject: respect hide_internal flag

---
 passes/sat/sim.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 3c8d03cba..d33c20c51 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -161,7 +161,7 @@ struct SimInstance
 				}
 			}
 
-			if (shared->fst) {
+			if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
 				fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
 				if (id==0 && wire->name.isPublic())
 					log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str());
-- 
cgit v1.2.3


From 6db23de7b13c57eb82489d4bf2f0658b6deb4488 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Feb 2022 10:01:06 +0100
Subject: bug fix and cleanups

---
 passes/sat/sim.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index d33c20c51..b2425b531 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -752,7 +752,7 @@ struct SimInstance
 			} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
 				for(int i=0;i<fst_val.size();i++) {
 					if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
-						log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+						log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 						retVal = true;
 						break;
 					}
@@ -760,14 +760,14 @@ struct SimInstance
 			} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
 				for(int i=0;i<sim_val.size();i++) {
 					if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
-						log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+						log_warning("Signal '%s' in file %s in simulation %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 						retVal = true;
 						break;
 					}
 				}
 			} else {
 				if (fst_val!=sim_val) {
-					log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+					log_warning("Signal '%s' in file %s in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
 					retVal = true;
 				}
 			}
@@ -1048,9 +1048,9 @@ struct SimWorker : SimShared
 		fst->reconstructAllAtTimes(samples);
 		bool initial = true;
 		int cycle = 0;
-		log("Co-simulation from %zu%s to %zu%s\n", startCount, fst->getTimescaleString(), stopCount, fst->getTimescaleString());
+		log("Co-simulation from %lu%s to %lu%s\n", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
 		for(auto &time : samples) {
-			log("Co-simulating cycle %d [%zu%s].\n", cycle, time, fst->getTimescaleString());
+			log("Co-simulating cycle %d [%lu%s].\n", cycle, (unsigned long)time, fst->getTimescaleString());
 			for(auto &item : inputs) {
 				std::string v = fst->valueAt(item.second, time);
 				top->set_state(item.first, Const::from_string(v));
-- 
cgit v1.2.3


From c0a156bcb43bb0bb42eb3f2d94c12cda9ca5ee37 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Feb 2022 11:11:36 +0100
Subject: Error detection for co-simulation

---
 passes/sat/sim.cc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'passes/sat')

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index b2425b531..0687e3e0f 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -961,6 +961,9 @@ struct SimWorker : SimShared
 		log_assert(top == nullptr);
 		fst = new FstData(sim_filename);
 
+		if (scope.empty())
+			log_error("Scope must be defined for co-simulation.\n");
+
 		top = new SimInstance(this, scope, topmod);
 
 		std::vector<fstHandle> fst_clock;
-- 
cgit v1.2.3