From b08797da6bf0061073dc662441e03b2fd218f11f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 21:33:14 -0700 Subject: Only pack out registers if \init is zero or x; then remove \init from PREG --- passes/pmgen/xilinx_dsp.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'passes/pmgen/xilinx_dsp.cc') diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 055b3d6aa..5d50c7795 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -451,6 +451,16 @@ void pack_xilinx_dsp(dict &bit_to_driver, xilinx_dsp_pm &pm) P.replace(pm.sigmap(D), Q); st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); + for (auto c : Q.chunks()) { + auto it = c.wire->attributes.find("\\init"); + if (it == c.wire->attributes.end()) + continue; + for (int i = c.offset; i < c.offset+c.width; i++) { + log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx); + it->second[i] = State::Sx; + } + } + cell->setParam("\\PREG", State::S1); } -- cgit v1.2.3