From 8f0e796be131c2a47694e786ff901cc9970917c6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 10:38:13 -0700
Subject: Add support for ice40 signed multipliers

---
 passes/pmgen/ice40_dsp.cc | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 39d033a04..963a7d7a1 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -62,32 +62,27 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		return;
 	}
 
-	bool mul_signed = st.mul->getParam("\\A_SIGNED").as_bool();
-
-	if (mul_signed) {
-		log("  inference of signed iCE40 DSP arithmetic is currently not supported.\n");
-		return;
-	}
-
-	log("  replacing $mul with SB_MAC16 cell.\n");
+	log("  replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
 
 	Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
 	pm.module->swap_names(cell, st.mul);
 
 	// SB_MAC16 Input Interface
+	bool a_signed = st.mul->getParam("\\A_SIGNED").as_bool();
+	bool b_signed = st.mul->getParam("\\B_SIGNED").as_bool();
 
 	SigSpec A = st.sigA;
-	A.extend_u0(16, mul_signed);
+	A.extend_u0(16, a_signed);
 
 	SigSpec B = st.sigB;
-	B.extend_u0(16, mul_signed);
+	B.extend_u0(16, b_signed);
 
 	SigSpec CD;
 	if (st.muxA)
 		CD = st.muxA->getPort("\\B");
 	if (st.muxB)
 		CD = st.muxB->getPort("\\A");
-	CD.extend_u0(32, mul_signed);
+	CD.extend_u0(32, a_signed && b_signed);
 
 	cell->setPort("\\A", A);
 	cell->setPort("\\B", B);
@@ -198,8 +193,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
 
 	cell->setParam("\\MODE_8x8", State::S0);
-	cell->setParam("\\A_SIGNED", mul_signed ? State::S1 : State::S0);
-	cell->setParam("\\B_SIGNED", mul_signed ? State::S1 : State::S0);
+	cell->setParam("\\A_SIGNED", a_signed);
+	cell->setParam("\\B_SIGNED", b_signed);
 
 	pm.autoremove(st.mul);
 	pm.autoremove(st.ffY);
-- 
cgit v1.2.3


From 9ad11ea2cc25f764bcd4e27dfc12c0f8041cb48a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 10:57:32 -0700
Subject: Fine tune ice40_dsp.pmg, add support for packing subsets of registers

---
 passes/pmgen/ice40_dsp.cc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 963a7d7a1..f6a701540 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -23,13 +23,16 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+template<class T> bool includes(const T &lhs, const T &rhs) {
+	return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
+}
 #include "passes/pmgen/ice40_dsp_pm.h"
 
 void create_ice40_dsp(ice40_dsp_pm &pm)
 {
 	auto &st = pm.st_ice40_dsp;
 
-#if 0
+#if 1
 	log("\n");
 	log("ffA:   %s\n", log_id(st.ffA, "--"));
 	log("ffB:   %s\n", log_id(st.ffB, "--"));
@@ -100,7 +103,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setPort("\\IRSTTOP", State::S0);
 	cell->setPort("\\IRSTBOT", State::S0);
 
-	if (st.clock_vld)
+	if (st.clock != SigBit())
 	{
 		cell->setPort("\\CLK", st.clock);
 		cell->setPort("\\CE", State::S1);
-- 
cgit v1.2.3


From 5a14b6e1f6331d7587d566173e0d82e0c6c77f4c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Jul 2019 13:01:49 -0700
Subject: Pack adders not just accumulators

---
 passes/pmgen/ice40_dsp.cc | 38 ++++++++++++++++++++++++++------------
 1 file changed, 26 insertions(+), 12 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f6a701540..7215ed473 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -80,17 +80,25 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	SigSpec B = st.sigB;
 	B.extend_u0(16, b_signed);
 
+        // MAC only if ffS exists and adder's other input (sigS)
+        //   is output of ffS
+        bool accum = (st.ffS && st.sigS == st.ffS->getPort("\\Q"));
+
 	SigSpec CD;
-	if (st.muxA)
-		CD = st.muxA->getPort("\\B");
-	if (st.muxB)
-		CD = st.muxB->getPort("\\A");
+        if (st.ffS) {
+                if (st.muxA)
+                        CD = st.muxA->getPort("\\B");
+                else if (st.muxB)
+                        CD = st.muxB->getPort("\\A");
+        }
+        else if (!accum)
+                CD = st.sigS.extend_u0(32, st.sigS_signed);
 	CD.extend_u0(32, a_signed && b_signed);
 
 	cell->setPort("\\A", A);
 	cell->setPort("\\B", B);
-	cell->setPort("\\C", CD.extract(0, 16));
-	cell->setPort("\\D", CD.extract(16, 16));
+	cell->setPort("\\C", CD.extract(16, 16));
+	cell->setPort("\\D", CD.extract(0, 16));
 
 	cell->setParam("\\A_REG", st.ffA ? State::S1 : State::S0);
 	cell->setParam("\\B_REG", st.ffB ? State::S1 : State::S0);
@@ -145,14 +153,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Output Interface
 
-	SigSpec O = st.ffS ? st.sigS : st.sigY;
+        if (st.addAB) log_cell(st.addAB);
+	SigSpec O = st.ffS ? st.sigS : (st.addAB ? st.addAB->getPort("\\Y") : st.sigY);
 	if (GetSize(O) < 32)
 		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 
 	cell->setPort("\\O", O);
 
 	if (st.addAB) {
-		log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+                log_warning("sigS = %s\n", log_signal(st.sigS));
+                if (accum)
+                        log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+                else
+                        log("  adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
 		cell->setPort("\\ADDSUBTOP", st.addAB->type == "$add" ? State::S0 : State::S1);
 		cell->setPort("\\ADDSUBBOT", st.addAB->type == "$add" ? State::S0 : State::S1);
 	} else {
@@ -185,14 +198,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffY ? State::S1 : State::S0);
 	cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
 
-	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : 3, 2));
+	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
-	cell->setParam("\\TOPADDSUB_UPPERINPUT", State::S0);
+	cell->setParam("\\TOPADDSUB_UPPERINPUT", st.ffS ? State::S0 : State::S1);
 	cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
 
-	cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : 3, 2));
+	cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
-	cell->setParam("\\BOTADDSUB_UPPERINPUT", State::S0);
+	cell->setParam("\\BOTADDSUB_UPPERINPUT", st.ffS ? State::S0 : State::S1);
 	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
 
 	cell->setParam("\\MODE_8x8", State::S0);
@@ -201,6 +214,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	pm.autoremove(st.mul);
 	pm.autoremove(st.ffY);
+	pm.autoremove(st.addAB);
 	pm.autoremove(st.ffS);
 }
 
-- 
cgit v1.2.3


From 304cefbbe2b0c000c30e8d73d1761488be65ccf0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Jul 2019 15:05:16 -0700
Subject: Pack Y register

---
 passes/pmgen/ice40_dsp.cc | 48 +++++++++++++++++++++++++++++------------------
 1 file changed, 30 insertions(+), 18 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 7215ed473..5f6a20dfc 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -80,20 +80,25 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	SigSpec B = st.sigB;
 	B.extend_u0(16, b_signed);
 
-        // MAC only if ffS exists and adder's other input (sigS)
-        //   is output of ffS
-        bool accum = (st.ffS && st.sigS == st.ffS->getPort("\\Q"));
-
 	SigSpec CD;
-        if (st.ffS) {
-                if (st.muxA)
-                        CD = st.muxA->getPort("\\B");
-                else if (st.muxB)
-                        CD = st.muxB->getPort("\\A");
-        }
-        else if (!accum)
-                CD = st.sigS.extend_u0(32, st.sigS_signed);
-	CD.extend_u0(32, a_signed && b_signed);
+	bool CD_signed = false;
+	if (st.muxAB != st.addAB) {
+		if (st.muxA)
+			CD = st.muxA->getPort("\\B");
+		else if (st.muxB)
+			CD = st.muxB->getPort("\\A");
+		else log_abort();
+		CD_signed = a_signed && b_signed; // TODO: Do muxes have [AB]_SIGNED?
+	}
+	else if (st.addAB) {
+		if (st.addA)
+			CD = st.addAB->getPort("\\B");
+		else if (st.addB)
+			CD = st.addAB->getPort("\\A");
+		else log_abort();
+		CD_signed = st.sigS_signed;
+	}
+	CD.extend_u0(32, CD_signed);
 
 	cell->setPort("\\A", A);
 	cell->setPort("\\B", B);
@@ -153,15 +158,21 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Output Interface
 
-        if (st.addAB) log_cell(st.addAB);
 	SigSpec O = st.ffS ? st.sigS : (st.addAB ? st.addAB->getPort("\\Y") : st.sigY);
 	if (GetSize(O) < 32)
 		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 
 	cell->setPort("\\O", O);
 
+	// MAC only if ffS exists and adder's other input (sigS)
+	//   is output of ffS
+	bool accum = false;
 	if (st.addAB) {
-                log_warning("sigS = %s\n", log_signal(st.sigS));
+                if (st.addA)
+                      accum = (st.ffS && st.addAB->getPort("\\B") == st.ffS->getPort("\\Q"));
+                else if (st.addB)
+                      accum = (st.ffS && st.addAB->getPort("\\A") == st.ffS->getPort("\\Q"));
+                else log_abort();
                 if (accum)
                         log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
                 else
@@ -200,12 +211,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
-	cell->setParam("\\TOPADDSUB_UPPERINPUT", st.ffS ? State::S0 : State::S1);
+	cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
 	cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
 
 	cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
-	cell->setParam("\\BOTADDSUB_UPPERINPUT", st.ffS ? State::S0 : State::S1);
+	cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
 	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
 
 	cell->setParam("\\MODE_8x8", State::S0);
@@ -215,7 +226,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.autoremove(st.mul);
 	pm.autoremove(st.ffY);
 	pm.autoremove(st.addAB);
-	pm.autoremove(st.ffS);
+        if (st.ffS)
+                st.ffS->connections_.at("\\Q").replace(st.sigS, pm.module->addWire(NEW_ID, GetSize(st.sigS)));
 }
 
 struct Ice40DspPass : public Pass {
-- 
cgit v1.2.3


From 4d71ab384d640f53435d2e4773b2277f385cda27 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Jul 2019 15:08:26 -0700
Subject: Rename according to vendor doc TN1295

---
 passes/pmgen/ice40_dsp.cc | 48 +++++++++++++++++++++++------------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 5f6a20dfc..d4e2914d9 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -37,10 +37,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	log("ffA:   %s\n", log_id(st.ffA, "--"));
 	log("ffB:   %s\n", log_id(st.ffB, "--"));
 	log("mul:   %s\n", log_id(st.mul, "--"));
-	log("ffY:   %s\n", log_id(st.ffY, "--"));
+	log("ffH:   %s\n", log_id(st.ffH, "--"));
 	log("addAB: %s\n", log_id(st.addAB, "--"));
 	log("muxAB: %s\n", log_id(st.muxAB, "--"));
-	log("ffS:   %s\n", log_id(st.ffS, "--"));
+	log("ffO:   %s\n", log_id(st.ffO, "--"));
 #endif
 
 	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -55,13 +55,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		return;
 	}
 
-	if (GetSize(st.sigS) > 32) {
-		log("  accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigS), GetSize(st.sigS));
+	if (GetSize(st.sigO) > 32) {
+		log("  accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigO), GetSize(st.sigO));
 		return;
 	}
 
-	if (GetSize(st.sigY) > 32) {
-		log("  output (%s) is too large (%d > 32).\n", log_signal(st.sigY), GetSize(st.sigY));
+	if (GetSize(st.sigH) > 32) {
+		log("  output (%s) is too large (%d > 32).\n", log_signal(st.sigH), GetSize(st.sigH));
 		return;
 	}
 
@@ -96,7 +96,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		else if (st.addB)
 			CD = st.addAB->getPort("\\A");
 		else log_abort();
-		CD_signed = st.sigS_signed;
+		CD_signed = st.sigO_signed;
 	}
 	CD.extend_u0(32, CD_signed);
 
@@ -130,11 +130,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		if (st.ffB)
 			log(" ffB:%s", log_id(st.ffB));
 
-		if (st.ffY)
-			log(" ffY:%s", log_id(st.ffY));
+		if (st.ffH)
+			log(" ffH:%s", log_id(st.ffH));
 
-		if (st.ffS)
-			log(" ffS:%s", log_id(st.ffS));
+		if (st.ffO)
+			log(" ffO:%s", log_id(st.ffO));
 
 		log("\n");
 	}
@@ -158,20 +158,20 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Output Interface
 
-	SigSpec O = st.ffS ? st.sigS : (st.addAB ? st.addAB->getPort("\\Y") : st.sigY);
+	SigSpec O = st.ffO ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH);
 	if (GetSize(O) < 32)
 		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 
 	cell->setPort("\\O", O);
 
-	// MAC only if ffS exists and adder's other input (sigS)
-	//   is output of ffS
+	// MAC only if ffO exists and adder's other input (sigO)
+	//   is output of ffO
 	bool accum = false;
 	if (st.addAB) {
                 if (st.addA)
-                      accum = (st.ffS && st.addAB->getPort("\\B") == st.ffS->getPort("\\Q"));
+                      accum = (st.ffO && st.addAB->getPort("\\B") == st.ffO->getPort("\\Q"));
                 else if (st.addB)
-                      accum = (st.ffS && st.addAB->getPort("\\A") == st.ffS->getPort("\\Q"));
+                      accum = (st.ffO && st.addAB->getPort("\\A") == st.ffO->getPort("\\Q"));
                 else log_abort();
                 if (accum)
                         log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
@@ -204,17 +204,17 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\C_REG", State::S0);
 	cell->setParam("\\D_REG", State::S0);
 
-	cell->setParam("\\TOP_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
-	cell->setParam("\\BOT_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
-	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffY ? State::S1 : State::S0);
+	cell->setParam("\\TOP_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
+	cell->setParam("\\BOT_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
+	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffH ? State::S1 : State::S0);
 	cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
 
-	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
+	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
 	cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
 	cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
 
-	cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
+	cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
 	cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
 	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
@@ -224,10 +224,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\B_SIGNED", b_signed);
 
 	pm.autoremove(st.mul);
-	pm.autoremove(st.ffY);
+	pm.autoremove(st.ffH);
 	pm.autoremove(st.addAB);
-        if (st.ffS)
-                st.ffS->connections_.at("\\Q").replace(st.sigS, pm.module->addWire(NEW_ID, GetSize(st.sigS)));
+        if (st.ffO)
+                st.ffO->connections_.at("\\Q").replace(st.sigO, pm.module->addWire(NEW_ID, GetSize(st.sigO)));
 }
 
 struct Ice40DspPass : public Pass {
-- 
cgit v1.2.3


From 068617f0948b411fcf9cdf047c6dfc600a0689bb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Jul 2019 16:12:57 -0700
Subject: Pack hi and lo registers separately

---
 passes/pmgen/ice40_dsp.cc | 47 +++++++++++++++++++++++++++--------------------
 1 file changed, 27 insertions(+), 20 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index d4e2914d9..6b6fd5640 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -34,13 +34,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 #if 1
 	log("\n");
-	log("ffA:   %s\n", log_id(st.ffA, "--"));
-	log("ffB:   %s\n", log_id(st.ffB, "--"));
-	log("mul:   %s\n", log_id(st.mul, "--"));
-	log("ffH:   %s\n", log_id(st.ffH, "--"));
-	log("addAB: %s\n", log_id(st.addAB, "--"));
-	log("muxAB: %s\n", log_id(st.muxAB, "--"));
-	log("ffO:   %s\n", log_id(st.ffO, "--"));
+	log("ffA:    %s\n", log_id(st.ffA, "--"));
+	log("ffB:    %s\n", log_id(st.ffB, "--"));
+	log("mul:    %s\n", log_id(st.mul, "--"));
+	log("ffH:    %s\n", log_id(st.ffH, "--"));
+	log("addAB:  %s\n", log_id(st.addAB, "--"));
+	log("muxAB:  %s\n", log_id(st.muxAB, "--"));
+	log("ffO_lo: %s\n", log_id(st.ffO_lo, "--"));
+	log("ffO_hi: %s\n", log_id(st.ffO_hi, "--"));
 #endif
 
 	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -133,8 +134,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		if (st.ffH)
 			log(" ffH:%s", log_id(st.ffH));
 
-		if (st.ffO)
-			log(" ffO:%s", log_id(st.ffO));
+		if (st.ffO_lo)
+			log(" ffO_lo:%s", log_id(st.ffO_lo));
+		if (st.ffO_hi)
+			log(" ffO_hi:%s", log_id(st.ffO_hi));
 
 		log("\n");
 	}
@@ -158,20 +161,22 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Output Interface
 
-	SigSpec O = st.ffO ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH);
-	if (GetSize(O) < 32)
-		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
+	SigSpec O_lo = (st.ffO_lo ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(0,16);
+	if (GetSize(O_lo) < 16)
+		O_lo.append(pm.module->addWire(NEW_ID, 16-GetSize(O_lo)));
+	SigSpec O_hi = (st.ffO_hi ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(16,16);
+	if (GetSize(O_hi) < 16)
+		O_hi.append(pm.module->addWire(NEW_ID, 16-GetSize(O_hi)));
 
+	SigSpec O{O_hi,O_lo};
 	cell->setPort("\\O", O);
 
-	// MAC only if ffO exists and adder's other input (sigO)
-	//   is output of ffO
 	bool accum = false;
 	if (st.addAB) {
                 if (st.addA)
-                      accum = (st.ffO && st.addAB->getPort("\\B") == st.ffO->getPort("\\Q"));
+                      accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == O);
                 else if (st.addB)
-                      accum = (st.ffO && st.addAB->getPort("\\A") == st.ffO->getPort("\\Q"));
+                      accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == O);
                 else log_abort();
                 if (accum)
                         log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
@@ -209,12 +214,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffH ? State::S1 : State::S0);
 	cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
 
-	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2));
+	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO_hi ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
 	cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
 	cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
 
-	cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2));
+	cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO_lo ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
 	cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
 	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
@@ -226,8 +231,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.autoremove(st.mul);
 	pm.autoremove(st.ffH);
 	pm.autoremove(st.addAB);
-        if (st.ffO)
-                st.ffO->connections_.at("\\Q").replace(st.sigO, pm.module->addWire(NEW_ID, GetSize(st.sigO)));
+        if (st.ffO_lo)
+                st.ffO_lo->connections_.at("\\Q").replace(O.extract(0,16), pm.module->addWire(NEW_ID, 16));
+        if (st.ffO_hi)
+                st.ffO_hi->connections_.at("\\Q").replace(O.extract(16,16), pm.module->addWire(NEW_ID, 16));
 }
 
 struct Ice40DspPass : public Pass {
-- 
cgit v1.2.3


From 33c984a0445b2bb24081adf324b2254c454266d1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Jul 2019 16:37:13 -0700
Subject: Fix spacing

---
 passes/pmgen/ice40_dsp.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 6b6fd5640..f365ae8b6 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -174,9 +174,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	bool accum = false;
 	if (st.addAB) {
                 if (st.addA)
-                      accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == O);
+			accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == O);
                 else if (st.addB)
-                      accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == O);
+			accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == O);
                 else log_abort();
                 if (accum)
                         log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
-- 
cgit v1.2.3


From dc0c853abeadd11e81da280c657fd1341405de3b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Jul 2019 14:20:34 -0700
Subject: Simplify and fix for MACs

---
 passes/pmgen/ice40_dsp.cc | 61 ++++++++++++++++-------------------------------
 1 file changed, 20 insertions(+), 41 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f365ae8b6..f18fad060 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -81,25 +81,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	SigSpec B = st.sigB;
 	B.extend_u0(16, b_signed);
 
-	SigSpec CD;
-	bool CD_signed = false;
-	if (st.muxAB != st.addAB) {
-		if (st.muxA)
-			CD = st.muxA->getPort("\\B");
-		else if (st.muxB)
-			CD = st.muxB->getPort("\\A");
-		else log_abort();
-		CD_signed = a_signed && b_signed; // TODO: Do muxes have [AB]_SIGNED?
-	}
-	else if (st.addAB) {
-		if (st.addA)
-			CD = st.addAB->getPort("\\B");
-		else if (st.addB)
-			CD = st.addAB->getPort("\\A");
-		else log_abort();
-		CD_signed = st.sigO_signed;
-	}
-	CD.extend_u0(32, CD_signed);
+	SigSpec CD = st.sigCD;
+	CD.extend_u0(32, st.sigCD_signed);
 
 	cell->setPort("\\A", A);
 	cell->setPort("\\B", B);
@@ -161,27 +144,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Output Interface
 
-	SigSpec O_lo = (st.ffO_lo ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(0,16);
-	if (GetSize(O_lo) < 16)
-		O_lo.append(pm.module->addWire(NEW_ID, 16-GetSize(O_lo)));
-	SigSpec O_hi = (st.ffO_hi ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(16,16);
-	if (GetSize(O_hi) < 16)
-		O_hi.append(pm.module->addWire(NEW_ID, 16-GetSize(O_hi)));
-
-	SigSpec O{O_hi,O_lo};
-	cell->setPort("\\O", O);
+	cell->setPort("\\O", st.sigO);
 
 	bool accum = false;
 	if (st.addAB) {
-                if (st.addA)
-			accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == O);
-                else if (st.addB)
-			accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == O);
-                else log_abort();
-                if (accum)
-                        log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
-                else
-                        log("  adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+		if (st.addA)
+			accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == st.sigO);
+		else if (st.addB)
+			accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == st.sigO);
+		else log_abort();
+		if (accum)
+			log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+		else
+			log("  adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
 		cell->setPort("\\ADDSUBTOP", st.addAB->type == "$add" ? State::S0 : State::S1);
 		cell->setPort("\\ADDSUBBOT", st.addAB->type == "$add" ? State::S0 : State::S1);
 	} else {
@@ -231,10 +206,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.autoremove(st.mul);
 	pm.autoremove(st.ffH);
 	pm.autoremove(st.addAB);
-        if (st.ffO_lo)
-                st.ffO_lo->connections_.at("\\Q").replace(O.extract(0,16), pm.module->addWire(NEW_ID, 16));
-        if (st.ffO_hi)
-                st.ffO_hi->connections_.at("\\Q").replace(O.extract(16,16), pm.module->addWire(NEW_ID, 16));
+	if (st.ffO_lo) {
+			SigSpec O = st.sigO.extract(0,16);
+			st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+	}
+	if (st.ffO_hi) {
+			SigSpec O = st.sigO.extract(16,16);
+			st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+	}
 }
 
 struct Ice40DspPass : public Pass {
-- 
cgit v1.2.3


From 0dd2a125f655c459b17b5c56c4d34a21d0833bc8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Jul 2019 14:21:45 -0700
Subject: Remove debug print

---
 passes/pmgen/ice40_dsp.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f18fad060..ee4e4f5e8 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -32,7 +32,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 {
 	auto &st = pm.st_ice40_dsp;
 
-#if 1
+#if 0
 	log("\n");
 	log("ffA:    %s\n", log_id(st.ffA, "--"));
 	log("ffB:    %s\n", log_id(st.ffB, "--"));
-- 
cgit v1.2.3


From 79fd6edc5a076d263a9d68f0e1a103a9d643a9df Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Jul 2019 15:13:30 -0700
Subject: Eliminate warnings by sizing O correctly

---
 passes/pmgen/ice40_dsp.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index ee4e4f5e8..3ceffdbf6 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -144,7 +144,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Output Interface
 
-	cell->setPort("\\O", st.sigO);
+	SigSpec O = st.sigO;
+	if (GetSize(O) < 32)
+		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
+
+	cell->setPort("\\O", O);
 
 	bool accum = false;
 	if (st.addAB) {
-- 
cgit v1.2.3


From c1a05f45577223c0585e93d728c8e04169c4598d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Jul 2019 10:15:36 -0700
Subject: Allow adders/accumulators with 33 bits using CO output

---
 passes/pmgen/ice40_dsp.cc | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 3ceffdbf6..c5655ad20 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -56,8 +56,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		return;
 	}
 
-	if (GetSize(st.sigO) > 32) {
-		log("  accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigO), GetSize(st.sigO));
+	if (GetSize(st.sigO) > 33) {
+		log("  adder/accumulator (%s) is too large (%d > 33).\n", log_signal(st.sigO), GetSize(st.sigO));
 		return;
 	}
 
@@ -137,7 +137,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID));
 
 	cell->setPort("\\CI", State::Sx);
-	cell->setPort("\\CO", pm.module->addWire(NEW_ID));
 
 	cell->setPort("\\ACCUMCI", State::Sx);
 	cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID));
@@ -145,6 +144,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	// SB_MAC16 Output Interface
 
 	SigSpec O = st.sigO;
+	if (GetSize(O) == 33)
+		cell->setPort("\\CO", st.sigO[32]);
+	else {
+		log_assert(GetSize(O) <= 32);
+		cell->setPort("\\CO", pm.module->addWire(NEW_ID));
+	}
 	if (GetSize(O) < 32)
 		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 
-- 
cgit v1.2.3


From 4c25d1a76fc006cac0d9e2038617f41ca90685c1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Jul 2019 10:27:30 -0700
Subject: Pop the CO bit from O

---
 passes/pmgen/ice40_dsp.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index c5655ad20..369cb211e 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -144,8 +144,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	// SB_MAC16 Output Interface
 
 	SigSpec O = st.sigO;
-	if (GetSize(O) == 33)
+	if (GetSize(O) == 33) {
 		cell->setPort("\\CO", st.sigO[32]);
+		O.remove(32);
+	}
 	else {
 		log_assert(GetSize(O) <= 32);
 		cell->setPort("\\CO", pm.module->addWire(NEW_ID));
-- 
cgit v1.2.3


From e4a638c29297e3e8b915cf84a2dddc339f511476 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 31 Jul 2019 15:45:15 -0700
Subject: Restore old CO behaviour

---
 passes/pmgen/ice40_dsp.cc | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 369cb211e..00794ca0d 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -144,14 +144,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	// SB_MAC16 Output Interface
 
 	SigSpec O = st.sigO;
-	if (GetSize(O) == 33) {
-		cell->setPort("\\CO", st.sigO[32]);
-		O.remove(32);
+	int O_width = GetSize(O);
+	if (O_width == 33) {
+		log_assert(st.addAB);
+		cell->setPort("\\CO", O[-1]);
+		O.remove(O_width-1);
 	}
-	else {
-		log_assert(GetSize(O) <= 32);
+	else
 		cell->setPort("\\CO", pm.module->addWire(NEW_ID));
-	}
+	log_assert(GetSize(O) <= 32);
 	if (GetSize(O) < 32)
 		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 
-- 
cgit v1.2.3


From c54a39069d1f536da7a830fa2fa504bc72c20c18 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 1 Aug 2019 10:00:49 -0700
Subject: CO is sign extension only if signed multiplier

---
 passes/pmgen/ice40_dsp.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 00794ca0d..f88cd62dd 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -147,7 +147,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	int O_width = GetSize(O);
 	if (O_width == 33) {
 		log_assert(st.addAB);
-		cell->setPort("\\CO", O[-1]);
+		// If we have a signed multiply-add, then perform sign extension
+		// TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
+		if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool())
+			pm.module->connect(O[-1], O[-2]);
+		else
+			cell->setPort("\\CO", O[-1]);
 		O.remove(O_width-1);
 	}
 	else
-- 
cgit v1.2.3


From e19d33b003702a03b191fa2eda14d016a6bce0aa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 1 Aug 2019 12:44:56 -0700
Subject: Cope with sign extension in mul2dsp

---
 passes/pmgen/ice40_dsp.cc | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f88cd62dd..f6ae3a13f 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -72,17 +72,17 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.module->swap_names(cell, st.mul);
 
 	// SB_MAC16 Input Interface
-	bool a_signed = st.mul->getParam("\\A_SIGNED").as_bool();
-	bool b_signed = st.mul->getParam("\\B_SIGNED").as_bool();
-
 	SigSpec A = st.sigA;
-	A.extend_u0(16, a_signed);
+	log_assert(GetSize(A) == 16);
 
 	SigSpec B = st.sigB;
-	B.extend_u0(16, b_signed);
+	log_assert(GetSize(B) == 16);
 
 	SigSpec CD = st.sigCD;
-	CD.extend_u0(32, st.sigCD_signed);
+	if (CD.empty())
+		CD = RTLIL::Const(0, 32);
+	else
+		log_assert(GetSize(CD) == 32);
 
 	cell->setPort("\\A", A);
 	cell->setPort("\\B", B);
@@ -217,8 +217,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
 
 	cell->setParam("\\MODE_8x8", State::S0);
-	cell->setParam("\\A_SIGNED", a_signed);
-	cell->setParam("\\B_SIGNED", b_signed);
+	cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
+	cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
 	pm.autoremove(st.mul);
 	pm.autoremove(st.ffH);
-- 
cgit v1.2.3


From d90b8b081a6102303f2392fc21164fddde90e587 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 13:58:26 -0700
Subject: Do not SigSpec::extract() beyond bounds

---
 passes/pmgen/ice40_dsp.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f6ae3a13f..5e87d6497 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -224,11 +224,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.autoremove(st.ffH);
 	pm.autoremove(st.addAB);
 	if (st.ffO_lo) {
-			SigSpec O = st.sigO.extract(0,16);
+			SigSpec O = st.sigO.extract(0,GetSize(st.ffO_lo));
 			st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 	if (st.ffO_hi) {
-			SigSpec O = st.sigO.extract(16,16);
+			SigSpec O = st.sigO.extract(16,GetSize(st.ffo_hi));
 			st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 }
-- 
cgit v1.2.3


From fb568ddb4e2ccaab352d9d062f6b4926aca75680 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 14:31:55 -0700
Subject: Fix compile error

---
 passes/pmgen/ice40_dsp.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 5e87d6497..45d7a34df 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -224,11 +224,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.autoremove(st.ffH);
 	pm.autoremove(st.addAB);
 	if (st.ffO_lo) {
-			SigSpec O = st.sigO.extract(0,GetSize(st.ffO_lo));
+			SigSpec O = st.sigO.extract(0,st.ffO_lo->getParam("\\WIDTH").as_int());
 			st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 	if (st.ffO_hi) {
-			SigSpec O = st.sigO.extract(16,GetSize(st.ffo_hi));
+			SigSpec O = st.sigO.extract(16,st.ffO_hi->getParam("\\WIDTH").as_int());
 			st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 }
-- 
cgit v1.2.3


From 2c0be7aa5d7dcdf18678fb7b09ba1b3b5dd00998 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 8 Aug 2019 12:56:05 -0700
Subject: Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing

---
 passes/pmgen/ice40_dsp.cc | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 45d7a34df..bb45b8a4e 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -32,7 +32,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 {
 	auto &st = pm.st_ice40_dsp;
 
-#if 0
+#if 1
 	log("\n");
 	log("ffA:    %s\n", log_id(st.ffA, "--"));
 	log("ffB:    %s\n", log_id(st.ffB, "--"));
@@ -66,10 +66,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		return;
 	}
 
-	log("  replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
+	Cell *cell = st.mul;
+	if (cell->type == "$mul") {
+		log("  replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
 
-	Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
-	pm.module->swap_names(cell, st.mul);
+		cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
+		pm.module->swap_names(cell, st.mul);
+	}
+	else log_assert(cell->type == "\\SB_MAC16");
 
 	// SB_MAC16 Input Interface
 	SigSpec A = st.sigA;
@@ -220,15 +224,18 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
 	cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
-	pm.autoremove(st.mul);
+	if (cell != st.mul)
+		pm.autoremove(st.mul);
+	else
+		pm.blacklist(st.mul);
 	pm.autoremove(st.ffH);
 	pm.autoremove(st.addAB);
 	if (st.ffO_lo) {
-			SigSpec O = st.sigO.extract(0,st.ffO_lo->getParam("\\WIDTH").as_int());
+			SigSpec O = st.sigO.extract(0,std::min(16,st.ffO_lo->getParam("\\WIDTH").as_int()));
 			st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 	if (st.ffO_hi) {
-			SigSpec O = st.sigO.extract(16,st.ffO_hi->getParam("\\WIDTH").as_int());
+			SigSpec O = st.sigO.extract_end(16);
 			st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 }
-- 
cgit v1.2.3


From 1b0e68db945ee8a62a445cf41668844812c436eb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 13 Aug 2019 17:09:28 -0700
Subject: Revert changes to RTLIL::SigSpec methods

---
 passes/pmgen/ice40_dsp.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index bb45b8a4e..66f70399d 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -23,9 +23,10 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-template<class T> bool includes(const T &lhs, const T &rhs) {
+template<class T> inline bool includes(const T &lhs, const T &rhs) {
 	return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
 }
+#include <set>
 #include "passes/pmgen/ice40_dsp_pm.h"
 
 void create_ice40_dsp(ice40_dsp_pm &pm)
-- 
cgit v1.2.3


From aad97168b070509b7bd479ed3b9956452a28e3ec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 10:22:33 -0700
Subject: Fixes for reverting SigSpec helper functions

---
 passes/pmgen/ice40_dsp.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 66f70399d..6f0539679 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -155,9 +155,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		// If we have a signed multiply-add, then perform sign extension
 		// TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
 		if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool())
-			pm.module->connect(O[-1], O[-2]);
+			pm.module->connect(O[32], O[31]);
 		else
-			cell->setPort("\\CO", O[-1]);
+			cell->setPort("\\CO", O[32]);
 		O.remove(O_width-1);
 	}
 	else
-- 
cgit v1.2.3


From 27d5df9467fb425234a466d0d63b8a94e37ca596 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 15 Aug 2019 12:19:34 -0700
Subject: ffH -> ffFJKG

---
 passes/pmgen/ice40_dsp.cc | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 6f0539679..a1a397b83 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -38,7 +38,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	log("ffA:    %s\n", log_id(st.ffA, "--"));
 	log("ffB:    %s\n", log_id(st.ffB, "--"));
 	log("mul:    %s\n", log_id(st.mul, "--"));
-	log("ffH:    %s\n", log_id(st.ffH, "--"));
+	log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
 	log("addAB:  %s\n", log_id(st.addAB, "--"));
 	log("muxAB:  %s\n", log_id(st.muxAB, "--"));
 	log("ffO_lo: %s\n", log_id(st.ffO_lo, "--"));
@@ -119,8 +119,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		if (st.ffB)
 			log(" ffB:%s", log_id(st.ffB));
 
-		if (st.ffH)
-			log(" ffH:%s", log_id(st.ffH));
+		if (st.ffFJKG)
+			log(" ffFJKG:%s", log_id(st.ffFJKG));
 
 		if (st.ffO_lo)
 			log(" ffO_lo:%s", log_id(st.ffO_lo));
@@ -206,9 +206,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\C_REG", State::S0);
 	cell->setParam("\\D_REG", State::S0);
 
-	cell->setParam("\\TOP_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
-	cell->setParam("\\BOT_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
-	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffH ? State::S1 : State::S0);
+	cell->setParam("\\TOP_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
+	cell->setParam("\\BOT_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
+	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffFJKG ? State::S1 : State::S0);
 	cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
 
 	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO_hi ? 1 : (st.addAB ? 0 : 3), 2));
@@ -229,7 +229,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		pm.autoremove(st.mul);
 	else
 		pm.blacklist(st.mul);
-	pm.autoremove(st.ffH);
+	pm.autoremove(st.ffFJKG);
 	pm.autoremove(st.addAB);
 	if (st.ffO_lo) {
 			SigSpec O = st.sigO.extract(0,std::min(16,st.ffO_lo->getParam("\\WIDTH").as_int()));
-- 
cgit v1.2.3


From 4cc74346f11e96b9a2bce1c984c674a22771a00a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 20:27:05 -0700
Subject: Fix compile error

---
 passes/pmgen/ice40_dsp.cc | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index a1a397b83..31e11c742 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -23,10 +23,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-template<class T> inline bool includes(const T &lhs, const T &rhs) {
-	return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
-}
-#include <set>
 #include "passes/pmgen/ice40_dsp_pm.h"
 
 void create_ice40_dsp(ice40_dsp_pm &pm)
-- 
cgit v1.2.3


From 888ae1d05e322666821262218a87b3f5577b66d0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 17:58:19 -0700
Subject: Fix broken ice40_dsp

---
 passes/pmgen/ice40_dsp.cc | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 31e11c742..8f5191be7 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -28,6 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
 void create_ice40_dsp(ice40_dsp_pm &pm)
 {
 	auto &st = pm.st_ice40_dsp;
+	Cell* ffO = st.ffO ? st.ffO : st.ffO_lo;
 
 #if 1
 	log("\n");
@@ -37,8 +38,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
 	log("addAB:  %s\n", log_id(st.addAB, "--"));
 	log("muxAB:  %s\n", log_id(st.muxAB, "--"));
-	log("ffO_lo: %s\n", log_id(st.ffO_lo, "--"));
-	log("ffO_hi: %s\n", log_id(st.ffO_hi, "--"));
+	log("ffO:    %s\n", log_id(ffO, "--"));
 #endif
 
 	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -118,10 +118,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		if (st.ffFJKG)
 			log(" ffFJKG:%s", log_id(st.ffFJKG));
 
-		if (st.ffO_lo)
-			log(" ffO_lo:%s", log_id(st.ffO_lo));
-		if (st.ffO_hi)
-			log(" ffO_hi:%s", log_id(st.ffO_hi));
+		if (ffO)
+			log(" ffO:%s", log_id(ffO));
 
 		log("\n");
 	}
@@ -167,9 +165,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	bool accum = false;
 	if (st.addAB) {
 		if (st.addA)
-			accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == st.sigO);
+			accum = (ffO && st.addAB->getPort("\\B") == st.sigO);
 		else if (st.addB)
-			accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == st.sigO);
+			accum = (ffO && st.addAB->getPort("\\A") == st.sigO);
 		else log_abort();
 		if (accum)
 			log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
@@ -207,12 +205,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffFJKG ? State::S1 : State::S0);
 	cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
 
-	cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO_hi ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
 	cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
 	cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
 
-	cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO_lo ? 1 : (st.addAB ? 0 : 3), 2));
 	cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
 	cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
 	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
@@ -221,20 +217,26 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
 	cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
+	if (ffO) {
+		if (st.ffO)
+			cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
+		else
+			cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
+
+		ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+		cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));
+	}
+	else {
+		cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
+		cell->setParam("\\BOTOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
+	}
+
 	if (cell != st.mul)
 		pm.autoremove(st.mul);
 	else
 		pm.blacklist(st.mul);
 	pm.autoremove(st.ffFJKG);
 	pm.autoremove(st.addAB);
-	if (st.ffO_lo) {
-			SigSpec O = st.sigO.extract(0,std::min(16,st.ffO_lo->getParam("\\WIDTH").as_int()));
-			st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
-	}
-	if (st.ffO_hi) {
-			SigSpec O = st.sigO.extract_end(16);
-			st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
-	}
 }
 
 struct Ice40DspPass : public Pass {
-- 
cgit v1.2.3


From 5a2fc6fcb5141573cbfcebdec4354fc11056a8f4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 18:06:59 -0700
Subject: Refactor ice40_dsp

---
 passes/pmgen/ice40_dsp.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 8f5191be7..f62f627bb 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -74,9 +74,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Input Interface
 	SigSpec A = st.sigA;
+	A.extend_u0(16, st.mul->getParam("\\A_SIGNED").as_bool());
 	log_assert(GetSize(A) == 16);
 
 	SigSpec B = st.sigB;
+	B.extend_u0(16, st.mul->getParam("\\B_SIGNED").as_bool());
 	log_assert(GetSize(B) == 16);
 
 	SigSpec CD = st.sigCD;
-- 
cgit v1.2.3


From dc10559f31410e2395e1321d6ca6126024c7cea3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 21:39:52 -0700
Subject: Cleanup

---
 passes/pmgen/ice40_dsp.cc | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f62f627bb..7858b8972 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -28,7 +28,6 @@ PRIVATE_NAMESPACE_BEGIN
 void create_ice40_dsp(ice40_dsp_pm &pm)
 {
 	auto &st = pm.st_ice40_dsp;
-	Cell* ffO = st.ffO ? st.ffO : st.ffO_lo;
 
 #if 1
 	log("\n");
@@ -38,7 +37,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
 	log("addAB:  %s\n", log_id(st.addAB, "--"));
 	log("muxAB:  %s\n", log_id(st.muxAB, "--"));
-	log("ffO:    %s\n", log_id(ffO, "--"));
+	log("ffO:    %s\n", log_id(st.ffO, "--"));
 #endif
 
 	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -120,8 +119,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		if (st.ffFJKG)
 			log(" ffFJKG:%s", log_id(st.ffFJKG));
 
-		if (ffO)
-			log(" ffO:%s", log_id(ffO));
+		if (st.ffO)
+			log(" ffO:%s", log_id(st.ffO));
 
 		log("\n");
 	}
@@ -167,9 +166,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	bool accum = false;
 	if (st.addAB) {
 		if (st.addA)
-			accum = (ffO && st.addAB->getPort("\\B") == st.sigO);
+			accum = (st.ffO && st.addAB->getPort("\\B") == st.sigO);
 		else if (st.addB)
-			accum = (ffO && st.addAB->getPort("\\A") == st.sigO);
+			accum = (st.ffO && st.addAB->getPort("\\A") == st.sigO);
 		else log_abort();
 		if (accum)
 			log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
@@ -219,13 +218,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
 	cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
-	if (ffO) {
-		if (st.ffO)
+	if (st.ffO) {
+		if (st.ffO_hilo)
 			cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
 		else
 			cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
 
-		ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+		st.ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 		cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));
 	}
 	else {
-- 
cgit v1.2.3


From da8fe83f7ac6305d6cc884823a561828b13e7931 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 12:16:40 -0700
Subject: Tidy up ice40_dsp some more

---
 passes/pmgen/ice40_dsp.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 7858b8972..68fc29f31 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -219,10 +219,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
 	if (st.ffO) {
-		if (st.ffO_hilo)
-			cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
-		else
+		if (st.ffO_lo)
 			cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
+		else
+			cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
 
 		st.ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 		cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));
-- 
cgit v1.2.3


From c8310a6e768991f7499f250542eeda3503d3977c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 12:00:48 -0700
Subject: Refactor ice40_dsp.pmg

---
 passes/pmgen/ice40_dsp.cc | 51 +++++++++++++++++++++++------------------------
 1 file changed, 25 insertions(+), 26 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 68fc29f31..4132857d6 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -31,12 +31,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 #if 1
 	log("\n");
-	log("ffA:    %s\n", log_id(st.ffA, "--"));
-	log("ffB:    %s\n", log_id(st.ffB, "--"));
+	log("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
+	log("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
 	log("mul:    %s\n", log_id(st.mul, "--"));
-	log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
-	log("addAB:  %s\n", log_id(st.addAB, "--"));
-	log("muxAB:  %s\n", log_id(st.muxAB, "--"));
+	log("ffFJKG: %s n/a %s\n", log_id(st.ffFJKG, "--"), log_id(st.ffFJKGrstmux, "--"));
+	log("add:    %s\n", log_id(st.add, "--"));
+	log("mux:    %s\n", log_id(st.mux, "--"));
 	log("ffO:    %s\n", log_id(st.ffO, "--"));
 #endif
 
@@ -146,10 +146,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	SigSpec O = st.sigO;
 	int O_width = GetSize(O);
 	if (O_width == 33) {
-		log_assert(st.addAB);
+		log_assert(st.add);
 		// If we have a signed multiply-add, then perform sign extension
 		// TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
-		if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool())
+		if (st.add->getParam("\\A_SIGNED").as_bool() && st.add->getParam("\\B_SIGNED").as_bool())
 			pm.module->connect(O[32], O[31]);
 		else
 			cell->setPort("\\CO", O[32]);
@@ -164,18 +164,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setPort("\\O", O);
 
 	bool accum = false;
-	if (st.addAB) {
-		if (st.addA)
-			accum = (st.ffO && st.addAB->getPort("\\B") == st.sigO);
-		else if (st.addB)
-			accum = (st.ffO && st.addAB->getPort("\\A") == st.sigO);
-		else log_abort();
+	if (st.add) {
+		accum = (st.ffO && st.add->getPort(st.addAB == "\\A" ? "\\B" : "\\A") == st.sigO);
 		if (accum)
-			log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+			log("  accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
 		else
-			log("  adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
-		cell->setPort("\\ADDSUBTOP", st.addAB->type == "$add" ? State::S0 : State::S1);
-		cell->setPort("\\ADDSUBBOT", st.addAB->type == "$add" ? State::S0 : State::S1);
+			log("  adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
+		cell->setPort("\\ADDSUBTOP", st.add->type == "$add" ? State::S0 : State::S1);
+		cell->setPort("\\ADDSUBBOT", st.add->type == "$add" ? State::S0 : State::S1);
 	} else {
 		cell->setPort("\\ADDSUBTOP", State::S0);
 		cell->setPort("\\ADDSUBBOT", State::S0);
@@ -188,10 +184,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setPort("\\OHOLDBOT", State::S0);
 
 	SigSpec acc_reset = State::S0;
-	if (st.muxA)
-		acc_reset = st.muxA->getPort("\\S");
-	if (st.muxB)
-		acc_reset = pm.module->Not(NEW_ID, st.muxB->getPort("\\S"));
+	if (st.mux) {
+		if (st.muxAB == "\\A")
+			acc_reset = st.mux->getPort("\\S");
+		else
+			acc_reset = pm.module->Not(NEW_ID, st.mux->getPort("\\S"));
+	}
 
 	cell->setPort("\\OLOADTOP", acc_reset);
 	cell->setPort("\\OLOADBOT", acc_reset);
@@ -219,8 +217,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
 	if (st.ffO) {
-		if (st.ffO_lo)
-			cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
+		if (st.o_lo)
+			cell->setParam("\\TOPOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
 		else
 			cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
 
@@ -228,8 +226,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));
 	}
 	else {
-		cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
-		cell->setParam("\\BOTOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
+		cell->setParam("\\TOPOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
+		cell->setParam("\\BOTOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
 	}
 
 	if (cell != st.mul)
@@ -237,7 +235,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	else
 		pm.blacklist(st.mul);
 	pm.autoremove(st.ffFJKG);
-	pm.autoremove(st.addAB);
+	pm.autoremove(st.add);
 }
 
 struct Ice40DspPass : public Pass {
@@ -249,6 +247,7 @@ struct Ice40DspPass : public Pass {
 		log("    ice40_dsp [options] [selection]\n");
 		log("\n");
 		log("Map multipliers and multiply-accumulate blocks to iCE40 DSP resources.\n");
+		log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-- 
cgit v1.2.3


From 2766465a2bf73fcd490a160a124b6167851f2d10 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 12:14:33 -0700
Subject: Add support for SB_MAC16 CD and H registers

---
 passes/pmgen/ice40_dsp.cc | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 4132857d6..7592593a6 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -33,8 +33,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	log("\n");
 	log("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
 	log("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
+	log("ffCD:   %s %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--"), log_id(st.ffCDrstmux, "--"));
 	log("mul:    %s\n", log_id(st.mul, "--"));
 	log("ffFJKG: %s n/a %s\n", log_id(st.ffFJKG, "--"), log_id(st.ffFJKGrstmux, "--"));
+	log("ffH:    %s n/a %s\n", log_id(st.ffH, "--"), log_id(st.ffHrstmux, "--"));
 	log("add:    %s\n", log_id(st.add, "--"));
 	log("mux:    %s\n", log_id(st.mux, "--"));
 	log("ffO:    %s\n", log_id(st.ffO, "--"));
@@ -93,6 +95,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	cell->setParam("\\A_REG", st.ffA ? State::S1 : State::S0);
 	cell->setParam("\\B_REG", st.ffB ? State::S1 : State::S0);
+	cell->setParam("\\C_REG", st.ffCD ? State::S1 : State::S0);
+	cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0);
 
 	cell->setPort("\\AHOLD", State::S0);
 	cell->setPort("\\BHOLD", State::S0);
@@ -116,9 +120,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		if (st.ffB)
 			log(" ffB:%s", log_id(st.ffB));
 
+		if (st.ffCD)
+			log(" ffCD:%s", log_id(st.ffCD));
+
 		if (st.ffFJKG)
 			log(" ffFJKG:%s", log_id(st.ffFJKG));
 
+		if (st.ffH)
+			log(" ffH:%s", log_id(st.ffH));
+
 		if (st.ffO)
 			log(" ffO:%s", log_id(st.ffO));
 
@@ -196,13 +206,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	// SB_MAC16 Remaining Parameters
 
-	cell->setParam("\\C_REG", State::S0);
-	cell->setParam("\\D_REG", State::S0);
-
 	cell->setParam("\\TOP_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
 	cell->setParam("\\BOT_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
 	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffFJKG ? State::S1 : State::S0);
-	cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
+	cell->setParam("\\PIPELINE_16x16_MULT_REG2", st.ffH ? State::S1 : State::S0);
 
 	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
 	cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
-- 
cgit v1.2.3


From 429c9852cee3bd7f133944044c74c26b8f6a4209 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 14:02:55 -0700
Subject: Add HOLD/RST support for SB_MAC16

---
 passes/pmgen/ice40_dsp.cc | 63 +++++++++++++++++++++++++++++++++++------------
 1 file changed, 47 insertions(+), 16 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 7592593a6..f3cc83699 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -33,13 +33,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	log("\n");
 	log("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
 	log("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
-	log("ffCD:   %s %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--"), log_id(st.ffCDrstmux, "--"));
+	log("ffCD:   %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--"));
 	log("mul:    %s\n", log_id(st.mul, "--"));
-	log("ffFJKG: %s n/a %s\n", log_id(st.ffFJKG, "--"), log_id(st.ffFJKGrstmux, "--"));
-	log("ffH:    %s n/a %s\n", log_id(st.ffH, "--"), log_id(st.ffHrstmux, "--"));
+	log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
+	log("ffH:    %s\n", log_id(st.ffH, "--"));
 	log("add:    %s\n", log_id(st.add, "--"));
 	log("mux:    %s\n", log_id(st.mux, "--"));
-	log("ffO:    %s\n", log_id(st.ffO, "--"));
+	log("ffO:    %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOcemux, "--"), log_id(st.ffOrstmux, "--"));
 #endif
 
 	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -98,13 +98,35 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\C_REG", st.ffCD ? State::S1 : State::S0);
 	cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0);
 
-	cell->setPort("\\AHOLD", State::S0);
-	cell->setPort("\\BHOLD", State::S0);
-	cell->setPort("\\CHOLD", State::S0);
-	cell->setPort("\\DHOLD", State::S0);
-
-	cell->setPort("\\IRSTTOP", State::S0);
-	cell->setPort("\\IRSTBOT", State::S0);
+	SigSpec AHOLD, BHOLD, CDHOLD;
+	if (st.ffAcemux)
+		AHOLD = st.ffAcepol ? pm.module->Not(NEW_ID, st.ffAcemux->getPort("\\S")) : st.ffAcemux->getPort("\\S");
+	else
+		AHOLD = State::S0;
+	if (st.ffBcemux)
+		BHOLD = st.ffBcepol ? pm.module->Not(NEW_ID, st.ffBcemux->getPort("\\S")) : st.ffBcemux->getPort("\\S");
+	else
+		BHOLD = State::S0;
+	if (st.ffCDcemux)
+		CDHOLD = st.ffCDcepol ? pm.module->Not(NEW_ID, st.ffCDcemux->getPort("\\S")) : st.ffCDcemux->getPort("\\S");
+	else
+		CDHOLD = State::S0;
+	cell->setPort("\\AHOLD", AHOLD);
+	cell->setPort("\\BHOLD", BHOLD);
+	cell->setPort("\\CHOLD", CDHOLD);
+	cell->setPort("\\DHOLD", CDHOLD);
+
+	SigSpec IRSTTOP, IRSTBOT;
+	if (st.ffArstmux)
+		IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffArstmux->getPort("\\S"));
+	else
+		IRSTTOP = State::S0;
+	if (st.ffBrstmux)
+		IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffBrstmux->getPort("\\S"));
+	else
+		IRSTBOT = State::S0;
+	cell->setPort("\\IRSTTOP", IRSTTOP);
+	cell->setPort("\\IRSTBOT", IRSTBOT);
 
 	if (st.clock != SigBit())
 	{
@@ -187,11 +209,21 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		cell->setPort("\\ADDSUBBOT", State::S0);
 	}
 
-	cell->setPort("\\ORSTTOP", State::S0);
-	cell->setPort("\\ORSTBOT", State::S0);
+	SigSpec OHOLD;
+	if (st.ffOcemux)
+		OHOLD = st.ffOcemux ? pm.module->Not(NEW_ID, st.ffOcemux->getPort("\\S")) : st.ffOcemux->getPort("\\S");
+	else
+		OHOLD = State::S0;
+	cell->setPort("\\OHOLDTOP", OHOLD);
+	cell->setPort("\\OHOLDBOT", OHOLD);
 
-	cell->setPort("\\OHOLDTOP", State::S0);
-	cell->setPort("\\OHOLDBOT", State::S0);
+	SigSpec ORST;
+	if (st.ffOrstmux)
+		ORST = st.ffOrstmux ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S"));
+	else
+		ORST = State::S0;
+	cell->setPort("\\ORSTTOP", ORST);
+	cell->setPort("\\ORSTBOT", ORST);
 
 	SigSpec acc_reset = State::S0;
 	if (st.mux) {
@@ -200,7 +232,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		else
 			acc_reset = pm.module->Not(NEW_ID, st.mux->getPort("\\S"));
 	}
-
 	cell->setPort("\\OLOADTOP", acc_reset);
 	cell->setPort("\\OLOADBOT", acc_reset);
 
-- 
cgit v1.2.3


From 1a0f7ed09c5c14242aa89d572f617ad96ed42fa1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 14:27:25 -0700
Subject: Refactor ce{mux,pol} -> hold{mux,pol}

---
 passes/pmgen/ice40_dsp.cc | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f3cc83699..b119b6b7c 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -31,15 +31,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 #if 1
 	log("\n");
-	log("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--"));
-	log("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--"));
-	log("ffCD:   %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--"));
+	log("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAholdmux, "--"), log_id(st.ffArstmux, "--"));
+	log("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBholdmux, "--"), log_id(st.ffBrstmux, "--"));
+	log("ffCD:   %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDholdmux, "--"));
 	log("mul:    %s\n", log_id(st.mul, "--"));
 	log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
 	log("ffH:    %s\n", log_id(st.ffH, "--"));
 	log("add:    %s\n", log_id(st.add, "--"));
 	log("mux:    %s\n", log_id(st.mux, "--"));
-	log("ffO:    %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOcemux, "--"), log_id(st.ffOrstmux, "--"));
+	log("ffO:    %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOholdmux, "--"), log_id(st.ffOrstmux, "--"));
 #endif
 
 	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -99,16 +99,16 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0);
 
 	SigSpec AHOLD, BHOLD, CDHOLD;
-	if (st.ffAcemux)
-		AHOLD = st.ffAcepol ? pm.module->Not(NEW_ID, st.ffAcemux->getPort("\\S")) : st.ffAcemux->getPort("\\S");
+	if (st.ffAholdmux)
+		AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffAholdmux->getPort("\\S"));
 	else
 		AHOLD = State::S0;
-	if (st.ffBcemux)
-		BHOLD = st.ffBcepol ? pm.module->Not(NEW_ID, st.ffBcemux->getPort("\\S")) : st.ffBcemux->getPort("\\S");
+	if (st.ffBholdmux)
+		BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffBholdmux->getPort("\\S"));
 	else
 		BHOLD = State::S0;
-	if (st.ffCDcemux)
-		CDHOLD = st.ffCDcepol ? pm.module->Not(NEW_ID, st.ffCDcemux->getPort("\\S")) : st.ffCDcemux->getPort("\\S");
+	if (st.ffCDholdmux)
+		CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort("\\S"));
 	else
 		CDHOLD = State::S0;
 	cell->setPort("\\AHOLD", AHOLD);
@@ -210,8 +210,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	}
 
 	SigSpec OHOLD;
-	if (st.ffOcemux)
-		OHOLD = st.ffOcemux ? pm.module->Not(NEW_ID, st.ffOcemux->getPort("\\S")) : st.ffOcemux->getPort("\\S");
+	if (st.ffOholdmux)
+		OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOholdmux->getPort("\\S"));
 	else
 		OHOLD = State::S0;
 	cell->setPort("\\OHOLDTOP", OHOLD);
@@ -219,7 +219,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	SigSpec ORST;
 	if (st.ffOrstmux)
-		ORST = st.ffOrstmux ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S"));
+		ORST = st.ffOrstpol ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S"));
 	else
 		ORST = State::S0;
 	cell->setPort("\\ORSTTOP", ORST);
-- 
cgit v1.2.3


From 517ca49963a8f186b9f7b54b63e576b4ffb5b847 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 14:49:47 -0700
Subject: Remove TODO as check should not be necessary

---
 passes/pmgen/ice40_dsp.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index b119b6b7c..01a0869cc 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -180,7 +180,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	if (O_width == 33) {
 		log_assert(st.add);
 		// If we have a signed multiply-add, then perform sign extension
-		// TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
 		if (st.add->getParam("\\A_SIGNED").as_bool() && st.add->getParam("\\B_SIGNED").as_bool())
 			pm.module->connect(O[32], O[31]);
 		else
-- 
cgit v1.2.3


From a8bc46080548550e020155d1436470e0d3651eca Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 16:13:22 -0700
Subject: Use ID() macro

---
 passes/pmgen/ice40_dsp.cc | 148 +++++++++++++++++++++++-----------------------
 1 file changed, 74 insertions(+), 74 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 01a0869cc..ed3577400 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -65,21 +65,21 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	}
 
 	Cell *cell = st.mul;
-	if (cell->type == "$mul") {
+	if (cell->type == ID($mul)) {
 		log("  replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
 
-		cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
+		cell = pm.module->addCell(NEW_ID, ID(SB_MAC16));
 		pm.module->swap_names(cell, st.mul);
 	}
-	else log_assert(cell->type == "\\SB_MAC16");
+	else log_assert(cell->type == ID(SB_MAC16));
 
 	// SB_MAC16 Input Interface
 	SigSpec A = st.sigA;
-	A.extend_u0(16, st.mul->getParam("\\A_SIGNED").as_bool());
+	A.extend_u0(16, st.mul->getParam(ID(A_SIGNED)).as_bool());
 	log_assert(GetSize(A) == 16);
 
 	SigSpec B = st.sigB;
-	B.extend_u0(16, st.mul->getParam("\\B_SIGNED").as_bool());
+	B.extend_u0(16, st.mul->getParam(ID(B_SIGNED)).as_bool());
 	log_assert(GetSize(B) == 16);
 
 	SigSpec CD = st.sigCD;
@@ -88,51 +88,51 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	else
 		log_assert(GetSize(CD) == 32);
 
-	cell->setPort("\\A", A);
-	cell->setPort("\\B", B);
-	cell->setPort("\\C", CD.extract(16, 16));
-	cell->setPort("\\D", CD.extract(0, 16));
+	cell->setPort(ID::A, A);
+	cell->setPort(ID::B, B);
+	cell->setPort(ID(C), CD.extract(16, 16));
+	cell->setPort(ID(D), CD.extract(0, 16));
 
-	cell->setParam("\\A_REG", st.ffA ? State::S1 : State::S0);
-	cell->setParam("\\B_REG", st.ffB ? State::S1 : State::S0);
-	cell->setParam("\\C_REG", st.ffCD ? State::S1 : State::S0);
-	cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0);
+	cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0);
+	cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0);
+	cell->setParam(ID(C_REG), st.ffCD ? State::S1 : State::S0);
+	cell->setParam(ID(D_REG), st.ffCD ? State::S1 : State::S0);
 
 	SigSpec AHOLD, BHOLD, CDHOLD;
 	if (st.ffAholdmux)
-		AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffAholdmux->getPort("\\S"));
+		AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID(S)));
 	else
 		AHOLD = State::S0;
 	if (st.ffBholdmux)
-		BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffBholdmux->getPort("\\S"));
+		BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID(S)));
 	else
 		BHOLD = State::S0;
 	if (st.ffCDholdmux)
-		CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort("\\S"));
+		CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID(S)));
 	else
 		CDHOLD = State::S0;
-	cell->setPort("\\AHOLD", AHOLD);
-	cell->setPort("\\BHOLD", BHOLD);
-	cell->setPort("\\CHOLD", CDHOLD);
-	cell->setPort("\\DHOLD", CDHOLD);
+	cell->setPort(ID(AHOLD), AHOLD);
+	cell->setPort(ID(BHOLD), BHOLD);
+	cell->setPort(ID(CHOLD), CDHOLD);
+	cell->setPort(ID(DHOLD), CDHOLD);
 
 	SigSpec IRSTTOP, IRSTBOT;
 	if (st.ffArstmux)
-		IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffArstmux->getPort("\\S"));
+		IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID(S)));
 	else
 		IRSTTOP = State::S0;
 	if (st.ffBrstmux)
-		IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffBrstmux->getPort("\\S"));
+		IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID(S)));
 	else
 		IRSTBOT = State::S0;
-	cell->setPort("\\IRSTTOP", IRSTTOP);
-	cell->setPort("\\IRSTBOT", IRSTBOT);
+	cell->setPort(ID(IRSTTOP), IRSTTOP);
+	cell->setPort(ID(IRSTBOT), IRSTBOT);
 
 	if (st.clock != SigBit())
 	{
-		cell->setPort("\\CLK", st.clock);
-		cell->setPort("\\CE", State::S1);
-		cell->setParam("\\NEG_TRIGGER", st.clock_pol ? State::S0 : State::S1);
+		cell->setPort(ID(CLK), st.clock);
+		cell->setPort(ID(CE), State::S1);
+		cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1);
 
 		log("  clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
 
@@ -158,20 +158,20 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	}
 	else
 	{
-		cell->setPort("\\CLK", State::S0);
-		cell->setPort("\\CE", State::S0);
-		cell->setParam("\\NEG_TRIGGER", State::S0);
+		cell->setPort(ID(CLK), State::S0);
+		cell->setPort(ID(CE), State::S0);
+		cell->setParam(ID(NEG_TRIGGER), State::S0);
 	}
 
 	// SB_MAC16 Cascade Interface
 
-	cell->setPort("\\SIGNEXTIN", State::Sx);
-	cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID));
+	cell->setPort(ID(SIGNEXTIN), State::Sx);
+	cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID));
 
-	cell->setPort("\\CI", State::Sx);
+	cell->setPort(ID(CI), State::Sx);
 
-	cell->setPort("\\ACCUMCI", State::Sx);
-	cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID));
+	cell->setPort(ID(ACCUMCI), State::Sx);
+	cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID));
 
 	// SB_MAC16 Output Interface
 
@@ -180,91 +180,91 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	if (O_width == 33) {
 		log_assert(st.add);
 		// If we have a signed multiply-add, then perform sign extension
-		if (st.add->getParam("\\A_SIGNED").as_bool() && st.add->getParam("\\B_SIGNED").as_bool())
+		if (st.add->getParam(ID(A_SIGNED)).as_bool() && st.add->getParam(ID(B_SIGNED)).as_bool())
 			pm.module->connect(O[32], O[31]);
 		else
-			cell->setPort("\\CO", O[32]);
+			cell->setPort(ID(CO), O[32]);
 		O.remove(O_width-1);
 	}
 	else
-		cell->setPort("\\CO", pm.module->addWire(NEW_ID));
+		cell->setPort(ID(CO), pm.module->addWire(NEW_ID));
 	log_assert(GetSize(O) <= 32);
 	if (GetSize(O) < 32)
 		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 
-	cell->setPort("\\O", O);
+	cell->setPort(ID(O), O);
 
 	bool accum = false;
 	if (st.add) {
-		accum = (st.ffO && st.add->getPort(st.addAB == "\\A" ? "\\B" : "\\A") == st.sigO);
+		accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
 		if (accum)
 			log("  accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
 		else
 			log("  adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
-		cell->setPort("\\ADDSUBTOP", st.add->type == "$add" ? State::S0 : State::S1);
-		cell->setPort("\\ADDSUBBOT", st.add->type == "$add" ? State::S0 : State::S1);
+		cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1);
+		cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1);
 	} else {
-		cell->setPort("\\ADDSUBTOP", State::S0);
-		cell->setPort("\\ADDSUBBOT", State::S0);
+		cell->setPort(ID(ADDSUBTOP), State::S0);
+		cell->setPort(ID(ADDSUBBOT), State::S0);
 	}
 
 	SigSpec OHOLD;
 	if (st.ffOholdmux)
-		OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOholdmux->getPort("\\S"));
+		OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID(S)));
 	else
 		OHOLD = State::S0;
-	cell->setPort("\\OHOLDTOP", OHOLD);
-	cell->setPort("\\OHOLDBOT", OHOLD);
+	cell->setPort(ID(OHOLDTOP), OHOLD);
+	cell->setPort(ID(OHOLDBOT), OHOLD);
 
 	SigSpec ORST;
 	if (st.ffOrstmux)
-		ORST = st.ffOrstpol ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S"));
+		ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID(S)));
 	else
 		ORST = State::S0;
-	cell->setPort("\\ORSTTOP", ORST);
-	cell->setPort("\\ORSTBOT", ORST);
+	cell->setPort(ID(ORSTTOP), ORST);
+	cell->setPort(ID(ORSTBOT), ORST);
 
 	SigSpec acc_reset = State::S0;
 	if (st.mux) {
-		if (st.muxAB == "\\A")
-			acc_reset = st.mux->getPort("\\S");
+		if (st.muxAB == ID::A)
+			acc_reset = st.mux->getPort(ID(S));
 		else
-			acc_reset = pm.module->Not(NEW_ID, st.mux->getPort("\\S"));
+			acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID(S)));
 	}
-	cell->setPort("\\OLOADTOP", acc_reset);
-	cell->setPort("\\OLOADBOT", acc_reset);
+	cell->setPort(ID(OLOADTOP), acc_reset);
+	cell->setPort(ID(OLOADBOT), acc_reset);
 
 	// SB_MAC16 Remaining Parameters
 
-	cell->setParam("\\TOP_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
-	cell->setParam("\\BOT_8x8_MULT_REG", st.ffFJKG ? State::S1 : State::S0);
-	cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffFJKG ? State::S1 : State::S0);
-	cell->setParam("\\PIPELINE_16x16_MULT_REG2", st.ffH ? State::S1 : State::S0);
+	cell->setParam(ID(TOP_8x8_MULT_REG), st.ffFJKG ? State::S1 : State::S0);
+	cell->setParam(ID(BOT_8x8_MULT_REG), st.ffFJKG ? State::S1 : State::S0);
+	cell->setParam(ID(PIPELINE_16x16_MULT_REG1), st.ffFJKG ? State::S1 : State::S0);
+	cell->setParam(ID(PIPELINE_16x16_MULT_REG2), st.ffH ? State::S1 : State::S0);
 
-	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
-	cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
-	cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
+	cell->setParam(ID(TOPADDSUB_LOWERINPUT), Const(2, 2));
+	cell->setParam(ID(TOPADDSUB_UPPERINPUT), accum ? State::S0 : State::S1);
+	cell->setParam(ID(TOPADDSUB_CARRYSELECT), Const(3, 2));
 
-	cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
-	cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
-	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
+	cell->setParam(ID(BOTADDSUB_LOWERINPUT), Const(2, 2));
+	cell->setParam(ID(BOTADDSUB_UPPERINPUT), accum ? State::S0 : State::S1);
+	cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2));
 
-	cell->setParam("\\MODE_8x8", State::S0);
-	cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
-	cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
+	cell->setParam(ID(MODE_8x8), State::S0);
+	cell->setParam(ID(A_SIGNED), st.mul->getParam(ID(A_SIGNED)).as_bool());
+	cell->setParam(ID(B_SIGNED), st.mul->getParam(ID(B_SIGNED)).as_bool());
 
 	if (st.ffO) {
 		if (st.o_lo)
-			cell->setParam("\\TOPOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
+			cell->setParam(ID(TOPOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
 		else
-			cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
+			cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2));
 
-		st.ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
-		cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));
+		st.ffO->connections_.at(ID(Q)).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+		cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2));
 	}
 	else {
-		cell->setParam("\\TOPOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
-		cell->setParam("\\BOTOUTPUT_SELECT", Const(st.add ? 0 : 3, 2));
+		cell->setParam(ID(TOPOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
+		cell->setParam(ID(BOTOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
 	}
 
 	if (cell != st.mul)
-- 
cgit v1.2.3


From 34f9a8ceb285b6b59f24f994d3a877d5f4f09572 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 21:57:11 -0700
Subject: Update doc for ice40_dsp

---
 passes/pmgen/ice40_dsp.cc | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index ed3577400..2d264a6d1 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -283,9 +283,18 @@ struct Ice40DspPass : public Pass {
 		log("\n");
 		log("    ice40_dsp [options] [selection]\n");
 		log("\n");
-		log("Map multipliers and multiply-accumulate blocks to iCE40 DSP resources.\n");
+		log("Map multipliers ($mul/SB_MAC16) and multiply-accumulate ($mul/SB_MAC16 + $add)\n");
+		log("cells into iCE40 DSP resources.\n");
 		log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
 		log("\n");
+		log("Pack input registers (A, B, {C,D}; with optional hold/reset), pipeline registers\n");
+		log("({F,J,K,G}, H; with shared reset), output registers (O; with optional hold/reset),\n");
+		log("and post-adder into the SB_MAC16 resource.\n");
+		log("\n");
+		log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
+		log("input will be folded into the DSP. In this scenario only, resetting the\n");
+		log("the accumulator to an arbitrary value can be inferred to use the {C,D} input.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-- 
cgit v1.2.3


From 8cfcaf108e7fd7f538ab2939032f061dc134489b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 22:48:57 -0700
Subject: Disable support for SB_MAC16 reset since it is async

---
 passes/pmgen/ice40_dsp.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 2d264a6d1..cff4c5ddb 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -287,9 +287,9 @@ struct Ice40DspPass : public Pass {
 		log("cells into iCE40 DSP resources.\n");
 		log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
 		log("\n");
-		log("Pack input registers (A, B, {C,D}; with optional hold/reset), pipeline registers\n");
-		log("({F,J,K,G}, H; with shared reset), output registers (O; with optional hold/reset),\n");
-		log("and post-adder into the SB_MAC16 resource.\n");
+		log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
+		log("({F,J,K,G}, H), output registers (O; with optional hold), and post-adder into\n");
+		log("into the SB_MAC16 resource.\n");
 		log("\n");
 		log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
 		log("input will be folded into the DSP. In this scenario only, resetting the\n");
-- 
cgit v1.2.3


From 70c5444b25f18760781509104f4393b3d0a05fc0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 10:07:54 -0700
Subject: Update doc

---
 passes/pmgen/ice40_dsp.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index cff4c5ddb..0b7ffe64b 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -288,8 +288,8 @@ struct Ice40DspPass : public Pass {
 		log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
 		log("\n");
 		log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
-		log("({F,J,K,G}, H), output registers (O; with optional hold), and post-adder into\n");
-		log("into the SB_MAC16 resource.\n");
+		log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n");
+		log("optional hold), and post-adder into into the SB_MAC16 resource.\n");
 		log("\n");
 		log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
 		log("input will be folded into the DSP. In this scenario only, resetting the\n");
-- 
cgit v1.2.3


From d122083a112d51ba0d91e44c37b1d4d9d11080aa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 12:42:28 -0700
Subject: Output pattern matcher items as log_debug()

---
 passes/pmgen/ice40_dsp.cc | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 0b7ffe64b..641efe076 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -29,21 +29,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 {
 	auto &st = pm.st_ice40_dsp;
 
-#if 1
-	log("\n");
-	log("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAholdmux, "--"), log_id(st.ffArstmux, "--"));
-	log("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBholdmux, "--"), log_id(st.ffBrstmux, "--"));
-	log("ffCD:   %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDholdmux, "--"));
-	log("mul:    %s\n", log_id(st.mul, "--"));
-	log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
-	log("ffH:    %s\n", log_id(st.ffH, "--"));
-	log("add:    %s\n", log_id(st.add, "--"));
-	log("mux:    %s\n", log_id(st.mux, "--"));
-	log("ffO:    %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOholdmux, "--"), log_id(st.ffOrstmux, "--"));
-#endif
-
 	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
 
+	log_debug("\n");
+	log_debug("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAholdmux, "--"), log_id(st.ffArstmux, "--"));
+	log_debug("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBholdmux, "--"), log_id(st.ffBrstmux, "--"));
+	log_debug("ffCD:   %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDholdmux, "--"));
+	log_debug("mul:    %s\n", log_id(st.mul, "--"));
+	log_debug("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
+	log_debug("ffH:    %s\n", log_id(st.ffH, "--"));
+	log_debug("add:    %s\n", log_id(st.add, "--"));
+	log_debug("mux:    %s\n", log_id(st.mux, "--"));
+	log_debug("ffO:    %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOholdmux, "--"), log_id(st.ffOrstmux, "--"));
+
 	if (GetSize(st.sigA) > 16) {
 		log("  input A (%s) is too large (%d > 16).\n", log_signal(st.sigA), GetSize(st.sigA));
 		return;
-- 
cgit v1.2.3


From 26a6c55665e3d7826779d27f32031e58296ed68d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Sep 2019 13:27:00 -0700
Subject: Move log_debug("\n") later

---
 passes/pmgen/ice40_dsp.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/pmgen/ice40_dsp.cc')

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 641efe076..f60e67158 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -31,7 +31,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
 
-	log_debug("\n");
 	log_debug("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAholdmux, "--"), log_id(st.ffArstmux, "--"));
 	log_debug("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBholdmux, "--"), log_id(st.ffBrstmux, "--"));
 	log_debug("ffCD:   %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDholdmux, "--"));
@@ -41,6 +40,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	log_debug("add:    %s\n", log_id(st.add, "--"));
 	log_debug("mux:    %s\n", log_id(st.mux, "--"));
 	log_debug("ffO:    %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOholdmux, "--"), log_id(st.ffOrstmux, "--"));
+	log_debug("\n");
 
 	if (GetSize(st.sigA) > 16) {
 		log("  input A (%s) is too large (%d > 16).\n", log_signal(st.sigA), GetSize(st.sigA));
-- 
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