From e7058593f41ace45cb19aba24935a39de70733ca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 Apr 2020 15:57:48 -0700 Subject: opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too --- passes/opt/opt_expr.cc | 39 +++++++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 10 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 2b35ace5e..b213d2280 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -148,7 +148,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ std::vector bits_a = sig_a, bits_b = sig_b, bits_y = sig_y; - enum { GRP_DYN, GRP_CONST_A, GRP_CONST_B, GRP_CONST_AB, GRP_N }; + enum { GRP_DYN, GRP_CONST_A, GRP_CONST_B, GRP_CONST_AB, GRP_CONST_X, GRP_N }; std::map, std::set> grouped_bits[GRP_N]; for (int i = 0; i < GetSize(bits_y); i++) @@ -165,9 +165,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ if (bit_a.wire == NULL && bit_b.wire == NULL) group_idx = GRP_CONST_AB; else if (bit_a.wire == NULL) - group_idx = GRP_CONST_A; + group_idx = (bit_a == State::S0 || bit_a == State::S1 ? GRP_CONST_A : GRP_CONST_X); else if (bit_b.wire == NULL && commutative) - group_idx = GRP_CONST_A, std::swap(bit_a, bit_b); + group_idx = (bit_b == State::S0 || bit_b == State::S1 ? GRP_CONST_A : GRP_CONST_X), std::swap(bit_a, bit_b); else if (bit_b.wire == NULL) group_idx = GRP_CONST_B; @@ -476,13 +476,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (detect_const_and && (found_zero || found_inv)) { + if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef))) { cover("opt.opt_expr.const_and"); replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0); goto next_cell; } - if (detect_const_or && (found_one || found_inv)) { + if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef))) { cover("opt.opt_expr.const_or"); replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1); goto next_cell; @@ -499,9 +499,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { SigBit sig_a = assign_map(cell->getPort(ID::A)); SigBit sig_b = assign_map(cell->getPort(ID::B)); + if (sig_a == sig_b) { + if (cell->type.in(ID($xor), ID($_XOR_))) { + cover("opt.opt_expr.const_xor"); + replace_cell(assign_map, module, cell, "const_xor", ID::Y, RTLIL::State::S0); + goto next_cell; + } + if (cell->type.in(ID($xnor), ID($_XNOR_))) { + cover("opt.opt_expr.const_xnor"); + replace_cell(assign_map, module, cell, "const_xnor", ID::Y, RTLIL::State::S1); + goto next_cell; + } + log_abort(); + } + if (!sig_a.wire) std::swap(sig_a, sig_b); - if (sig_b == State::S0 || sig_b == State::S1) { + if (!sig_b.wire && (sig_b == State::S0 || sig_b == State::S1 || !keepdc)) { if (cell->type.in(ID($xor), ID($_XOR_))) { cover("opt.opt_expr.xor_buffer"); SigSpec sig_y; @@ -844,7 +858,7 @@ skip_fine_alu: if (input.match("**")) ACTION_DO_Y(x); if (input.match("1*")) ACTION_DO_Y(x); if (input.match("*1")) ACTION_DO_Y(x); - if (consume_x) { + if (!keepdc) { if (input.match(" *")) ACTION_DO_Y(0); if (input.match("* ")) ACTION_DO_Y(0); } @@ -863,7 +877,7 @@ skip_fine_alu: if (input.match("**")) ACTION_DO_Y(x); if (input.match("0*")) ACTION_DO_Y(x); if (input.match("*0")) ACTION_DO_Y(x); - if (consume_x) { + if (!keepdc) { if (input.match(" *")) ACTION_DO_Y(1); if (input.match("* ")) ACTION_DO_Y(1); } @@ -880,8 +894,10 @@ skip_fine_alu: if (input.match("01")) ACTION_DO_Y(1); if (input.match("10")) ACTION_DO_Y(1); if (input.match("11")) ACTION_DO_Y(0); - if (input.match(" *")) ACTION_DO_Y(x); - if (input.match("* ")) ACTION_DO_Y(x); + if (!keepdc) { + if (input.match(" *")) ACTION_DO(ID::Y, input.extract(0, 1)); + if (input.match("* ")) ACTION_DO(ID::Y, input.extract(1, 1)); + } } if (cell->type == ID($_MUX_)) { @@ -1094,6 +1110,9 @@ skip_fine_alu: if (b.is_fully_const() && b.as_bool() == false) identity_wrt_a = true; + + if (cell->type == ID($xor) && a == b) + identity_wrt_a = true; } if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) -- cgit v1.2.3 From 90b71eb84bbf172cf0c66db7dd8c86178bf93f94 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 Apr 2020 18:15:07 -0700 Subject: opt_expr: do not group by X, more fixes --- passes/opt/opt_expr.cc | 77 ++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 59 insertions(+), 18 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index b213d2280..5ada11336 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -132,7 +132,7 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, did_something = true; } -bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap) +bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap, bool keepdc) { IdString b_name = cell->hasPort(ID::B) ? ID::B : ID::A; @@ -148,7 +148,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ std::vector bits_a = sig_a, bits_b = sig_b, bits_y = sig_y; - enum { GRP_DYN, GRP_CONST_A, GRP_CONST_B, GRP_CONST_AB, GRP_CONST_X, GRP_N }; + enum { GRP_DYN, GRP_CONST_A, GRP_CONST_B, GRP_CONST_AB, GRP_N }; std::map, std::set> grouped_bits[GRP_N]; for (int i = 0; i < GetSize(bits_y); i++) @@ -162,14 +162,16 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ if (cell->type == ID($and) && (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0)) bit_a = bit_b = RTLIL::State::S0; - if (bit_a.wire == NULL && bit_b.wire == NULL) - group_idx = GRP_CONST_AB; - else if (bit_a.wire == NULL) - group_idx = (bit_a == State::S0 || bit_a == State::S1 ? GRP_CONST_A : GRP_CONST_X); - else if (bit_b.wire == NULL && commutative) - group_idx = (bit_b == State::S0 || bit_b == State::S1 ? GRP_CONST_A : GRP_CONST_X), std::swap(bit_a, bit_b); - else if (bit_b.wire == NULL) - group_idx = GRP_CONST_B; + if (!keepdc || (bit_a != State::Sx && bit_a != State::Sz && bit_a != State::Sx && bit_a != State::Sx)) { + if (bit_a.wire == NULL && bit_b.wire == NULL) + group_idx = GRP_CONST_AB; + else if (bit_a.wire == NULL) + group_idx = GRP_CONST_A; + else if (bit_b.wire == NULL && commutative) + group_idx = GRP_CONST_A, std::swap(bit_a, bit_b); + else if (bit_b.wire == NULL) + group_idx = GRP_CONST_B; + } grouped_bits[group_idx][std::pair(bit_a, bit_b)].insert(bits_y[i]); } @@ -186,26 +188,64 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ if (grouped_bits[i].empty()) continue; - RTLIL::Wire *new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i])); + RTLIL::SigSpec new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i])); RTLIL::SigSpec new_a, new_b; RTLIL::SigSig new_conn; for (auto &it : grouped_bits[i]) { for (auto &bit : it.second) { new_conn.first.append(bit); - new_conn.second.append(RTLIL::SigBit(new_y, new_a.size())); + new_conn.second.append(new_y[new_a.size()]); } new_a.append(it.first.first); new_b.append(it.first.second); } if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) { + if (cell->type == ID($and)) + new_a.replace(dict{{State::Sx, State::S0}, {State::Sz, State::S0}}, &new_b); + else if (cell->type == ID($or)) + new_a.replace(dict{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b); + else log_abort(); log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a)); module->connect(new_y, new_b); module->connect(new_conn); continue; } + if (!keepdc && cell->type.in(ID($xor), ID($xnor)) && i == GRP_CONST_A) { + SigSpec undef_a, undef_y, undef_b; + SigSpec def_y, def_a, def_b; + for (int i = 0; i < GetSize(new_y); i++) + if (new_a[i] == State::Sx || new_a[i] == State::Sz) { + undef_a.append(new_a[i]); + if (cell->type == ID($xor)) + undef_b.append(State::S0); + // For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_ + else if (cell->type == ID($xnor)) + undef_b.append(State::S1); + else log_abort(); + undef_y.append(new_y[i]); + } + else { + def_a.append(new_a[i]); + def_b.append(new_b[i]); + def_y.append(new_y[i]); + } + if (!undef_y.empty()) { + log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), log_id(cell->type), log_signal(undef_a)); + module->connect(undef_y, undef_b); + } + if (def_y.empty()) { + module->connect(new_conn); + continue; + } + new_a = std::move(def_a); + new_b = std::move(def_b); + new_y = std::move(def_y); + } + + RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); c->setPort(ID::A, new_a); @@ -219,7 +259,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ } c->setPort(ID::Y, new_y); - c->parameters[ID::Y_WIDTH] = new_y->width; + c->parameters[ID::Y_WIDTH] = GetSize(new_y); c->check(); module->connect(new_conn); @@ -499,7 +539,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { SigBit sig_a = assign_map(cell->getPort(ID::A)); SigBit sig_b = assign_map(cell->getPort(ID::B)); - if (sig_a == sig_b) { + if (!keepdc && (sig_a == sig_b || sig_a == State::Sx || sig_a == State::Sz || sig_b == State::Sx || sig_b == State::Sz)) { if (cell->type.in(ID($xor), ID($_XOR_))) { cover("opt.opt_expr.const_xor"); replace_cell(assign_map, module, cell, "const_xor", ID::Y, RTLIL::State::S0); @@ -507,6 +547,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (cell->type.in(ID($xnor), ID($_XNOR_))) { cover("opt.opt_expr.const_xnor"); + // For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_ replace_cell(assign_map, module, cell, "const_xnor", ID::Y, RTLIL::State::S1); goto next_cell; } @@ -515,7 +556,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!sig_a.wire) std::swap(sig_a, sig_b); - if (!sig_b.wire && (sig_b == State::S0 || sig_b == State::S1 || !keepdc)) { + if (sig_b == State::S0 || sig_b == State::S1) { if (cell->type.in(ID($xor), ID($_XOR_))) { cover("opt.opt_expr.xor_buffer"); SigSpec sig_y; @@ -564,7 +605,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (do_fine) { if (cell->type.in(ID($not), ID($pos), ID($and), ID($or), ID($xor), ID($xnor))) - if (group_cell_inputs(module, cell, true, assign_map)) + if (group_cell_inputs(module, cell, true, assign_map, keepdc)) goto next_cell; if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or), ID($reduce_or), ID($reduce_and), ID($reduce_bool))) @@ -895,8 +936,8 @@ skip_fine_alu: if (input.match("10")) ACTION_DO_Y(1); if (input.match("11")) ACTION_DO_Y(0); if (!keepdc) { - if (input.match(" *")) ACTION_DO(ID::Y, input.extract(0, 1)); - if (input.match("* ")) ACTION_DO(ID::Y, input.extract(1, 1)); + if (input.match(" *")) ACTION_DO_Y(0); + if (input.match("* ")) ACTION_DO_Y(0); } } -- cgit v1.2.3 From 83570bc0da7773b16eca7cebfd792ae799eb5c0f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 Apr 2020 11:15:29 -0700 Subject: opt_expr: more fixes for $xor/$xnor --- passes/opt/opt_expr.cc | 70 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 47 insertions(+), 23 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 5ada11336..38dc09af5 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -156,13 +156,27 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ int group_idx = GRP_DYN; RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i]; - if (cell->type == ID($or) && (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1)) - bit_a = bit_b = RTLIL::State::S1; - - if (cell->type == ID($and) && (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0)) - bit_a = bit_b = RTLIL::State::S0; + if (cell->type == ID($or)) { + if (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1) + bit_a = bit_b = RTLIL::State::S1; + } + else if (cell->type == ID($and)) { + if (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0) + bit_a = bit_b = RTLIL::State::S0; + } + else if (!keepdc) { + if (cell->type == ID($xor)) { + if (bit_a == bit_b) + bit_a = bit_b = RTLIL::State::S0; + } + else if (cell->type == ID($xnor)) { + if (bit_a == bit_b) + bit_a = bit_b = RTLIL::State::S1; // For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_ + } + } - if (!keepdc || (bit_a != State::Sx && bit_a != State::Sz && bit_a != State::Sx && bit_a != State::Sx)) { + bool def = (bit_a != State::Sx && bit_a != State::Sz && bit_b != State::Sx && bit_b != State::Sx); + if (def || !keepdc) { if (bit_a.wire == NULL && bit_b.wire == NULL) group_idx = GRP_CONST_AB; else if (bit_a.wire == NULL) @@ -202,43 +216,56 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ } if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) { - if (cell->type == ID($and)) - new_a.replace(dict{{State::Sx, State::S0}, {State::Sz, State::S0}}, &new_b); - else if (cell->type == ID($or)) - new_a.replace(dict{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b); - else log_abort(); + if (!keepdc) { + if (cell->type == ID($and)) + new_a.replace(dict{{State::Sx, State::S0}, {State::Sz, State::S0}}, &new_b); + else if (cell->type == ID($or)) + new_a.replace(dict{{State::Sx, State::S1}, {State::Sz, State::S1}}, &new_b); + else log_abort(); + } log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a)); module->connect(new_y, new_b); module->connect(new_conn); continue; } - if (!keepdc && cell->type.in(ID($xor), ID($xnor)) && i == GRP_CONST_A) { + if (cell->type.in(ID($xor), ID($xnor)) && i == GRP_CONST_A) { SigSpec undef_a, undef_y, undef_b; SigSpec def_y, def_a, def_b; - for (int i = 0; i < GetSize(new_y); i++) - if (new_a[i] == State::Sx || new_a[i] == State::Sz) { + for (int i = 0; i < GetSize(new_y); i++) { + bool undef = new_a[i] == State::Sx || new_a[i] == State::Sz; + if (!keepdc && (undef || new_a[i] == new_b[i])) { undef_a.append(new_a[i]); if (cell->type == ID($xor)) undef_b.append(State::S0); - // For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_ + // For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_ else if (cell->type == ID($xnor)) undef_b.append(State::S1); else log_abort(); undef_y.append(new_y[i]); } + else if (new_a[i] == State::S0 || new_a[i] == State::S1) { + undef_a.append(new_a[i]); + if (cell->type == ID($xor)) + undef_b.append(new_a[i] == State::S1 ? module->Not(NEW_ID, new_b[i]).as_bit() : new_b[i]); + else if (cell->type == ID($xnor)) + undef_b.append(new_a[i] == State::S1 ? new_b[i] : module->Not(NEW_ID, new_b[i]).as_bit()); + else log_abort(); + undef_y.append(new_y[i]); + } else { def_a.append(new_a[i]); def_b.append(new_b[i]); def_y.append(new_y[i]); } + } if (!undef_y.empty()) { log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(undef_b), log_id(cell->type), log_signal(undef_a)); module->connect(undef_y, undef_b); - } - if (def_y.empty()) { - module->connect(new_conn); - continue; + if (def_y.empty()) { + module->connect(new_conn); + continue; + } } new_a = std::move(def_a); new_b = std::move(def_b); @@ -547,7 +574,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (cell->type.in(ID($xnor), ID($_XNOR_))) { cover("opt.opt_expr.const_xnor"); - // For consistency with gate-level which does $xnor -> $_XOR_ + $_NOT_ + // For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_ replace_cell(assign_map, module, cell, "const_xnor", ID::Y, RTLIL::State::S1); goto next_cell; } @@ -1151,9 +1178,6 @@ skip_fine_alu: if (b.is_fully_const() && b.as_bool() == false) identity_wrt_a = true; - - if (cell->type == ID($xor) && a == b) - identity_wrt_a = true; } if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) -- cgit v1.2.3 From b5f38f834207fab3a563c55568c4543a3b5dcc1f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 Apr 2020 14:13:45 -0700 Subject: opt_expr: const_xnor replacement to pad Y with 1'b1 --- passes/opt/opt_expr.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 38dc09af5..d895fc691 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -575,7 +575,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in(ID($xnor), ID($_XNOR_))) { cover("opt.opt_expr.const_xnor"); // For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_ - replace_cell(assign_map, module, cell, "const_xnor", ID::Y, RTLIL::State::S1); + int width = cell->getParam(ID::Y_WIDTH).as_int(); + replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width)); goto next_cell; } log_abort(); -- cgit v1.2.3 From 17f4e06247b608034f730efe6391fd5fe250bd79 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 8 May 2020 11:07:44 -0700 Subject: opt_expr: restore consume_x; use for coarse grained too --- passes/opt/opt_expr.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index d895fc691..60221f32d 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -543,13 +543,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef))) { + if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef && consume_x))) { cover("opt.opt_expr.const_and"); replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0); goto next_cell; } - if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef))) { + if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef && consume_x))) { cover("opt.opt_expr.const_or"); replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1); goto next_cell; @@ -927,7 +927,7 @@ skip_fine_alu: if (input.match("**")) ACTION_DO_Y(x); if (input.match("1*")) ACTION_DO_Y(x); if (input.match("*1")) ACTION_DO_Y(x); - if (!keepdc) { + if (consume_x) { if (input.match(" *")) ACTION_DO_Y(0); if (input.match("* ")) ACTION_DO_Y(0); } @@ -946,7 +946,7 @@ skip_fine_alu: if (input.match("**")) ACTION_DO_Y(x); if (input.match("0*")) ACTION_DO_Y(x); if (input.match("*0")) ACTION_DO_Y(x); - if (!keepdc) { + if (consume_x) { if (input.match(" *")) ACTION_DO_Y(1); if (input.match("* ")) ACTION_DO_Y(1); } @@ -963,7 +963,7 @@ skip_fine_alu: if (input.match("01")) ACTION_DO_Y(1); if (input.match("10")) ACTION_DO_Y(1); if (input.match("11")) ACTION_DO_Y(0); - if (!keepdc) { + if (consume_x) { if (input.match(" *")) ACTION_DO_Y(0); if (input.match("* ")) ACTION_DO_Y(0); } @@ -1149,7 +1149,7 @@ skip_fine_alu: goto next_cell; } - if (!keepdc) + if (!keepdc && consume_x) { bool identity_wrt_a = false; bool identity_wrt_b = false; -- cgit v1.2.3 From 9694dc42dd8badde03a27072b294556cb77f5bb5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 8 May 2020 11:12:43 -0700 Subject: opt_expr: consume_x to require/imply !keepdc --- passes/opt/opt_expr.cc | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 60221f32d..9a8bc0869 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -543,13 +543,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef && consume_x))) { + if (detect_const_and && (found_zero || found_inv || (found_undef && consume_x))) { cover("opt.opt_expr.const_and"); replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0); goto next_cell; } - if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef && consume_x))) { + if (detect_const_or && (found_one || found_inv || (found_undef && consume_x))) { cover("opt.opt_expr.const_or"); replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1); goto next_cell; @@ -1149,7 +1149,7 @@ skip_fine_alu: goto next_cell; } - if (!keepdc && consume_x) + if (consume_x) { bool identity_wrt_a = false; bool identity_wrt_b = false; @@ -2041,11 +2041,12 @@ struct OptExprPass : public Pass { do { do { did_something = false; - replace_const_cells(design, module, false, mux_undef, mux_bool, do_fine, keepdc, clkinv); + replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv); if (did_something) design->scratchpad_set_bool("opt.did_something", true); } while (did_something); - replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc, clkinv); + if (!keepdc) + replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv); if (did_something) design->scratchpad_set_bool("opt.did_something", true); } while (did_something); -- cgit v1.2.3 From cd92a706aeef938625f6402d22825729e32649d8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 09:51:17 -0700 Subject: Fix whitespace --- passes/opt/opt_expr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 9a8bc0869..b484b9776 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -2046,7 +2046,7 @@ struct OptExprPass : public Pass { design->scratchpad_set_bool("opt.did_something", true); } while (did_something); if (!keepdc) - replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv); + replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv); if (did_something) design->scratchpad_set_bool("opt.did_something", true); } while (did_something); -- cgit v1.2.3