From 83d36394f86510abf944ada407d4a1f4d7eefcd0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 10:26:37 -0800 Subject: opt_merge to discard \init of '$' cells with 'Q' port when merging --- passes/opt/opt_merge.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'passes/opt') diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index aaea6159e..643cf0215 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -323,6 +323,17 @@ struct OptMergeWorker log_signal(it.second), log_signal(other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); + + if (cell->type.begins_with("$") && it.first == ID(Q)) { + for (auto c : it.second.chunks()) { + auto jt = c.wire->attributes.find(ID(init)); + if (jt == c.wire->attributes.end()) + continue; + for (int i = c.offset; i < c.offset + c.width; i++) + jt->second[i] = State::Sx; + } + dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second))); + } } } log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); -- cgit v1.2.3 From d038cea3c7c5dd9f147c4da0e44de0e664df089f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Dec 2019 12:32:00 -0800 Subject: More stringent check for flop cells --- passes/opt/opt_merge.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 643cf0215..8dd238bc7 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -222,7 +222,8 @@ struct OptMergeWorker return true; } - if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) { + if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || cell1->type.in("$adff", "$sr", "$ff") || + cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH"))) { std::vector q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector(); std::vector q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector(); for (size_t i = 0; i < q1.size(); i++) @@ -324,7 +325,8 @@ struct OptMergeWorker module->connect(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); - if (cell->type.begins_with("$") && it.first == ID(Q)) { + if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || cell->type.in("$adff", "$sr", "$ff") || + cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH"))) { for (auto c : it.second.chunks()) { auto jt = c.wire->attributes.find(ID(init)); if (jt == c.wire->attributes.end()) -- cgit v1.2.3 From f5e0a07ad679696b0d3077ef877941d4c1f864d7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Dec 2019 13:00:04 -0800 Subject: Add $_FF_ and $_SR* courtesy of @mwkmwkmwk --- passes/opt/opt_merge.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 8dd238bc7..8823a9061 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -222,8 +222,9 @@ struct OptMergeWorker return true; } - if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || cell1->type.in("$adff", "$sr", "$ff") || - cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH"))) { + if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || + cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") || + cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) { std::vector q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector(); std::vector q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector(); for (size_t i = 0; i < q1.size(); i++) @@ -325,8 +326,9 @@ struct OptMergeWorker module->connect(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); - if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || cell->type.in("$adff", "$sr", "$ff") || - cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH"))) { + if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || + cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") || + cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) { for (auto c : it.second.chunks()) { auto jt = c.wire->attributes.find(ID(init)); if (jt == c.wire->attributes.end()) -- cgit v1.2.3