From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- passes/memory/memory_collect.cc | 23 +++++++++++------------ passes/memory/memory_dff.cc | 1 - passes/memory/memory_map.cc | 1 - passes/memory/memory_unpack.cc | 1 - 4 files changed, 11 insertions(+), 15 deletions(-) (limited to 'passes/memory') diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index d2803ae78..40c68abc1 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -22,7 +22,6 @@ #include #include #include -#include static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) { @@ -136,12 +135,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\SIZE"] = RTLIL::Const(memory->size); mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits); - assert(sig_wr_clk.size() == wr_ports); - assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); - assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); - assert(sig_wr_addr.size() == wr_ports * addr_bits); - assert(sig_wr_data.size() == wr_ports * memory->width); - assert(sig_wr_en.size() == wr_ports * memory->width); + log_assert(sig_wr_clk.size() == wr_ports); + log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); + log_assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); + log_assert(sig_wr_addr.size() == wr_ports * addr_bits); + log_assert(sig_wr_data.size() == wr_ports * memory->width); + log_assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); @@ -152,11 +151,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->set("\\WR_DATA", sig_wr_data); mem->set("\\WR_EN", sig_wr_en); - assert(sig_rd_clk.size() == rd_ports); - assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); - assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); - assert(sig_rd_addr.size() == rd_ports * addr_bits); - assert(sig_rd_data.size() == rd_ports * memory->width); + log_assert(sig_rd_clk.size() == rd_ports); + log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); + log_assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); + log_assert(sig_rd_addr.size() == rd_ports * addr_bits); + log_assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 85249142e..325056170 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -20,7 +20,6 @@ #include "kernel/register.h" #include "kernel/log.h" #include -#include #include static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 53394b19a..49291656c 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -22,7 +22,6 @@ #include #include #include -#include static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") { diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index d2b9c0eeb..cdf7db04b 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -22,7 +22,6 @@ #include #include #include -#include static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) { -- cgit v1.2.3