From e2fc18f27b5e9f506724a486787c2106b9f7fb4f Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Tue, 26 Feb 2019 10:28:42 -0800 Subject: Reduce amount of trailing whitespace in code base --- misc/yosys.proto | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'misc') diff --git a/misc/yosys.proto b/misc/yosys.proto index 2870176cb..a583e6265 100644 --- a/misc/yosys.proto +++ b/misc/yosys.proto @@ -1,12 +1,12 @@ // // yosys -- Yosys Open SYnthesis Suite -// +// // Copyright (C) 2018 Serge Bazanski -// +// // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. -// +// // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -73,7 +73,7 @@ message Module { BitVector bits = 2; } map port = 2; - + // Named cells in this module. message Cell { // Set to true when the name of this cell is automatically created and @@ -129,7 +129,7 @@ message Model { TYPE_FALSE = 6; }; Type type = 1; - + message Port { // Name of port. string portname = 1; @@ -148,7 +148,7 @@ message Model { // Set for AND, NAND. Gate gate = 3; } - + // Set when the node drives given output port(s). message OutPort { // Name of port. -- cgit v1.2.3