From e0e6d130cd083a8285ea2991629e0049023da234 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 19 Feb 2015 13:36:54 +0100 Subject: YosysJS stuff --- misc/yosysjs/demo03.html | 103 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 misc/yosysjs/demo03.html (limited to 'misc/yosysjs/demo03.html') diff --git a/misc/yosysjs/demo03.html b/misc/yosysjs/demo03.html new file mode 100644 index 000000000..720b82e90 --- /dev/null +++ b/misc/yosysjs/demo03.html @@ -0,0 +1,103 @@ + +YosysJS Example Application #02 + + + + + + + +

YosysJS Example Application #03

+ Your mission: Create a behavioral Verilog model for the following circuit: +

+ +

module top(input clk, reset, input [7:0] A, output reg [7:0] Y);
+  always @(posedge clock) begin
+    Y <= A | {4{reset}};
+  end
+endmodule

+ +

+ + -- cgit v1.2.3