From 9c29969bbc1b19f251011feaa791d242ac8e5e81 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 13:45:47 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex               | 45 +++++++++++++++++++++++++++
 manual/PRESENTATION_ExAdv/Makefile          |  5 ++-
 manual/PRESENTATION_ExAdv/red_or3x1_cells.v |  5 +++
 manual/PRESENTATION_ExAdv/red_or3x1_map.v   | 48 +++++++++++++++++++++++++++++
 manual/PRESENTATION_ExAdv/red_or3x1_test.v  |  5 +++
 manual/PRESENTATION_ExAdv/red_or3x1_test.ys |  7 +++++
 6 files changed, 114 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/red_or3x1_cells.v
 create mode 100644 manual/PRESENTATION_ExAdv/red_or3x1_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/red_or3x1_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/red_or3x1_test.ys

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 21c5cdecc..3f5743da7 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -239,6 +239,51 @@ show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
 \subsectionpagesuffix
 \end{frame}
 
+\subsubsection{Introduction to techmap}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item
+The {\tt techmap} command replaces cells in the design with implementations given
+as verilog code (called ``map files''). It can replace Yosys' internal cell
+types (such as {\tt \$or}) as well as user-defined cell types.
+\medskip\item
+Verilog parameters are used extensively to customize the internal cell types.
+\medskip\item
+Additional special parameters are used by techmap to communicate meta-data to the
+map files.
+\medskip\item
+Special wires are used to instruct techmap how to handle a module in the map file.
+\medskip\item
+Generate blocks and recursion are powerful tools for writing map files.
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t]{\subsubsecname -- Example 1/2}
+\vskip-0.2cm
+To map the Verilog OR-reduction operator to 3-input OR gates:
+\vskip-0.2cm
+\begin{columns}
+\column[t]{0.35\linewidth}
+\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=24]{PRESENTATION_ExAdv/red_or3x1_map.v}
+\column[t]{0.65\linewidth}
+\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=25]{PRESENTATION_ExAdv/red_or3x1_map.v}
+\end{columns}
+\end{frame}
+
+\begin{frame}[t]{\subsubsecname -- Example 2/2}
+\vbox to 0cm{
+\hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf}
+\vss
+}
+\begin{columns}
+\column[t]{6cm}
+\column[t]{4cm}
+\vskip-0.6cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, firstline=4, lastline=4, frame=single]{PRESENTATION_ExAdv/red_or3x1_test.ys}
+\vskip-0.2cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/red_or3x1_test.v}
+\end{columns}
+\end{frame}
+
 \subsubsection{TBD}
 
 \begin{frame}{\subsubsecname}
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index f38bd6ceb..673b3a213 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,6 +1,9 @@
 
-all: select_01.pdf
+all: select_01.pdf red_or3x1.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
 
+red_or3x1.pdf: red_or3x1_*
+	../../yosys red_or3x1_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_cells.v b/manual/PRESENTATION_ExAdv/red_or3x1_cells.v
new file mode 100644
index 000000000..0750a1307
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_cells.v
@@ -0,0 +1,5 @@
+module OR3X1(A, B, C, Y);
+    input A, B, C;
+    output Y;
+    assign Y = A | B | C;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_map.v b/manual/PRESENTATION_ExAdv/red_or3x1_map.v
new file mode 100644
index 000000000..24ca9dab4
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_map.v
@@ -0,0 +1,48 @@
+module \$reduce_or (A, Y);
+
+    parameter A_SIGNED = 0;
+    parameter A_WIDTH = 0;
+    parameter Y_WIDTH = 0;
+    
+    input [A_WIDTH-1:0] A;
+    output [Y_WIDTH-1:0] Y;
+    
+    function integer min;
+        input integer a, b;
+        begin
+            if (a < b)
+                min = a;
+            else
+                min = b;
+        end
+    endfunction
+    
+    genvar i;
+    generate begin
+        if (A_WIDTH == 0) begin
+            assign Y = 0;
+        end
+        if (A_WIDTH == 1) begin
+            assign Y = A;
+        end
+        if (A_WIDTH == 2) begin
+            wire ybuf;
+            OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
+            assign Y = ybuf;
+        end
+        if (A_WIDTH == 3) begin
+            wire ybuf;
+            OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
+            assign Y = ybuf;
+        end
+        if (A_WIDTH > 3) begin
+            localparam next_stage_sz = (A_WIDTH+2) / 3;
+            wire [next_stage_sz-1:0] next_stage;
+            for (i = 0; i < next_stage_sz; i = i+1) begin
+                localparam bits = min(A_WIDTH - 3*i, 3);
+                assign next_stage[i] = |A[3*i +: bits];
+            end
+            assign Y = |next_stage;
+        end
+    end endgenerate
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_test.v b/manual/PRESENTATION_ExAdv/red_or3x1_test.v
new file mode 100644
index 000000000..bcdd32cbf
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_test.v
@@ -0,0 +1,5 @@
+module test (A, Y);
+    input [6:0] A;
+    output Y;
+    assign Y = |A;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_test.ys b/manual/PRESENTATION_ExAdv/red_or3x1_test.ys
new file mode 100644
index 000000000..b92346034
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_test.ys
@@ -0,0 +1,7 @@
+read_verilog red_or3x1_test.v
+hierarchy -check -top test
+
+techmap -map red_or3x1_map.v;;
+
+splitnets -ports
+show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v
-- 
cgit v1.2.3


From aeb36b0b8b499a5b758840998afe9f1b4d7fc166 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 14:32:56 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex             | 40 +++++++++++++++++++++++++++++--
 manual/PRESENTATION_ExAdv/Makefile        |  5 +++-
 manual/PRESENTATION_ExAdv/sym_mul_cells.v |  6 +++++
 manual/PRESENTATION_ExAdv/sym_mul_map.v   | 15 ++++++++++++
 manual/PRESENTATION_ExAdv/sym_mul_test.v  |  5 ++++
 manual/PRESENTATION_ExAdv/sym_mul_test.ys |  6 +++++
 6 files changed, 74 insertions(+), 3 deletions(-)
 create mode 100644 manual/PRESENTATION_ExAdv/sym_mul_cells.v
 create mode 100644 manual/PRESENTATION_ExAdv/sym_mul_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/sym_mul_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/sym_mul_test.ys

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 3f5743da7..4ef10d7ad 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -259,7 +259,7 @@ Generate blocks and recursion are powerful tools for writing map files.
 \end{itemize}
 \end{frame}
 
-\begin{frame}[t]{\subsubsecname -- Example 1/2}
+\begin{frame}[t]{\subsubsecname{} -- Example 1/2}
 \vskip-0.2cm
 To map the Verilog OR-reduction operator to 3-input OR gates:
 \vskip-0.2cm
@@ -271,7 +271,7 @@ To map the Verilog OR-reduction operator to 3-input OR gates:
 \end{columns}
 \end{frame}
 
-\begin{frame}[t]{\subsubsecname -- Example 2/2}
+\begin{frame}[t]{\subsubsecname{} -- Example 2/2}
 \vbox to 0cm{
 \hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf}
 \vss
@@ -284,6 +284,42 @@ To map the Verilog OR-reduction operator to 3-input OR gates:
 \end{columns}
 \end{frame}
 
+\subsubsection{Conditional techmap}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item In some cases only cells with certain properties should be substituted.
+\medskip
+\item The special wire {\tt \_TECHMAP\_FAIL\_} can be used to disable a module
+in the map file for a certain set of parameters.
+\medskip
+\item The wire {\tt \_TECHMAP\_FAIL\_} must be set to a constant value. If it
+is non-zero then the module is disabled for this set of parameters.
+\medskip
+\item Example use-cases:
+\begin{itemize}
+\item coarse-grain cell types that only operate on certain bit widths
+\item memory resources for different memory geometries (width, depth, ports, etc.)
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t]{\subsubsecname{} -- Example}
+\vbox to 0cm{
+\vskip-0.5cm
+\hfill\includegraphics[width=6cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/sym_mul.pdf}
+\vss
+}
+\vskip-0.5cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/sym_mul_map.v}
+\begin{columns}
+\column[t]{6cm}
+\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/sym_mul_test.v}
+\column[t]{4cm}
+\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=4]{PRESENTATION_ExAdv/sym_mul_test.ys}
+\end{columns}
+\end{frame}
+
 \subsubsection{TBD}
 
 \begin{frame}{\subsubsecname}
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 673b3a213..4ee5886d2 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -7,3 +7,6 @@ select_01.pdf: select_01.v select_01.ys
 red_or3x1.pdf: red_or3x1_*
 	../../yosys red_or3x1_test.ys
 
+sym_mul.pdf: sym_mul_*
+	../../yosys sym_mul_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_cells.v b/manual/PRESENTATION_ExAdv/sym_mul_cells.v
new file mode 100644
index 000000000..ce1771544
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/sym_mul_cells.v
@@ -0,0 +1,6 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output [WIDTH-1:0] Y;
+    assign Y = A * B;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_map.v b/manual/PRESENTATION_ExAdv/sym_mul_map.v
new file mode 100644
index 000000000..293c5b841
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/sym_mul_map.v
@@ -0,0 +1,15 @@
+module \$mul (A, B, Y);
+    parameter A_SIGNED = 0;
+    parameter B_SIGNED = 0;
+    parameter A_WIDTH = 1;
+    parameter B_WIDTH = 1;
+    parameter Y_WIDTH = 1;
+    
+    input [A_WIDTH-1:0] A;
+    input [B_WIDTH-1:0] B;
+    output [Y_WIDTH-1:0] Y;
+    
+    wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
+    
+    MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_test.v b/manual/PRESENTATION_ExAdv/sym_mul_test.v
new file mode 100644
index 000000000..eb715f83d
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/sym_mul_test.v
@@ -0,0 +1,5 @@
+module test(A, B, C, Y1, Y2);
+    input   [7:0] A, B, C;
+    output  [7:0] Y1 = A * B;
+    output [15:0] Y2 = A * C;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_test.ys b/manual/PRESENTATION_ExAdv/sym_mul_test.ys
new file mode 100644
index 000000000..0c07e7e87
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/sym_mul_test.ys
@@ -0,0 +1,6 @@
+read_verilog sym_mul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v;;
+
+show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v
-- 
cgit v1.2.3


From f08c71b96c325f2432abb4f95fd823ae243e003b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 17:56:19 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex           | 41 +++++++++++++++++++++++++++++++++
 manual/PRESENTATION_ExAdv/Makefile      |  5 +++-
 manual/PRESENTATION_ExAdv/mymul_map.v   | 15 ++++++++++++
 manual/PRESENTATION_ExAdv/mymul_test.v  |  4 ++++
 manual/PRESENTATION_ExAdv/mymul_test.ys | 15 ++++++++++++
 5 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_test.ys

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 4ef10d7ad..cf36d32cc 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -320,6 +320,47 @@ is non-zero then the module is disabled for this set of parameters.
 \end{columns}
 \end{frame}
 
+\subsubsection{Scripting in map modules}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts
+in the context of the replacement module.
+\medskip
+\item The wire that comes first in alphatecial oder is interprated as string (must
+be connected to constants) that is executed as script. Then the wire is removed. Repeat.
+\medskip
+\item You can even call techmap recursively!
+\medskip
+\item Example use-cases:
+\begin{itemize}
+\item Using always blocks in map module: call {\tt proc}
+\item Perform expensive optimizations (such as {\tt freduce}) on cells where
+this is known to work well.
+\item Interacting with custom commands.
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t]{\subsubsecname{} -- Example}
+\vbox to 0cm{
+\vskip4.2cm
+\hskip0.5cm\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mymul.pdf}
+\vss
+}
+\vskip-0.6cm
+\begin{columns}
+\column[t]{6cm}
+\vskip-0.6cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mymul_map.v}
+\column[t]{4.2cm}
+\vskip-0.6cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mymul_test.v}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mymul_test.ys}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, frame=single, language=ys, firstline=7, lastline=12]{PRESENTATION_ExAdv/mymul_test.ys}
+\end{columns}
+\end{frame}
+
 \subsubsection{TBD}
 
 \begin{frame}{\subsubsecname}
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 4ee5886d2..74f263270 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -10,3 +10,6 @@ red_or3x1.pdf: red_or3x1_*
 sym_mul.pdf: sym_mul_*
 	../../yosys sym_mul_test.ys
 
+mymul.pdf: mymul_*
+	../../yosys mymul_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/mymul_map.v b/manual/PRESENTATION_ExAdv/mymul_map.v
new file mode 100644
index 000000000..e888a7a7c
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_map.v
@@ -0,0 +1,15 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output reg [WIDTH-1:0] Y;
+
+    wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+    integer i;
+    always @* begin
+        Y = 0;
+        for (i = 0; i < WIDTH; i=i+1)
+            if (A[i])
+                Y = Y + (B << i);
+    end
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mymul_test.v b/manual/PRESENTATION_ExAdv/mymul_test.v
new file mode 100644
index 000000000..620a06d9e
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_test.v
@@ -0,0 +1,4 @@
+module test(A, B, Y);
+    input  [1:0] A, B;
+    output [1:0] Y = A * B;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mymul_test.ys b/manual/PRESENTATION_ExAdv/mymul_test.ys
new file mode 100644
index 000000000..48203e319
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_test.ys
@@ -0,0 +1,15 @@
+read_verilog mymul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+        -map mymul_map.v;;
+
+rename test test_mapped
+read_verilog mymul_test.v
+miter -equiv test test_mapped miter
+flatten miter
+
+sat -verify -prove trigger 0 miter
+
+splitnets -ports test_mapped/A
+show -prefix mymul -format pdf -notitle test_mapped
-- 
cgit v1.2.3


From 37cbb1ca60b03cbaaef5041db5f631b90a303f9a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 22:31:53 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex              | 38 ++++++++++++++++++++++++++++++
 manual/PRESENTATION_ExAdv/Makefile         |  5 +++-
 manual/PRESENTATION_ExAdv/mulshift_map.v   | 26 ++++++++++++++++++++
 manual/PRESENTATION_ExAdv/mulshift_test.v  |  5 ++++
 manual/PRESENTATION_ExAdv/mulshift_test.ys |  7 ++++++
 5 files changed, 80 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/mulshift_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/mulshift_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/mulshift_test.ys

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index cf36d32cc..483389d84 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -361,6 +361,44 @@ this is known to work well.
 \end{columns}
 \end{frame}
 
+\subsubsection{Handling constant inputs}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item The special parameters {\tt \_TECHMAP\_CONSTMSK\_\it <port-name>\tt \_} and
+{\tt \_TECHMAP\_CONSTVAL\_\it <port-name>\tt \_} can be used to handle constant
+input values to cells.
+\medskip
+\item The former contains 1-bits for all constant input bits on the port.
+\medskip
+\item The latter contains the constant bits or undef (x) for non-constant bits.
+\medskip
+\item Example use-cases:
+\begin{itemize}
+\item Converting arithmetic (for example multiply to shift)
+\item Identify constant addresses or enable bits in memory interfaces.
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t]{\subsubsecname{} -- Example}
+\vbox to 0cm{
+\vskip5.2cm
+\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mulshift.pdf}
+\vss
+}
+\vskip-0.6cm
+\begin{columns}
+\column[t]{6cm}
+\vskip-0.4cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mulshift_map.v}
+\column[t]{4.2cm}
+\vskip-0.6cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mulshift_test.v}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mulshift_test.ys}
+\end{columns}
+\end{frame}
+
 \subsubsection{TBD}
 
 \begin{frame}{\subsubsecname}
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 74f263270..3bbc239a4 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -13,3 +13,6 @@ sym_mul.pdf: sym_mul_*
 mymul.pdf: mymul_*
 	../../yosys mymul_test.ys
 
+mulshift.pdf: mulshift_*
+	../../yosys mulshift_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/mulshift_map.v b/manual/PRESENTATION_ExAdv/mulshift_map.v
new file mode 100644
index 000000000..4a3c2a062
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_map.v
@@ -0,0 +1,26 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output reg [WIDTH-1:0] Y;
+
+    parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
+    parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
+
+    reg _TECHMAP_FAIL_;
+    wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+    integer i;
+    always @* begin
+    	_TECHMAP_FAIL_ <= 1;
+        for (i = 0; i < WIDTH; i=i+1) begin
+            if (_TECHMAP_CONSTVAL_A_ === WIDTH'd1 << i) begin
+	        _TECHMAP_FAIL_ <= 0;
+                Y <= B << i;
+	    end
+            if (_TECHMAP_CONSTVAL_B_ === WIDTH'd1 << i) begin
+	        _TECHMAP_FAIL_ <= 0;
+                Y <= A << i;
+	    end
+	end
+    end
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mulshift_test.v b/manual/PRESENTATION_ExAdv/mulshift_test.v
new file mode 100644
index 000000000..4b975f414
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_test.v
@@ -0,0 +1,5 @@
+module test (A, X, Y);
+input [7:0] A;
+output [7:0] X = A * 8'd 6;
+output [7:0] Y = A * 8'd 8;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mulshift_test.ys b/manual/PRESENTATION_ExAdv/mulshift_test.ys
new file mode 100644
index 000000000..c5dac49eb
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_test.ys
@@ -0,0 +1,7 @@
+read_verilog mulshift_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+        -map mulshift_map.v;;
+
+show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v
-- 
cgit v1.2.3


From 0fbc1a59dd617aa3e9e9219180b8df0a37447300 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 17 Feb 2014 09:45:04 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex | 40 ++++++++++++++++++++++++++++++++++------
 manual/PRESENTATION_ExSyn.tex |  2 +-
 manual/PRESENTATION_Intro.tex |  4 ++--
 3 files changed, 37 insertions(+), 9 deletions(-)

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 483389d84..80210b96d 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -87,7 +87,7 @@ cd ..                 # switch back to design
 \end{lstlisting}
 
 \bigskip
-Note: Most synthesis script never switch to module context. But it is a very powerful
+Note: Most synthesis scripts never switch to module context. But it is a very powerful
 tool for interactive design investigation.
 \end{frame}
 
@@ -101,7 +101,7 @@ Special pattern can be used to select by object property or type. For example:
 select w:reg_*        # select all wires whose names start with reg_
 select a:foobar       # select all objects with the attribute foobar set
 select a:foobar=42    # select all objects with the attribute foobar set to 42
-select A:blabla       # select all module with the attribute blabla set
+select A:blabla       # select all modules with the attribute blabla set
 select foo/t:$add     # select all $add cells from the module foo
 \end{lstlisting}
 
@@ -114,7 +114,7 @@ reference to the {\tt select} command.
 
 \begin{frame}[fragile]{\subsubsecname}
 When more than one selection expression is used in one statement they are
-pushed on a stack. At the final elements on the stack are combined into a union:
+pushed on a stack. The final elements on the stack are combined into a union:
 
 \medskip
 \begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
@@ -170,7 +170,7 @@ See {\tt help select} for full documentation of this expressions.
 
 \begin{frame}[fragile]{\subsubsecname}
 Sometime a selection can most easily described by a series of add/delete operations.
-For the commands {\tt select -add} and {\tt select -del} add or remove objects
+The commands {\tt select -add} and {\tt select -del} respectively add or remove objects
 from the current selection instead of overwriting it.
 
 \medskip
@@ -327,7 +327,7 @@ is non-zero then the module is disabled for this set of parameters.
 \item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts
 in the context of the replacement module.
 \medskip
-\item The wire that comes first in alphatecial oder is interprated as string (must
+\item The wire that comes first in alphabetical oder is interpreted as string (must
 be connected to constants) that is executed as script. Then the wire is removed. Repeat.
 \medskip
 \item You can even call techmap recursively!
@@ -340,6 +340,10 @@ this is known to work well.
 \item Interacting with custom commands.
 \end{itemize}
 \end{itemize}
+
+\scriptsize
+PROTIP: Commands such as {\tt shell}, {\tt show -pause}, and {\tt dump} can be use
+in the {\tt \_TECHMAP\_DO\_*} scripts for debugging map modules.
 \end{frame}
 
 \begin{frame}[t]{\subsubsecname{} -- Example}
@@ -399,12 +403,36 @@ input values to cells.
 \end{columns}
 \end{frame}
 
-\subsubsection{TBD}
+\subsubsection{Handling shorted inputs}
 
 \begin{frame}{\subsubsecname}
 TBD
 \end{frame}
 
+\subsubsection{Notes on using techmap}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item Don't use positional cell parameters in map modules.
+\medskip
+\item Don't try to implement basic logic optimization with techmap. \\
+{\small (So the OR-reduce using OR3X1 cells map was actually a bad example.)}
+\medskip
+\item You can use the {\tt \$\_\,\_}-prefix for internal cell types to avoid
+collisions with the user-namespace. But always use two underscores or the
+internal consistency checker will trigger on this cells.
+\medskip
+\item Techmap has two major use cases:
+\begin{itemize}
+\item Creating good logic-level representation of arithmetic functions. \\
+This also means using dedicated hardware resources such as half- and full-adder
+cells in ASICS or dedicated carry logic in FPGAs.
+\smallskip
+\item Mapping of coarse-grain resources such as block memory or DSP cells.
+\end{itemize}
+\end{itemize}
+\end{frame}
+
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Coarse-grain synthesis}
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index 35d0b8a78..432ce3688 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -223,7 +223,7 @@ The designs in {\tt yosys-bigsim} are a good playground for experimenting with
 the effects of calling {\tt opt} in various places of the flow.
 
 \bigskip
-It generally is a good idea us call {\tt opt} before inherently expensive
+It generally is a good idea to call {\tt opt} before inherently expensive
 commands such as {\tt sat} or {\tt freduce}, as the possible gain is much
 higher in this cases as the possible loss.
 
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 312cb8986..275766474 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -326,7 +326,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 	Read Verilog source file and convert to internal representation.
 }%
 \only<2>{
-	Elaborate the design hierarchy. Should alsways be the first
+	Elaborate the design hierarchy. Should always be the first
 	command after reading the design.
 }%
 \only<3>{
@@ -794,7 +794,7 @@ We need you as a developer:
 \begin{frame}{\subsecname}
 \begin{itemize}
 \item Yosys is a powerful tool and framework for Verilog synthesis.
-\item Is uses a command-based interface and can be controlled by scripts.
+\item It uses a command-based interface and can be controlled by scripts.
 \item By combining existing commands and implementing new commands Yosys can
 be used in a wide range of application far beyond simple synthesis.
 \end{itemize}
-- 
cgit v1.2.3


From 3d9da919d8ec2f73df77dc1df02b132b12241d8e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 18 Feb 2014 19:37:39 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex              | 37 +++++++++++++++++++++++++++++-
 manual/PRESENTATION_ExAdv/Makefile         |  5 +++-
 manual/PRESENTATION_ExAdv/addshift_map.v   | 20 ++++++++++++++++
 manual/PRESENTATION_ExAdv/addshift_test.v  |  5 ++++
 manual/PRESENTATION_ExAdv/addshift_test.ys |  6 +++++
 manual/PRESENTATION_Intro.tex              |  2 +-
 6 files changed, 72 insertions(+), 3 deletions(-)
 create mode 100644 manual/PRESENTATION_ExAdv/addshift_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/addshift_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/addshift_test.ys

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 80210b96d..e42a535f4 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -406,7 +406,42 @@ input values to cells.
 \subsubsection{Handling shorted inputs}
 
 \begin{frame}{\subsubsecname}
-TBD
+\begin{itemize}
+\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and
+{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs.
+\medskip
+\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide
+number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}.
+\medskip
+\item Each unique signal bit is assigned its own number. Identical fields in the {\tt
+\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits.
+\medskip
+\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively.
+\medskip
+\item Example use-cases:
+\begin{itemize}
+\item Detecting shared clock or control signals in memory interfaces.
+\item In some cases this can be used for for optimization.
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t]{\subsubsecname{} -- Example}
+\vbox to 0cm{
+\vskip4.5cm
+\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf}
+\vss
+}
+\vskip-0.6cm
+\begin{columns}
+\column[t]{6cm}
+\vskip-0.4cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v}
+\column[t]{4.2cm}
+\vskip-0.6cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys}
+\end{columns}
 \end{frame}
 
 \subsubsection{Notes on using techmap}
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 3bbc239a4..2a2858e5f 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -16,3 +16,6 @@ mymul.pdf: mymul_*
 mulshift.pdf: mulshift_*
 	../../yosys mulshift_test.ys
 
+addshift.pdf: addshift_*
+	../../yosys addshift_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/addshift_map.v b/manual/PRESENTATION_ExAdv/addshift_map.v
new file mode 100644
index 000000000..b6d91b01b
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/addshift_map.v
@@ -0,0 +1,20 @@
+module \$add (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
+  
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
+  
+  parameter _TECHMAP_BITS_CONNMAP_ = 0;
+  parameter _TECHMAP_CONNMAP_A_ = 0;
+  parameter _TECHMAP_CONNMAP_B_ = 0;
+  
+  wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
+                        _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
+  
+  assign Y = A << 1;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/addshift_test.v b/manual/PRESENTATION_ExAdv/addshift_test.v
new file mode 100644
index 000000000..b53271faa
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/addshift_test.v
@@ -0,0 +1,5 @@
+module test (A, B, X, Y);
+input [7:0] A, B;
+output [7:0] X = A + B;
+output [7:0] Y = A + A;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/addshift_test.ys b/manual/PRESENTATION_ExAdv/addshift_test.ys
new file mode 100644
index 000000000..c08f1106a
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/addshift_test.ys
@@ -0,0 +1,6 @@
+read_verilog addshift_test.v
+hierarchy -check -top test
+
+techmap -map addshift_map.v;;
+
+show -prefix addshift -format pdf -notitle
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 275766474..1c07928b0 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -359,7 +359,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 	Map registers to available hardware flip-flops.
 }%
 \only<12>{
-	Map logix to available hardware gates.
+	Map logic to available hardware gates.
 }%
 \only<13>{
 	Clean up the design (just the last step of {\tt opt}).
-- 
cgit v1.2.3


From 98940260e1a0e5d9d5d305b5fabe0aed89c9f57c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Feb 2014 12:46:29 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex                   | 86 +++++++++++++++++++++++--
 manual/PRESENTATION_ExAdv/Makefile              | 10 ++-
 manual/PRESENTATION_ExAdv/macc_simple_test.v    |  6 ++
 manual/PRESENTATION_ExAdv/macc_simple_test.ys   | 36 +++++++++++
 manual/PRESENTATION_ExAdv/macc_simple_test_01.v |  6 ++
 manual/PRESENTATION_ExAdv/macc_simple_test_02.v |  6 ++
 manual/PRESENTATION_ExAdv/macc_simple_xmap.v    |  6 ++
 manual/PRESENTATION_ExAdv/select.v              | 15 +++++
 manual/PRESENTATION_ExAdv/select.ys             | 10 +++
 manual/PRESENTATION_ExAdv/select_01.v           | 15 -----
 manual/PRESENTATION_ExAdv/select_01.ys          | 10 ---
 manual/PRESENTATION_Intro.tex                   |  2 +-
 12 files changed, 175 insertions(+), 33 deletions(-)
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test.ys
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test_01.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test_02.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_xmap.v
 create mode 100644 manual/PRESENTATION_ExAdv/select.v
 create mode 100644 manual/PRESENTATION_ExAdv/select.ys
 delete mode 100644 manual/PRESENTATION_ExAdv/select_01.v
 delete mode 100644 manual/PRESENTATION_ExAdv/select_01.ys

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index e42a535f4..155403b85 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -223,11 +223,11 @@ show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
 \begin{frame}[fragile]{\subsubsecname{} -- Example}
 \begin{columns}
 \column[t]{4cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select_01.v}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select.v}
 \column[t]{7cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select_01.ys}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select.ys}
 \end{columns}
-\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select_01.pdf}
+\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select.pdf}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -477,7 +477,85 @@ cells in ASICS or dedicated carry logic in FPGAs.
 \subsectionpagesuffix
 \end{frame}
 
-\subsubsection{TBD}
+\subsubsection{Intro to coarse-grain synthesis}
+
+\begin{frame}[fragile]{\subsubsecname}
+In coarse-grain synthesis the target architecure has cells of the same
+complexity or larger complexity than the internal RTL representation.
+
+For example:
+\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]
+	wire [15:0] a, b;
+	wire [31:0] c, y;
+	assign y = a * b + c;
+\end{lstlisting}
+
+This circuit contains two cells in the RTL representation: one multiplier and
+one adder.
+
+\medskip
+Coarse grain synthesis is mapping this circuit to a single multiply-add cell
+of the target architecture, for example using an FPGA DSP core.
+
+\bigskip
+Fine-grain synthesis would be matching the circuit to smaller elements, such
+as LUTs, gates, or half- and full-adders.
+\end{frame}
+
+\subsubsection{The extract pass}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item Like the {\tt techmap} pass, the {\tt extract} pass is called with
+a map file. It compares the circuits inside the modules of the map file
+with the design and looks for sub-circuits in the design that match any
+of the modules in the map file.
+\bigskip
+\item If a match is found, the {\tt extract} pass will replace the matching
+subcircuit with an instance of the module from the map file.
+\bigskip
+\item In a way the {\tt extract} pass is the inverse of the techmap pass.
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- Example 1/2}
+\vbox to 0cm{
+\vskip2cm
+\begin{tikzpicture}
+    \node at (0,0) {\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00a.pdf}};
+    \node at (3,-3) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00b.pdf}};
+    \draw[yshift=0.2cm,thick,-latex] (1,-1) -- (2,-2);
+\end{tikzpicture}
+\vss}
+\vskip-1.2cm
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test.v}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/macc_simple_xmap.v}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys]
+read_verilog macc_simple_test.v
+hierarchy -check -top test
+
+extract -map macc_simple_xmap.v;;
+\end{lstlisting}
+\end{columns}
+\end{frame}
+
+\begin{frame}[fragile]{\subsubsecname{} -- Example 2/2}
+\hfil\begin{tabular}{cc}
+\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_01.v}}} &
+\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_02.v}}} \\
+$\downarrow$ & $\downarrow$ \\
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01a.pdf}} &
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02a.pdf}} \\
+$\downarrow$ & $\downarrow$ \\
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01b.pdf}} &
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02b.pdf}} \\
+\end{tabular}
+\end{frame}
+
+\subsubsection{The wrap-extract-unwrap method}
 
 \begin{frame}{\subsubsecname}
 TBD
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 2a2858e5f..60da31693 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,8 +1,9 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
+all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
+		macc_simple_xmap.pdf
 
-select_01.pdf: select_01.v select_01.ys
-	../../yosys select_01.ys
+select.pdf: select.v select.ys
+	../../yosys select.ys
 
 red_or3x1.pdf: red_or3x1_*
 	../../yosys red_or3x1_test.ys
@@ -19,3 +20,6 @@ mulshift.pdf: mulshift_*
 addshift.pdf: addshift_*
 	../../yosys addshift_test.ys
 
+macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
+	../../yosys macc_simple_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.v b/manual/PRESENTATION_ExAdv/macc_simple_test.v
new file mode 100644
index 000000000..6358a47c9
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, y);
+input [15:0] a, b;
+input [31:0] c, d;
+output [31:0] y;
+assign y = a * b + c + d;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.ys b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
new file mode 100644
index 000000000..d5b01237b
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
@@ -0,0 +1,36 @@
+read_verilog macc_simple_test.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -constports -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+read_verilog macc_simple_test_01.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_test_02.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_xmap.v
+hierarchy -check -top macc_16_16_32;;
+
+show -prefix macc_simple_xmap -format pdf -notitle
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test_01.v b/manual/PRESENTATION_ExAdv/macc_simple_test_01.v
new file mode 100644
index 000000000..8391fb383
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test_01.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + c*d + x;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test_02.v b/manual/PRESENTATION_ExAdv/macc_simple_test_02.v
new file mode 100644
index 000000000..3630102fa
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test_02.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + (c*d + x);
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_xmap.v b/manual/PRESENTATION_ExAdv/macc_simple_xmap.v
new file mode 100644
index 000000000..42f5bae95
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_xmap.v
@@ -0,0 +1,6 @@
+module macc_16_16_32(a, b, c, y);
+input [15:0] a, b;
+input [31:0] c;
+output [31:0] y;
+assign y = a*b + c;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/select.v b/manual/PRESENTATION_ExAdv/select.v
new file mode 100644
index 000000000..1b0bb7eeb
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/select.v
@@ -0,0 +1,15 @@
+module test(clk, s, a, y);
+    input clk, s;
+    input [15:0] a;
+    output [15:0] y;
+    reg [15:0] b, c;
+
+    always @(posedge clk) begin
+        b <= a;
+        c <= b;
+    end
+
+    wire [15:0] state_a = (a ^ b) + c;
+    wire [15:0] state_b = (a ^ b) - c;
+    assign y = !s ? state_a : state_b;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/select.ys b/manual/PRESENTATION_ExAdv/select.ys
new file mode 100644
index 000000000..9832c104b
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/select.ys
@@ -0,0 +1,10 @@
+read_verilog select.v
+hierarchy -check -top test
+proc; opt
+cd test
+select -set cone_a state_a %ci*:-$dff
+select -set cone_b state_b %ci*:-$dff
+select -set cone_ab @cone_a @cone_b %i
+show -prefix select -format pdf -notitle \
+     -color red @cone_ab -color magenta @cone_a \
+     -color blue @cone_b
diff --git a/manual/PRESENTATION_ExAdv/select_01.v b/manual/PRESENTATION_ExAdv/select_01.v
deleted file mode 100644
index 1b0bb7eeb..000000000
--- a/manual/PRESENTATION_ExAdv/select_01.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module test(clk, s, a, y);
-    input clk, s;
-    input [15:0] a;
-    output [15:0] y;
-    reg [15:0] b, c;
-
-    always @(posedge clk) begin
-        b <= a;
-        c <= b;
-    end
-
-    wire [15:0] state_a = (a ^ b) + c;
-    wire [15:0] state_b = (a ^ b) - c;
-    assign y = !s ? state_a : state_b;
-endmodule
diff --git a/manual/PRESENTATION_ExAdv/select_01.ys b/manual/PRESENTATION_ExAdv/select_01.ys
deleted file mode 100644
index a7fe27288..000000000
--- a/manual/PRESENTATION_ExAdv/select_01.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog select_01.v
-hierarchy -check -top test
-proc; opt
-cd test
-select -set cone_a state_a %ci*:-$dff
-select -set cone_b state_b %ci*:-$dff
-select -set cone_ab @cone_a @cone_b %i
-show -prefix select_01 -format pdf -notitle \
-     -color red @cone_ab -color magenta @cone_a \
-     -color blue @cone_b
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 1c07928b0..543fb41ed 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -680,7 +680,7 @@ basic functionality. Extensibility was one of Yosys' design goals.
 Because of the framework characterisitcs of Yosys, an increasing number of features
 become available in one tool. Yosys not only can be used for circuit synthesis but
 also for formal equivialence checking, SAT solving, and for circuit analysis, to
-name just a few other application domains. With propritaery software one needs to
+name just a few other application domains. With proprietary software one needs to
 learn a new tool for each of this applications.
 \end{itemize}
 \end{frame}
-- 
cgit v1.2.3


From b0e84802ecf3e224387317245786cd1437773a42 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Feb 2014 20:44:41 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v   | 30 +++++++
 manual/PRESENTATION_ExAdv/macc_xilinx_test.v       |  6 ++
 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys      | 17 ++++
 manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v | 63 +++++++++++++++
 manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v   | 91 ++++++++++++++++++++++
 5 files changed, 207 insertions(+)
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
new file mode 100644
index 000000000..1f4867d11
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
@@ -0,0 +1,30 @@
+
+(* techmap_celltype = "$mul" *)
+module mul_swap_ports (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
+
+\$mul #(
+	.A_SIGNED(B_SIGNED),
+	.B_SIGNED(A_SIGNED),
+	.A_WIDTH(B_WIDTH),
+	.B_WIDTH(A_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(B),
+	.B(A),
+	.Y(Y)
+);
+
+endmodule
+
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
new file mode 100644
index 000000000..d08d939e9
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, e, f, y);
+input [19:0] a, b, c;
+input [15:0] d, e, f;
+output [41:0] y;
+assign y = a*b + c*d + e*f;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
new file mode 100644
index 000000000..8cbc80b5e
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -0,0 +1,17 @@
+read_verilog macc_xilinx_test.v
+read_verilog -lib -icells macc_xilinx_unwrap_map.v
+hierarchy -check -top test;;
+
+show -prefix macc_xilinx_test_a -format pdf -notitle
+
+techmap -map macc_xilinx_swap_map.v;;
+
+show -prefix macc_xilinx_test_b -format pdf -notitle
+
+techmap -map macc_xilinx_wrap_map.v
+
+connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
+             -unsigned $__add_wrapper Y Y_WIDTH;;
+
+show -prefix macc_xilinx_test_c -format pdf -notitle
+
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
new file mode 100644
index 000000000..386635ac2
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
@@ -0,0 +1,63 @@
+
+module \$__mul_wrapper (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [A_WIDTH-1:0] A_ORIG = A;
+wire [B_WIDTH-1:0] B_ORIG = B;
+wire [Y_WIDTH-1:0] Y_ORIG;
+assign Y = Y_ORIG;
+
+\$mul #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_ORIG),
+	.B(B_ORIG),
+	.Y(Y_ORIG)
+);
+
+endmodule
+
+module \$__add_wrapper (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [A_WIDTH-1:0] A_ORIG = A;
+wire [B_WIDTH-1:0] B_ORIG = B;
+wire [Y_WIDTH-1:0] Y_ORIG;
+assign Y = Y_ORIG;
+
+\$add #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_ORIG),
+	.B(B_ORIG),
+	.Y(Y_ORIG)
+);
+
+endmodule
+
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
new file mode 100644
index 000000000..d1ded2954
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
@@ -0,0 +1,91 @@
+
+(* techmap_celltype = "$mul" *)
+module mul_wrap (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [24:0] A_25 = A;
+wire [17:0] B_18 = B;
+wire [47:0] Y_48;
+assign Y = Y_48;
+
+wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+reg _TECHMAP_FAIL_;
+initial begin
+	_TECHMAP_FAIL_ <= 0;
+	if (A_SIGNED || B_SIGNED)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH < 4 || B_WIDTH < 4)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH > 25 || B_WIDTH > 18)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH*B_WIDTH < 100)
+		_TECHMAP_FAIL_ <= 1;
+end
+
+\$__mul_wrapper #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_25),
+	.B(B_18),
+	.Y(Y_48)
+);
+
+endmodule
+
+(* techmap_celltype = "$add" *)
+module add_wrap (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [47:0] A_48 = A;
+wire [47:0] B_48 = B;
+wire [47:0] Y_48;
+assign Y = Y_48;
+
+wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+reg _TECHMAP_FAIL_;
+initial begin
+	_TECHMAP_FAIL_ <= 0;
+	if (A_SIGNED || B_SIGNED)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH < 10 && B_WIDTH < 10)
+		_TECHMAP_FAIL_ <= 1;
+end
+
+\$__add_wrapper #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_48),
+	.B(B_48),
+	.Y(Y_48)
+);
+
+endmodule
+
-- 
cgit v1.2.3


From 9351e4d3caef1af7b7768d66b7f6edc12713d109 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Feb 2014 23:44:28 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/macc_xilinx_test.v       |  9 ++++++-
 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys      | 31 +++++++++++++++++++---
 manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v | 12 ++++-----
 manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v       | 10 +++++++
 4 files changed, 51 insertions(+), 11 deletions(-)
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
index d08d939e9..d8fdf724c 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
@@ -1,6 +1,13 @@
-module test(a, b, c, d, e, f, y);
+module test1(a, b, c, d, e, f, y);
 input [19:0] a, b, c;
 input [15:0] d, e, f;
 output [41:0] y;
 assign y = a*b + c*d + e*f;
 endmodule
+
+module test2(a, b, c, d, e, f, y);
+input [19:0] a, b, c;
+input [15:0] d, e, f;
+output [41:0] y;
+assign y = a*b + (c*d + e*f);
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
index 8cbc80b5e..85c4a24f6 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -1,17 +1,40 @@
 read_verilog macc_xilinx_test.v
 read_verilog -lib -icells macc_xilinx_unwrap_map.v
-hierarchy -check -top test;;
+read_verilog -lib -icells macc_xilinx_xmap.v
+hierarchy -check ;;
 
-show -prefix macc_xilinx_test_a -format pdf -notitle
+show -prefix macc_xilinx_test1_a -format pdf -notitle test1
+show -prefix macc_xilinx_test2_a -format pdf -notitle test2
 
 techmap -map macc_xilinx_swap_map.v;;
 
-show -prefix macc_xilinx_test_b -format pdf -notitle
+show -prefix macc_xilinx_test1_b -format pdf -notitle test1
+show -prefix macc_xilinx_test2_b -format pdf -notitle test2
 
 techmap -map macc_xilinx_wrap_map.v
 
 connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
              -unsigned $__add_wrapper Y Y_WIDTH;;
 
-show -prefix macc_xilinx_test_c -format pdf -notitle
+show -prefix macc_xilinx_test1_c -format pdf -notitle test1
+show -prefix macc_xilinx_test2_c -format pdf -notitle test2
+
+design -push
+read_verilog macc_xilinx_xmap.v
+techmap -map macc_xilinx_swap_map.v
+techmap -map macc_xilinx_wrap_map.v;;
+design -save __macc_xilinx_xmap
+design -pop
+
+extract -constports -ignore_parameters \
+        -map %__macc_xilinx_xmap       \
+        -swap $__add_wrapper A,B ;;
+
+show -prefix macc_xilinx_test1_d -format pdf -notitle test1
+show -prefix macc_xilinx_test2_d -format pdf -notitle test2
+
+techmap -map macc_xilinx_unwrap_map.v;;
+
+show -prefix macc_xilinx_test1_e -format pdf -notitle test1
+show -prefix macc_xilinx_test2_e -format pdf -notitle test2
 
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
index 386635ac2..a80538d5b 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
@@ -7,9 +7,9 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] Y;
+input [24:0] A;
+input [17:0] B;
+output [47:0] Y;
 
 wire [A_WIDTH-1:0] A_ORIG = A;
 wire [B_WIDTH-1:0] B_ORIG = B;
@@ -38,9 +38,9 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] Y;
+input [47:0] A;
+input [47:0] B;
+output [47:0] Y;
 
 wire [A_WIDTH-1:0] A_ORIG = A;
 wire [B_WIDTH-1:0] B_ORIG = B;
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
new file mode 100644
index 000000000..15bd04ed1
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
@@ -0,0 +1,10 @@
+module DSP48_MACC (a, b, c, y);
+
+input [24:0] a;
+input [17:0] b;
+input [47:0] c;
+output [47:0] y;
+
+assign y = a*b + c;
+
+endmodule
-- 
cgit v1.2.3


From 2aff7b2a47d2ad65ff34e10f008733da9ef50c4a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Feb 2014 02:13:02 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex                 | 151 ++++++++++++++++++++++++++
 manual/PRESENTATION_ExAdv/Makefile            |   5 +-
 manual/PRESENTATION_ExAdv/macc_simple_test.ys |   1 +
 manual/PRESENTATION_ExAdv/macc_xilinx_test.v  |  16 +--
 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys |  23 ++--
 5 files changed, 177 insertions(+), 19 deletions(-)

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 155403b85..f2080922b 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -561,6 +561,157 @@ $\downarrow$ & $\downarrow$ \\
 TBD
 \end{frame}
 
+\subsubsection{Example: DSP48\_MACC}
+
+\begin{frame}[fragile]{\subsubsecname{} -- ?/?}
+\hfil\begin{tabular}{cc}
+{\tt test1} & {\tt test2} \\
+\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=1, lastline=6, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} &
+\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=8, lastline=13, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} \\
+$\downarrow$ & $\downarrow$ \\
+\end{tabular}
+\vskip-0.5cm
+\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+                            read_verilog macc_xilinx_test.v
+                            hierarchy -check
+\end{lstlisting}
+\vskip-0.5cm
+\hfil\begin{tabular}{cc}
+$\downarrow$ & $\downarrow$ \\
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\
+\end{tabular}
+\end{frame}
+
+\begin{frame}[fragile]{\subsubsecname{} -- ?/?}
+\hfil\begin{tabular}{cc}
+{\tt test1} & {\tt test2} \\
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\
+$\downarrow$ & $\downarrow$ \\
+\end{tabular}
+\vskip-0.2cm
+\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+                         techmap -map macc_xilinx_swap_map.v ;;
+\end{lstlisting}
+\vskip-0.2cm
+\hfil\begin{tabular}{cc}
+$\downarrow$ & $\downarrow$ \\
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}} &
+\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}} \\
+\end{tabular}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+Wrapping in {\tt test1}:
+\begin{columns}
+\column[t]{5cm}
+\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}}\vss}
+\column[t]{6cm}
+\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+techmap -map macc_xilinx_wrap_map.v
+
+connwrappers -unsigned $__mul_wrapper \
+                            Y Y_WIDTH \
+             -unsigned $__add_wrapper \
+                            Y Y_WIDTH ;;
+\end{lstlisting}
+\end{columns}
+
+\vskip1cm
+\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+Wrapping in {\tt test2}:
+\begin{columns}
+\column[t]{5cm}
+\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}}\vss}
+\column[t]{6cm}
+\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+techmap -map macc_xilinx_wrap_map.v
+
+connwrappers -unsigned $__mul_wrapper \
+                            Y Y_WIDTH \
+             -unsigned $__add_wrapper \
+                            Y Y_WIDTH ;;
+\end{lstlisting}
+\end{columns}
+
+\vskip1cm
+\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+Extract in {\tt test1}:
+\begin{columns}
+\column[t]{4.5cm}
+\vbox to 0cm{
+\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+design -push
+read_verilog macc_xilinx_xmap.v
+techmap -map macc_xilinx_swap_map.v
+techmap -map macc_xilinx_wrap_map.v;;
+design -save __macc_xilinx_xmap
+design -pop
+\end{lstlisting}
+\vss}
+\column[t]{5.5cm}
+\vskip-1cm
+\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+extract -constports -ignore_parameters \
+        -map %__macc_xilinx_xmap       \
+        -swap $__add_wrapper A,B ;;
+\end{lstlisting}
+\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}}\vss}
+\end{columns}
+
+\vskip2cm
+\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1d.pdf}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+Extract in {\tt test2}:
+\begin{columns}
+\column[t]{4.5cm}
+\vbox to 0cm{
+\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+design -push
+read_verilog macc_xilinx_xmap.v
+techmap -map macc_xilinx_swap_map.v
+techmap -map macc_xilinx_wrap_map.v;;
+design -save __macc_xilinx_xmap
+design -pop
+\end{lstlisting}
+\vss}
+\column[t]{5.5cm}
+\vskip-1cm
+\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+extract -constports -ignore_parameters \
+        -map %__macc_xilinx_xmap       \
+        -swap $__add_wrapper A,B ;;
+\end{lstlisting}
+\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}}\vss}
+\end{columns}
+
+\vskip2cm
+\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+Unwrap in {\tt test2}:
+
+\hfil\begin{tikzpicture}
+\node at (1,-1.7) {\begin{lstlisting}[linewidth=5.5cm, frame=single, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+techmap -map macc_xilinx_unwrap_map.v ;;
+\end{lstlisting}};
+\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}};
+\node at (0,-4) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}};
+\draw[-latex] (4,-0.7) .. controls (5,-1.7) .. (4,-2.7);
+\end{tikzpicture}
+\end{frame}
+
+
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Automatic design changes}
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 60da31693..993a9d9e1 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,6 +1,6 @@
 
 all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
-		macc_simple_xmap.pdf
+		macc_simple_xmap.pdf macc_xilinx_xmap.pdf
 
 select.pdf: select.v select.ys
 	../../yosys select.ys
@@ -23,3 +23,6 @@ addshift.pdf: addshift_*
 macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
 	../../yosys macc_simple_test.ys
 
+macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
+	../../yosys macc_xilinx_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.ys b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
index d5b01237b..8d106a28c 100644
--- a/manual/PRESENTATION_ExAdv/macc_simple_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
@@ -8,6 +8,7 @@ show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
 
 #################################################
 
+design -reset
 read_verilog macc_simple_test_01.v
 hierarchy -check -top test;;
 
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
index d8fdf724c..683d9d847 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
@@ -1,13 +1,13 @@
 module test1(a, b, c, d, e, f, y);
-input [19:0] a, b, c;
-input [15:0] d, e, f;
-output [41:0] y;
-assign y = a*b + c*d + e*f;
+    input [19:0] a, b, c;
+    input [15:0] d, e, f;
+    output [41:0] y;
+    assign y = a*b + c*d + e*f;
 endmodule
 
 module test2(a, b, c, d, e, f, y);
-input [19:0] a, b, c;
-input [15:0] d, e, f;
-output [41:0] y;
-assign y = a*b + (c*d + e*f);
+    input [19:0] a, b, c;
+    input [15:0] d, e, f;
+    output [41:0] y;
+    assign y = a*b + (c*d + e*f);
 endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
index 85c4a24f6..3f7893fa2 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -3,21 +3,21 @@ read_verilog -lib -icells macc_xilinx_unwrap_map.v
 read_verilog -lib -icells macc_xilinx_xmap.v
 hierarchy -check ;;
 
-show -prefix macc_xilinx_test1_a -format pdf -notitle test1
-show -prefix macc_xilinx_test2_a -format pdf -notitle test2
+show -prefix macc_xilinx_test1a -format pdf -notitle test1
+show -prefix macc_xilinx_test2a -format pdf -notitle test2
 
 techmap -map macc_xilinx_swap_map.v;;
 
-show -prefix macc_xilinx_test1_b -format pdf -notitle test1
-show -prefix macc_xilinx_test2_b -format pdf -notitle test2
+show -prefix macc_xilinx_test1b -format pdf -notitle test1
+show -prefix macc_xilinx_test2b -format pdf -notitle test2
 
 techmap -map macc_xilinx_wrap_map.v
 
 connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
              -unsigned $__add_wrapper Y Y_WIDTH;;
 
-show -prefix macc_xilinx_test1_c -format pdf -notitle test1
-show -prefix macc_xilinx_test2_c -format pdf -notitle test2
+show -prefix macc_xilinx_test1c -format pdf -notitle test1
+show -prefix macc_xilinx_test2c -format pdf -notitle test2
 
 design -push
 read_verilog macc_xilinx_xmap.v
@@ -30,11 +30,14 @@ extract -constports -ignore_parameters \
         -map %__macc_xilinx_xmap       \
         -swap $__add_wrapper A,B ;;
 
-show -prefix macc_xilinx_test1_d -format pdf -notitle test1
-show -prefix macc_xilinx_test2_d -format pdf -notitle test2
+show -prefix macc_xilinx_test1d -format pdf -notitle test1
+show -prefix macc_xilinx_test2d -format pdf -notitle test2
 
 techmap -map macc_xilinx_unwrap_map.v;;
 
-show -prefix macc_xilinx_test1_e -format pdf -notitle test1
-show -prefix macc_xilinx_test2_e -format pdf -notitle test2
+show -prefix macc_xilinx_test1e -format pdf -notitle test1
+show -prefix macc_xilinx_test2e -format pdf -notitle test2
+
+design -load
+show -prefix macc_xilinx_xmap -format pdf -notitle
 
-- 
cgit v1.2.3


From 79edcd4318590974ef49b2d5f561382eea3454bf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Feb 2014 14:59:59 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex                      | 117 ++++++++++++++++++---
 manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v   |   4 +-
 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys      |   2 +-
 manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v |   6 +-
 manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v   |  12 +--
 manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v       |   4 +-
 6 files changed, 113 insertions(+), 32 deletions(-)

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index f2080922b..bf9b350ff 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -491,15 +491,13 @@ For example:
 \end{lstlisting}
 
 This circuit contains two cells in the RTL representation: one multiplier and
-one adder.
-
-\medskip
-Coarse grain synthesis is mapping this circuit to a single multiply-add cell
-of the target architecture, for example using an FPGA DSP core.
+one adder. In some architectures this circuit can be implemented using
+a single circuit element, for example an FPGA DSP core. Coarse grain synthesis
+is this mapping of groups of circuit elements to larger components.
 
 \bigskip
-Fine-grain synthesis would be matching the circuit to smaller elements, such
-as LUTs, gates, or half- and full-adders.
+Fine-grain synthesis would be matching the circuit elements to smaller
+components, such as LUTs, gates, or half- and full-adders.
 \end{frame}
 
 \subsubsection{The extract pass}
@@ -558,12 +556,101 @@ $\downarrow$ & $\downarrow$ \\
 \subsubsection{The wrap-extract-unwrap method}
 
 \begin{frame}{\subsubsecname}
-TBD
+\scriptsize
+Often a coarse-grain element has a constant bit-width, but can be used to
+implement oprations with a smaller bit-width. For example, a 18x25-bit multiplier
+can also be used to implement 16x20-bit multiplication.
+
+\bigskip
+A way of mapping such elements in coarse grain synthesis is the wrap-extract-unwrap method:
+
+\begin{itemize}
+\item {\bf wrap} \\
+Identify candidate-cells in the circuit and wrap them in a cell with a constant
+wider bit-width using {\tt techmap}. The wrappers use the same parameters as the original cell, so
+the information about the original width of the ports is preserved. \\
+Then use the {\tt connwrappers} command to connect up the bit-extended in- and
+outputs of the wrapper cells.
+\item {\bf extract} \\
+Now all operations are encoded using the same bit-width as the coarse grain element. The {\tt
+extract} command can be used to replace circuits with cells of the target architecture.
+\item {\bf unwrap} \\
+The remaining wrapper cell can be unwrapped using {\tt techmap}.
+\end{itemize}
+
+\bigskip
+The following sides detail an example that shows how to map MACC operations of
+arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder (such as
+the Xilinx DSP48 cells).
 \end{frame}
 
 \subsubsection{Example: DSP48\_MACC}
 
-\begin{frame}[fragile]{\subsubsecname{} -- ?/?}
+\begin{frame}[t, fragile]{\subsubsecname{} -- 1/13}
+Preconditioning: {\tt macc\_xilinx\_swap\_map.v} \\
+Make sure {\tt A} is the smaller port on all multipliers
+
+\begin{columns}
+\column{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=15]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v}
+\column{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=16]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v}
+\end{columns}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- 2/13}
+Wrapping multipliers: {\tt macc\_xilinx\_wrap\_map.v}
+
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=23]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=24, lastline=46]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
+\end{columns}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- 3/13}
+Wrapping adders: {\tt macc\_xilinx\_wrap\_map.v}
+
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=48, lastline=67]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=68, lastline=89]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
+\end{columns}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- 4/13}
+Extract: {\tt macc\_xilinx\_xmap.v}
+
+\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1,  lastline=17]{PRESENTATION_ExAdv/macc_xilinx_xmap.v}
+
+.. simply use the same wrapping commands on this module as on the design to create a template for the {\tt extract} command.
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- 5/13}
+Unwrapping multipliers: {\tt macc\_xilinx\_unwrap\_map.v}
+
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1,  lastline=17]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=18, lastline=30]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
+\end{columns}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname{} -- 6/13}
+Unwrapping adders: {\tt macc\_xilinx\_unwrap\_map.v}
+
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=32, lastline=48]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=49, lastline=61]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
+\end{columns}
+\end{frame}
+
+\begin{frame}[fragile]{\subsubsecname{} -- 7/13}
 \hfil\begin{tabular}{cc}
 {\tt test1} & {\tt test2} \\
 \fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=1, lastline=6, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} &
@@ -583,7 +670,7 @@ $\downarrow$ & $\downarrow$ \\
 \end{tabular}
 \end{frame}
 
-\begin{frame}[fragile]{\subsubsecname{} -- ?/?}
+\begin{frame}[fragile]{\subsubsecname{} -- 8/13}
 \hfil\begin{tabular}{cc}
 {\tt test1} & {\tt test2} \\
 \fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
@@ -602,7 +689,7 @@ $\downarrow$ & $\downarrow$ \\
 \end{tabular}
 \end{frame}
 
-\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+\begin{frame}[t, fragile]{\subsubsecname{} -- 9/13}
 Wrapping in {\tt test1}:
 \begin{columns}
 \column[t]{5cm}
@@ -622,7 +709,7 @@ connwrappers -unsigned $__mul_wrapper \
 \hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}
 \end{frame}
 
-\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+\begin{frame}[t, fragile]{\subsubsecname{} -- 10/13}
 Wrapping in {\tt test2}:
 \begin{columns}
 \column[t]{5cm}
@@ -642,7 +729,7 @@ connwrappers -unsigned $__mul_wrapper \
 \hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}
 \end{frame}
 
-\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+\begin{frame}[t, fragile]{\subsubsecname{} -- 11/13}
 Extract in {\tt test1}:
 \begin{columns}
 \column[t]{4.5cm}
@@ -670,7 +757,7 @@ extract -constports -ignore_parameters \
 \hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1d.pdf}
 \end{frame}
 
-\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+\begin{frame}[t, fragile]{\subsubsecname{} -- 12/13}
 Extract in {\tt test2}:
 \begin{columns}
 \column[t]{4.5cm}
@@ -698,7 +785,7 @@ extract -constports -ignore_parameters \
 \hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}
 \end{frame}
 
-\begin{frame}[t, fragile]{\subsubsecname{} -- ?/?}
+\begin{frame}[t, fragile]{\subsubsecname{} -- 13/13}
 Unwrap in {\tt test2}:
 
 \hfil\begin{tikzpicture}
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
index 1f4867d11..e36967225 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
@@ -1,4 +1,3 @@
-
 (* techmap_celltype = "$mul" *)
 module mul_swap_ports (A, B, Y);
 
@@ -12,7 +11,7 @@ input [A_WIDTH-1:0] A;
 input [B_WIDTH-1:0] B;
 output [Y_WIDTH-1:0] Y;
 
-wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
+wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
 
 \$mul #(
 	.A_SIGNED(B_SIGNED),
@@ -27,4 +26,3 @@ wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
 );
 
 endmodule
-
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
index 3f7893fa2..f3e8af4f0 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -38,6 +38,6 @@ techmap -map macc_xilinx_unwrap_map.v;;
 show -prefix macc_xilinx_test1e -format pdf -notitle test1
 show -prefix macc_xilinx_test2e -format pdf -notitle test2
 
-design -load
+design -load __macc_xilinx_xmap
 show -prefix macc_xilinx_xmap -format pdf -notitle
 
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
index a80538d5b..9dfaef131 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
@@ -1,4 +1,3 @@
-
 module \$__mul_wrapper (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -7,8 +6,8 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [24:0] A;
-input [17:0] B;
+input [17:0] A;
+input [24:0] B;
 output [47:0] Y;
 
 wire [A_WIDTH-1:0] A_ORIG = A;
@@ -60,4 +59,3 @@ assign Y = Y_ORIG;
 );
 
 endmodule
-
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
index d1ded2954..f23f6c02a 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
@@ -1,4 +1,3 @@
-
 (* techmap_celltype = "$mul" *)
 module mul_wrap (A, B, Y);
 
@@ -12,8 +11,8 @@ input [A_WIDTH-1:0] A;
 input [B_WIDTH-1:0] B;
 output [Y_WIDTH-1:0] Y;
 
-wire [24:0] A_25 = A;
-wire [17:0] B_18 = B;
+wire [17:0] A_18 = A;
+wire [24:0] B_25 = B;
 wire [47:0] Y_48;
 assign Y = Y_48;
 
@@ -26,7 +25,7 @@ initial begin
 		_TECHMAP_FAIL_ <= 1;
 	if (A_WIDTH < 4 || B_WIDTH < 4)
 		_TECHMAP_FAIL_ <= 1;
-	if (A_WIDTH > 25 || B_WIDTH > 18)
+	if (A_WIDTH > 18 || B_WIDTH > 25)
 		_TECHMAP_FAIL_ <= 1;
 	if (A_WIDTH*B_WIDTH < 100)
 		_TECHMAP_FAIL_ <= 1;
@@ -39,8 +38,8 @@ end
 	.B_WIDTH(B_WIDTH),
 	.Y_WIDTH(Y_WIDTH)
 ) _TECHMAP_REPLACE_ (
-	.A(A_25),
-	.B(B_18),
+	.A(A_18),
+	.B(B_25),
 	.Y(Y_48)
 );
 
@@ -88,4 +87,3 @@ end
 );
 
 endmodule
-
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
index 15bd04ed1..06372f5af 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
@@ -1,7 +1,7 @@
 module DSP48_MACC (a, b, c, y);
 
-input [24:0] a;
-input [17:0] b;
+input [17:0] a;
+input [24:0] b;
 input [47:0] c;
 output [47:0] y;
 
-- 
cgit v1.2.3


From 66a5da5edc41a2b33413c965337001bb179d30f6 Mon Sep 17 00:00:00 2001
From: "Anthony J. Bentley" <anthony@cathet.us>
Date: Fri, 4 Apr 2014 16:51:27 -0600
Subject: POSIX find requires a path argument.

---
 manual/clean.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual')

diff --git a/manual/clean.sh b/manual/clean.sh
index 13554c01b..f4a2ea83a 100755
--- a/manual/clean.sh
+++ b/manual/clean.sh
@@ -1,2 +1,2 @@
 #!/bin/bash
-for f in $( find -name .gitignore ); do sed -re "s,^,find ${f%.gitignore} -name ',; s,$,' | xargs -r rm -vf,;" $f; done | bash -v
+for f in $( find . -name .gitignore ); do sed -re "s,^,find ${f%.gitignore} -name ',; s,$,' | xargs -r rm -f,;" $f; done | bash -v
-- 
cgit v1.2.3


From 9c1e578afe6af40be4600c20c883fa016fc7fa26 Mon Sep 17 00:00:00 2001
From: "Anthony J. Bentley" <anthony@cathet.us>
Date: Fri, 11 Apr 2014 02:42:59 -0600
Subject: Typos and grammar fixes through chapter 2.

---
 manual/CHAPTER_Basics.tex | 30 +++++++++++++++---------------
 manual/CHAPTER_Intro.tex  |  8 ++++----
 manual/manual.tex         |  4 ++--
 3 files changed, 21 insertions(+), 21 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Basics.tex b/manual/CHAPTER_Basics.tex
index 9cc4720e2..c0eda0e84 100644
--- a/manual/CHAPTER_Basics.tex
+++ b/manual/CHAPTER_Basics.tex
@@ -56,7 +56,7 @@ and how they relate to different kinds of synthesis.
 Regardless of the way a lower level representation of a circuit is
 obtained (synthesis or manual design), the lower level representation is usually
 verified by comparing simulation results of the lower level and the higher level
-representation \footnote{In the last years formal equivalence 
+representation \footnote{In recent years formal equivalence 
 checking also became an important verification method for validating RTL and 
 lower abstraction representation of the design.}.
 Therefore even if no synthesis is used, there must still be a simulatable
@@ -71,7 +71,7 @@ be considered a ``High-Level Language'' today.
 \subsection{System Level}
 
 The System Level abstraction of a system only looks at its biggest building
-blocks like CPUs and computing cores. On this level the circuit is usually described
+blocks like CPUs and computing cores. At this level the circuit is usually described
 using traditional programming languages like C/C++ or Matlab. Sometimes special
 software libraries are used that are aimed at simulation circuits on the system
 level, such as SystemC.
@@ -177,9 +177,9 @@ synthesis operations.
 
 \subsection{Logical Gate Level}
 
-On the logical gate level the design is represented by a netlist that uses only
+At the logical gate level the design is represented by a netlist that uses only
 cells from a small number of single-bit cells, such as basic logic gates (AND,
-OR, NOT, XOR, etc.) and Registers (usually D-Type Flip-flops).
+OR, NOT, XOR, etc.) and registers (usually D-Type Flip-flops).
 
 A number of netlist formats exists that can be used on this level, e.g.~the Electronic Design
 Interchange Format (EDIF), but for ease of simulation often a HDL netlist is used. The latter
@@ -191,8 +191,8 @@ within the gate level netlist and second the optimal (or at least good) mapping
 gate netlist to an equivalent netlist of physically available gate types.
 
 The simplest approach to logic synthesis is {\it two-level logic synthesis}, where a logic function
-is converted into a sum-of-products representation, e.g.~using a karnaugh map.
-This is a simple approach, but has exponential worst-case effort and can not make efficient use of
+is converted into a sum-of-products representation, e.g.~using a Karnaugh map.
+This is a simple approach, but has exponential worst-case effort and cannot make efficient use of
 physical gates other than AND/NAND-, OR/NOR- and NOT-Gates.
 
 Therefore modern logic synthesis tools utilize much more complicated {\it multi-level logic
@@ -287,7 +287,7 @@ applications to be used with a richer set of Verilog features.
 \subsection{Behavioural Modelling}
 
 Code that utilizes the Verilog {\tt always} statement is using {\it Behavioural
-Modelling}. In behavioural, modelling a circuit is described by means of imperative
+Modelling}. In behavioural modelling, a circuit is described by means of imperative
 program code that is executed on certain events, namely any change, a rising
 edge, or a falling edge of a signal. This is a very flexible construct during
 simulation but is only synthesizable when one of the following is modelled:
@@ -457,7 +457,7 @@ Correctness is crucial. In some areas this is obvious (such as
 correct synthesis of basic behavioural models). But it is also crucial for the
 areas that concern minor details of the standard, such as the exact rules
 for handling signed expressions, even when the HDL code does not target
-different synthesis tools. This is because (different to software source code that
+different synthesis tools. This is because (unlike software source code that
 is only processed by compilers), in most design flows HDL code is not only
 processed by the synthesis tool but also by one or more simulators and sometimes
 even a formal verification tool. It is key for this verification process
@@ -467,9 +467,9 @@ that all these tools use the same interpretation for the HDL code.
 
 Generally it is hard to give a one-dimensional description of how well a synthesis tool
 optimizes the design. First of all because not all optimizations are applicable to all
-designs and all synthesis tasks. Some optimizations work (best) on a coarse grain level
-(with complex cells such as adders or multipliers) and others work (best) on a fine
-grain level (single bit gates). Some optimizations target area and others target speed.
+designs and all synthesis tasks. Some optimizations work (best) on a coarse-grained level
+(with complex cells such as adders or multipliers) and others work (best) on a fine-grained
+level (single bit gates). Some optimizations target area and others target speed.
 Some work well on large designs while others don't scale well and can only be applied 
 to small designs.
 
@@ -610,7 +610,7 @@ The lexer is usually generated by a lexer generator (e.g.~{\tt flex} \citeweblin
 description file that is using regular expressions to specify the text pattern that should match
 the individual tokens.
 
-The lexer is also responsible for skipping ignored characters (such as white spaces outside string
+The lexer is also responsible for skipping ignored characters (such as whitespace outside string
 constants and comments in the case of Verilog) and converting the original text snippet to a token
 value.
 
@@ -714,11 +714,11 @@ be connected in two different ways: through {\it Single-Pass Pipelining} and by
 Traditionally a parser and lexer are connected using the pipelined approach: The lexer provides a function that
 is called by the parser. This function reads data from the input until a complete lexical token has been read. Then
 this token is returned to the parser. So the lexer does not first generate a complete list of lexical tokens
-and then passes it to the parser. Instead they are running concurrently and the parser can consume tokens as
+and then pass it to the parser. Instead they run concurrently and the parser can consume tokens as
 the lexer produces them.
 
-The single-pass pipelining approach has the advantage of lower memory footprint (at no time the complete design
-must be kept in memory) but has the disadvantage of tighter coupling between the interacting components.
+The single-pass pipelining approach has the advantage of lower memory footprint (at no time must the complete design
+be kept in memory) but has the disadvantage of tighter coupling between the interacting components.
 
 Therefore single-pass pipelining should only be used when the lower memory footprint is required or the
 components are also conceptually tightly coupled. The latter certainly is the case for a parser and its lexer.
diff --git a/manual/CHAPTER_Intro.tex b/manual/CHAPTER_Intro.tex
index 675d24026..f735d46b2 100644
--- a/manual/CHAPTER_Intro.tex
+++ b/manual/CHAPTER_Intro.tex
@@ -45,7 +45,7 @@ researched field. All the information required to write such tools has been open
 available for a long time, and it is therefore likely that a FOSS HDL synthesis tool
 with a feature-complete Verilog or VHDL front end must exist which can be used as a basis for a custom RTL synthesis tool.
 
-Due to the authors preference for Verilog over VHDL it has been decided early
+Due to the author's preference for Verilog over VHDL it was decided early
 on to go for Verilog instead of VHDL\footnote{A quick investigation into FOSS
 VHDL tools yielded similar grim results for FOSS VHDL synthesis tools.}.
 So the existing FOSS Verilog synthesis tools were evaluated (see
@@ -56,12 +56,12 @@ is discussed in this document.
 
 \section{Structure of this Document}
 
-The structure of this document is a follows:
+The structure of this document is as follows:
 
 Chapter~\ref{chapter:intro} is this introduction.
 
 Chapter~\ref{chapter:basics} covers a short introduction to the world of HDL
-synthesis. Basic principles and the terminology is outlined in this chapter.
+synthesis. Basic principles and the terminology are outlined in this chapter.
 
 Chapter~\ref{chapter:approach} gives the quickest possible outline to how the
 problem of implementing a HDL synthesis tool is approached in the case of
@@ -82,7 +82,7 @@ Yosys source code. The chapter concludes with an example loadable module
 for Yosys.
 
 Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} 
-cover three improtant pieces of the synthesis pileline: The Verilog frontend,
+cover three important pieces of the synthesis pipeline: The Verilog frontend,
 the optimization passes and the technology mapping to the target architecture,
 respectively.
 
diff --git a/manual/manual.tex b/manual/manual.tex
index d6ffd95a6..c305ecb05 100644
--- a/manual/manual.tex
+++ b/manual/manual.tex
@@ -140,7 +140,7 @@ bookmarksopen=false%
 \eject
 
 \chapter*{Abstract}
-Most of todays digital design is done in HDL code (mostly Verilog or VHDL) and
+Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
 with the help of HDL synthesis tools.
 
 In special cases such as synthesis for coarse-grain cell libraries or when
@@ -158,7 +158,7 @@ by Yosys to perform advanced gate-level optimizations.
 An evaluation of Yosys based on real-world designs is included. It is shown
 that Yosys can be used as-is to synthesize such designs. The results produced
 by Yosys in this tests where successflly verified using formal verification
-and are compareable in quality to the results produced by a commercial
+and are comparable in quality to the results produced by a commercial
 synthesis tool.
 
 \bigskip
-- 
cgit v1.2.3


From 154c9f8b513db97d0397ac8d4c3c5c7276f6260f Mon Sep 17 00:00:00 2001
From: "Anthony J. Bentley" <anthony@cathet.us>
Date: Fri, 2 May 2014 03:08:40 -0600
Subject: Typos and grammar fixes through chapter 4.

---
 manual/CHAPTER_Approach.tex | 14 ++++++-------
 manual/CHAPTER_Overview.tex | 50 ++++++++++++++++++++++-----------------------
 2 files changed, 32 insertions(+), 32 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Approach.tex b/manual/CHAPTER_Approach.tex
index a2c40bea4..691225805 100644
--- a/manual/CHAPTER_Approach.tex
+++ b/manual/CHAPTER_Approach.tex
@@ -8,7 +8,7 @@ approach followed in the effort to implement this tool.
 
 \section{Data- and Control-Flow}
 
-The data- and control-flow of a typical synthesis-tool is very similar to the data- and control-flow of a typical
+The data- and control-flow of a typical synthesis tool is very similar to the data- and control-flow of a typical
 compiler: different subsystems are called in a predetermined order, each consuming the data generated by the
 last subsystem and generating the data for the next subsystem (see Fig.~\ref{fig:approach_flow}).
 
@@ -44,10 +44,10 @@ last subsystem and generating the data for the next subsystem (see Fig.~\ref{fig
 \end{figure}
 
 The first subsystem to be called is usually called a {\it frontend}. It does not process the data generated by
-another subsystem but instead reads the user input; in the case of a HDL synthesis tool the behavioural
+another subsystem but instead reads the user input---in the case of a HDL synthesis tool, the behavioural
 HDL code.
 
-The subsystems that consume data from previous subsystems and produces data for the next subsystems (usually in the
+The subsystems that consume data from previous subsystems and produce data for the next subsystems (usually in the
 same or a similar format) are called {\it passes}.
 
 The last subsystem that is executed transforms the data generated by the last pass into a suitable output
@@ -61,7 +61,7 @@ script.
 
 Yosys uses two different internal formats. The first is used to store an abstract syntax tree (AST) of a verilog
 input file. This format is simply called {\it AST} and is generated by the Verilog Frontend. This data structure
-is then consumed by a subsystem called {\it AST Frontend}\footnote{In Yosys the term {\it pass} is only used to
+is consumed by a subsystem called {\it AST Frontend}\footnote{In Yosys the term {\it pass} is only used to
 refer to commands that operate on the RTLIL data structure.}. This AST Frontend then generates a design in Yosys'
 main internal format, the Register-Transfer-Level-Intermediate-Language (RTLIL) representation. It does that
 by first performing a number of simplifications within the AST representation and then generating RTLIL from
@@ -71,10 +71,10 @@ The RTLIL representation is used by all passes as input and outputs. This has th
 using different representational formats between different passes:
 
 \begin{itemize}
-\item The passes can be re-arranged in a different order and passes can be removed or inserted.
+\item The passes can be rearranged in a different order and passes can be removed or inserted.
 \item Passes can simply pass-thru the parts of the design they don't change without the need
       to convert between formats. In fact Yosys passes output the same data structure they received
-      as input and perform all changes in place.
+      as input and performs all changes in place.
 \item All passes use the same interface, thus reducing the effort required to understand a pass
       when reading the Yosys source code, e.g.~when adding additional features.
 \end{itemize}
@@ -95,7 +95,7 @@ The use of RTLIL also has the disadvantage of having a very powerful format
 between all passes, even when doing gate-level synthesis where the more
 advanced features are not needed. In order to reduce complexity for passes that
 operate on a low-level representation, these passes check the features used in
-the input RTLIL and fail to run when non-supported high-level constructs are
+the input RTLIL and fail to run when unsupported high-level constructs are
 used. In such cases a pass that transforms the higher-level constructs to
 lower-level constructs must be called from the synthesis script first.
 
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index b9df57d1c..ec402231f 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -3,8 +3,8 @@
 \label{chapter:overview}
 
 Yosys is an extensible open source hardware synthesis tool. It is aimed at
-designers who are looking for an easy accessible, universal, and vendor
-independent synthesis tool, and scientists who do research in
+designers who are looking for an easily accessible, universal, and
+vendor-independent synthesis tool, as well as scientists who do research in
 electronic design automation (EDA) and are looking for an open synthesis
 framework that can be used to test algorithms on complex real-world designs.
 
@@ -49,7 +49,7 @@ of the backends, namely the Verilog Backend for generating Verilog netlists
 and the ILANG Backend for writing the RTLIL data in the same format that is
 understood by the ILANG Frontend.
 
-With the exception of the AST Frontend, that is called by the high-level HDL
+With the exception of the AST Frontend, which is called by the high-level HDL
 frontends and can't be called directly by the user, all program modules are
 called by the user (usually using a synthesis script that contains text
 commands for Yosys).
@@ -57,7 +57,7 @@ commands for Yosys).
 By combining passes in different ways and/or adding additional passes to Yosys
 it is possible to adapt Yosys to a wide range of applications. For this to be
 possible it is key that (1) all passes operate on the same data structure
-(RTLIL) and (2) that this data structure is powerful enough represent the design
+(RTLIL) and (2) that this data structure is powerful enough to represent the design
 in different stages of the synthesis.
 
 \begin{figure}[t]
@@ -97,7 +97,7 @@ refers to the fact, that RTLIL also has a text representation, usually referred
 The only exception are the high-level frontends that use the AST representation as an intermediate step before generating RTLIL
 data.
 
-In order to avoid re-inventing names for the RTLIL classes, they are simply referred to by their full C++ name, i.e.~including
+In order to avoid reinventing names for the RTLIL classes, they are simply referred to by their full C++ name, i.e.~including
 the {\tt RTLIL::} namespace prefix, in this document.
 
 Figure~\ref{fig:Overview_RTLIL} shows a simplified Entity-Relationship Diagram (ER Diagram) of RTLIL. In $1:N$ relationships the arrow
@@ -105,7 +105,7 @@ points from the $N$ side to the $1$. For example one RTLIL::Design contains $N$
 A two-pointed arrow indicates a $1:1$ relationship.
 
 The RTLIL::Design is the root object of the RTLIL data structure. There is always one ``current design'' in memory
-on which passes operate, frontends add data to it and backends convert to exportable formats. But in some cases passes
+which passes operate on, frontends add data to and backends convert to exportable formats. But in some cases passes
 internally generate additional RTLIL::Design objects. For example when a pass is reading an auxiliary Verilog file such
 as a cell library, it might create an additional RTLIL::Design object and call the Verilog frontend with this
 other object to parse the cell library.
@@ -154,12 +154,12 @@ transformed to an RTLIL-compatible representation by the HDL frontend. This incl
 Verilog-features such as generate-blocks, loops and parameters.
 
 The following sections contain a more detailed description of the different
-parts of RTLIL and rationales behind some of the design decisions.
+parts of RTLIL and rationale behind some of the design decisions.
 
 \subsection{RTLIL Identifiers}
 
 All identifiers in RTLIL (such as module names, port names, signal names, cell
-types, etc.) follow the following naming convention: They must either start with
+types, etc.) follow the following naming convention: they must either start with
 a backslash (\textbackslash) or a dollar sign (\$).
 
 Identifiers starting with a backslash are public visible identifiers. Usually
@@ -172,13 +172,13 @@ identifiers that start with a backslash.
 This has three advantages:
 
 \begin{itemize}
-\item Firstly it is impossible that an auto-generated identifier collides with
+\item First, it is impossible that an auto-generated identifier collides with
 an identifier that was provided by the user.
-\item Secondly the information about which identifiers were originally
+\item Second, the information about which identifiers were originally
 provided by the user is always available which can help guide some optimizations. For example the ``opt\_rmunused''
-is trying to preserve signals with a user-provided name but doesn't hesitate to delete signals that have
+tries to preserve signals with a user-provided name but doesn't hesitate to delete signals that have
 auto-generated names when they just duplicate other signals.
-\item Thirdly the delicate job of finding suitable auto-generated public visible
+\item Third, the delicate job of finding suitable auto-generated public visible
 names is deferred to one central location. Internally auto-generated names that
 may hold important information for Yosys developers can be used without
 disturbing external tools. For example the Verilog backend assigns names in the form {\tt \_{\it integer}\_}.
@@ -216,7 +216,7 @@ Verilog and VHDL both support parametric modules (known as ``generic entities''
 format does not support parametric modules itself. Instead each module contains a callback function
 into the AST frontend to generate a parametrized variation of the RTLIL::Module as needed. This
 callback then returns the auto-generated name of the parametrized variation of the module. (A hash
-over the parameters and the module name is used to prohibit the same parametrized variation to be
+over the parameters and the module name is used to prohibit the same parametrized variation from being
 generated twice. For modules with only a few parameters, a name directly containing all parameters
 is generated instead of a hash string.)
 
@@ -233,7 +233,7 @@ An RTLIL::Wire object has the following properties:
 \begin{itemize}
 \item The wire name
 \item A list of attributes
-\item A width (busses are just wires with a width > 1)
+\item A width (buses are just wires with a width > 1)
 \item If the wire is a port: port number and direction (input/output/inout)
 \end{itemize}
 
@@ -256,7 +256,7 @@ An RTLIL::Cell object has the following properties:
 \end{itemize}
 
 The connections of ports to wires are coded by assigning an RTLIL::SigSpec
-to each cell ports. The RTLIL::SigSpec data type is described in the next section.
+to each cell port. The RTLIL::SigSpec data type is described in the next section.
 
 \subsection{RTLIL::SigSpec}
 
@@ -382,7 +382,7 @@ end
 
 This pass has transformed the outer RTLIL::SwitchRule into a modified RTLIL::SyncRule object
 for the {\tt \textbackslash{}reset} signal. Further processing converts the RTLIL::Process
-e.g.~into a d-type flip-flop with asynchronous reset and a multiplexer for the enable signal:
+into e.g.~a d-type flip-flop with asynchronous reset and a multiplexer for the enable signal:
 
 \begin{lstlisting}[numbers=left,frame=single,language=rtlil]
 cell $adff $procdff$6
@@ -442,31 +442,31 @@ The {\tt memory} pass performs this conversion and can (depending on the options
 to it) transform the memories directly to d-type flip-flops and address logic or yield
 multiport memory blocks (represented using {\tt \$mem} cells).
 
-See Sec.~\ref{sec:memcells} for details on the memory cell types.
+See Sec.~\ref{sec:memcells} for details about the memory cell types.
 
 \section{Command Interface and Synthesis Scripts}
 
 Yosys reads and processes commands from synthesis scripts, command line arguments and
 an interactive command prompt. Yosys commands consist of a command name and an optional
-whitespace sparated list of arguments. Commands are terminated using the newline character
+whitespace separated list of arguments. Commands are terminated using the newline character
 or a semicolon ({\tt ;}). Empty lines and lines starting with the hash sign ({\tt \#}) are ignored. 
 See Sec.~\ref{sec:typusecase} for an example synthesis script.
 
 The command {\tt help} can be used to access the command reference manual.
 
-Most commands can operate not only on the entire design but also only on {\it selected}
+Most commands can operate not only on the entire design but also specifically on {\it selected}
 parts of the design. For example the command {\tt dump} will print all selected objects
 in the current design while {\tt dump foobar} will only print the module {\tt foobar}
 and {\tt dump *} will print the entire design regardless of the current selection.
 
 The selection mechanism is very powerful. For example the command {\tt dump */t:\$add
 \%x:+[A] */w:* \%i} will print all wires that are connected to the \B{A} port of
-a {\tt \$add} cell.  A detailed documentation of the select framework can be
+a {\tt \$add} cell.  Detailed documentation of the select framework can be
 found in the command reference for the {\tt select} command.
 
 \section{Source Tree and Build System}
 
-The Yosys source tree is organized in the following top-level directories:
+The Yosys source tree is organized into the following top-level directories:
 
 \begin{itemize}
 
@@ -512,15 +512,15 @@ and a {\tt Makefile.inc}. The Yosys kernel automatically detects all commands li
 Yosys. So it is not needed to add additional commands to a central list of commands.
 \end{sloppypar}
 
-A good starting point for reading example source code for learning how to write passes
+Good starting points for reading example source code to learn how to write passes
 are {\tt passes/opt/opt\_rmdff.cc} and {\tt passes/opt/opt\_share.cc}.
 
 See the top-level README file for a quick {\it Getting Started} guide and build
-instructions. Yosys is a pure Makefile based project.
+instructions. The Yosys build is based solely on Makefiles.
 
 Users of the Qt Creator IDE can generate a QT Creator project file using {\tt
 make qtcreator}. Users of the Eclipse IDE can use the ``Makefile Project with
 Existing Code'' project type in the Eclipse ``New Project'' dialog (only
-available after the CDT plugin has been installed) to create an Eclipse Project
-for programming extensions to Yosys or just browsing the Yosys code base.
+available after the CDT plugin has been installed) to create an Eclipse project
+in order to programming extensions to Yosys or just browse the Yosys code base.
 
-- 
cgit v1.2.3


From 51a615b26d95eddb39e7389d431c0ab7002d52bb Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 6 May 2014 14:42:04 +0200
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex | 71 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 63 insertions(+), 8 deletions(-)

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index bf9b350ff..7aa014242 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -789,11 +789,11 @@ extract -constports -ignore_parameters \
 Unwrap in {\tt test2}:
 
 \hfil\begin{tikzpicture}
+\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}};
+\node at (0,-4) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}};
 \node at (1,-1.7) {\begin{lstlisting}[linewidth=5.5cm, frame=single, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
 techmap -map macc_xilinx_unwrap_map.v ;;
 \end{lstlisting}};
-\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}};
-\node at (0,-4) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}};
 \draw[-latex] (4,-0.7) .. controls (5,-1.7) .. (4,-2.7);
 \end{tikzpicture}
 \end{frame}
@@ -808,10 +808,67 @@ techmap -map macc_xilinx_unwrap_map.v ;;
 \subsectionpagesuffix
 \end{frame}
 
-\subsubsection{TBD}
+\subsubsection{Changing the design from Yosys}
 
 \begin{frame}{\subsubsecname}
-TBD
+Yosys commands can be used to change the design in memory. Examples of this are:
+
+\begin{itemize}
+\item {\bf Changes in design hierarchy} \\
+Commands such as {\tt flatten} and {\tt submod} can be used to change the design hierarchy, i.e.
+flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis
+scripts as well as in reverse engineering and analysis.
+
+\item {\bf Behavioral changes} \\
+Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example
+changing asynchonous resets to synchronous resets. This has applications in design space exploration
+(evaluation of various architectures for one circuit).
+\end{itemize}
+\end{frame}
+
+\subsubsection{Example: Async reset to sync reset}
+
+\begin{frame}[t, fragile]{\subsubsecname}
+The following techmap map file replaces all positive-edge async reset flip-flops with
+positive-edge sync reset flip-flops. The code is taken from the example Yosys script
+for ASIC synthesis of the Amber ARMv2 CPU.
+
+\begin{columns}
+\column[t]{6cm}
+\vbox to 0cm{
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
+(* techmap_celltype = "$adff" *)
+module adff2dff (CLK, ARST, D, Q);
+
+    parameter WIDTH = 1;
+    parameter CLK_POLARITY = 1;
+    parameter ARST_POLARITY = 1;
+    parameter ARST_VALUE = 0;
+    
+    input CLK, ARST;
+    input [WIDTH-1:0] D;
+    output reg [WIDTH-1:0] Q;
+    
+    wire [1023:0] _TECHMAP_DO_ = "proc";
+    
+    wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
+\end{lstlisting}
+\vss}
+\column[t]{4cm}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
+// ..continued..
+
+
+    always @(posedge CLK)
+        if (ARST)
+            Q <= ARST_VALUE;
+        else
+             <= D;
+
+endmodule
+\end{lstlisting}
+\end{columns}
+
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -820,10 +877,8 @@ TBD
 
 \begin{frame}{\subsecname}
 \begin{itemize}
-\item TBD
-\item TBD
-\item TBD
-\item TBD
+\item A lot can be achived in Yosys just with the standard set of commands.
+\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks.
 \end{itemize}
 
 \bigskip
-- 
cgit v1.2.3


From 1a487303a081849bd7561772641f90126dcce24e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 14 Jun 2014 16:42:30 +0200
Subject: Progress in presentation

---
 manual/PRESENTATION_ExOth.tex          | 66 ++++++++++++++++++++++++++++++++--
 manual/PRESENTATION_ExOth/.gitignore   |  1 +
 manual/PRESENTATION_ExOth/Makefile     |  8 +++++
 manual/PRESENTATION_ExOth/scrambler.v  | 14 ++++++++
 manual/PRESENTATION_ExOth/scrambler.ys | 23 ++++++++++++
 5 files changed, 109 insertions(+), 3 deletions(-)
 create mode 100644 manual/PRESENTATION_ExOth/.gitignore
 create mode 100644 manual/PRESENTATION_ExOth/Makefile
 create mode 100644 manual/PRESENTATION_ExOth/scrambler.v
 create mode 100644 manual/PRESENTATION_ExOth/scrambler.ys

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex
index 13ec3d193..64c4af721 100644
--- a/manual/PRESENTATION_ExOth.tex
+++ b/manual/PRESENTATION_ExOth.tex
@@ -23,10 +23,70 @@ This section contains 3 subsections:
 \subsectionpagesuffix
 \end{frame}
 
-\subsubsection{TBD}
+\begin{frame}{\subsecname}
+Yosys can also be used to investigate designs (or netlists created
+from other tools).
 
-\begin{frame}{\subsubsecname}
-TBD
+\begin{itemize}
+\item
+The selection mechanism (see slides ``Using Selections''), especially pattern such
+as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
+are connected.
+
+\item
+Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used 
+to transform the design into an equivialent design that is easier to analyse.
+
+\item
+Commands such as {\tt eval} and {\tt sat} can be used to investigate the
+behavior of the circuit.
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t, fragile]{Example: Reorganizing a module}
+\begin{columns}
+\column[t]{4cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExOth/scrambler.v}
+\column[t]{7cm}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
+read_verilog scrambler.v
+
+hierarchy; proc;;
+
+cd scrambler
+submod -name xorshift32 xs %c %ci %D \
+           %c %ci:+[D] %D %ci*:-$dff \
+           xs %co %ci %d
+\end{lstlisting}
+\end{columns}
+
+\hfil\includegraphics[width=11cm,trim=0 0cm 0 1.5cm]{PRESENTATION_ExOth/scrambler_p01.pdf}
+
+\hfil\includegraphics[width=11cm,trim=0 0cm 0 2cm]{PRESENTATION_ExOth/scrambler_p02.pdf}
+\end{frame}
+
+\begin{frame}[t, fragile]{Example: Analysis of circuit behavior}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+> read_verilog scrambler.v
+> hierarchy; proc;; cd scrambler
+> submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
+
+> cd xorshift32
+> rename n2 in
+> rename n1 out
+
+> eval -set in 1 -show out
+Eval result: \out = 270369.
+
+> eval -set in 270369 -show out
+Eval result: \out = 67634689.
+
+> sat -set out 632435482
+Signal Name                 Dec        Hex                                   Bin
+-------------------- ---------- ---------- -------------------------------------
+\in                   745495504   2c6f5bd0      00101100011011110101101111010000
+\out                  632435482   25b2331a      00100101101100100011001100011010
+\end{lstlisting}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
diff --git a/manual/PRESENTATION_ExOth/.gitignore b/manual/PRESENTATION_ExOth/.gitignore
new file mode 100644
index 000000000..cf658897d
--- /dev/null
+++ b/manual/PRESENTATION_ExOth/.gitignore
@@ -0,0 +1 @@
+*.dot
diff --git a/manual/PRESENTATION_ExOth/Makefile b/manual/PRESENTATION_ExOth/Makefile
new file mode 100644
index 000000000..a12beadad
--- /dev/null
+++ b/manual/PRESENTATION_ExOth/Makefile
@@ -0,0 +1,8 @@
+
+all: scrambler_p01.pdf scrambler_p02.pdf
+
+scrambler_p01.pdf: scrambler.ys scrambler.v
+	../../yosys scrambler.ys
+
+scrambler_p02.pdf: scrambler_p01.pdf
+
diff --git a/manual/PRESENTATION_ExOth/scrambler.v b/manual/PRESENTATION_ExOth/scrambler.v
new file mode 100644
index 000000000..d4c1fa2bb
--- /dev/null
+++ b/manual/PRESENTATION_ExOth/scrambler.v
@@ -0,0 +1,14 @@
+module scrambler(
+        input clk, rst, in_bit,
+        output reg out_bit
+);
+    reg [31:0] xs;
+    always @(posedge clk) begin
+    	if (rst)
+	    xs = 1;
+        xs = xs ^ (xs << 13);
+        xs = xs ^ (xs >> 17);
+        xs = xs ^ (xs << 5);
+        out_bit <= in_bit ^ xs[0];
+    end
+endmodule
diff --git a/manual/PRESENTATION_ExOth/scrambler.ys b/manual/PRESENTATION_ExOth/scrambler.ys
new file mode 100644
index 000000000..2ef14c56e
--- /dev/null
+++ b/manual/PRESENTATION_ExOth/scrambler.ys
@@ -0,0 +1,23 @@
+
+read_verilog scrambler.v
+
+hierarchy; proc;;
+
+cd scrambler
+submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
+cd ..
+
+show -prefix scrambler_p01 -format pdf -notitle scrambler
+show -prefix scrambler_p02 -format pdf -notitle xorshift32
+
+echo on
+
+cd xorshift32
+rename n2 in
+rename n1 out
+
+eval -set in 1 -show out
+eval -set in 270369 -show out
+
+sat -set out 632435482
+
-- 
cgit v1.2.3


From b18fa95d2f1f4118cdb7c16e3415059bd81e2325 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 21 Jun 2014 16:33:33 +0200
Subject: Progress in presentation

---
 manual/PRESENTATION_ExOth.tex              | 115 ++++++++++++++++++++++++-----
 manual/PRESENTATION_ExOth/Makefile         |  10 ++-
 manual/PRESENTATION_ExOth/axis_master.v    |  27 +++++++
 manual/PRESENTATION_ExOth/axis_test.v      |  27 +++++++
 manual/PRESENTATION_ExOth/axis_test.ys     |   5 ++
 manual/PRESENTATION_ExOth/equiv.ys         |  17 +++++
 manual/PRESENTATION_ExSyn.tex              |   2 +-
 manual/PRESENTATION_ExSyn/Makefile         |   2 +-
 manual/PRESENTATION_ExSyn/techmap_01_map.v |   6 +-
 9 files changed, 188 insertions(+), 23 deletions(-)
 create mode 100644 manual/PRESENTATION_ExOth/axis_master.v
 create mode 100644 manual/PRESENTATION_ExOth/axis_test.v
 create mode 100644 manual/PRESENTATION_ExOth/axis_test.ys
 create mode 100644 manual/PRESENTATION_ExOth/equiv.ys

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex
index 64c4af721..3f0749cdd 100644
--- a/manual/PRESENTATION_ExOth.tex
+++ b/manual/PRESENTATION_ExOth.tex
@@ -6,11 +6,10 @@
 \end{frame}
 
 \begin{frame}{Overview}
-This section contains 3 subsections:
+This section contains 2 subsections:
 \begin{itemize}
 \item Interactive Design Investigation
 \item Symbolic Model Checking
-\item Reverse Engineering
 \end{itemize}
 \end{frame}
 
@@ -98,25 +97,107 @@ Signal Name                 Dec        Hex                                   Bin
 \subsectionpagesuffix
 \end{frame}
 
-\subsubsection{TBD}
+\begin{frame}{\subsecname}
+Symbolic Model Checking (SMC) is used to formally prove that a circuit has
+(or has not) a given property.
+
+\bigskip
+One appliction is Formal Equivalence Checking: Proving that two circuits
+are identical. For example this is a very useful feature when debugging custom
+passes in Yosys.
+
+\bigskip
+Other applications include checking if a module conforms to interface
+standards.
 
-\begin{frame}{\subsubsecname}
-TBD
+\bigskip
+The {\tt sat} command in Yosys can be used to perform Symbolic Model Checking.
 \end{frame}
 
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\begin{frame}[t]{Example: Formal Equivalence Checking (1/2)}
+Remember the following example? 
+\vskip1em
 
-\subsection{Reverse Engineering}
+\vbox to 0cm{
+\vskip-0.3cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/techmap_01_map.v}
+}\vbox to 0cm{
+\vskip-0.5cm
+\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExSyn/techmap_01.v}
+\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/techmap_01.ys}}
 
-\begin{frame}
-\subsectionpage
-\subsectionpagesuffix
+\vskip5cm\hskip5cm
+Lets see if it is correct..
+\end{frame}
+
+\begin{frame}[t, fragile]{Example: Formal Equivalence Checking (2/2)}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
+# read test design
+read_verilog techmap_01.v
+hierarchy -top test
+
+# create two version of the design: test_orig and test_mapped
+copy test test_orig
+rename test test_mapped
+
+# apply the techmap only to test_mapped
+techmap -map techmap_01_map.v test_mapped
+
+# create a miter circuit to test equivialence
+miter -equiv -make_assert -make_outputs test_orig test_mapped miter
+flatten miter
+
+# run equivialence check
+sat -verify -prove-asserts -show-inputs -show-outputs miter
+\end{lstlisting}
+
+\dots
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
+Solving problem with 945 variables and 2505 clauses..
+SAT proof finished - no model found: SUCCESS!
+\end{lstlisting}
 \end{frame}
 
-\subsubsection{TBD}
+\begin{frame}[t, fragile]{Example: Symbolic Model Checking (1/2)}
+\small
+The following AXI4 Stream Master has a bug. But the bug is not exposed if the
+slave keeps {\tt tready} asserted all the time. (Somtheing a test bench might do.)
 
-\begin{frame}{\subsubsecname}
-TBD
+\medskip
+Symbolic Model Checking can be used to expose the bug and find a sequence
+of values for {\tt tready} that yield the incorrect behavior.
+
+\vskip-1em
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{5pt}{6pt}\selectfont, language=verilog]{PRESENTATION_ExOth/axis_master.v}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{5pt}{6pt}\selectfont, language=verilog]{PRESENTATION_ExOth/axis_test.v}
+\end{columns}
+\end{frame}
+
+\begin{frame}[t, fragile]{Example: Symbolic Model Checking (2/2)}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
+read_verilog -sv axis_master.v axis_test.v
+hierarchy -top axis_test
+
+proc; flatten;;
+sat -seq 50 -prove-asserts
+\end{lstlisting}
+
+\bigskip
+\dots with unmodified {\tt axis\_master.v}:
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
+Solving problem with 159344 variables and 442126 clauses..
+SAT proof finished - model found: FAIL!
+\end{lstlisting}
+
+\bigskip
+\dots with fixed {\tt axis\_master.v}:
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
+Solving problem with 159144 variables and 441626 clauses..
+SAT proof finished - no model found: SUCCESS!
+\end{lstlisting}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -125,10 +206,10 @@ TBD
 
 \begin{frame}{\subsecname}
 \begin{itemize}
-\item TBD
-\item TBD
-\item TBD
-\item TBD
+\item Yosys provides useful features beyond synthesis.
+\item The commands {\tt sat} and {\tt eval} can be used to analyse the behavior of a circuit.
+\item The {\tt sat} command can also be used for symbolic model checking.
+\item This can be useful for debugging and testing designs and Yosys extensions alike.
 \end{itemize}
 
 \bigskip
diff --git a/manual/PRESENTATION_ExOth/Makefile b/manual/PRESENTATION_ExOth/Makefile
index a12beadad..4864d8d52 100644
--- a/manual/PRESENTATION_ExOth/Makefile
+++ b/manual/PRESENTATION_ExOth/Makefile
@@ -1,8 +1,16 @@
 
-all: scrambler_p01.pdf scrambler_p02.pdf
+all: scrambler_p01.pdf scrambler_p02.pdf equiv.log axis_test.log
 
 scrambler_p01.pdf: scrambler.ys scrambler.v
 	../../yosys scrambler.ys
 
 scrambler_p02.pdf: scrambler_p01.pdf
 
+equiv.log: equiv.ys
+	../../yosys -l equiv.log_new equiv.ys
+	mv equiv.log_new equiv.log
+
+axis_test.log: axis_test.ys axis_master.v axis_test.v
+	../../yosys -l axis_test.log_new axis_test.ys
+	mv axis_test.log_new axis_test.log
+
diff --git a/manual/PRESENTATION_ExOth/axis_master.v b/manual/PRESENTATION_ExOth/axis_master.v
new file mode 100644
index 000000000..25a1feee4
--- /dev/null
+++ b/manual/PRESENTATION_ExOth/axis_master.v
@@ -0,0 +1,27 @@
+module axis_master(aclk, aresetn, tvalid, tready, tdata);
+    input aclk, aresetn, tready;
+    output reg tvalid;
+    output reg [7:0] tdata;
+
+    reg [31:0] state;
+    always @(posedge aclk) begin
+        if (!aresetn) begin
+	    state <= 314159265;
+	    tvalid <= 0;
+	    tdata <= 'bx;
+	end else begin
+	    if (tvalid && tready)
+	    	tvalid <= 0;
+	    if (!tvalid || !tready) begin
+	    //             ^- should be not inverted!
+                state = state ^ state << 13;
+                state = state ^ state >> 7;
+                state = state ^ state << 17;
+		if (state[9:8] == 0) begin
+		    tvalid <= 1;
+		    tdata <= state;
+		end
+	    end
+	end
+    end
+endmodule
diff --git a/manual/PRESENTATION_ExOth/axis_test.v b/manual/PRESENTATION_ExOth/axis_test.v
new file mode 100644
index 000000000..0be833f16
--- /dev/null
+++ b/manual/PRESENTATION_ExOth/axis_test.v
@@ -0,0 +1,27 @@
+module axis_test(aclk, tready);
+    input aclk, tready;
+    wire aresetn, tvalid;
+    wire [7:0] tdata;
+
+    integer counter = 0;
+    reg aresetn = 0;
+
+    axis_master uut (aclk, aresetn, tvalid, tready, tdata);
+
+    always @(posedge aclk) begin
+    	if (aresetn && tready && tvalid) begin
+	    if (counter == 0) assert(tdata ==  19);
+	    if (counter == 1) assert(tdata ==  99);
+	    if (counter == 2) assert(tdata ==   1);
+	    if (counter == 3) assert(tdata == 244);
+	    if (counter == 4) assert(tdata == 133);
+	    if (counter == 5) assert(tdata == 209);
+	    if (counter == 6) assert(tdata == 241);
+	    if (counter == 7) assert(tdata == 137);
+	    if (counter == 8) assert(tdata == 176);
+	    if (counter == 9) assert(tdata ==   6);
+	    counter <= counter + 1;
+	end
+	aresetn <= 1;
+    end
+endmodule
diff --git a/manual/PRESENTATION_ExOth/axis_test.ys b/manual/PRESENTATION_ExOth/axis_test.ys
new file mode 100644
index 000000000..19663ac77
--- /dev/null
+++ b/manual/PRESENTATION_ExOth/axis_test.ys
@@ -0,0 +1,5 @@
+read_verilog -sv axis_master.v axis_test.v
+hierarchy -top axis_test
+
+proc; flatten;;
+sat -falsify -seq 50 -prove-asserts
diff --git a/manual/PRESENTATION_ExOth/equiv.ys b/manual/PRESENTATION_ExOth/equiv.ys
new file mode 100644
index 000000000..09a4045db
--- /dev/null
+++ b/manual/PRESENTATION_ExOth/equiv.ys
@@ -0,0 +1,17 @@
+# read test design
+read_verilog ../PRESENTATION_ExSyn/techmap_01.v
+hierarchy -top test
+
+# create two version of the design: test_orig and test_mapped
+copy test test_orig
+rename test test_mapped
+
+# apply the techmap only to test_mapped
+techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
+
+# create a miter circuit to test equivialence
+miter -equiv -make_assert -make_outputs test_orig test_mapped miter
+flatten miter
+
+# run equivialence check
+sat -verify -prove-asserts -show-inputs -show-outputs miter
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index 432ce3688..d1d8abe45 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -346,7 +346,7 @@ Finally the {\tt fsm\_map} command can be used to convert the (optimized) {\tt
 \subsection{The {\tt techmap} command}
 
 \begin{frame}[t]{\subsecname}
-\vbox to 0cm{\includegraphics[width=12cm,trim=-18cm 0cm 0cm -34cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss}
+\vbox to 0cm{\includegraphics[width=12cm,trim=-15cm 0cm 0cm -20cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss}
 \vskip-0.8cm
 The {\tt techmap} command replaces cells with implementations given as
 verilog source. For example implementing a 32 bit adder using 16 bit adders:
diff --git a/manual/PRESENTATION_ExSyn/Makefile b/manual/PRESENTATION_ExSyn/Makefile
index bcff48aad..c34eae3ff 100644
--- a/manual/PRESENTATION_ExSyn/Makefile
+++ b/manual/PRESENTATION_ExSyn/Makefile
@@ -8,7 +8,7 @@ TARGETS += abc_01
 all: $(addsuffix .pdf,$(TARGETS))
 
 define make_pdf_template
-$(1).pdf: $(1).v $(1).ys
+$(1).pdf: $(1)*.v $(1)*.ys
 	../../yosys -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
 endef
 
diff --git a/manual/PRESENTATION_ExSyn/techmap_01_map.v b/manual/PRESENTATION_ExSyn/techmap_01_map.v
index 64c0b87c5..4fd86e854 100644
--- a/manual/PRESENTATION_ExSyn/techmap_01_map.v
+++ b/manual/PRESENTATION_ExSyn/techmap_01_map.v
@@ -13,9 +13,9 @@ output [Y_WIDTH-1:0] Y;
 generate
   if ((A_WIDTH == 32) && (B_WIDTH == 32))
     begin
-      wire [15:0] CARRY = |{A[15:0], B[15:0]} && ~|Y[15:0];
-      assign Y[15:0] = A[15:0] + B[15:0];
-      assign Y[31:16] = A[31:16] + B[31:16] + CARRY;
+      wire [16:0] S1 = A[15:0] + B[15:0];
+      wire [15:0] S2 = A[31:16] + B[31:16] + S1[16];
+      assign Y = {S2[15:0], S1[15:0]};
     end
   else
     wire _TECHMAP_FAIL_ = 1;
-- 
cgit v1.2.3


From 072604f30f58ab535bfd8d004163607900adf86e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 21 Jun 2014 21:13:18 +0200
Subject: fixed typo

---
 manual/PRESENTATION_ExOth.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex
index 3f0749cdd..9e7e9dc7f 100644
--- a/manual/PRESENTATION_ExOth.tex
+++ b/manual/PRESENTATION_ExOth.tex
@@ -161,7 +161,7 @@ SAT proof finished - no model found: SUCCESS!
 \begin{frame}[t, fragile]{Example: Symbolic Model Checking (1/2)}
 \small
 The following AXI4 Stream Master has a bug. But the bug is not exposed if the
-slave keeps {\tt tready} asserted all the time. (Somtheing a test bench might do.)
+slave keeps {\tt tready} asserted all the time. (Something a test bench might do.)
 
 \medskip
 Symbolic Model Checking can be used to expose the bug and find a sequence
-- 
cgit v1.2.3


From a7aea179599045feafcaf26f5ed334a7318a69b4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 22 Jun 2014 12:50:29 +0200
Subject: Progress in presentation

---
 manual/PRESENTATION_Prog.tex           | 440 +++++++++++++++++++++++++++++----
 manual/PRESENTATION_Prog/.gitignore    |   1 +
 manual/PRESENTATION_Prog/Makefile      |  18 ++
 manual/PRESENTATION_Prog/absval_ref.v  |   3 +
 manual/PRESENTATION_Prog/my_cmd.cc     |  78 ++++++
 manual/PRESENTATION_Prog/sigmap_test.v |   3 +
 manual/presentation.sh                 |   2 +
 7 files changed, 503 insertions(+), 42 deletions(-)
 create mode 100644 manual/PRESENTATION_Prog/.gitignore
 create mode 100644 manual/PRESENTATION_Prog/Makefile
 create mode 100644 manual/PRESENTATION_Prog/absval_ref.v
 create mode 100644 manual/PRESENTATION_Prog/my_cmd.cc
 create mode 100644 manual/PRESENTATION_Prog/sigmap_test.v

(limited to 'manual')

diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index 45f0cb0c6..1e7f697b1 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -7,14 +7,6 @@
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-\subsection{Why writing Yosys extensions?}
-
-\begin{frame}{\subsecname}
-TBD
-\end{frame}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
 \subsection{Program Components and Data Formats}
 
 \begin{frame}{\subsecname}
@@ -109,55 +101,293 @@ For simplicity we only discuss this version of RTLIL in this presentation.
 \subsection{Using dump and show commands}
 
 \begin{frame}{\subsecname}
-TBD
+\begin{itemize}
+\item The {\tt dump} command prints the design (or parts of it) in ILANG format. This is
+a text representation of RTLIL.
+
+\bigskip
+\item The {\tt show} command visualizes how the components in the design are connected.
+\end{itemize}
+
+\bigskip
+When trying to understand what a command does, create a small test case and
+look at the output of {\tt dump} and {\tt show} before and after the command
+has been executed.
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-\subsection{The RTLIL::Const Structure}
+\subsection{The RTLIL Data Structures}
 
 \begin{frame}{\subsecname}
-TBD
+The RTLIL data structures are simple structs utilizing C++ {\tt std::}
+containers.
+
+\bigskip
+\begin{itemize}
+\item Most operations are performed directly on the RTLIL structs without
+setter or getter functions.
+
+\bigskip
+\item In debug builds a consistency checker is run over the in-memory design
+between commands to make sure that the RTLIL representation is intact.
+
+\bigskip
+\item Most RTLIL structs have helper methods that perform the most common operations.
+\end{itemize}
+
+\bigskip
+See {\tt yosys/kernel/rtlil.h} for details.
 \end{frame}
 
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{RTLIL::IdString}
 
-\subsection{The RTLIL::SigSpec Structure}
+\begin{frame}{\subsubsecname}{}
+{\tt RTLIL::IdString} is a simple wrapper for {\tt std::string}. It is used for names of RTLIL objects.
 
-\begin{frame}{\subsecname}
-TBD
+\medskip
+The first character of a {\tt RTLIL::IdString} specifies if the name is {\it public\/} or {\it private\/}:
+
+\medskip
+\begin{itemize}
+\item {\tt RTLIL::IdString[0] == '\textbackslash\textbackslash'}: \\
+This is a public name. Usually this means it is a name that was declared in a Verilog file.
+
+\bigskip
+\item {\tt RTLIL::IdString[0] == '\$'}: \\
+This is a private name. It was assigned by Yosys.
+\end{itemize}
+
+\bigskip
+Use the {\tt NEW\_ID} macro to create a new unique private name.
 \end{frame}
 
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{RTLIL::Design and RTLIL::Module}
 
-\subsection{RTLIL::Design, RTLIL::Module}
+\begin{frame}[t, fragile]{\subsubsecname}
+The {\tt RTLIL::Design} and {\tt RTLIL::Module} structs are the top-level RTLIL
+data structures.
 
-\begin{frame}{\subsecname}
-TBD
+Yosys always operates on one active design, but can hold many designs in memory.
+
+\bigskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+struct RTLIL::Design {
+    std::map<RTLIL::IdString, RTLIL::Module*> modules;
+    ...
+};
+
+struct RTLIL::Module {
+    RTLIL::IdString name;
+    std::map<RTLIL::IdString, RTLIL::Wire*> wires;
+    std::map<RTLIL::IdString, RTLIL::Cell*> cells;
+    std::vector<RTLIL::SigSig> connections;
+    ...
+};
+\end{lstlisting}
 \end{frame}
 
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{The RTLIL::Wire Structure}
 
-\subsection{RTLIL::Wire and connections}
+\begin{frame}[t, fragile]{\subsubsecname}
+Each wire in the design is represented by a {\tt RTLIL::Wire} struct:
 
-\begin{frame}{\subsecname}
-TBD
+\medskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+struct RTLIL::Wire {
+    RTLIL::IdString name;
+    int width, start_offset, port_id;
+    bool port_input, port_output;
+    ...
+};
+\end{lstlisting}
+
+\medskip
+\hfil\begin{tabular}{p{3cm}l}
+{\tt width} \dotfill & The total number of bits. E.g. 10 for {\tt [9:0]}. \\
+{\tt start\_offset} \dotfill & The lowest bit index. E.g. 3 for {\tt [5:3]}. \\
+{\tt port\_id} \dotfill & Zero for non-ports. Positive index for ports. \\
+{\tt port\_input} \dotfill & True for {\tt input} and {\tt inout} ports. \\
+{\tt port\_output} \dotfill & True for {\tt output} and {\tt inout} ports. \\
+\end{tabular}
 \end{frame}
 
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{RTLIL::State and RTLIL::Const}
+
+\begin{frame}[t, fragile]{\subsubsecname}
+The {\tt RTLIL::State} enum represents a simple 1-bit logic level:
+
+\smallskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+enum RTLIL::State {
+    S0 = 0,
+    S1 = 1,
+    Sx = 2, // undefined value or conflict
+    Sz = 3, // high-impedance / not-connected
+    Sa = 4, // don't care (used only in cases)
+    Sm = 5  // marker (used internally by some passes)
+};
+\end{lstlisting}
 
-\subsection{RTLIL::Cell}
+\bigskip
+The {\tt RTLIL::Const} struct represents a constant multi-bit value:
+
+\smallskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+struct RTLIL::Const {
+    std::vector<RTLIL::State> bits;
+    ...
+};
+\end{lstlisting}
 
-\begin{frame}{\subsecname}
-TBD
+\bigskip
+Notice that Yosys is not using special {\tt VCC} or {\tt GND} driver cells to represent constants. Instead
+constants are part of the RTLIL representation itself.
+\end{frame}
+
+\subsubsection{The RTLIL::SigSpec Structure}
+
+\begin{frame}[t, fragile]{\subsubsecname}
+The {\tt RTLIL::SigSpec} struct represents a signal vector. Each bit can either be a bit from a wire
+or a constant value. Consecutive bits from a wire or consecutive constant bits are consolidated into
+a {\tt RTLIL::SigChunk}:
+
+\bigskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+struct RTLIL::SigChunk {
+    RTLIL::Wire *wire;
+    RTLIL::Const data; // only used if wire == NULL, LSB at index 0
+    int width, offset;
+    ...
+};
+
+struct RTLIL::SigSpec {
+    std::vector<RTLIL::SigChunk> chunks; // LSB at index 0
+    int width;
+    ...
+};
+\end{lstlisting}
+
+\bigskip
+The {\tt RTLIL::SigSpec} struct has a ton of additional helper methods to compare, analyze, and
+manipulate instances of {\tt RTLIL::SigSpec}.
+\end{frame}
+
+\subsubsection{The RTLIL::Cell Structure}
+
+\begin{frame}[t, fragile]{\subsubsecname (1/2)}
+The {\tt RTLIL::Cell} strcut represents an instance of a module or library cell.
+
+\smallskip
+The ports of the cell
+are associated with {\tt RTLIL::SigSpec} instances and the parameters are associated with {\tt RTLIL::Const}
+instances:
+
+\bigskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+struct RTLIL::Cell {
+    RTLIL::IdString name, type;
+    std::map<RTLIL::IdString, RTLIL::SigSpec> connections;
+    std::map<RTLIL::IdString, RTLIL::Const> parameters;
+    ...
+};
+\end{lstlisting}
+
+\bigskip
+The {\tt type} may refer to another module in the same design, a cell name from a cell library, or a
+cell name from the internal cell library:
+
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
+$not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
+$reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
+$pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $safe_pmux $lut $assert $sr $dff
+$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_INV_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
+$_SR_NP_ $_SR_PN_ $_SR_PP_ $_DFF_N_ $_DFF_P_ $_DFF_NN0_ $_DFF_NN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PN0_
+$_DFF_PN1_ $_DFF_PP0_ $_DFF_PP1_ $_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PNN_
+$_DFFSR_PNP_ $_DFFSR_PPN_ $_DFFSR_PPP_ $_DLATCH_N_ $_DLATCH_P_ $_DLATCHSR_NNN_ $_DLATCHSR_NNP_
+$_DLATCHSR_NPN_ $_DLATCHSR_NPP_ $_DLATCHSR_PNN_ $_DLATCHSR_PNP_ $_DLATCHSR_PPN_ $_DLATCHSR_PPP_
+\end{lstlisting}
+\end{frame}
+
+\begin{frame}[t, fragile]{\subsubsecname (2/2)}
+Simulation models (i.e. {\it documentation\/}) for the internal cell library:
+
+\smallskip
+\hskip2em {\tt yosys/techlibs/common/simlib.v} and \\
+\hskip2em {\tt yosys/techlibs/common/simcells.v}
+
+\bigskip
+The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable
+width. This so-called {\it RTL cells\/} are the cells described in {\tt simlib.v}. 
+
+\bigskip
+The upper-case cell types (such as {\tt \$\_AND\_}) single-bit cells that are not
+parameterized. This so-called {\it internal Logic Gates} are the cells described
+in {\tt simcells.v}.
+
+\bigskip
+The consistency checker also checks the interfaces to the internal cell library.
+If you want to use private cell types for your own purposes, use the {\tt \$\_\_}-prefix
+to avoid name collisions.
+\end{frame}
+
+\subsubsection{Connecting wires or constant drivers}
+
+\begin{frame}[t, fragile]{\subsubsecname}
+Additional connections between wires or between wires and constants are modelled using
+{\tt RTLIL::Module::connections}:
+
+\bigskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+typedef std::pair<RTLIL::SigSpec, RTLIL::SigSpec> RTLIL::SigSig;
+
+struct RTLIL::Module {
+    ...
+    std::vector<RTLIL::SigSig> connections;
+    ...
+};
+\end{lstlisting}
+
+\bigskip
+{\tt RTLIL::SigSig::first} is the driven signal and {\tt RTLIL::SigSig::second} is the driving signal.
+Example usage (setting wire {\tt foo} to value {\tt 42}):
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+module->connections.push_back(RTLIL::SigSig(module->wires.at("\\foo"),
+        RTLIL::SigSpec(42, module->wires.at("\\foo")->width)));
+\end{lstlisting}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Creating modules from scratch}
 
-\begin{frame}{\subsecname}
-TBD
+\begin{frame}[t, fragile]{\subsecname}
+Let's create the following module using the RTLIL API:
+
+\smallskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
+module absval(input signed [3:0] a, output [3:0] y);
+    assign y = a[3] ? -a : a;
+endmodule
+\end{lstlisting}
+
+\smallskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+RTLIL::Module *module = new RTLIL::Module;
+module->name = "\\absval";
+
+RTLIL::Wire *a = module->new_wire(4, "\\a");
+a->port_input = true;
+a->port_id = 1;
+
+RTLIL::Wire *y = module->new_wire(4, "\\y");
+y->port_output = true;
+y->port_id = 2;
+
+RTLIL::Wire *a_inv = module->new_wire(4, NEW_ID);
+module->addNeg(NEW_ID, a, a_inv, true);
+module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y);
+\end{lstlisting}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -165,39 +395,163 @@ TBD
 \subsection{Modifying modules}
 
 \begin{frame}{\subsecname}
-TBD
+Most commands modify existing modules, not create new ones.
+
+When modifying existing modules, stick to the following DOs and DON'Ts:
+
+\begin{itemize}
+\item Do not remove wires. Simply disconnect them and let a successive {\tt clean} command worry about removing it.
+
+\item Use {\tt module->fixup\_ports()} after changing the {\tt port\_*} properties of wires.
+
+\item You can safely remove cells or change the {\tt connetions} property of a cell, but be careful when
+changing the size of the {\tt SigSpec} connected to a cell port.
+
+\item Use the {\tt SigMap} helper class (see next slide) when you need a unique handle for each signal bit.
+\end{itemize}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Using the SigMap helper class}
 
-\begin{frame}{\subsecname}
-TBD
+\begin{frame}[t, fragile]{\subsecname}
+Consider the following module:
+
+\smallskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog]
+module test(input a, output x, y);
+    assign x = a, y = a;
+endmodule
+\end{lstlisting}
+
+In this case {\tt a}, {\tt x}, and {\tt y} are all different names for the same signal. However:
+
+\smallskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")),
+                                           y(module->wires.at("\\y"));
+log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
+\end{lstlisting}
+
+The {\tt SigMap} helper class can be used to map all such aliasing signals to a
+unique signal from the group (usually the wire that is directly driven by a cell or port).
+
+\smallskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+SigMap sigmap(module);
+log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
+                  sigmap(y) == sigmap(a)); // will print "1 1 1"
+\end{lstlisting}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Printing log messages}
 
-\begin{frame}{\subsecname}
-TBD
+\begin{frame}[t, fragile]{\subsecname}
+The {\tt log()} function is a {\tt printf()}-like function that can be used to create log messages.
+
+\medskip
+Use {\tt log\_signal()} to create a C-string for a SigSpec object\footnote[frame]{The pointer returned
+by {\tt log\_signal()} is automatically freed by the log framework at a later time.}:
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+log("Mapped signal x: %s\n", log_signal(sigmap(x)));
+\end{lstlisting}
+
+\medskip
+Use {\tt RTLIL::id2cstr()} to create a C-string for an {\tt RTLIL::IdString}:
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
+\end{lstlisting}
+
+\medskip
+Use {\tt log\_header()} and {\tt log\_push()}/{\tt log\_pop()} to structure log messages:
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+log_header("Doing important stuff!\n");
+log_push();
+for (int i = 0; i < 10; i++)
+    log("Log message #%d.\n", i);
+log_pop();
+\end{lstlisting}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\subsection{Error handling}
+
+\begin{frame}[t, fragile]{\subsecname}
+Use {\tt log\_error()} to report a non-recoverable error:
+
+\medskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+if (design->modules.count(module->name) != 0)
+    log_error("A module with the name %s already exists!\n",
+            RTLIL::id2cstr(module->name));
+\end{lstlisting}
+
+\bigskip
+Use {\tt log\_cmd\_error()} to report a recoverable error:
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+if (design->selection_stack.back().empty())
+    log_cmd_error("This command can't operator on an empty selection!\n");
+\end{lstlisting}
+
+\bigskip
+Use {\tt log\_assert()} and {\tt log\_abort()} instead of {\tt assert()} and {\tt abort()}.
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Creating a command}
 
-\begin{frame}{\subsecname}
-TBD
+\begin{frame}[t, fragile]{\subsecname}
+Simply create a global instance of a class derived from {\tt Pass} to create
+a new yosys command:
+
+\bigskip
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
+#include "kernel/rtlil.h"
+#include "kernel/register.h"
+#include "kernel/log.h"
+
+struct MyPass : public Pass {
+    MyPass() : Pass("my_cmd", "just a simple test") { }
+    virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+    {
+        log("Arguments to my_cmd:\n");
+        for (auto &arg : args)
+            log("  %s\n", arg.c_str());
+
+        log("Modules in current design:\n");
+        for (auto &mod : design->modules)
+            log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
+                    mod.second->wires.size(), mod.second->cells.size());
+    }
+} MyPass;
+\end{lstlisting}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Creating a plugin}
 
-\begin{frame}{\subsecname}
-TBD
+\begin{frame}[fragile]{\subsecname}
+Yosys can be extended by adding additional C++ code to the Yosys code base, or
+by loading plugins into Yosys.
+
+\bigskip
+Use the following command to compile a Yosys plugin:
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
+yosys-config --exec --cxx --cxxflags --ldflags \
+             -o my_cmd.so -shared my_cmd.cc --ldlibs
+\end{lstlisting}
+
+\bigskip
+Load the plugin using the yosys {\tt -m} option:
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
+yosys -m ./my_cmd.so -p 'my_cmd foo bar'
+\end{lstlisting}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -206,10 +560,12 @@ TBD
 
 \begin{frame}{\subsecname}
 \begin{itemize}
-\item TBD
-\item TBD
-\item TBD
-\item TBD
+\item Writing Yosys extensions is very straight-forward.
+\item \dots and even simpler if you don't need RTLIL::Memory or RTLIL::Process objects.
+
+\bigskip
+\item Writing synthesis software? Consider learning the Yosys API and make your stuff
+part of the Yosys framework.
 \end{itemize}
 
 \bigskip
diff --git a/manual/PRESENTATION_Prog/.gitignore b/manual/PRESENTATION_Prog/.gitignore
new file mode 100644
index 000000000..7fd560762
--- /dev/null
+++ b/manual/PRESENTATION_Prog/.gitignore
@@ -0,0 +1 @@
+my_cmd.so
diff --git a/manual/PRESENTATION_Prog/Makefile b/manual/PRESENTATION_Prog/Makefile
new file mode 100644
index 000000000..8da6bcd63
--- /dev/null
+++ b/manual/PRESENTATION_Prog/Makefile
@@ -0,0 +1,18 @@
+
+all: test0.log test1.log test2.log
+
+my_cmd.so: my_cmd.cc
+	../../yosys-config --exec --cxx --cxxflags --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
+
+test0.log: my_cmd.so
+	../../yosys -l test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
+	mv test0.log_new test0.log
+
+test1.log: my_cmd.so
+	../../yosys -l test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
+	mv test1.log_new test1.log
+
+test2.log: my_cmd.so
+	../../yosys -l test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
+	mv test2.log_new test2.log
+
diff --git a/manual/PRESENTATION_Prog/absval_ref.v b/manual/PRESENTATION_Prog/absval_ref.v
new file mode 100644
index 000000000..ca0a115a0
--- /dev/null
+++ b/manual/PRESENTATION_Prog/absval_ref.v
@@ -0,0 +1,3 @@
+module absval_ref(input signed [3:0] a, output [3:0] y);
+    assign y = a[3] ? -a : a;
+endmodule
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
new file mode 100644
index 000000000..cf8a4add8
--- /dev/null
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -0,0 +1,78 @@
+#include "kernel/rtlil.h"
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include "kernel/sigtools.h"
+
+struct MyPass : public Pass {
+    MyPass() : Pass("my_cmd", "just a simple test") { }
+    virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+    {
+        log("Arguments to my_cmd:\n");
+        for (auto &arg : args)
+            log("  %s\n", arg.c_str());
+
+        log("Modules in current design:\n");
+        for (auto &mod : design->modules)
+            log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
+                    mod.second->wires.size(), mod.second->cells.size());
+    }
+} MyPass;
+
+
+struct Test1Pass : public Pass {
+    Test1Pass() : Pass("test1", "creating the absval module") { }
+    virtual void execute(std::vector<std::string>, RTLIL::Design *design)
+    {
+        RTLIL::Module *module = new RTLIL::Module;
+        module->name = "\\absval";
+
+        RTLIL::Wire *a = module->new_wire(4, "\\a");
+        a->port_input = true;
+        a->port_id = 1;
+
+        RTLIL::Wire *y = module->new_wire(4, "\\y");
+        y->port_output = true;
+        y->port_id = 2;
+
+        RTLIL::Wire *a_inv = module->new_wire(4, NEW_ID);
+        module->addNeg(NEW_ID, a, a_inv, true);
+        module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y);
+
+        log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
+
+        if (design->modules.count(module->name) != 0)
+            log_error("A module with the name %s already exists!\n",
+                    RTLIL::id2cstr(module->name));
+
+        design->modules[module->name] = module;
+    }
+} Test1Pass;
+
+
+struct Test2Pass : public Pass {
+    Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
+    virtual void execute(std::vector<std::string>, RTLIL::Design *design)
+    {
+        if (design->selection_stack.back().empty())
+            log_cmd_error("This command can't operator on an empty selection!\n");
+
+        RTLIL::Module *module = design->modules.at("\\test");
+
+        RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")),
+                                                   y(module->wires.at("\\y"));
+        log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
+
+        SigMap sigmap(module);
+        log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
+                          sigmap(y) == sigmap(a)); // will print "1 1 1"
+
+        log("Mapped signal x: %s\n", log_signal(sigmap(x)));
+
+        log_header("Doing important stuff!\n");
+        log_push();
+        for (int i = 0; i < 10; i++)
+            log("Log message #%d.\n", i);
+        log_pop();
+    }
+} Test2Pass;
+
diff --git a/manual/PRESENTATION_Prog/sigmap_test.v b/manual/PRESENTATION_Prog/sigmap_test.v
new file mode 100644
index 000000000..18dcf5eb7
--- /dev/null
+++ b/manual/PRESENTATION_Prog/sigmap_test.v
@@ -0,0 +1,3 @@
+module test(input a, output x, y);
+assign x = a, y = a;
+endmodule
diff --git a/manual/presentation.sh b/manual/presentation.sh
index 6771ba7c9..980e17723 100755
--- a/manual/presentation.sh
+++ b/manual/presentation.sh
@@ -29,6 +29,8 @@ if ! $fast_mode; then
 	make -C PRESENTATION_Intro
 	make -C PRESENTATION_ExSyn
 	make -C PRESENTATION_ExAdv
+	make -C PRESENTATION_ExOth
+	make -C PRESENTATION_Prog
 fi
 
 set -ex
-- 
cgit v1.2.3


From 3e96ce86809fa0a4ea737fa4a9d3e6261f40a191 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 26 Jun 2014 22:05:39 +0200
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv.tex        |   6 +-
 manual/PRESENTATION_ExOth.tex        |   8 +--
 manual/PRESENTATION_ExSyn.tex        |  20 +++----
 manual/PRESENTATION_Intro.tex        | 111 +++++++++++++++++++++--------------
 manual/PRESENTATION_Intro/counter.ys |  11 ++--
 manual/PRESENTATION_Prog.tex         |  24 ++++----
 manual/presentation.tex              |   4 +-
 7 files changed, 105 insertions(+), 79 deletions(-)

(limited to 'manual')

diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 7aa014242..471516b40 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -94,7 +94,7 @@ tool for interactive design investigation.
 \subsubsection{Selecting by object property or type}
 
 \begin{frame}[fragile]{\subsubsecname}
-Special pattern can be used to select by object property or type. For example:
+Special patterns can be used to select by object property or type. For example:
 
 \bigskip
 \begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
@@ -113,7 +113,7 @@ reference to the {\tt select} command.
 \subsubsection{Combining selection}
 
 \begin{frame}[fragile]{\subsubsecname}
-When more than one selection expression is used in one statement they are
+When more than one selection expression is used in one statement, then they are
 pushed on a stack. The final elements on the stack are combined into a union:
 
 \medskip
@@ -169,7 +169,7 @@ See {\tt help select} for full documentation of this expressions.
 \subsubsection{Incremental selection}
 
 \begin{frame}[fragile]{\subsubsecname}
-Sometime a selection can most easily described by a series of add/delete operations.
+Sometimes a selection can most easily be described by a series of add/delete operations.
 The commands {\tt select -add} and {\tt select -del} respectively add or remove objects
 from the current selection instead of overwriting it.
 
diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex
index 9e7e9dc7f..f86dcd7ac 100644
--- a/manual/PRESENTATION_ExOth.tex
+++ b/manual/PRESENTATION_ExOth.tex
@@ -28,7 +28,7 @@ from other tools).
 
 \begin{itemize}
 \item
-The selection mechanism (see slides ``Using Selections''), especially pattern such
+The selection mechanism (see slides ``Using Selections''), especially patterns such
 as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
 are connected.
 
@@ -53,9 +53,9 @@ read_verilog scrambler.v
 hierarchy; proc;;
 
 cd scrambler
-submod -name xorshift32 xs %c %ci %D \
-           %c %ci:+[D] %D %ci*:-$dff \
-           xs %co %ci %d
+submod -name xorshift32 \
+           xs %c %ci %D %c %ci:+[D] %D \
+           %ci*:-$dff xs %co %ci %d
 \end{lstlisting}
 \end{columns}
 
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index d1d8abe45..f68b6f984 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -12,7 +12,7 @@
 \begin{frame}{\subsecname}
 \begin{itemize}
 \item Reading and elaborating the design
-\item High-level synthesis and optimization
+\item Higher-level synthesis and optimization
 \begin{itemize}
 \item Converting {\tt always}-blocks to logic and registers
 \item Perform coarse-grain optimizations (resource sharing, const folding, ...)
@@ -21,7 +21,7 @@
 \end{itemize}
 \item Convert remaining logic to bit-level logic functions
 \item Perform optimizations on bit-level logic functions
-\item Map bit-level logic and register to gates from cell library
+\item Map bit-level logic gates and registers to cell library
 \item Write results to output file 
 \end{itemize}
 \end{frame}
@@ -64,8 +64,8 @@ all needed variations of parametric modules.
 #
 hierarchy
 
-# recommended form. fail if parts of the design hierarchy are missing. remove
-# everything that is unreachable by the top module. mark the top module.
+# recommended form. fails if parts of the design hierarchy are missing, removes
+# everything that is unreachable from the top module, and marks the top module.
 #
 hierarchy -check -top top_module
 \end{lstlisting}
@@ -253,7 +253,7 @@ memory_dff
 # into one multi-port memory cell.
 memory_collect
 
-# this takes the multi-port memory cells and transforms it to address decoder
+# this takes the multi-port memory cell and transforms it to address decoder
 # logic and registers. This step is skipped if "memory" is called with -nomap.
 memory_map
 \end{lstlisting}
@@ -279,7 +279,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
 \end{frame}
 
 \begin{frame}[t, fragile]{\subsecname{} -- Example 2/2}
-\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
+\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -5cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
 \vskip-1cm
 \begin{columns}
 \column[t]{5cm}
@@ -303,11 +303,11 @@ fsm_detect          # unless got option -nodetect
 fsm_extract
 
 fsm_opt
-opt_clean
+clean
 fsm_opt
 
 fsm_expand          # if got option -expand
-opt_clean           # if got option -expand
+clean               # if got option -expand
 fsm_opt             # if got option -expand
 
 fsm_recode          # unless got option -norecode
@@ -366,7 +366,7 @@ When {\tt techmap} is used without a map file, it uses a built-in map file
 to map all RTL cell types to a generic library of built-in logic gates and registers.
 
 \bigskip
-\begin{block}{The build-in logic gate types are:}
+\begin{block}{The built-in logic gate types are:}
 {\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
 \end{block}
 
@@ -496,7 +496,7 @@ the next part (Section 3, ``Advanced Synthesis'') of this presentation.}
 \begin{itemize}
 \item Yosys provides commands for each phase of the synthesis.
 \item Each command solves a (more or less) simple problem.
-\item Complex command are often only front-ends to simple commands.
+\item Complex commands are often only front-ends to simple commands.
 \item {\tt proc; opt; memory; opt; fsm; opt; techmap; opt; abc;;}
 \end{itemize}
 
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 543fb41ed..40b3c2268 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -5,6 +5,7 @@
 \sectionpage
 \end{frame}
 
+\iffalse
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Representations of (digital) Circuits}
@@ -51,6 +52,7 @@
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\fi
 
 \subsection{Levels of Abstraction for Digital Circuits}
 
@@ -74,7 +76,7 @@
 \only<6>{Physical Gate Level}%
 \only<7>{Switch Level}}
 \only<1>{
-	Overall view of the circuit: E.g. block-diagrams or instruction-set architecture descriptions
+	Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions.
 }%
 \only<2>{
 	Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
@@ -94,7 +96,7 @@
 \only<6>{
 	Netlist of cells that actually are available on the target architecture
 	(such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
-	area and/or and/or speed (static timing or number of logic levels).
+	area, power, and/or speed (static timing or number of logic levels).
 }%
 \only<7>{
 	Netlist of individual transistors.
@@ -179,8 +181,8 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 	This scripts contain three types of commands:
 	\begin{itemize}
 	\item {\bf Frontends}, that read input files (usually Verilog).
-	\item {\bf Passes}, that perform transformation on the design in memory.
-	\item {\bf Backends}, that write the design in memory to a file (various formats are available, e.g. Verilog, BLIF, EDIF, SPICE, BTOR, etc.).
+	\item {\bf Passes}, that perform transformations on the design in memory.
+	\item {\bf Backends}, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, \dots).
 	\end{itemize}
 
 	\bigskip
@@ -247,26 +249,23 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-\subsection{Example Problem}
+\subsection{Example Project}
 
-\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
-\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
-\end{columns}
+\begin{frame}[t]{\subsecname}
+The following slides cover an example project. This project contains three files:
+\begin{itemize}
+\item A simple ASIC synthesis script
+\item A digital design written in Verilog
+\item A simple CMOS cell library
+\end{itemize}
+\vfill
+Direct link to the files: \\ \footnotesize
+\url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-\subsection{Example Synthesis Script}
-
-\begin{frame}[t]{\subsecname}
+\begin{frame}[t]{\subsecname{} -- Synthesis Script}
 
 \setbeamercolor{alerted text}{fg=white,bg=red}
 
@@ -283,9 +282,6 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 \medskip
 {\color{YosysGreen}\# mapping to internal cell library}\\
 \boxalert<9>{techmap}; \boxalert<10>{opt}
-
-\bigskip
-\it continued\dots
 \end{minipage}
 \begin{minipage}[t]{5cm}
 \tt\scriptsize
@@ -327,7 +323,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 }%
 \only<2>{
 	Elaborate the design hierarchy. Should always be the first
-	command after reading the design.
+	command after reading the design. Can re-run AST front-end.
 }%
 \only<3>{
 	Convert ``processes'' (the internal representation of behavioral
@@ -373,6 +369,21 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
+\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
+\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
+\end{frame}
+
+\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
+\end{columns}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
 \subsection{Running the Synthesis Script}
 
 \begin{frame}[t, fragile]{\subsecname{} -- Step 1/4}
@@ -410,8 +421,8 @@ abc -liberty mycells.lib
 clean
 \end{verbatim}
 
-\vfill
-\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
+\vfill\hfil
+\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -422,7 +433,7 @@ clean
 Command reference:
 \begin{itemize}
 \item Use ``{\tt help}'' for a command list and ``{\tt help \it command}'' for details.
-\item Or run ``{\tt yosys -H}'' and ``{\tt yosys -h \it command}''.
+\item Or run ``{\tt yosys -H}'' or ``{\tt yosys -h \it command}''.
 \item Or go to \url{http://www.clifford.at/yosys/documentation.html}.
 \end{itemize}
 
@@ -560,7 +571,7 @@ endmodule
 module cam(clk, wr_enable, wr_addr, wr_data, rd_data, rd_addr, rd_match);
     parameter WIDTH = 8;
     parameter DEPTH = 16;
-    localparam ADDR_BITS = $clog2(DEPTH);
+    localparam ADDR_BITS = $clog2(DEPTH-1);
 
     input clk, wr_enable;
     input [ADDR_BITS-1:0] wr_addr;
@@ -595,7 +606,7 @@ Contiously checking the correctness of Yosys and making sure that new features
 do not break old ones is a high priority in Yosys.
 
 \bigskip
-There are two external test suites build for Yosys: VlogHammer and yosys-bigsim
+Two external test suites have been built for Yosys: VlogHammer and yosys-bigsim
 (see next slides)
 
 \bigskip
@@ -608,8 +619,8 @@ the internal state after each command.
 
 \begin{frame}[fragile]{\subsecname{} -- VlogHammer}
 VlogHammer is a Verilog regression test suite developed to test the different
-subsystems in Yosys by comparing them to each other and the implementations
-generated by some proprietary tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
+subsystems in Yosys by comparing them to each other and to the output created
+by some other tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
 
 \bigskip
 Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology mapping,
@@ -624,8 +635,8 @@ assign y11 = (~&(-{(-3'sd3),($unsigned($signed($unsigned({p0,b4,b1}))))}));
 \end{lstlisting}
 
 \bigskip
-Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 20 bugs in
-the proprietary tools used as external reference where found and reported.
+Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 50 bugs in
+the other tools used as external reference where found and reported so far.
 \end{frame}
 
 \begin{frame}{\subsecname{} -- yosys-bigsim}
@@ -634,7 +645,7 @@ benches. yosys-bigsim compares the testbench outpus of simulations of the origin
 Verilog code and synthesis results.
 
 \bigskip
-The following designs are part of yosys-bigsim:
+The following designs are included in yosys-bigsim (excerpt):
 \begin{itemize}
 \item {\tt openmsp430} -- an MSP430 compatible 16 bit CPU
 \item {\tt aes\_5cycle\_2stage} -- an AES encryption core
@@ -651,6 +662,19 @@ The following designs are part of yosys-bigsim:
 
 \subsection{Benefits of Open Source HDL Synthesis}
 
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Cost (also applies to ``free as in free beer'' solutions)
+\item Availablity and Reproducability
+\item Framework- and all-in-one-aspects
+\item Educational Tool
+\end{itemize}
+
+\bigskip
+
+Yosys is open source under the ISC license.
+\end{frame}
+
 \begin{frame}{\subsecname{} -- 1/3}
 \begin{itemize}
 \item Cost (also applies to ``free as in free beer'' solutions): \smallskip\par
@@ -688,14 +712,13 @@ learn a new tool for each of this applications.
 \begin{frame}{\subsecname{} -- 3/3}
 \begin{itemize}
 \item Educational Tool: \smallskip\par
-Propritaery synthesis tools are at times where secretive about their inner
-workings. They often are ``black boxes'' where a design goes in and synthesis
-results come out. Yosys is very open about its internals and it is easy to
-observe the different steps of synthesis.
+Propritaery synthesis tools are at times very secretive about their inner
+workings. They often are ``black boxes''. Yosys is very open about its
+internals and it is easy to observe the different steps of synthesis.
 \end{itemize}
 
 \bigskip
-\begin{block}{BTW: Yosys is licensed under the ISC license:}
+\begin{block}{Yosys is licensed under the ISC license:}
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
 copyright notice and this permission notice appear in all copies.
@@ -743,24 +766,24 @@ but also formal verification, reverse engineering, ...}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-\subsection{What the Yosys project needs from you}
+\subsection{Yosys needs you}
 
 \begin{frame}{\subsecname}
-We need you as an active user:
+\dots as an active user:
 \begin{itemize}
-\item Use Yosys for on your own designs
+\item Use Yosys for on your own projects
 \item .. even if you are not using it as final synthesis tool
 \item Join the discussion on the Subreddit
 \item Report bugs and send in feature requests
 \end{itemize}
 
 \bigskip
-We need you as a developer:
+\dots as a developer:
 \begin{itemize}
-\item Use Yosys as environment for your research work
+\item Use Yosys as environment for your (research) work
 \item .. you might also want to look into ABC for logic-level stuff
 \item Fork the project on github or create loadable plugins
-\item We desperately need a VHDL frontend or a VHDL-to-Verilog converter
+\item We need a VHDL frontend or a good VHDL-to-Verilog converter
 \end{itemize}
 \end{frame}
 
diff --git a/manual/PRESENTATION_Intro/counter.ys b/manual/PRESENTATION_Intro/counter.ys
index bcfe387e4..8b3390ed4 100644
--- a/manual/PRESENTATION_Intro/counter.ys
+++ b/manual/PRESENTATION_Intro/counter.ys
@@ -2,17 +2,18 @@
 read_verilog counter.v
 hierarchy -check -top counter
 
-show -stretch -format pdf -prefix counter_00
+show -notitle -stretch -format pdf -prefix counter_00
 
 # the high-level stuff
 proc; opt; memory; opt; fsm; opt
 
-show -stretch -format pdf -prefix counter_01
+show -notitle -stretch -format pdf -prefix counter_01
 
 # mapping to internal cell library
-techmap; splitnets -ports; opt
+techmap; opt
 
-show -stretch -format pdf -prefix counter_02
+splitnets -ports;;
+show -notitle -stretch -format pdf -prefix counter_02
 
 # mapping flip-flops to mycells.lib
 dfflibmap -liberty mycells.lib
@@ -23,4 +24,4 @@ abc -liberty mycells.lib
 # cleanup
 clean
 
-show -stretch -lib mycells.v -format pdf -prefix counter_03
+show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index 1e7f697b1..21a93d55c 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -1,5 +1,5 @@
 
-\section{Programming Yosys Extensions}
+\section{Writing Yosys extensions in C++}
 
 \begin{frame}
 \sectionpage
@@ -43,8 +43,9 @@
 \subsection{Simplified RTLIL Entity-Relationship Diagram}
 
 \begin{frame}{\subsecname}
-Between passses and frontends/backends the design in stored in Yosys' internal RTLIL (RTL Intermediate Language) format. For
-writing Yosys extensions it is key to understand this format.
+Between passses and frontends/backends the design is stored in Yosys' internal
+RTLIL (RTL Intermediate Language) format. For writing Yosys extensions it is
+key to understand this format.
 
 \bigskip
 \begin{center}
@@ -71,7 +72,8 @@ writing Yosys extensions it is key to understand this format.
 \subsection{RTLIL without memories and processes}
 
 \begin{frame}[fragile]{\subsecname}
-After the command {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are left with a much simpler version of RTLIL:
+After the commands {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are
+left with a much simpler version of RTLIL:
 
 \begin{center}
 \begin{tikzpicture}[scale=0.6, every node/.style={transform shape}]
@@ -85,7 +87,7 @@ After the command {\tt proc} and {\tt memory} (or {\tt memory -nomap}), we are l
 \end{center}
 
 \bigskip
-Many command simply choose to only work on this simpler version:
+Many commands simply choose to only work on this simpler version:
 \begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
 if (module->processes.size() != 0 || module->memories.size() != 0)
     log_error("This command does not operate on modules with processes "
@@ -256,7 +258,7 @@ a {\tt RTLIL::SigChunk}:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
 struct RTLIL::SigChunk {
     RTLIL::Wire *wire;
-    RTLIL::Const data; // only used if wire == NULL, LSB at index 0
+    RTLIL::Const data; // only used if wire == NULL
     int width, offset;
     ...
 };
@@ -276,7 +278,7 @@ manipulate instances of {\tt RTLIL::SigSpec}.
 \subsubsection{The RTLIL::Cell Structure}
 
 \begin{frame}[t, fragile]{\subsubsecname (1/2)}
-The {\tt RTLIL::Cell} strcut represents an instance of a module or library cell.
+The {\tt RTLIL::Cell} struct represents an instance of a module or library cell.
 
 \smallskip
 The ports of the cell
@@ -310,7 +312,7 @@ $_DLATCHSR_NPN_ $_DLATCHSR_NPP_ $_DLATCHSR_PNN_ $_DLATCHSR_PNP_ $_DLATCHSR_PPN_
 \end{frame}
 
 \begin{frame}[t, fragile]{\subsubsecname (2/2)}
-Simulation models (i.e. {\it documentation\/}) for the internal cell library:
+Simulation models (i.e. {\it documentation\/} :-) for the internal cell library:
 
 \smallskip
 \hskip2em {\tt yosys/techlibs/common/simlib.v} and \\
@@ -318,11 +320,11 @@ Simulation models (i.e. {\it documentation\/}) for the internal cell library:
 
 \bigskip
 The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable
-width. This so-called {\it RTL cells\/} are the cells described in {\tt simlib.v}. 
+width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}. 
 
 \bigskip
-The upper-case cell types (such as {\tt \$\_AND\_}) single-bit cells that are not
-parameterized. This so-called {\it internal Logic Gates} are the cells described
+The upper-case cell types (such as {\tt \$\_AND\_}) are single-bit cells that are not
+parameterized. This so-called {\it Internal Logic Gates} are the cells described
 in {\tt simcells.v}.
 
 \bigskip
diff --git a/manual/presentation.tex b/manual/presentation.tex
index 35a409cbe..d098e815f 100644
--- a/manual/presentation.tex
+++ b/manual/presentation.tex
@@ -81,7 +81,7 @@
 
 \title{Yosys Open SYnthesis Suite}
 \author{Clifford Wolf}
-\institute{http://www.clifford.at/}
+\institute{http://www.clifford.at/yosys/}
 
 \usetheme{Madrid}
 \usecolortheme{seagull}
@@ -133,7 +133,7 @@ Outline of this presentation:
 \item Yosys by example: synthesis
 \item Yosys by example: advanced synthesis
 \item Yosys by example: beyond synthesis
-\item Programming Yosys extensions
+\item Writing Yosys extensions in C++
 \end{itemize}
 \end{frame}
 
-- 
cgit v1.2.3


From 3a3f5d5923840f44a6fb30fc7d70b6ed6ad7ccbb Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 29 Jun 2014 09:14:49 +0200
Subject: Progress in presentation

---
 manual/PRESENTATION_Intro.tex | 78 +++++++++++++++++++++++++++++++++++++++++++
 manual/presentation.tex       | 19 +++++++++++
 2 files changed, 97 insertions(+)

(limited to 'manual')

diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 40b3c2268..7697266de 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -599,6 +599,23 @@ endmodule
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
+\subsection{Currently unsupported Verilog-2005 language features}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Multi-dimensional arrays (memories)
+\item Writing to arrays using bit- and part-selects (todo for 0.4.0)
+\item The wor/wand wire types (maybe for 0.4.0)
+\item Tri-state logic
+
+\bigskip
+\item Latched logic (is synthesized as logic with feedback loops)
+\item Some non-synthesizable features that should be ignored in synthesis are not supported by the parser and cause a parser error (file a bug report if you encounter this problem)
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
 \subsection{Verification of Yosys}
 
 \begin{frame}{\subsecname}
@@ -744,6 +761,67 @@ but also formal verification, reverse engineering, ...}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
+\subsection{Projects (that I know of) using Yosys}
+
+\begin{frame}{\subsecname{} -- (1/2)}
+\begin{itemize}
+\item Ongoing PhD project on coarse grain synthesis \\
+{\setlength{\parindent}{0.5cm}\footnotesize
+Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect
+Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
+Architectures. In Jan Haase, editor, \it Models, Methods, and Tools for Complex
+Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp
+201-221. Springer, 2013.}
+
+\bigskip
+\item I know several people that use Yosys simply as Verilog frontend for other
+flows (using either the BLIF and BTOR backends).
+
+\bigskip
+\item I know some analog chip designers that use Yosys for small digital
+control logic because it is simpler than setting up a commercial flow.
+\end{itemize}
+\end{frame}
+
+\begin{frame}{\subsecname{} -- (2/2)}
+\begin{itemize}
+\item Efabless
+\begin{itemize}
+\smallskip \item Not much information on the website (\url{http://efabless.com}) yet.
+\smallskip \item Very cheap 180nm prototyping process (partnering with various fabs)
+\smallskip \item A semiconductor company, NOT an EDA company
+\smallskip \item Web-based design environment
+\smallskip \item HDL Synthesis using Yosys
+\smallskip \item Custom place\&route tool
+
+\bigskip
+\item efabless is building an Open Source IC as reference design. \\
+\hskip1cm (to be announced soon: \url{http://www.openic.io})
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\subsection{Supported Platforms}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Main development OS: Kubuntu 14.04
+\item There is a PPA for ubuntu (not maintained by me)
+\item Any current Debian-based system should work out of the box
+\item When building on other Linux distributions:
+\begin{itemize}
+\item Needs compiler with some C++11 support
+\item Post to the subreddit if you get stuck
+\end{itemize}
+\item Ported to OS X (Darwin) and OpenBSD
+\item No win32 support (yet)
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
 \subsection{Other Open Source Tools}
 
 \begin{frame}{\subsecname}
diff --git a/manual/presentation.tex b/manual/presentation.tex
index d098e815f..a76a1c00b 100644
--- a/manual/presentation.tex
+++ b/manual/presentation.tex
@@ -122,6 +122,25 @@ non-synthesis applications (such as formal equivialence checking) and
 writing extensions to Yosys using the C++ API.
 \end{frame}
 
+\section{About me}
+\begin{frame}{About me}
+Hi! I'm Clifford Wolf.
+
+\bigskip
+I like writing open source software. For example:
+\begin{itemize}
+\item Yosys
+\item OpenSCAD (now maintained by Marius Kintel)
+\item SPL (a not very popular scripting language)
+\item EmbedVM (a very simple colipler+vm for 8 bit micros)
+\item Lib(X)SVF (a library to play SVF/XSVF files over JTAG, used at LHC)
+\item ROCK Linux (inactive since 2010)
+\end{itemize}
+
+\bigskip
+What do I do for a living? Ask me off the record..
+\end{frame}
+
 \section{Outline}
 \begin{frame}{Outline}
 Yosys is an Open Source Verilog synthesis tool, and more.
-- 
cgit v1.2.3


From d26561cc44d90bd83a7c55d5270bf4cbade0a8f7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 29 Jun 2014 09:27:03 +0200
Subject: Tiny fix in presentation

---
 manual/presentation.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual')

diff --git a/manual/presentation.tex b/manual/presentation.tex
index a76a1c00b..cad9e9f15 100644
--- a/manual/presentation.tex
+++ b/manual/presentation.tex
@@ -102,7 +102,7 @@
 \titlepage
 \end{frame}
 
-\setcounter{section}{-2}
+\setcounter{section}{-3}
 
 \section{Abstract}
 \begin{frame}{Abstract}
-- 
cgit v1.2.3


From 1c81ab49e7b57f4c64e533a3617fe8bbe257cdb5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 2 Jul 2014 06:16:31 +0200
Subject: small changes in presentation

---
 manual/presentation.tex | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'manual')

diff --git a/manual/presentation.tex b/manual/presentation.tex
index cad9e9f15..9a876de0c 100644
--- a/manual/presentation.tex
+++ b/manual/presentation.tex
@@ -132,13 +132,10 @@ I like writing open source software. For example:
 \item Yosys
 \item OpenSCAD (now maintained by Marius Kintel)
 \item SPL (a not very popular scripting language)
-\item EmbedVM (a very simple colipler+vm for 8 bit micros)
+\item EmbedVM (a very simple compiler+vm for 8 bit micros)
 \item Lib(X)SVF (a library to play SVF/XSVF files over JTAG, used at LHC)
-\item ROCK Linux (inactive since 2010)
+\item ROCK Linux (discontinued since 2010)
 \end{itemize}
-
-\bigskip
-What do I do for a living? Ask me off the record..
 \end{frame}
 
 \section{Outline}
-- 
cgit v1.2.3


From 73e0e13d2f1b959a05d69ed715c8fdde84894d6f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 16 Jul 2014 11:38:02 +0200
Subject: Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal

---
 manual/CHAPTER_CellLib.tex | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index e7895521a..f09c49298 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -256,8 +256,9 @@ If this parameter is set to {\tt 1'b1}, a read and write to the same address in
 return the new value. Otherwise the old value is returned.
 \end{itemize}
 
-The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN}, an address input \B{ADDR}
-and a data input \B{DATA}. They also have the following parameters:
+The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN} (one
+enable bit for each data bit), an address input \B{ADDR} and a data input
+\B{DATA}. They also have the following parameters:
 
 \begin{itemize}
 \item \B{MEMID} \\
@@ -341,7 +342,7 @@ This input is \B{RD\_PORTS}*\B{WIDTH} bits wide, containing all data signals for
 This input is \B{WR\_PORTS} bits wide, containing all clock signals for the write ports.
 
 \item \B{WR\_EN} \\
-This input is \B{WR\_PORTS} bits wide, containing all enable signals for the write ports.
+This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all enable signals for the write ports.
 
 \item \B{WR\_ADDR} \\
 This input is \B{WR\_PORTS}*\B{ABITS} bits wide, containing all address signals for the write ports.
-- 
cgit v1.2.3


From a62c21c9c64ad5b3e0dae5d4ee4857425f73068e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 23 Jul 2014 16:09:27 +0200
Subject: Removed RTLIL::SigSpec::expand() method

---
 manual/CHAPTER_Prog/stubnets.cc | 19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 1c71f78b8..efb3ca958 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -21,7 +21,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 	SigMap sigmap(module);
 
 	// count how many times a single-bit signal is used
-	std::map<RTLIL::SigSpec, int> bit_usage_count;
+	std::map<RTLIL::SigBit, int> bit_usage_count;
 
 	// count ouput lines for this module (needed only for summary output at the end)
 	int line_count = 0;
@@ -36,13 +36,10 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 		// (use sigmap to get a uniqe signal name)
 		RTLIL::SigSpec sig = sigmap(conn.second);
 
-		// split the signal up into single-bit chunks
-		sig.expand();
-
-		// add each chunk to bit_usage_count, unless it is a constant
-		for (auto &c : sig.chunks)
-			if (c.wire != NULL)
-				bit_usage_count[c]++;
+		// add each bit to bit_usage_count, unless it is a constant
+		for (auto &bit : sig)
+			if (bit.wire != NULL)
+				bit_usage_count[bit]++;
 	}
 
 	// for each wire in the module
@@ -62,13 +59,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 
 		// get a signal description for this wire and split it into seperate bits
 		RTLIL::SigSpec sig = sigmap(wire);
-		sig.expand();
 
 		// for each bit (unless it is a constant):
 		// check if it is used at least two times and add to stub_bits otherwise
-		for (size_t i = 0; i < sig.chunks.size(); i++)
-			if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] +
-					usage_offset) < 2)
+		for (size_t i = 0; i < SIZE(sig); i++)
+			if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
 				stub_bits.insert(i);
 
 		// continue if no stub bits found
-- 
cgit v1.2.3


From 3ec785b881a7bbceb5ac4db1e761b75c07f8642a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 23 Jul 2014 19:36:43 +0200
Subject: Fixed manual/CHAPTER_Prog/stubnets.cc

---
 manual/CHAPTER_Prog/stubnets.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index efb3ca958..3f8d553ad 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -62,7 +62,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 
 		// for each bit (unless it is a constant):
 		// check if it is used at least two times and add to stub_bits otherwise
-		for (size_t i = 0; i < SIZE(sig); i++)
+		for (int i = 0; i < SIZE(sig); i++)
 			if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
 				stub_bits.insert(i);
 
@@ -72,7 +72,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 
 		// report stub bits and/or stub wires, don't report single bits
 		// if called with report_bits set to false.
-		if (int(stub_bits.size()) == sig.width) {
+		if (SIZE(stub_bits) == SIZE(sig)) {
 			log("  found stub wire: %s\n", RTLIL::id2cstr(wire->name));
 		} else {
 			if (!report_bits)
-- 
cgit v1.2.3


From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 11:58:03 +0200
Subject: Renamed RTLIL::{Module,Cell}::connections to connections_

---
 manual/CHAPTER_Prog/stubnets.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 3f8d553ad..f6c1528ee 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -30,7 +30,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 
 	// For all ports on all cells
 	for (auto &cell_iter : module->cells)
-	for (auto &conn : cell_iter.second->connections)
+	for (auto &conn : cell_iter.second->connections_)
 	{
 		// Get the signals on the port
 		// (use sigmap to get a uniqe signal name)
-- 
cgit v1.2.3


From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 14:32:50 +0200
Subject: Changed users of cell->connections_ to the new API (sed command)

git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
---
 manual/CHAPTER_Prog/stubnets.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index f6c1528ee..f67ffe1e8 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -30,7 +30,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 
 	// For all ports on all cells
 	for (auto &cell_iter : module->cells)
-	for (auto &conn : cell_iter.second->connections_)
+	for (auto &conn : cell_iter.second->connections())
 	{
 		// Get the signals on the port
 		// (use sigmap to get a uniqe signal name)
-- 
cgit v1.2.3


From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 01:49:51 +0200
Subject: Refactoring: Renamed RTLIL::Module::wires to wires_

---
 manual/CHAPTER_Prog/stubnets.cc    | 2 +-
 manual/PRESENTATION_Prog/my_cmd.cc | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index f67ffe1e8..9eacfbcb5 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -43,7 +43,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 	}
 
 	// for each wire in the module
-	for (auto &wire_iter : module->wires)
+	for (auto &wire_iter : module->wires_)
 	{
 		RTLIL::Wire *wire = wire_iter.second;
 
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index cf8a4add8..0cd1da808 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -14,7 +14,7 @@ struct MyPass : public Pass {
         log("Modules in current design:\n");
         for (auto &mod : design->modules)
             log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
-                    mod.second->wires.size(), mod.second->cells.size());
+                    mod.second->wires_.size(), mod.second->cells.size());
     }
 } MyPass;
 
@@ -58,8 +58,8 @@ struct Test2Pass : public Pass {
 
         RTLIL::Module *module = design->modules.at("\\test");
 
-        RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")),
-                                                   y(module->wires.at("\\y"));
+        RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
+                                                   y(module->wires_.at("\\y"));
         log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
 
         SigMap sigmap(module);
-- 
cgit v1.2.3


From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 01:51:45 +0200
Subject: Refactoring: Renamed RTLIL::Module::cells to cells_

---
 manual/CHAPTER_Prog/stubnets.cc    | 2 +-
 manual/PRESENTATION_Prog/my_cmd.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 9eacfbcb5..a57907435 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -29,7 +29,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 	log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
 
 	// For all ports on all cells
-	for (auto &cell_iter : module->cells)
+	for (auto &cell_iter : module->cells_)
 	for (auto &conn : cell_iter.second->connections())
 	{
 		// Get the signals on the port
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index 0cd1da808..c724ce375 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -14,7 +14,7 @@ struct MyPass : public Pass {
         log("Modules in current design:\n");
         for (auto &mod : design->modules)
             log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
-                    mod.second->wires_.size(), mod.second->cells.size());
+                    mod.second->wires_.size(), mod.second->cells_.size());
     }
 } MyPass;
 
-- 
cgit v1.2.3


From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 10:18:00 +0200
Subject: Refactoring: Renamed RTLIL::Design::modules to modules_

---
 manual/CHAPTER_Prog/stubnets.cc    | 2 +-
 manual/PRESENTATION_Prog/my_cmd.cc | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index a57907435..4d1452c97 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -120,7 +120,7 @@ struct StubnetsPass : public Pass {
 
 		// call find_stub_nets() for each module that is either
 		// selected as a whole or contains selected objects.
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 			if (design->selected_module(it.first))
 				find_stub_nets(design, it.second, report_bits);
 	}
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index c724ce375..8dc72c750 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -12,7 +12,7 @@ struct MyPass : public Pass {
             log("  %s\n", arg.c_str());
 
         log("Modules in current design:\n");
-        for (auto &mod : design->modules)
+        for (auto &mod : design->modules_)
             log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
                     mod.second->wires_.size(), mod.second->cells_.size());
     }
@@ -40,11 +40,11 @@ struct Test1Pass : public Pass {
 
         log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
 
-        if (design->modules.count(module->name) != 0)
+        if (design->modules_.count(module->name) != 0)
             log_error("A module with the name %s already exists!\n",
                     RTLIL::id2cstr(module->name));
 
-        design->modules[module->name] = module;
+        design->modules_[module->name] = module;
     }
 } Test1Pass;
 
@@ -56,7 +56,7 @@ struct Test2Pass : public Pass {
         if (design->selection_stack.back().empty())
             log_cmd_error("This command can't operator on an empty selection!\n");
 
-        RTLIL::Module *module = design->modules.at("\\test");
+        RTLIL::Module *module = design->modules_.at("\\test");
 
         RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
                                                    y(module->wires_.at("\\y"));
-- 
cgit v1.2.3


From 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 02:32:00 +0200
Subject: Renamed "stdcells.v" to "techmap.v"

---
 manual/CHAPTER_Techmap.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex
index be74c3567..26632d0b5 100644
--- a/manual/CHAPTER_Techmap.tex
+++ b/manual/CHAPTER_Techmap.tex
@@ -27,7 +27,7 @@ cells with the provided implementation.
 
 When no map file is provided, {\tt techmap} uses a built-in map file that
 maps the Yosys RTL cell types to the internal gate library used by Yosys.
-The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in
+The curious reader may find this map file as {\tt techlibs/common/techmap.v} in
 the Yosys source tree.
 
 Additional features have been added to {\tt techmap} to allow for conditional
-- 
cgit v1.2.3


From e6d33513a5b809facc6e3e5e75d2248bfa94f82b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 14:11:39 +0200
Subject: Added module->design and cell->module, wire->module pointers

---
 manual/PRESENTATION_Prog/Makefile  |  6 +++---
 manual/PRESENTATION_Prog/my_cmd.cc | 35 ++++++++++++++---------------------
 2 files changed, 17 insertions(+), 24 deletions(-)

(limited to 'manual')

diff --git a/manual/PRESENTATION_Prog/Makefile b/manual/PRESENTATION_Prog/Makefile
index 8da6bcd63..794f5c12c 100644
--- a/manual/PRESENTATION_Prog/Makefile
+++ b/manual/PRESENTATION_Prog/Makefile
@@ -5,14 +5,14 @@ my_cmd.so: my_cmd.cc
 	../../yosys-config --exec --cxx --cxxflags --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
 
 test0.log: my_cmd.so
-	../../yosys -l test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
+	../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
 	mv test0.log_new test0.log
 
 test1.log: my_cmd.so
-	../../yosys -l test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
+	../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
 	mv test1.log_new test1.log
 
 test2.log: my_cmd.so
-	../../yosys -l test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
+	../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
 	mv test2.log_new test2.log
 
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index 8dc72c750..381b05871 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -1,6 +1,4 @@
-#include "kernel/rtlil.h"
-#include "kernel/register.h"
-#include "kernel/log.h"
+#include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 
 struct MyPass : public Pass {
@@ -12,9 +10,9 @@ struct MyPass : public Pass {
             log("  %s\n", arg.c_str());
 
         log("Modules in current design:\n");
-        for (auto &mod : design->modules_)
-            log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
-                    mod.second->wires_.size(), mod.second->cells_.size());
+        for (auto mod : design->modules())
+            log("  %s (%zd wires, %zd cells)\n", log_id(mod),
+                    SIZE(mod->wires()), SIZE(mod->cells()));
     }
 } MyPass;
 
@@ -23,28 +21,24 @@ struct Test1Pass : public Pass {
     Test1Pass() : Pass("test1", "creating the absval module") { }
     virtual void execute(std::vector<std::string>, RTLIL::Design *design)
     {
-        RTLIL::Module *module = new RTLIL::Module;
-        module->name = "\\absval";
+        if (design->has("\\absval") != 0)
+            log_error("A module with the name absval already exists!\n");
 
-        RTLIL::Wire *a = module->new_wire(4, "\\a");
+        RTLIL::Module *module = design->addModule("\\absval");
+
+        RTLIL::Wire *a = module->addWire("\\a", 4);
         a->port_input = true;
         a->port_id = 1;
 
-        RTLIL::Wire *y = module->new_wire(4, "\\y");
+        RTLIL::Wire *y = module->addWire("\\y", 4);
         y->port_output = true;
         y->port_id = 2;
 
-        RTLIL::Wire *a_inv = module->new_wire(4, NEW_ID);
+        RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
         module->addNeg(NEW_ID, a, a_inv, true);
-        module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y);
-
-        log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
-
-        if (design->modules_.count(module->name) != 0)
-            log_error("A module with the name %s already exists!\n",
-                    RTLIL::id2cstr(module->name));
+        module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
 
-        design->modules_[module->name] = module;
+        log("Name of this module: %s\n", log_id(module));
     }
 } Test1Pass;
 
@@ -58,8 +52,7 @@ struct Test2Pass : public Pass {
 
         RTLIL::Module *module = design->modules_.at("\\test");
 
-        RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
-                                                   y(module->wires_.at("\\y"));
+        RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")), y(module->wire("\\y"));
         log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
 
         SigMap sigmap(module);
-- 
cgit v1.2.3


From bd74ed7da467de11128c57c4c424febe4a7e2f39 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 1 Aug 2014 19:01:10 +0200
Subject: Replaced sha1 implementation

---
 manual/CHAPTER_Auxlibs.tex | 6 +++---
 manual/weblinks.bib        | 6 ------
 2 files changed, 3 insertions(+), 9 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Auxlibs.tex b/manual/CHAPTER_Auxlibs.tex
index 0726e031f..8d3ed7430 100644
--- a/manual/CHAPTER_Auxlibs.tex
+++ b/manual/CHAPTER_Auxlibs.tex
@@ -6,9 +6,9 @@ with Yosys.
 
 \section{SHA1}
 
-The files in {\tt libs/sha1/} provide a SHA1 implementation written by Micael
-Hildenborg \citeweblink{smallsha1}. It is used for generating unique names when
-specializing parameterized modules.
+The files in {\tt libs/sha1/} provide a public domain SHA1 implementation written
+by Steve Reid, Bruce Guenter, and Volker Grabsch. It is used for generating
+unique names when specializing parameterized modules.
 
 \section{BigInt}
 
diff --git a/manual/weblinks.bib b/manual/weblinks.bib
index 9b6032edb..5215a6ca3 100644
--- a/manual/weblinks.bib
+++ b/manual/weblinks.bib
@@ -132,9 +132,3 @@
 	note = {\url{http://mattmccutchen.net/bigint/}}
 }
 
-@misc{smallsha1,
-	author = {Micael Hildenborg},
-	title = {{smallsha1}},
-	note = {\url{https://code.google.com/p/smallsha1/}}
-}
-
-- 
cgit v1.2.3


From 13f2f36884fa3e4a8329dab2556af7000cb085df Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Aug 2014 11:39:46 +0200
Subject: RIP $safe_pmux

---
 manual/PRESENTATION_Prog.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual')

diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index 21a93d55c..3b2145444 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -302,7 +302,7 @@ cell name from the internal cell library:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
 $not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
 $reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
-$pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $safe_pmux $lut $assert $sr $dff
+$pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
 $dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_INV_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
 $_SR_NP_ $_SR_PN_ $_SR_PP_ $_DFF_N_ $_DFF_P_ $_DFF_NN0_ $_DFF_NN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PN0_
 $_DFF_PN1_ $_DFF_PP0_ $_DFF_PP1_ $_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PNN_
-- 
cgit v1.2.3


From bf486002d9a6d976b3d086700ccdcfb0fb70ba0b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Aug 2014 14:04:35 +0200
Subject: Removed old doc references to $safe_pmux

---
 manual/CHAPTER_CellLib.tex  | 4 ----
 manual/CHAPTER_Optimize.tex | 2 +-
 2 files changed, 1 insertion(+), 5 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index f09c49298..f05c1b7ad 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -125,10 +125,6 @@ than one bit from \B{S} is set the output is undefined. Cells of this type are u
 ``parallel cases'' (defined by using the {\tt parallel\_case} attribute or detected by
 an optimization).
 
-The {\tt \$safe\_pmux} behaves similarly to the {\tt \$pmux} cell type. But when more than one bit
-of \B{S} is set, it is guaranteed that this cell type will output the value of the \B{A} input instead of
-an undefined value.
-
 Behavioural code with cascaded {\tt if-then-else}- and {\tt case}-statements
 usually results in trees of multiplexer cells. Many passes (from various
 optimizations to FSM extraction) heavily depend on these multiplexer trees to
diff --git a/manual/CHAPTER_Optimize.tex b/manual/CHAPTER_Optimize.tex
index c562650b8..af8e22497 100644
--- a/manual/CHAPTER_Optimize.tex
+++ b/manual/CHAPTER_Optimize.tex
@@ -136,7 +136,7 @@ This pass performs trivial resource sharing. This means that this pass identifie
 with identical inputs and replaces them with a single instance of the cell.
 
 The option {\tt -nomux} can be used to disable resource sharing for multiplexer
-cells ({\tt \$mux}, {\tt \$pmux}, and {\tt \$safe\_pmux}). This can be useful as
+cells ({\tt \$mux} and {\tt \$pmux}. This can be useful as
 it prevents multiplexer trees to be merged, which might prevent {\tt opt\_muxtree}
 to identify possible optimizations.
 
-- 
cgit v1.2.3


From f092b5014895dc5dc62b8103fcedf94cfa9f85a8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Aug 2014 14:11:40 +0200
Subject: Renamed $_INV_ cell type to $_NOT_

---
 manual/CHAPTER_CellLib.tex                  | 4 ++--
 manual/CHAPTER_StateOfTheArt/simlib_yosys.v | 4 ++--
 manual/PRESENTATION_ExSyn.tex               | 2 +-
 manual/PRESENTATION_Prog.tex                | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index f05c1b7ad..ea4ae8d40 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -371,7 +371,7 @@ source tree.
 \begin{tabular}[t]{ll}
 Verilog & Cell Type \\
 \hline
-\lstinline[language=Verilog]; Y = ~A;    & {\tt \$\_INV\_} \\
+\lstinline[language=Verilog]; Y = ~A;    & {\tt \$\_NOT\_} \\
 \lstinline[language=Verilog]; Y = A & B; & {\tt \$\_AND\_} \\
 \lstinline[language=Verilog]; Y = A | B; & {\tt \$\_OR\_} \\
 \lstinline[language=Verilog]; Y = A ^ B; & {\tt \$\_XOR\_} \\
@@ -398,7 +398,7 @@ $ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\
 \end{table}
 
 Table~\ref{tab:CellLib_gates} lists all cell types used for gate level logic. The cell types
-{\tt \$\_INV\_}, {\tt \$\_AND\_}, {\tt \$\_OR\_}, {\tt \$\_XOR\_} and {\tt \$\_MUX\_}
+{\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_OR\_}, {\tt \$\_XOR\_} and {\tt \$\_MUX\_}
 are used to model combinatorial logic. The cell types {\tt \$\_DFF\_N\_} and {\tt \$\_DFF\_P\_}
 represent d-type flip-flops.
 
diff --git a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
index a2df8f648..54c076614 100644
--- a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
+++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
@@ -20,12 +20,12 @@
  *  The internal logic cell simulation library.
  *
  *  This verilog library contains simple simulation models for the internal
- *  logic cells (_INV_, _AND_, ...) that are generated by the default technology
+ *  logic cells (_NOT_, _AND_, ...) that are generated by the default technology
  *  mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
  *
  */
 
-module _INV_(A, Y);
+module _NOT_(A, Y);
 input A;
 output Y;
 assign Y = ~A;
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index f68b6f984..803982295 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -367,7 +367,7 @@ to map all RTL cell types to a generic library of built-in logic gates and regis
 
 \bigskip
 \begin{block}{The built-in logic gate types are:}
-{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
+{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
 \end{block}
 
 \bigskip
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index 3b2145444..4e9f4b21e 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -303,7 +303,7 @@ cell name from the internal cell library:
 $not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
 $reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
 $pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
-$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_INV_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
+$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
 $_SR_NP_ $_SR_PN_ $_SR_PP_ $_DFF_N_ $_DFF_P_ $_DFF_NN0_ $_DFF_NN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PN0_
 $_DFF_PN1_ $_DFF_PP0_ $_DFF_PP1_ $_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PNN_
 $_DFFSR_PNP_ $_DFFSR_PPN_ $_DFFSR_PPP_ $_DLATCH_N_ $_DLATCH_P_ $_DLATCHSR_NNN_ $_DLATCHSR_NNP_
-- 
cgit v1.2.3


From 47c2637a961839f1eb1a0386f7e54d94be50bc10 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 16 Aug 2014 18:18:30 +0200
Subject: Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_
 $_AOI4_ $_OAI4_

---
 manual/CHAPTER_CellLib.tex | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'manual')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index ea4ae8d40..3eb2f9469 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -430,3 +430,7 @@ Add information about {\tt \$assert} cells.
 Add information about {\tt \$slice} and {\tt \$concat} cells.
 \end{fixme}
 
+\begin{fixme}
+Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
+\end{fixme}
+
-- 
cgit v1.2.3


From 4724d94fbce587b39cd7343dc8de3b859311f55c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 30 Aug 2014 18:59:05 +0200
Subject: Added $alu cell type

---
 manual/CHAPTER_CellLib.tex | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'manual')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 3eb2f9469..82473f6a2 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -430,6 +430,10 @@ Add information about {\tt \$assert} cells.
 Add information about {\tt \$slice} and {\tt \$concat} cells.
 \end{fixme}
 
+\begin{fixme}
+Add information about {\tt \$alu} cells.
+\end{fixme}
+
 \begin{fixme}
 Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
 \end{fixme}
-- 
cgit v1.2.3


From 37fe7c7bdfd65071311049ce4287ef235797096e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 2 Sep 2014 04:03:06 +0200
Subject: Removed references to yosys-svgviewer from docs

---
 manual/APPNOTE_011_Design_Investigation.tex | 24 ++++++++++--------------
 manual/CHAPTER_Auxprogs.tex                 |  7 -------
 2 files changed, 10 insertions(+), 21 deletions(-)

(limited to 'manual')

diff --git a/manual/APPNOTE_011_Design_Investigation.tex b/manual/APPNOTE_011_Design_Investigation.tex
index c04811864..504ab7ec6 100644
--- a/manual/APPNOTE_011_Design_Investigation.tex
+++ b/manual/APPNOTE_011_Design_Investigation.tex
@@ -54,7 +54,7 @@
 \begin{document}
 
 \title{Yosys Application Note 011: \\ Interactive Design Investigation}
-\author{Clifford Wolf \\ December 2013}
+\author{Clifford Wolf \\ Original Verision December 2013}
 \maketitle
 
 \begin{abstract}
@@ -74,9 +74,7 @@ commands for evaluating circuits and solving SAT problems.
 This Application Note is based on the Yosys \cite{yosys} GIT Rev. {\tt 2b90ba1} from
 2013-12-08. The {\tt README} file covers how to install Yosys. The
 {\tt show} command requires a working installation of GraphViz \cite{graphviz}
-for generating the actual circuit diagrams. Yosys must be build with Qt
-support for the built-in SVG viewer. Alternatively an external viewer can be
-used, if Qt is not available.
+and \cite{xdot} for generating the actual circuit diagrams.
 
 \section{Overview}
 
@@ -131,8 +129,8 @@ The {\tt show} command generates a circuit diagram for the design in its
 current state. Various options can be used to change the appearance of the
 circuit diagram, set the name and format for the output file, and so forth.
 When called without any special options, it saves the circuit diagram in
-a temporary file and launches {\tt yosys-svgviewer} to display the diagram.
-Subsequent calls to {\tt show} re-use the {\tt yosys-svgviewer} instance
+a temporary file and launches {\tt xdot} to display the diagram.
+Subsequent calls to {\tt show} re-use the {\tt xdot} instance
 (if still running).
 
 \subsection{A simple circuit}
@@ -270,18 +268,12 @@ command only operates on interior signals.
 
 \subsection{Miscellaneous notes}
 
-Per default the {\tt show} command outputs a temporary SVG file and launches
-{\tt yosys-svgviewer} to display it. The options {\tt -format}, {\tt -viewer}
+Per default the {\tt show} command outputs a temporary {\tt dot} file and launches
+{\tt xdot} to display it. The options {\tt -format}, {\tt -viewer}
 and {\tt -prefix} can be used to change format, viewer and filename prefix.
 Note that the {\tt pdf} and {\tt ps} format are the only formats that support
 plotting multiple modules in one run.
 
-In {\tt yosys-svgviewer} the left mouse button is per default bound to move the
-diagram (and the mouse wheel can be used for zooming in and out). However, in
-some cases one wants to copy text from the diagram. In this cases the
-View->Interactive checkbox must be activated. This switches the rendering back-end
-in a mode that supports interaction with the SVG file, such as selecting text.
-
 In densely connected circuits it is sometimes hard to keep track of the
 individual signal wires. For this cases it can be useful to call {\tt show}
 with the {\tt -colors <integer>} argument, which randomly assigns colors to the
@@ -1056,6 +1048,10 @@ Clifford Wolf. The Yosys Open SYnthesis Suite.
 Graphviz - Graph Visualization Software.
 \url{http://www.graphviz.org/}
 
+\bibitem{xdot}
+xdot.py - an interactive viewer for graphs written in Graphviz's dot language.
+\url{https://github.com/jrfonseca/xdot.py}
+
 \bibitem{CircuitSAT}
 {\it Circuit satisfiability problem} on Wikipedia
 \url{http://en.wikipedia.org/wiki/Circuit_satisfiability}
diff --git a/manual/CHAPTER_Auxprogs.tex b/manual/CHAPTER_Auxprogs.tex
index eefd36970..cce3741c2 100644
--- a/manual/CHAPTER_Auxprogs.tex
+++ b/manual/CHAPTER_Auxprogs.tex
@@ -17,10 +17,3 @@ The {\tt yosys-filterlib} tool is a small utility that can be used to strip
 or extract information from a Liberty file. See Sec.~\ref{sec:techmap_extern}
 for details.
 
-\section{yosys-svgviewer}
-
-The {\tt yosys-svgviewer} tool is a small Qt program that can be used to view
-SVG files. This tool is automatically launched by the {\tt show} command when
-no {\tt -format} and no {\tt -viewer} option is passed to the command. See
-{\tt help show} or Sec.~\ref{cmd:show} for details.
-
-- 
cgit v1.2.3


From 8927aa6148f5575b2da9bfb76afb4af076fe18f3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 4 Sep 2014 02:07:52 +0200
Subject: Removed $bu0 cell type

---
 manual/CHAPTER_CellLib.tex          | 6 ------
 manual/PRESENTATION_Prog.tex        | 2 +-
 manual/command-reference-manual.tex | 2 +-
 3 files changed, 2 insertions(+), 8 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 82473f6a2..5045960cb 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -97,12 +97,6 @@ The width of the output port \B{Y}.
 
 Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators.
 
-The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always
-extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments
-with {\tt x}-bits if the most significant bit is {\tt x}.) This is used
-internally to correctly implement the {\tt ==} and {\tt !=} operators for
-constant arguments.
-
 \subsection{Multiplexers}
 
 Multiplexers are generated by the Verilog HDL frontend for {\tt
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index 4e9f4b21e..590451be0 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -300,7 +300,7 @@ The {\tt type} may refer to another module in the same design, a cell name from
 cell name from the internal cell library:
 
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
-$not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
+$not $pos $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
 $reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
 $pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
 $dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 54fec542a..9d9665c1e 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -1204,7 +1204,7 @@ unless another prefix is specified using -prefix <prefix>.
 This pass maps a small selection of simple coarse-grain cells to yosys gate
 primitives. The following internal cell types are mapped by this pass:
 
-  $not, $pos, $bu0, $and, $or, $xor, $xnor
+  $not, $pos, $and, $or, $xor, $xnor
   $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
   $logic_not, $logic_and, $logic_or, $mux
   $sr, $dff, $dffsr, $adff, $dlatch
-- 
cgit v1.2.3


From 79cbf9067c07ed810b3466174278d77b9a05b46d Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 6 Sep 2014 08:47:06 +0200
Subject: Corrected spelling mistakes found by lintian

---
 manual/CHAPTER_Prog/stubnets.cc     |  2 +-
 manual/CHAPTER_Techmap.tex          |  2 +-
 manual/CHAPTER_Verilog.tex          |  6 +++---
 manual/command-reference-manual.tex | 14 +++++++-------
 manual/manual.tex                   |  2 +-
 5 files changed, 13 insertions(+), 13 deletions(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 4d1452c97..ef4b1245d 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -57,7 +57,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 		// we will record which bits of the (possibly multi-bit) wire are stub signals
 		std::set<int> stub_bits;
 
-		// get a signal description for this wire and split it into seperate bits
+		// get a signal description for this wire and split it into separate bits
 		RTLIL::SigSpec sig = sigmap(wire);
 
 		// for each bit (unless it is a constant):
diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex
index 26632d0b5..e5c7456c4 100644
--- a/manual/CHAPTER_Techmap.tex
+++ b/manual/CHAPTER_Techmap.tex
@@ -32,7 +32,7 @@ the Yosys source tree.
 
 Additional features have been added to {\tt techmap} to allow for conditional
 mapping of cells (see {\tt help techmap} or Sec.~\ref{cmd:techmap}). This can
-for example be usefull if the target architecture supports hardware multipliers for
+for example be useful if the target architecture supports hardware multipliers for
 certain bit-widths but not for others.
 
 A usual synthesis flow would first use the {\tt techmap} pass to directly map
diff --git a/manual/CHAPTER_Verilog.tex b/manual/CHAPTER_Verilog.tex
index 960747747..485b4f357 100644
--- a/manual/CHAPTER_Verilog.tex
+++ b/manual/CHAPTER_Verilog.tex
@@ -444,7 +444,7 @@ on the AST data structure:
 \begin{itemize}
 \item Inline all task and function calls.
 \item Evaluate all \lstinline[language=Verilog]{generate}-statements and unroll all \lstinline[language=Verilog]{for}-loops.
-\item Perform const folding where it is neccessary (e.g.~in the value part of {\tt AST\_PARAMETER}, {\tt AST\_LOCALPARAM},
+\item Perform const folding where it is necessary (e.g.~in the value part of {\tt AST\_PARAMETER}, {\tt AST\_LOCALPARAM},
 {\tt AST\_PARASET} and {\tt AST\_RANGE} nodes).
 \item Replace {\tt AST\_PRIMITIVE} nodes with appropriate {\tt AST\_ASSIGN} nodes.
 \item Replace dynamic bit ranges in the left-hand-side of assignments with {\tt AST\_CASE} nodes with {\tt AST\_COND} children
@@ -819,7 +819,7 @@ the \C{RTLIL::SyncRule}s that describe the output registers.
 %
 \item {\tt proc\_dff} \\
 This pass replaces the \C{RTLIL::SyncRule}s to d-type flip-flops (with
-asynchronous resets if neccessary).
+asynchronous resets if necessary).
 %
 \item {\tt proc\_clean} \\
 A final call to {\tt proc\_clean} removes the now empty \C{RTLIL::Process} objects.
@@ -827,7 +827,7 @@ A final call to {\tt proc\_clean} removes the now empty \C{RTLIL::Process} objec
 
 Performing these last processing steps in passes instead of in the Verilog frontend has two important benefits:
 
-First it improves the transparency of the process. Everything that happens in a seperate pass is easier to debug,
+First it improves the transparency of the process. Everything that happens in a separate pass is easier to debug,
 as the RTLIL data structures can be easily investigated before and after each of the steps.
 
 Second it improves flexibility. This scheme can easily be extended to support other types of storage-elements, such
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 9d9665c1e..35249ed88 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -85,10 +85,10 @@ This is just a shortcut for 'select -clear'.
 
 This is identical to 'opt_clean', but less verbose.
 
-When commands are seperated using the ';;' token, this command will be executed
+When commands are separated using the ';;' token, this command will be executed
 between the commands.
 
-When commands are seperated using the ';;;' token, this command will be executed
+When commands are separated using the ';;;' token, this command will be executed
 in -purge mode between the commands.
 \end{lstlisting}
 
@@ -419,7 +419,7 @@ commands.
     hierarchy [-check] [-top <module>]
     hierarchy -generate <cell-types> <port-decls>
 
-In parametric designs, a module might exists in serveral variations with
+In parametric designs, a module might exists in several variations with
 different parameter values. This pass looks at all modules in the current
 design an re-runs the language frontends for the parametric modules as
 needed.
@@ -881,7 +881,7 @@ The following options can be used to set up a sequential problem:
     -set-def-at <N> <signal>
     -set-any-undef-at <N> <signal>
     -set-all-undef-at <N> <signal>
-        add undef contraints in the given timestep.
+        add undef constraints in the given timestep.
 
     -set-init <signal> <value>
         set the initial value for the register driving the signal to the value
@@ -942,7 +942,7 @@ design.
 
     -all_cell_types
         Usually this command only considers internal non-memory cells. With
-        this option set, all cells are considered. For unkown cells all ports
+        this option set, all cells are considered. For unknown cells all ports
         are assumed to be bidirectional 'inout' ports.
 
     -set_attr <name> <value>
@@ -1089,7 +1089,7 @@ The following actions can be performed on the top sets on the stack:
         (i.e. select all cells connected to selected wires and select all
         wires connected to selected cells) The rules specify which cell
         ports to use for this. the syntax for a rule is a '-' for exclusion
-        and a '+' for inclusion, followed by an optional comma seperated
+        and a '+' for inclusion, followed by an optional comma separated
         list of cell types followed by an optional comma separated list of
         cell ports in square brackets. a rule can also be just a cell or wire
         name that limits the expansion (is included but does not go beyond).
@@ -1452,7 +1452,7 @@ Write the current design to an BLIF file.
     -false <cell-type> <out-port>
         use the specified cell types to drive nets that are constant 1 or 0
 
-The following options can be usefull when the generated file is not going to be
+The following options can be useful when the generated file is not going to be
 read by a BLIF parser but a custom tool. It is recommended to not name the output
 file *.blif when any of this options is used.
 
diff --git a/manual/manual.tex b/manual/manual.tex
index c305ecb05..19d3b7b2f 100644
--- a/manual/manual.tex
+++ b/manual/manual.tex
@@ -144,7 +144,7 @@ Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
 with the help of HDL synthesis tools.
 
 In special cases such as synthesis for coarse-grain cell libraries or when
-testing new synthesis algorithms it might be neccessary to write a custom HDL
+testing new synthesis algorithms it might be necessary to write a custom HDL
 synthesis tool or add new features to an existing one. It this cases the
 availability of a Free and Open Source (FOSS) synthesis tool that can be used
 as basis for custom tools would be helpful.
-- 
cgit v1.2.3


From af0c8873bbc13eea10b3d705061b4cf68fe27c17 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 8 Sep 2014 13:28:23 +0200
Subject: Added $lcu cell type

---
 manual/CHAPTER_CellLib.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'manual')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 5045960cb..64d3633e9 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -425,7 +425,7 @@ Add information about {\tt \$slice} and {\tt \$concat} cells.
 \end{fixme}
 
 \begin{fixme}
-Add information about {\tt \$alu} cells.
+Add information about {\tt \$alu}, {\tt \$macc}, {\tt \$fa}, and {\tt \$lcu} cells.
 \end{fixme}
 
 \begin{fixme}
-- 
cgit v1.2.3