From a6750b375301f2c2ebb51a2496cdf2c820b2546b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 3 Feb 2014 13:01:45 +0100 Subject: Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) --- manual/CHAPTER_CellLib.tex | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'manual') diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index b848a2b60..c8c2b6c6c 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -250,6 +250,10 @@ the \B{CLK} input is not used. \item \B{CLK\_POLARITY} \\ Clock is active on the positive edge if this parameter has the value {\tt 1'b1} and on the negative edge if this parameter is {\tt 1'b0}. + +\item \B{TRANSPARENT} \\ +If this parameter is set to {\tt 1'b1}, a read and write to the same address in the same cycle will +return the new value. Otherwise the old value is returned. \end{itemize} The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN}, an address input \B{ADDR} @@ -308,6 +312,9 @@ This parameter is \B{RD\_PORTS} bits wide, containing a clock enable bit for eac \item \B{RD\_CLK\_POLARITY} \\ This parameter is \B{RD\_PORTS} bits wide, containing a clock polarity bit for each read port. +\item \B{RD\_TRANSPARENT} \\ +This parameter is \B{RD\_PORTS} bits wide, containing a transparent bit for each read port. + \item \B{WR\_PORTS} \\ The number of write ports on this memory cell. -- cgit v1.2.3