From 924d9d6e86a5e9a2294479345daac1c03d78008a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Sep 2015 12:23:11 +0200 Subject: Added read-enable to memory model --- manual/CHAPTER_CellLib.tex | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'manual') diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 9f9ec2e2b..c648eb1fe 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -220,8 +220,9 @@ cell is created. Having individual cells for read and write ports has the advant consolidated using resource sharing passes. In some cases this drastically reduces the number of required ports on the memory cell. -The {\tt \$memrd} cells have a clock input \B{CLK}, an address input \B{ADDR} and a data output -\B{DATA}. They also have the following parameters: +The {\tt \$memrd} cells have a clock input \B{CLK}, an enable input \B{EN}, an +address input \B{ADDR}, and a data output \B{DATA}. They also have the +following parameters: \begin{itemize} \item \B{MEMID} \\ @@ -322,6 +323,9 @@ The {\tt \$mem} cell has the following ports: \item \B{RD\_CLK} \\ This input is \B{RD\_PORTS} bits wide, containing all clock signals for the read ports. +\item \B{RD\_EN} \\ +This input is \B{RD\_PORTS} bits wide, containing all enable signals for the read ports. + \item \B{RD\_ADDR} \\ This input is \B{RD\_PORTS}*\B{ABITS} bits wide, containing all address signals for the read ports. -- cgit v1.2.3