From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 01:51:45 +0200
Subject: Refactoring: Renamed RTLIL::Module::cells to cells_
---
manual/CHAPTER_Prog/stubnets.cc | 2 +-
manual/PRESENTATION_Prog/my_cmd.cc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
(limited to 'manual')
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 9eacfbcb5..a57907435 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -29,7 +29,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
// For all ports on all cells
- for (auto &cell_iter : module->cells)
+ for (auto &cell_iter : module->cells_)
for (auto &conn : cell_iter.second->connections())
{
// Get the signals on the port
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index 0cd1da808..c724ce375 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -14,7 +14,7 @@ struct MyPass : public Pass {
log("Modules in current design:\n");
for (auto &mod : design->modules)
log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
- mod.second->wires_.size(), mod.second->cells.size());
+ mod.second->wires_.size(), mod.second->cells_.size());
}
} MyPass;
--
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