From 993a77d19b3fb56ef2da3a6dfafa8a1488039d01 Mon Sep 17 00:00:00 2001 From: Gustavo Romero Date: Wed, 11 Dec 2019 08:09:48 -0300 Subject: manual: Fix text in Abstract section --- manual/manual.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual') diff --git a/manual/manual.tex b/manual/manual.tex index 67982cbc8..75f087eca 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -146,7 +146,7 @@ with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or when testing new synthesis algorithms it might be necessary to write a custom HDL -synthesis tool or add new features to an existing one. It this cases the +synthesis tool or add new features to an existing one. In these cases the availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful. -- cgit v1.2.3 From e9dc2759c414bdc8ab663fd5c8350b40b099b456 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Fri, 13 Dec 2019 10:17:05 -0300 Subject: Fixed some missing "verilog_" in documentation --- manual/CHAPTER_Verilog.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'manual') diff --git a/manual/CHAPTER_Verilog.tex b/manual/CHAPTER_Verilog.tex index e9ca6114e..d4cc55647 100644 --- a/manual/CHAPTER_Verilog.tex +++ b/manual/CHAPTER_Verilog.tex @@ -93,7 +93,7 @@ frontends/verilog/preproc.cc} in the Yosys source tree. \begin{sloppypar} The Verilog Lexer is written using the lexer generator {\it flex} \citeweblink{flex}. Its source code -can be found in {\tt frontends/verilog/lexer.l} in the Yosys source tree. +can be found in {\tt frontends/verilog/verilog\_lexer.l} in the Yosys source tree. The lexer does little more than identifying all keywords and literals recognised by the Yosys Verilog frontend. \end{sloppypar} @@ -115,7 +115,7 @@ whenever possible.) \subsection{The Verilog Parser} The Verilog Parser is written using the parser generator {\it bison} \citeweblink{bison}. Its source code -can be found in {\tt frontends/verilog/parser.y} in the Yosys source tree. +can be found in {\tt frontends/verilog/verilog\_parser.y} in the Yosys source tree. It generates an AST using the \lstinline[language=C++]{AST::AstNode} data structure defined in {\tt frontends/ast/ast.h}. An \lstinline[language=C++]{AST::AstNode} object has -- cgit v1.2.3