From 9c1e578afe6af40be4600c20c883fa016fc7fa26 Mon Sep 17 00:00:00 2001 From: "Anthony J. Bentley" Date: Fri, 11 Apr 2014 02:42:59 -0600 Subject: Typos and grammar fixes through chapter 2. --- manual/manual.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'manual/manual.tex') diff --git a/manual/manual.tex b/manual/manual.tex index d6ffd95a6..c305ecb05 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -140,7 +140,7 @@ bookmarksopen=false% \eject \chapter*{Abstract} -Most of todays digital design is done in HDL code (mostly Verilog or VHDL) and +Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or when @@ -158,7 +158,7 @@ by Yosys to perform advanced gate-level optimizations. An evaluation of Yosys based on real-world designs is included. It is shown that Yosys can be used as-is to synthesize such designs. The results produced by Yosys in this tests where successflly verified using formal verification -and are compareable in quality to the results produced by a commercial +and are comparable in quality to the results produced by a commercial synthesis tool. \bigskip -- cgit v1.2.3