From 9c29969bbc1b19f251011feaa791d242ac8e5e81 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 13:45:47 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/Makefile          |  5 ++-
 manual/PRESENTATION_ExAdv/red_or3x1_cells.v |  5 +++
 manual/PRESENTATION_ExAdv/red_or3x1_map.v   | 48 +++++++++++++++++++++++++++++
 manual/PRESENTATION_ExAdv/red_or3x1_test.v  |  5 +++
 manual/PRESENTATION_ExAdv/red_or3x1_test.ys |  7 +++++
 5 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/red_or3x1_cells.v
 create mode 100644 manual/PRESENTATION_ExAdv/red_or3x1_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/red_or3x1_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/red_or3x1_test.ys

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index f38bd6ceb..673b3a213 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,6 +1,9 @@
 
-all: select_01.pdf
+all: select_01.pdf red_or3x1.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
 
+red_or3x1.pdf: red_or3x1_*
+	../../yosys red_or3x1_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_cells.v b/manual/PRESENTATION_ExAdv/red_or3x1_cells.v
new file mode 100644
index 000000000..0750a1307
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_cells.v
@@ -0,0 +1,5 @@
+module OR3X1(A, B, C, Y);
+    input A, B, C;
+    output Y;
+    assign Y = A | B | C;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_map.v b/manual/PRESENTATION_ExAdv/red_or3x1_map.v
new file mode 100644
index 000000000..24ca9dab4
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_map.v
@@ -0,0 +1,48 @@
+module \$reduce_or (A, Y);
+
+    parameter A_SIGNED = 0;
+    parameter A_WIDTH = 0;
+    parameter Y_WIDTH = 0;
+    
+    input [A_WIDTH-1:0] A;
+    output [Y_WIDTH-1:0] Y;
+    
+    function integer min;
+        input integer a, b;
+        begin
+            if (a < b)
+                min = a;
+            else
+                min = b;
+        end
+    endfunction
+    
+    genvar i;
+    generate begin
+        if (A_WIDTH == 0) begin
+            assign Y = 0;
+        end
+        if (A_WIDTH == 1) begin
+            assign Y = A;
+        end
+        if (A_WIDTH == 2) begin
+            wire ybuf;
+            OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
+            assign Y = ybuf;
+        end
+        if (A_WIDTH == 3) begin
+            wire ybuf;
+            OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
+            assign Y = ybuf;
+        end
+        if (A_WIDTH > 3) begin
+            localparam next_stage_sz = (A_WIDTH+2) / 3;
+            wire [next_stage_sz-1:0] next_stage;
+            for (i = 0; i < next_stage_sz; i = i+1) begin
+                localparam bits = min(A_WIDTH - 3*i, 3);
+                assign next_stage[i] = |A[3*i +: bits];
+            end
+            assign Y = |next_stage;
+        end
+    end endgenerate
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_test.v b/manual/PRESENTATION_ExAdv/red_or3x1_test.v
new file mode 100644
index 000000000..bcdd32cbf
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_test.v
@@ -0,0 +1,5 @@
+module test (A, Y);
+    input [6:0] A;
+    output Y;
+    assign Y = |A;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_test.ys b/manual/PRESENTATION_ExAdv/red_or3x1_test.ys
new file mode 100644
index 000000000..b92346034
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_test.ys
@@ -0,0 +1,7 @@
+read_verilog red_or3x1_test.v
+hierarchy -check -top test
+
+techmap -map red_or3x1_map.v;;
+
+splitnets -ports
+show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v
-- 
cgit v1.2.3


From aeb36b0b8b499a5b758840998afe9f1b4d7fc166 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 14:32:56 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/Makefile        |  5 ++++-
 manual/PRESENTATION_ExAdv/sym_mul_cells.v |  6 ++++++
 manual/PRESENTATION_ExAdv/sym_mul_map.v   | 15 +++++++++++++++
 manual/PRESENTATION_ExAdv/sym_mul_test.v  |  5 +++++
 manual/PRESENTATION_ExAdv/sym_mul_test.ys |  6 ++++++
 5 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/sym_mul_cells.v
 create mode 100644 manual/PRESENTATION_ExAdv/sym_mul_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/sym_mul_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/sym_mul_test.ys

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 673b3a213..4ee5886d2 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -7,3 +7,6 @@ select_01.pdf: select_01.v select_01.ys
 red_or3x1.pdf: red_or3x1_*
 	../../yosys red_or3x1_test.ys
 
+sym_mul.pdf: sym_mul_*
+	../../yosys sym_mul_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_cells.v b/manual/PRESENTATION_ExAdv/sym_mul_cells.v
new file mode 100644
index 000000000..ce1771544
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/sym_mul_cells.v
@@ -0,0 +1,6 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output [WIDTH-1:0] Y;
+    assign Y = A * B;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_map.v b/manual/PRESENTATION_ExAdv/sym_mul_map.v
new file mode 100644
index 000000000..293c5b841
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/sym_mul_map.v
@@ -0,0 +1,15 @@
+module \$mul (A, B, Y);
+    parameter A_SIGNED = 0;
+    parameter B_SIGNED = 0;
+    parameter A_WIDTH = 1;
+    parameter B_WIDTH = 1;
+    parameter Y_WIDTH = 1;
+    
+    input [A_WIDTH-1:0] A;
+    input [B_WIDTH-1:0] B;
+    output [Y_WIDTH-1:0] Y;
+    
+    wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
+    
+    MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_test.v b/manual/PRESENTATION_ExAdv/sym_mul_test.v
new file mode 100644
index 000000000..eb715f83d
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/sym_mul_test.v
@@ -0,0 +1,5 @@
+module test(A, B, C, Y1, Y2);
+    input   [7:0] A, B, C;
+    output  [7:0] Y1 = A * B;
+    output [15:0] Y2 = A * C;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_test.ys b/manual/PRESENTATION_ExAdv/sym_mul_test.ys
new file mode 100644
index 000000000..0c07e7e87
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/sym_mul_test.ys
@@ -0,0 +1,6 @@
+read_verilog sym_mul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v;;
+
+show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v
-- 
cgit v1.2.3


From f08c71b96c325f2432abb4f95fd823ae243e003b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 17:56:19 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/Makefile      |  5 ++++-
 manual/PRESENTATION_ExAdv/mymul_map.v   | 15 +++++++++++++++
 manual/PRESENTATION_ExAdv/mymul_test.v  |  4 ++++
 manual/PRESENTATION_ExAdv/mymul_test.ys | 15 +++++++++++++++
 4 files changed, 38 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/mymul_test.ys

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 4ee5886d2..74f263270 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -10,3 +10,6 @@ red_or3x1.pdf: red_or3x1_*
 sym_mul.pdf: sym_mul_*
 	../../yosys sym_mul_test.ys
 
+mymul.pdf: mymul_*
+	../../yosys mymul_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/mymul_map.v b/manual/PRESENTATION_ExAdv/mymul_map.v
new file mode 100644
index 000000000..e888a7a7c
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_map.v
@@ -0,0 +1,15 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output reg [WIDTH-1:0] Y;
+
+    wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+    integer i;
+    always @* begin
+        Y = 0;
+        for (i = 0; i < WIDTH; i=i+1)
+            if (A[i])
+                Y = Y + (B << i);
+    end
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mymul_test.v b/manual/PRESENTATION_ExAdv/mymul_test.v
new file mode 100644
index 000000000..620a06d9e
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_test.v
@@ -0,0 +1,4 @@
+module test(A, B, Y);
+    input  [1:0] A, B;
+    output [1:0] Y = A * B;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mymul_test.ys b/manual/PRESENTATION_ExAdv/mymul_test.ys
new file mode 100644
index 000000000..48203e319
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_test.ys
@@ -0,0 +1,15 @@
+read_verilog mymul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+        -map mymul_map.v;;
+
+rename test test_mapped
+read_verilog mymul_test.v
+miter -equiv test test_mapped miter
+flatten miter
+
+sat -verify -prove trigger 0 miter
+
+splitnets -ports test_mapped/A
+show -prefix mymul -format pdf -notitle test_mapped
-- 
cgit v1.2.3


From 37cbb1ca60b03cbaaef5041db5f631b90a303f9a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Feb 2014 22:31:53 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/Makefile         |  5 ++++-
 manual/PRESENTATION_ExAdv/mulshift_map.v   | 26 ++++++++++++++++++++++++++
 manual/PRESENTATION_ExAdv/mulshift_test.v  |  5 +++++
 manual/PRESENTATION_ExAdv/mulshift_test.ys |  7 +++++++
 4 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/mulshift_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/mulshift_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/mulshift_test.ys

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 74f263270..3bbc239a4 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -13,3 +13,6 @@ sym_mul.pdf: sym_mul_*
 mymul.pdf: mymul_*
 	../../yosys mymul_test.ys
 
+mulshift.pdf: mulshift_*
+	../../yosys mulshift_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/mulshift_map.v b/manual/PRESENTATION_ExAdv/mulshift_map.v
new file mode 100644
index 000000000..4a3c2a062
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_map.v
@@ -0,0 +1,26 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output reg [WIDTH-1:0] Y;
+
+    parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
+    parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
+
+    reg _TECHMAP_FAIL_;
+    wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+    integer i;
+    always @* begin
+    	_TECHMAP_FAIL_ <= 1;
+        for (i = 0; i < WIDTH; i=i+1) begin
+            if (_TECHMAP_CONSTVAL_A_ === WIDTH'd1 << i) begin
+	        _TECHMAP_FAIL_ <= 0;
+                Y <= B << i;
+	    end
+            if (_TECHMAP_CONSTVAL_B_ === WIDTH'd1 << i) begin
+	        _TECHMAP_FAIL_ <= 0;
+                Y <= A << i;
+	    end
+	end
+    end
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mulshift_test.v b/manual/PRESENTATION_ExAdv/mulshift_test.v
new file mode 100644
index 000000000..4b975f414
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_test.v
@@ -0,0 +1,5 @@
+module test (A, X, Y);
+input [7:0] A;
+output [7:0] X = A * 8'd 6;
+output [7:0] Y = A * 8'd 8;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mulshift_test.ys b/manual/PRESENTATION_ExAdv/mulshift_test.ys
new file mode 100644
index 000000000..c5dac49eb
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mulshift_test.ys
@@ -0,0 +1,7 @@
+read_verilog mulshift_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+        -map mulshift_map.v;;
+
+show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v
-- 
cgit v1.2.3


From 3d9da919d8ec2f73df77dc1df02b132b12241d8e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 18 Feb 2014 19:37:39 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/Makefile         |  5 ++++-
 manual/PRESENTATION_ExAdv/addshift_map.v   | 20 ++++++++++++++++++++
 manual/PRESENTATION_ExAdv/addshift_test.v  |  5 +++++
 manual/PRESENTATION_ExAdv/addshift_test.ys |  6 ++++++
 4 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 manual/PRESENTATION_ExAdv/addshift_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/addshift_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/addshift_test.ys

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 3bbc239a4..2a2858e5f 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
 
 select_01.pdf: select_01.v select_01.ys
 	../../yosys select_01.ys
@@ -16,3 +16,6 @@ mymul.pdf: mymul_*
 mulshift.pdf: mulshift_*
 	../../yosys mulshift_test.ys
 
+addshift.pdf: addshift_*
+	../../yosys addshift_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/addshift_map.v b/manual/PRESENTATION_ExAdv/addshift_map.v
new file mode 100644
index 000000000..b6d91b01b
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/addshift_map.v
@@ -0,0 +1,20 @@
+module \$add (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
+  
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
+  
+  parameter _TECHMAP_BITS_CONNMAP_ = 0;
+  parameter _TECHMAP_CONNMAP_A_ = 0;
+  parameter _TECHMAP_CONNMAP_B_ = 0;
+  
+  wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
+                        _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
+  
+  assign Y = A << 1;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/addshift_test.v b/manual/PRESENTATION_ExAdv/addshift_test.v
new file mode 100644
index 000000000..b53271faa
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/addshift_test.v
@@ -0,0 +1,5 @@
+module test (A, B, X, Y);
+input [7:0] A, B;
+output [7:0] X = A + B;
+output [7:0] Y = A + A;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/addshift_test.ys b/manual/PRESENTATION_ExAdv/addshift_test.ys
new file mode 100644
index 000000000..c08f1106a
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/addshift_test.ys
@@ -0,0 +1,6 @@
+read_verilog addshift_test.v
+hierarchy -check -top test
+
+techmap -map addshift_map.v;;
+
+show -prefix addshift -format pdf -notitle
-- 
cgit v1.2.3


From 98940260e1a0e5d9d5d305b5fabe0aed89c9f57c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Feb 2014 12:46:29 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/Makefile              | 10 ++++---
 manual/PRESENTATION_ExAdv/macc_simple_test.v    |  6 +++++
 manual/PRESENTATION_ExAdv/macc_simple_test.ys   | 36 +++++++++++++++++++++++++
 manual/PRESENTATION_ExAdv/macc_simple_test_01.v |  6 +++++
 manual/PRESENTATION_ExAdv/macc_simple_test_02.v |  6 +++++
 manual/PRESENTATION_ExAdv/macc_simple_xmap.v    |  6 +++++
 manual/PRESENTATION_ExAdv/select.v              | 15 +++++++++++
 manual/PRESENTATION_ExAdv/select.ys             | 10 +++++++
 manual/PRESENTATION_ExAdv/select_01.v           | 15 -----------
 manual/PRESENTATION_ExAdv/select_01.ys          | 10 -------
 10 files changed, 92 insertions(+), 28 deletions(-)
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test.ys
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test_01.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_test_02.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_simple_xmap.v
 create mode 100644 manual/PRESENTATION_ExAdv/select.v
 create mode 100644 manual/PRESENTATION_ExAdv/select.ys
 delete mode 100644 manual/PRESENTATION_ExAdv/select_01.v
 delete mode 100644 manual/PRESENTATION_ExAdv/select_01.ys

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 2a2858e5f..60da31693 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,8 +1,9 @@
 
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
+all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
+		macc_simple_xmap.pdf
 
-select_01.pdf: select_01.v select_01.ys
-	../../yosys select_01.ys
+select.pdf: select.v select.ys
+	../../yosys select.ys
 
 red_or3x1.pdf: red_or3x1_*
 	../../yosys red_or3x1_test.ys
@@ -19,3 +20,6 @@ mulshift.pdf: mulshift_*
 addshift.pdf: addshift_*
 	../../yosys addshift_test.ys
 
+macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
+	../../yosys macc_simple_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.v b/manual/PRESENTATION_ExAdv/macc_simple_test.v
new file mode 100644
index 000000000..6358a47c9
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, y);
+input [15:0] a, b;
+input [31:0] c, d;
+output [31:0] y;
+assign y = a * b + c + d;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.ys b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
new file mode 100644
index 000000000..d5b01237b
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
@@ -0,0 +1,36 @@
+read_verilog macc_simple_test.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -constports -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+read_verilog macc_simple_test_01.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_test_02.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_xmap.v
+hierarchy -check -top macc_16_16_32;;
+
+show -prefix macc_simple_xmap -format pdf -notitle
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test_01.v b/manual/PRESENTATION_ExAdv/macc_simple_test_01.v
new file mode 100644
index 000000000..8391fb383
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test_01.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + c*d + x;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test_02.v b/manual/PRESENTATION_ExAdv/macc_simple_test_02.v
new file mode 100644
index 000000000..3630102fa
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test_02.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + (c*d + x);
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_xmap.v b/manual/PRESENTATION_ExAdv/macc_simple_xmap.v
new file mode 100644
index 000000000..42f5bae95
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_xmap.v
@@ -0,0 +1,6 @@
+module macc_16_16_32(a, b, c, y);
+input [15:0] a, b;
+input [31:0] c;
+output [31:0] y;
+assign y = a*b + c;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/select.v b/manual/PRESENTATION_ExAdv/select.v
new file mode 100644
index 000000000..1b0bb7eeb
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/select.v
@@ -0,0 +1,15 @@
+module test(clk, s, a, y);
+    input clk, s;
+    input [15:0] a;
+    output [15:0] y;
+    reg [15:0] b, c;
+
+    always @(posedge clk) begin
+        b <= a;
+        c <= b;
+    end
+
+    wire [15:0] state_a = (a ^ b) + c;
+    wire [15:0] state_b = (a ^ b) - c;
+    assign y = !s ? state_a : state_b;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/select.ys b/manual/PRESENTATION_ExAdv/select.ys
new file mode 100644
index 000000000..9832c104b
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/select.ys
@@ -0,0 +1,10 @@
+read_verilog select.v
+hierarchy -check -top test
+proc; opt
+cd test
+select -set cone_a state_a %ci*:-$dff
+select -set cone_b state_b %ci*:-$dff
+select -set cone_ab @cone_a @cone_b %i
+show -prefix select -format pdf -notitle \
+     -color red @cone_ab -color magenta @cone_a \
+     -color blue @cone_b
diff --git a/manual/PRESENTATION_ExAdv/select_01.v b/manual/PRESENTATION_ExAdv/select_01.v
deleted file mode 100644
index 1b0bb7eeb..000000000
--- a/manual/PRESENTATION_ExAdv/select_01.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module test(clk, s, a, y);
-    input clk, s;
-    input [15:0] a;
-    output [15:0] y;
-    reg [15:0] b, c;
-
-    always @(posedge clk) begin
-        b <= a;
-        c <= b;
-    end
-
-    wire [15:0] state_a = (a ^ b) + c;
-    wire [15:0] state_b = (a ^ b) - c;
-    assign y = !s ? state_a : state_b;
-endmodule
diff --git a/manual/PRESENTATION_ExAdv/select_01.ys b/manual/PRESENTATION_ExAdv/select_01.ys
deleted file mode 100644
index a7fe27288..000000000
--- a/manual/PRESENTATION_ExAdv/select_01.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog select_01.v
-hierarchy -check -top test
-proc; opt
-cd test
-select -set cone_a state_a %ci*:-$dff
-select -set cone_b state_b %ci*:-$dff
-select -set cone_ab @cone_a @cone_b %i
-show -prefix select_01 -format pdf -notitle \
-     -color red @cone_ab -color magenta @cone_a \
-     -color blue @cone_b
-- 
cgit v1.2.3


From b0e84802ecf3e224387317245786cd1437773a42 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Feb 2014 20:44:41 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v   | 30 +++++++
 manual/PRESENTATION_ExAdv/macc_xilinx_test.v       |  6 ++
 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys      | 17 ++++
 manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v | 63 +++++++++++++++
 manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v   | 91 ++++++++++++++++++++++
 5 files changed, 207 insertions(+)
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_test.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
new file mode 100644
index 000000000..1f4867d11
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
@@ -0,0 +1,30 @@
+
+(* techmap_celltype = "$mul" *)
+module mul_swap_ports (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
+
+\$mul #(
+	.A_SIGNED(B_SIGNED),
+	.B_SIGNED(A_SIGNED),
+	.A_WIDTH(B_WIDTH),
+	.B_WIDTH(A_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(B),
+	.B(A),
+	.Y(Y)
+);
+
+endmodule
+
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
new file mode 100644
index 000000000..d08d939e9
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, e, f, y);
+input [19:0] a, b, c;
+input [15:0] d, e, f;
+output [41:0] y;
+assign y = a*b + c*d + e*f;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
new file mode 100644
index 000000000..8cbc80b5e
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -0,0 +1,17 @@
+read_verilog macc_xilinx_test.v
+read_verilog -lib -icells macc_xilinx_unwrap_map.v
+hierarchy -check -top test;;
+
+show -prefix macc_xilinx_test_a -format pdf -notitle
+
+techmap -map macc_xilinx_swap_map.v;;
+
+show -prefix macc_xilinx_test_b -format pdf -notitle
+
+techmap -map macc_xilinx_wrap_map.v
+
+connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
+             -unsigned $__add_wrapper Y Y_WIDTH;;
+
+show -prefix macc_xilinx_test_c -format pdf -notitle
+
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
new file mode 100644
index 000000000..386635ac2
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
@@ -0,0 +1,63 @@
+
+module \$__mul_wrapper (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [A_WIDTH-1:0] A_ORIG = A;
+wire [B_WIDTH-1:0] B_ORIG = B;
+wire [Y_WIDTH-1:0] Y_ORIG;
+assign Y = Y_ORIG;
+
+\$mul #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_ORIG),
+	.B(B_ORIG),
+	.Y(Y_ORIG)
+);
+
+endmodule
+
+module \$__add_wrapper (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [A_WIDTH-1:0] A_ORIG = A;
+wire [B_WIDTH-1:0] B_ORIG = B;
+wire [Y_WIDTH-1:0] Y_ORIG;
+assign Y = Y_ORIG;
+
+\$add #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_ORIG),
+	.B(B_ORIG),
+	.Y(Y_ORIG)
+);
+
+endmodule
+
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
new file mode 100644
index 000000000..d1ded2954
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
@@ -0,0 +1,91 @@
+
+(* techmap_celltype = "$mul" *)
+module mul_wrap (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [24:0] A_25 = A;
+wire [17:0] B_18 = B;
+wire [47:0] Y_48;
+assign Y = Y_48;
+
+wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+reg _TECHMAP_FAIL_;
+initial begin
+	_TECHMAP_FAIL_ <= 0;
+	if (A_SIGNED || B_SIGNED)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH < 4 || B_WIDTH < 4)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH > 25 || B_WIDTH > 18)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH*B_WIDTH < 100)
+		_TECHMAP_FAIL_ <= 1;
+end
+
+\$__mul_wrapper #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_25),
+	.B(B_18),
+	.Y(Y_48)
+);
+
+endmodule
+
+(* techmap_celltype = "$add" *)
+module add_wrap (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [47:0] A_48 = A;
+wire [47:0] B_48 = B;
+wire [47:0] Y_48;
+assign Y = Y_48;
+
+wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+reg _TECHMAP_FAIL_;
+initial begin
+	_TECHMAP_FAIL_ <= 0;
+	if (A_SIGNED || B_SIGNED)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH < 10 && B_WIDTH < 10)
+		_TECHMAP_FAIL_ <= 1;
+end
+
+\$__add_wrapper #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_48),
+	.B(B_48),
+	.Y(Y_48)
+);
+
+endmodule
+
-- 
cgit v1.2.3


From 9351e4d3caef1af7b7768d66b7f6edc12713d109 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Feb 2014 23:44:28 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/macc_xilinx_test.v       |  9 ++++++-
 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys      | 31 +++++++++++++++++++---
 manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v | 12 ++++-----
 manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v       | 10 +++++++
 4 files changed, 51 insertions(+), 11 deletions(-)
 create mode 100644 manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
index d08d939e9..d8fdf724c 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
@@ -1,6 +1,13 @@
-module test(a, b, c, d, e, f, y);
+module test1(a, b, c, d, e, f, y);
 input [19:0] a, b, c;
 input [15:0] d, e, f;
 output [41:0] y;
 assign y = a*b + c*d + e*f;
 endmodule
+
+module test2(a, b, c, d, e, f, y);
+input [19:0] a, b, c;
+input [15:0] d, e, f;
+output [41:0] y;
+assign y = a*b + (c*d + e*f);
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
index 8cbc80b5e..85c4a24f6 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -1,17 +1,40 @@
 read_verilog macc_xilinx_test.v
 read_verilog -lib -icells macc_xilinx_unwrap_map.v
-hierarchy -check -top test;;
+read_verilog -lib -icells macc_xilinx_xmap.v
+hierarchy -check ;;
 
-show -prefix macc_xilinx_test_a -format pdf -notitle
+show -prefix macc_xilinx_test1_a -format pdf -notitle test1
+show -prefix macc_xilinx_test2_a -format pdf -notitle test2
 
 techmap -map macc_xilinx_swap_map.v;;
 
-show -prefix macc_xilinx_test_b -format pdf -notitle
+show -prefix macc_xilinx_test1_b -format pdf -notitle test1
+show -prefix macc_xilinx_test2_b -format pdf -notitle test2
 
 techmap -map macc_xilinx_wrap_map.v
 
 connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
              -unsigned $__add_wrapper Y Y_WIDTH;;
 
-show -prefix macc_xilinx_test_c -format pdf -notitle
+show -prefix macc_xilinx_test1_c -format pdf -notitle test1
+show -prefix macc_xilinx_test2_c -format pdf -notitle test2
+
+design -push
+read_verilog macc_xilinx_xmap.v
+techmap -map macc_xilinx_swap_map.v
+techmap -map macc_xilinx_wrap_map.v;;
+design -save __macc_xilinx_xmap
+design -pop
+
+extract -constports -ignore_parameters \
+        -map %__macc_xilinx_xmap       \
+        -swap $__add_wrapper A,B ;;
+
+show -prefix macc_xilinx_test1_d -format pdf -notitle test1
+show -prefix macc_xilinx_test2_d -format pdf -notitle test2
+
+techmap -map macc_xilinx_unwrap_map.v;;
+
+show -prefix macc_xilinx_test1_e -format pdf -notitle test1
+show -prefix macc_xilinx_test2_e -format pdf -notitle test2
 
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
index 386635ac2..a80538d5b 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
@@ -7,9 +7,9 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] Y;
+input [24:0] A;
+input [17:0] B;
+output [47:0] Y;
 
 wire [A_WIDTH-1:0] A_ORIG = A;
 wire [B_WIDTH-1:0] B_ORIG = B;
@@ -38,9 +38,9 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] Y;
+input [47:0] A;
+input [47:0] B;
+output [47:0] Y;
 
 wire [A_WIDTH-1:0] A_ORIG = A;
 wire [B_WIDTH-1:0] B_ORIG = B;
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
new file mode 100644
index 000000000..15bd04ed1
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
@@ -0,0 +1,10 @@
+module DSP48_MACC (a, b, c, y);
+
+input [24:0] a;
+input [17:0] b;
+input [47:0] c;
+output [47:0] y;
+
+assign y = a*b + c;
+
+endmodule
-- 
cgit v1.2.3


From 2aff7b2a47d2ad65ff34e10f008733da9ef50c4a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Feb 2014 02:13:02 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/Makefile            |  5 ++++-
 manual/PRESENTATION_ExAdv/macc_simple_test.ys |  1 +
 manual/PRESENTATION_ExAdv/macc_xilinx_test.v  | 16 ++++++++--------
 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys | 23 +++++++++++++----------
 4 files changed, 26 insertions(+), 19 deletions(-)

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 60da31693..993a9d9e1 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,6 +1,6 @@
 
 all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
-		macc_simple_xmap.pdf
+		macc_simple_xmap.pdf macc_xilinx_xmap.pdf
 
 select.pdf: select.v select.ys
 	../../yosys select.ys
@@ -23,3 +23,6 @@ addshift.pdf: addshift_*
 macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
 	../../yosys macc_simple_test.ys
 
+macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
+	../../yosys macc_xilinx_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.ys b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
index d5b01237b..8d106a28c 100644
--- a/manual/PRESENTATION_ExAdv/macc_simple_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
@@ -8,6 +8,7 @@ show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
 
 #################################################
 
+design -reset
 read_verilog macc_simple_test_01.v
 hierarchy -check -top test;;
 
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
index d8fdf724c..683d9d847 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
@@ -1,13 +1,13 @@
 module test1(a, b, c, d, e, f, y);
-input [19:0] a, b, c;
-input [15:0] d, e, f;
-output [41:0] y;
-assign y = a*b + c*d + e*f;
+    input [19:0] a, b, c;
+    input [15:0] d, e, f;
+    output [41:0] y;
+    assign y = a*b + c*d + e*f;
 endmodule
 
 module test2(a, b, c, d, e, f, y);
-input [19:0] a, b, c;
-input [15:0] d, e, f;
-output [41:0] y;
-assign y = a*b + (c*d + e*f);
+    input [19:0] a, b, c;
+    input [15:0] d, e, f;
+    output [41:0] y;
+    assign y = a*b + (c*d + e*f);
 endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
index 85c4a24f6..3f7893fa2 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -3,21 +3,21 @@ read_verilog -lib -icells macc_xilinx_unwrap_map.v
 read_verilog -lib -icells macc_xilinx_xmap.v
 hierarchy -check ;;
 
-show -prefix macc_xilinx_test1_a -format pdf -notitle test1
-show -prefix macc_xilinx_test2_a -format pdf -notitle test2
+show -prefix macc_xilinx_test1a -format pdf -notitle test1
+show -prefix macc_xilinx_test2a -format pdf -notitle test2
 
 techmap -map macc_xilinx_swap_map.v;;
 
-show -prefix macc_xilinx_test1_b -format pdf -notitle test1
-show -prefix macc_xilinx_test2_b -format pdf -notitle test2
+show -prefix macc_xilinx_test1b -format pdf -notitle test1
+show -prefix macc_xilinx_test2b -format pdf -notitle test2
 
 techmap -map macc_xilinx_wrap_map.v
 
 connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
              -unsigned $__add_wrapper Y Y_WIDTH;;
 
-show -prefix macc_xilinx_test1_c -format pdf -notitle test1
-show -prefix macc_xilinx_test2_c -format pdf -notitle test2
+show -prefix macc_xilinx_test1c -format pdf -notitle test1
+show -prefix macc_xilinx_test2c -format pdf -notitle test2
 
 design -push
 read_verilog macc_xilinx_xmap.v
@@ -30,11 +30,14 @@ extract -constports -ignore_parameters \
         -map %__macc_xilinx_xmap       \
         -swap $__add_wrapper A,B ;;
 
-show -prefix macc_xilinx_test1_d -format pdf -notitle test1
-show -prefix macc_xilinx_test2_d -format pdf -notitle test2
+show -prefix macc_xilinx_test1d -format pdf -notitle test1
+show -prefix macc_xilinx_test2d -format pdf -notitle test2
 
 techmap -map macc_xilinx_unwrap_map.v;;
 
-show -prefix macc_xilinx_test1_e -format pdf -notitle test1
-show -prefix macc_xilinx_test2_e -format pdf -notitle test2
+show -prefix macc_xilinx_test1e -format pdf -notitle test1
+show -prefix macc_xilinx_test2e -format pdf -notitle test2
+
+design -load
+show -prefix macc_xilinx_xmap -format pdf -notitle
 
-- 
cgit v1.2.3


From 79edcd4318590974ef49b2d5f561382eea3454bf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Feb 2014 14:59:59 +0100
Subject: Progress in presentation

---
 manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v   |  4 +---
 manual/PRESENTATION_ExAdv/macc_xilinx_test.ys      |  2 +-
 manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v |  6 ++----
 manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v   | 12 +++++-------
 manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v       |  4 ++--
 5 files changed, 11 insertions(+), 17 deletions(-)

(limited to 'manual/PRESENTATION_ExAdv')

diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
index 1f4867d11..e36967225 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
@@ -1,4 +1,3 @@
-
 (* techmap_celltype = "$mul" *)
 module mul_swap_ports (A, B, Y);
 
@@ -12,7 +11,7 @@ input [A_WIDTH-1:0] A;
 input [B_WIDTH-1:0] B;
 output [Y_WIDTH-1:0] Y;
 
-wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
+wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
 
 \$mul #(
 	.A_SIGNED(B_SIGNED),
@@ -27,4 +26,3 @@ wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
 );
 
 endmodule
-
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
index 3f7893fa2..f3e8af4f0 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -38,6 +38,6 @@ techmap -map macc_xilinx_unwrap_map.v;;
 show -prefix macc_xilinx_test1e -format pdf -notitle test1
 show -prefix macc_xilinx_test2e -format pdf -notitle test2
 
-design -load
+design -load __macc_xilinx_xmap
 show -prefix macc_xilinx_xmap -format pdf -notitle
 
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
index a80538d5b..9dfaef131 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
@@ -1,4 +1,3 @@
-
 module \$__mul_wrapper (A, B, Y);
 
 parameter A_SIGNED = 0;
@@ -7,8 +6,8 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [24:0] A;
-input [17:0] B;
+input [17:0] A;
+input [24:0] B;
 output [47:0] Y;
 
 wire [A_WIDTH-1:0] A_ORIG = A;
@@ -60,4 +59,3 @@ assign Y = Y_ORIG;
 );
 
 endmodule
-
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
index d1ded2954..f23f6c02a 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
@@ -1,4 +1,3 @@
-
 (* techmap_celltype = "$mul" *)
 module mul_wrap (A, B, Y);
 
@@ -12,8 +11,8 @@ input [A_WIDTH-1:0] A;
 input [B_WIDTH-1:0] B;
 output [Y_WIDTH-1:0] Y;
 
-wire [24:0] A_25 = A;
-wire [17:0] B_18 = B;
+wire [17:0] A_18 = A;
+wire [24:0] B_25 = B;
 wire [47:0] Y_48;
 assign Y = Y_48;
 
@@ -26,7 +25,7 @@ initial begin
 		_TECHMAP_FAIL_ <= 1;
 	if (A_WIDTH < 4 || B_WIDTH < 4)
 		_TECHMAP_FAIL_ <= 1;
-	if (A_WIDTH > 25 || B_WIDTH > 18)
+	if (A_WIDTH > 18 || B_WIDTH > 25)
 		_TECHMAP_FAIL_ <= 1;
 	if (A_WIDTH*B_WIDTH < 100)
 		_TECHMAP_FAIL_ <= 1;
@@ -39,8 +38,8 @@ end
 	.B_WIDTH(B_WIDTH),
 	.Y_WIDTH(Y_WIDTH)
 ) _TECHMAP_REPLACE_ (
-	.A(A_25),
-	.B(B_18),
+	.A(A_18),
+	.B(B_25),
 	.Y(Y_48)
 );
 
@@ -88,4 +87,3 @@ end
 );
 
 endmodule
-
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
index 15bd04ed1..06372f5af 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
@@ -1,7 +1,7 @@
 module DSP48_MACC (a, b, c, y);
 
-input [24:0] a;
-input [17:0] b;
+input [17:0] a;
+input [24:0] b;
 input [47:0] c;
 output [47:0] y;
 
-- 
cgit v1.2.3