From f092b5014895dc5dc62b8103fcedf94cfa9f85a8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 14:11:40 +0200 Subject: Renamed $_INV_ cell type to $_NOT_ --- manual/CHAPTER_StateOfTheArt/simlib_yosys.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'manual/CHAPTER_StateOfTheArt') diff --git a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v index a2df8f648..54c076614 100644 --- a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v +++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v @@ -20,12 +20,12 @@ * The internal logic cell simulation library. * * This verilog library contains simple simulation models for the internal - * logic cells (_INV_, _AND_, ...) that are generated by the default technology + * logic cells (_NOT_, _AND_, ...) that are generated by the default technology * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. * */ -module _INV_(A, Y); +module _NOT_(A, Y); input A; output Y; assign Y = ~A; -- cgit v1.2.3