From 9c1e578afe6af40be4600c20c883fa016fc7fa26 Mon Sep 17 00:00:00 2001
From: "Anthony J. Bentley" <anthony@cathet.us>
Date: Fri, 11 Apr 2014 02:42:59 -0600
Subject: Typos and grammar fixes through chapter 2.

---
 manual/CHAPTER_Intro.tex | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'manual/CHAPTER_Intro.tex')

diff --git a/manual/CHAPTER_Intro.tex b/manual/CHAPTER_Intro.tex
index 675d24026..f735d46b2 100644
--- a/manual/CHAPTER_Intro.tex
+++ b/manual/CHAPTER_Intro.tex
@@ -45,7 +45,7 @@ researched field. All the information required to write such tools has been open
 available for a long time, and it is therefore likely that a FOSS HDL synthesis tool
 with a feature-complete Verilog or VHDL front end must exist which can be used as a basis for a custom RTL synthesis tool.
 
-Due to the authors preference for Verilog over VHDL it has been decided early
+Due to the author's preference for Verilog over VHDL it was decided early
 on to go for Verilog instead of VHDL\footnote{A quick investigation into FOSS
 VHDL tools yielded similar grim results for FOSS VHDL synthesis tools.}.
 So the existing FOSS Verilog synthesis tools were evaluated (see
@@ -56,12 +56,12 @@ is discussed in this document.
 
 \section{Structure of this Document}
 
-The structure of this document is a follows:
+The structure of this document is as follows:
 
 Chapter~\ref{chapter:intro} is this introduction.
 
 Chapter~\ref{chapter:basics} covers a short introduction to the world of HDL
-synthesis. Basic principles and the terminology is outlined in this chapter.
+synthesis. Basic principles and the terminology are outlined in this chapter.
 
 Chapter~\ref{chapter:approach} gives the quickest possible outline to how the
 problem of implementing a HDL synthesis tool is approached in the case of
@@ -82,7 +82,7 @@ Yosys source code. The chapter concludes with an example loadable module
 for Yosys.
 
 Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} 
-cover three improtant pieces of the synthesis pileline: The Verilog frontend,
+cover three important pieces of the synthesis pipeline: The Verilog frontend,
 the optimization passes and the technology mapping to the target architecture,
 respectively.
 
-- 
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