From 73e0e13d2f1b959a05d69ed715c8fdde84894d6f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 16 Jul 2014 11:38:02 +0200
Subject: Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal

---
 manual/CHAPTER_CellLib.tex | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'manual/CHAPTER_CellLib.tex')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index e7895521a..f09c49298 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -256,8 +256,9 @@ If this parameter is set to {\tt 1'b1}, a read and write to the same address in
 return the new value. Otherwise the old value is returned.
 \end{itemize}
 
-The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN}, an address input \B{ADDR}
-and a data input \B{DATA}. They also have the following parameters:
+The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN} (one
+enable bit for each data bit), an address input \B{ADDR} and a data input
+\B{DATA}. They also have the following parameters:
 
 \begin{itemize}
 \item \B{MEMID} \\
@@ -341,7 +342,7 @@ This input is \B{RD\_PORTS}*\B{WIDTH} bits wide, containing all data signals for
 This input is \B{WR\_PORTS} bits wide, containing all clock signals for the write ports.
 
 \item \B{WR\_EN} \\
-This input is \B{WR\_PORTS} bits wide, containing all enable signals for the write ports.
+This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all enable signals for the write ports.
 
 \item \B{WR\_ADDR} \\
 This input is \B{WR\_PORTS}*\B{ABITS} bits wide, containing all address signals for the write ports.
-- 
cgit v1.2.3

