From e97e33d00df9d702643a82152aa1becc611ef823 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 4 Dec 2019 11:59:36 +0000
Subject: kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.

Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
---
 kernel/rtlil.cc | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index bd2fd91a3..7c73f94c8 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -783,6 +783,14 @@ namespace {
 			return v;
 		}
 
+		int param_bool(RTLIL::IdString name, bool expected)
+		{
+			int v = param_bool(name);
+			if (v != expected)
+				error(__LINE__);
+			return v;
+		}
+
 		void param_bits(RTLIL::IdString name, int width)
 		{
 			param(name);
@@ -869,13 +877,23 @@ namespace {
 				return;
 			}
 
-			if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
+			if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
+				param_bool(ID(A_SIGNED));
+				param_bool(ID(B_SIGNED), /*expected=*/false);
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
+				check_expected(/*check_matched_sign=*/false);
+				return;
+			}
+
+			if (cell->type.in(ID($shift), ID($shiftx))) {
 				param_bool(ID(A_SIGNED));
 				param_bool(ID(B_SIGNED));
 				port(ID::A, param(ID(A_WIDTH)));
 				port(ID::B, param(ID(B_WIDTH)));
 				port(ID::Y, param(ID(Y_WIDTH)));
-				check_expected(false);
+				check_expected(/*check_matched_sign=*/false);
 				return;
 			}
 
@@ -957,7 +975,7 @@ namespace {
 				port(ID::A, param(ID(A_WIDTH)));
 				port(ID::B, param(ID(B_WIDTH)));
 				port(ID::Y, param(ID(Y_WIDTH)));
-				check_expected(false);
+				check_expected(/*check_matched_sign=*/false);
 				return;
 			}
 
-- 
cgit v1.2.3


From 3edb2e708b09c7c9ead2aeb11e2be3cae88f8ee5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 2 Jan 2020 18:58:45 +0100
Subject: Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/rtlil.cc | 29 +++++++++++++++++++++++++----
 1 file changed, 25 insertions(+), 4 deletions(-)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7c73f94c8..ab4f4f377 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1893,10 +1893,6 @@ DEF_METHOD(And,      max(sig_a.size(), sig_b.size()), ID($and))
 DEF_METHOD(Or,       max(sig_a.size(), sig_b.size()), ID($or))
 DEF_METHOD(Xor,      max(sig_a.size(), sig_b.size()), ID($xor))
 DEF_METHOD(Xnor,     max(sig_a.size(), sig_b.size()), ID($xnor))
-DEF_METHOD(Shl,      sig_a.size(), ID($shl))
-DEF_METHOD(Shr,      sig_a.size(), ID($shr))
-DEF_METHOD(Sshl,     sig_a.size(), ID($sshl))
-DEF_METHOD(Sshr,     sig_a.size(), ID($sshr))
 DEF_METHOD(Shift,    sig_a.size(), ID($shift))
 DEF_METHOD(Shiftx,   sig_a.size(), ID($shiftx))
 DEF_METHOD(Lt,       1, ID($lt))
@@ -1916,6 +1912,31 @@ DEF_METHOD(LogicAnd, 1, ID($logic_and))
 DEF_METHOD(LogicOr,  1, ID($logic_or))
 #undef DEF_METHOD
 
+#define DEF_METHOD(_func, _y_size, _type) \
+	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
+		RTLIL::Cell *cell = addCell(name, _type);           \
+		cell->parameters[ID(A_SIGNED)] = is_signed;         \
+		cell->parameters[ID(B_SIGNED)] = false;             \
+		cell->parameters[ID(A_WIDTH)] = sig_a.size();       \
+		cell->parameters[ID(B_WIDTH)] = sig_b.size();       \
+		cell->parameters[ID(Y_WIDTH)] = sig_y.size();       \
+		cell->setPort(ID::A, sig_a);                        \
+		cell->setPort(ID::B, sig_b);                        \
+		cell->setPort(ID::Y, sig_y);                        \
+		cell->set_src_attribute(src);                       \
+		return cell;                                        \
+	} \
+	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
+		RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);         \
+		add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
+		return sig_y;                                            \
+	}
+DEF_METHOD(Shl,      sig_a.size(), ID($shl))
+DEF_METHOD(Shr,      sig_a.size(), ID($shr))
+DEF_METHOD(Sshl,     sig_a.size(), ID($sshl))
+DEF_METHOD(Sshr,     sig_a.size(), ID($sshr))
+#undef DEF_METHOD
+
 #define DEF_METHOD(_func, _type, _pmux) \
 	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
 		RTLIL::Cell *cell = addCell(name, _type);                 \
-- 
cgit v1.2.3


From a63e2508fcca395e795029d5c57c59acc63a9959 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 12:52:03 -0800
Subject: Add RTLIL::constpad, init by yosys_setup(); use for abc9

---
 kernel/rtlil.cc | 1 +
 kernel/rtlil.h  | 2 ++
 kernel/yosys.cc | 9 +++++++++
 3 files changed, 12 insertions(+)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ab4f4f377..f286d139f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -46,6 +46,7 @@ IdString RTLIL::ID::Y;
 IdString RTLIL::ID::keep;
 IdString RTLIL::ID::whitebox;
 IdString RTLIL::ID::blackbox;
+dict<std::string, std::string> RTLIL::constpad;
 
 RTLIL::Const::Const()
 {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index e5b24cc02..6251d265d 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -377,6 +377,8 @@ namespace RTLIL
 		extern IdString blackbox;
 	};
 
+	extern dict<std::string, std::string> constpad;
+
 	static inline std::string escape_id(std::string str) {
 		if (str.size() > 0 && str[0] != '\\' && str[0] != '$')
 			return "\\" + str;
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 5018a4888..6c8427c19 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -524,6 +524,15 @@ void yosys_setup()
 		PyRun_SimpleString("import sys");
 	#endif
 
+	RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -v; &mfs";
+	RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -a -v; &mfs";
+	RTLIL::constpad["abc9.script.default.fast"] = "&if {W} {D}";
+	RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
+		"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} -v; &save; &load; "\
+		"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} -v; &save; &load; "\
+		"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} -v; &save; &load; "\
+		"&mfs";
+
 	Pass::init_register();
 	yosys_design = new RTLIL::Design;
 	yosys_celltypes.setup();
-- 
cgit v1.2.3


From fbd9636e08b9a4ac5e58161ca6a6b5308cd795cb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 8 Jan 2020 12:15:01 -0800
Subject: Add abc9.if.script.flow{,2} to constpad

---
 kernel/yosys.cc | 38 ++++++++++++++++++++++++++++++++------
 1 file changed, 32 insertions(+), 6 deletions(-)

(limited to 'kernel')

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 6c8427c19..cd6955c3f 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -524,13 +524,39 @@ void yosys_setup()
 		PyRun_SimpleString("import sys");
 	#endif
 
-	RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -v; &mfs";
-	RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -a -v; &mfs";
-	RTLIL::constpad["abc9.script.default.fast"] = "&if {W} {D}";
+	RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
+	RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
+	RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
+	// Based on ABC's &flow
+	RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
+		/* Round 1 */ \
+		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+		"&st; &dsdb;" \
+		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+		"&st; &syn2 -m -R 10; &dsdb;" \
+		"&blut -a -K 6;" \
+		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+		/* Round 2 */ \
+		"&st; &sopb;" \
+		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+		"&st; &dsdb;" \
+		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+		"&st; &syn2 -m -R 10; &dsdb;" \
+		"&blut -a -K 6;" \
+		"&unmap; &if {C} {W} {D} {R} -v; &mfs";
+	// Based on ABC's &flow2
+	RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
+		/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+		/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+		"&load; &st; &sopb -R 10 -C 4; " \
+		/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+		/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
+		"&load";
+	// Based on ABC's &flow3
 	RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
-		"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} -v; &save; &load; "\
-		"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} -v; &save; &load; "\
-		"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} -v; &save; &load; "\
+		"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
+		"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
+		"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
 		"&mfs";
 
 	Pass::init_register();
-- 
cgit v1.2.3


From cd92a974f4cf8d4db74d504c38e51ce043e02403 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 9 Jan 2020 21:36:34 +0100
Subject: Add Pass::on_register() and Pass::on_shutdown()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/register.cc | 15 +++++++++++++++
 kernel/register.h  |  3 +++
 kernel/yosys.cc    |  3 ++-
 3 files changed, 20 insertions(+), 1 deletion(-)

(limited to 'kernel')

diff --git a/kernel/register.cc b/kernel/register.cc
index 37f2e5e1b..5d0fb3c8c 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -114,20 +114,35 @@ void Pass::run_register()
 
 void Pass::init_register()
 {
+	vector<Pass*> added_passes;
 	while (first_queued_pass) {
+		added_passes.push_back(first_queued_pass);
 		first_queued_pass->run_register();
 		first_queued_pass = first_queued_pass->next_queued_pass;
 	}
+	for (auto added_pass : added_passes)
+		added_pass->on_register();
 }
 
 void Pass::done_register()
 {
+	for (auto &it : pass_register)
+		it.second->on_shutdown();
+
 	frontend_register.clear();
 	pass_register.clear();
 	backend_register.clear();
 	log_assert(first_queued_pass == NULL);
 }
 
+void Pass::on_register()
+{
+}
+
+void Pass::on_shutdown()
+{
+}
+
 Pass::~Pass()
 {
 }
diff --git a/kernel/register.h b/kernel/register.h
index 85d552f0d..821faff3e 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -62,6 +62,9 @@ struct Pass
 	virtual void run_register();
 	static void init_register();
 	static void done_register();
+
+	virtual void on_register();
+	virtual void on_shutdown();
 };
 
 struct ScriptPass : Pass
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 5018a4888..8190d8902 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -544,6 +544,8 @@ void yosys_shutdown()
 	already_shutdown = true;
 	log_pop();
 
+	Pass::done_register();
+
 	delete yosys_design;
 	yosys_design = NULL;
 
@@ -553,7 +555,6 @@ void yosys_shutdown()
 	log_errfile = NULL;
 	log_files.clear();
 
-	Pass::done_register();
 	yosys_celltypes.clear();
 
 #ifdef YOSYS_ENABLE_TCL
-- 
cgit v1.2.3


From 67c9c41f7e566f5604a3e38e7ad402d6b5c80fd8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 17:10:54 -0800
Subject: Move abc9.* constpad entries to Abc9Pass::on_register()

---
 kernel/yosys.cc | 35 -----------------------------------
 1 file changed, 35 deletions(-)

(limited to 'kernel')

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 6956cbdc3..8190d8902 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -524,41 +524,6 @@ void yosys_setup()
 		PyRun_SimpleString("import sys");
 	#endif
 
-	RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
-	RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
-	RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
-	// Based on ABC's &flow
-	RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
-		/* Round 1 */ \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		"&st; &dsdb;" \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		"&st; &syn2 -m -R 10; &dsdb;" \
-		"&blut -a -K 6;" \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		/* Round 2 */ \
-		"&st; &sopb;" \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		"&st; &dsdb;" \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		"&st; &syn2 -m -R 10; &dsdb;" \
-		"&blut -a -K 6;" \
-		"&unmap; &if {C} {W} {D} {R} -v; &mfs";
-	// Based on ABC's &flow2
-	RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
-		/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-		/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-		"&load; &st; &sopb -R 10 -C 4; " \
-		/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-		/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
-		"&load";
-	// Based on ABC's &flow3
-	RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
-		"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
-		"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
-		"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
-		"&mfs";
-
 	Pass::init_register();
 	yosys_design = new RTLIL::Design;
 	yosys_celltypes.setup();
-- 
cgit v1.2.3


From a901a5fb44f146415ff45f9fed3f89ca3786b0da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 11:25:23 -0800
Subject: print_stats footer to return peak memory, option for including
 children

---
 kernel/driver.cc | 40 ++++++++++++----------------------------
 1 file changed, 12 insertions(+), 28 deletions(-)

(limited to 'kernel')

diff --git a/kernel/driver.cc b/kernel/driver.cc
index 70a97c4b9..cf676a591 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -564,39 +564,23 @@ int main(int argc, char **argv)
 #ifdef _WIN32
 		log("End of script. Logfile hash: %s\n", hash.c_str());
 #else
-		std::string meminfo;
 		std::string stats_divider = ", ";
-#  if defined(__linux__)
-		std::ifstream statm;
-		statm.open(stringf("/proc/%lld/statm", (long long)getpid()));
-		if (statm.is_open()) {
-			int sz_total, sz_resident;
-			statm >> sz_total >> sz_resident;
-			meminfo = stringf(", MEM: %.2f MB total, %.2f MB resident",
-					sz_total * (getpagesize() / 1024.0 / 1024.0),
-					sz_resident * (getpagesize() / 1024.0 / 1024.0));
-			stats_divider = "\n";
-		}
-#  elif defined(__FreeBSD__)
-		pid_t pid = getpid();
-		int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PID, (int)pid};
-		struct kinfo_proc kip;
-		size_t kip_len = sizeof(kip);
-		if (sysctl(mib, 4, &kip, &kip_len, NULL, 0) == 0) {
-			vm_size_t sz_total = kip.ki_size;
-			segsz_t sz_resident = kip.ki_rssize;
-			meminfo = stringf(", MEM: %.2f MB total, %.2f MB resident",
-				(int)sz_total / 1024.0 / 1024.0,
-				(int)sz_resident * (getpagesize() / 1024.0 / 1024.0));
-			stats_divider = "\n";
-		}
-#  endif
 
 		struct rusage ru_buffer;
 		getrusage(RUSAGE_SELF, &ru_buffer);
-		log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash.c_str(),
+		if (yosys_design->scratchpad_get_bool("print_stats.include_children")) {
+			struct rusage ru_buffer_children;
+			getrusage(RUSAGE_CHILDREN, &ru_buffer_children);
+			ru_buffer.ru_utime.tv_sec += ru_buffer_children.ru_utime.tv_sec;
+			ru_buffer.ru_utime.tv_usec += ru_buffer_children.ru_utime.tv_usec;
+			ru_buffer.ru_stime.tv_sec += ru_buffer_children.ru_stime.tv_sec;
+			ru_buffer.ru_stime.tv_usec += ru_buffer_children.ru_stime.tv_usec;
+			ru_buffer.ru_maxrss = std::max(ru_buffer.ru_maxrss, ru_buffer_children.ru_maxrss);
+		}
+		log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs, MEM: %.2f MB peak\n", hash.c_str(),
 				stats_divider.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec,
-				ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec, meminfo.c_str());
+				ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec,
+				ru_buffer.ru_maxrss / 1024.0);
 #endif
 		log("%s\n", yosys_version_str);
 
-- 
cgit v1.2.3


From ade57058f70590bb8353eda32d9b961a31c61fbc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 11:38:48 -0800
Subject: As before, only display MEM if Linux or FreeBSD

---
 kernel/driver.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'kernel')

diff --git a/kernel/driver.cc b/kernel/driver.cc
index cf676a591..f0d495b46 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -564,6 +564,7 @@ int main(int argc, char **argv)
 #ifdef _WIN32
 		log("End of script. Logfile hash: %s\n", hash.c_str());
 #else
+		std::string meminfo;
 		std::string stats_divider = ", ";
 
 		struct rusage ru_buffer;
@@ -577,10 +578,13 @@ int main(int argc, char **argv)
 			ru_buffer.ru_stime.tv_usec += ru_buffer_children.ru_stime.tv_usec;
 			ru_buffer.ru_maxrss = std::max(ru_buffer.ru_maxrss, ru_buffer_children.ru_maxrss);
 		}
-		log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs, MEM: %.2f MB peak\n", hash.c_str(),
-				stats_divider.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec,
-				ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec,
+#  if defined(__linux__) || defined(__FreeBSD__)
+		meminfo = stringf(", MEM: %.2f MB peak",
 				ru_buffer.ru_maxrss / 1024.0);
+#endif
+		log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash.c_str(),
+				stats_divider.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec,
+				ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec, meminfo.c_str());
 #endif
 		log("%s\n", yosys_version_str);
 
-- 
cgit v1.2.3