From 25ff27e37fcb12c6a298267eda2464431304d713 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 12:34:04 -0700 Subject: SigSpec::extract to take negative lengths --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a09f4a0d1..85b013bdc 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3353,7 +3353,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector(bits_.begin() + offset, bits_.begin() + offset + length); + return std::vector(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) -- cgit v1.2.3 From 54708dfbd786032e841f48f15af4875c1eabbbfe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 13:54:57 -0700 Subject: Add an SigSpec::at(offset, defval) convenience method --- kernel/rtlil.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 82cbfaf28..f9412e776 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -818,6 +818,7 @@ public: operator std::vector() const { return chunks(); } operator std::vector() const { return bits(); } + RTLIL::SigBit at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; } unsigned int hash() const { if (!hash_) updhash(); return hash_; }; -- cgit v1.2.3 From 95a6582f342537d387063be10cba55c001ed19f5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 6 Aug 2019 19:21:37 +0200 Subject: Be less aggressive with running design->check() Signed-off-by: Clifford Wolf --- kernel/driver.cc | 6 ++++++ kernel/register.cc | 10 +++------- kernel/yosys.cc | 10 ++++++++-- 3 files changed, 17 insertions(+), 9 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index f273057dd..70a97c4b9 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -522,6 +522,12 @@ int main(int argc, char **argv) if (!backend_command.empty()) run_backend(output_filename, backend_command); + yosys_design->check(); + for (auto it : saved_designs) + it.second->check(); + for (auto it : pushed_designs) + it->check(); + if (!depsfile.empty()) { FILE *f = fopen(depsfile.c_str(), "wt"); diff --git a/kernel/register.cc b/kernel/register.cc index 4c6e3591f..8f8f2c971 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -256,8 +256,6 @@ void Pass::call(RTLIL::Design *design, std::vector args) pass_register[args[0]]->post_execute(state); while (design->selection_stack.size() > orig_sel_stack_pos) design->selection_stack.pop_back(); - - design->check(); } void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command) @@ -339,8 +337,10 @@ void ScriptPass::run(std::string command, std::string info) log(" %s\n", command.c_str()); else log(" %s %s\n", command.c_str(), info.c_str()); - } else + } else { Pass::call(active_design, command); + active_design->check(); + } } void ScriptPass::run_script(RTLIL::Design *design, std::string run_from, std::string run_to) @@ -534,8 +534,6 @@ void Frontend::frontend_call(RTLIL::Design *design, std::istream *f, std::string args.push_back(filename); frontend_register[args[0]]->execute(args, design); } - - design->check(); } Backend::Backend(std::string name, std::string short_help) : @@ -645,8 +643,6 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f while (design->selection_stack.size() > orig_sel_stack_pos) design->selection_stack.pop_back(); - - design->check(); } static struct CellHelpMessages { diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 191b6d5c7..a4cc53f1a 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -964,14 +964,18 @@ void run_frontend(std::string filename, std::string command, std::string *backen command += next_line; } handle_label(command, from_to_active, run_from, run_to); - if (from_to_active) + if (from_to_active) { Pass::call(design, command); + design->check(); + } } if (!command.empty()) { handle_label(command, from_to_active, run_from, run_to); - if (from_to_active) + if (from_to_active) { Pass::call(design, command); + design->check(); + } } } catch (...) { @@ -1000,6 +1004,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen Pass::call(design, vector({command, filename})); else Frontend::frontend_call(design, NULL, filename, command); + design->check(); } void run_frontend(std::string filename, std::string command, RTLIL::Design *design) @@ -1183,6 +1188,7 @@ void shell(RTLIL::Design *design) design->selection_stack.pop_back(); log_reset_stack(); } + design->check(); } if (command == NULL) printf("exit\n"); -- cgit v1.2.3 From 0b56be8c5634f8b953cd3d087b4b6e2a11a2c173 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 15:24:55 -0700 Subject: Restore original SigSpec::extract() --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f2c81db72..ba8472ec1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3355,7 +3355,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); + return std::vector(bits_.begin() + offset, bits_.begin() + offset + length); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) -- cgit v1.2.3 From 84f52aee0d01378796792c9a2f068a22d955f586 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 15:25:11 -0700 Subject: Add SigSpec::extract_end() convenience function --- kernel/rtlil.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 633cb51d6..c07d39c65 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -788,6 +788,7 @@ public: RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(int offset, int length = 1) const; + RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); } void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); -- cgit v1.2.3 From 100c377451f18503fd85112d62d11ebdb6ac9d5a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 7 Aug 2019 01:12:14 +0200 Subject: Redesign of cell cost API Signed-off-by: Clifford Wolf --- kernel/cost.h | 148 ++++++++++++++++++++++++++++++---------------------------- 1 file changed, 77 insertions(+), 71 deletions(-) (limited to 'kernel') diff --git a/kernel/cost.h b/kernel/cost.h index e8e077ff5..7ff11eba2 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -24,86 +24,92 @@ YOSYS_NAMESPACE_BEGIN -int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache = nullptr, bool cmos_cost = false); - -inline int get_cell_cost(RTLIL::IdString type, const dict ¶meters = dict(), - RTLIL::Design *design = nullptr, dict *mod_cost_cache = nullptr, bool cmos_cost = false) +struct CellCosts { - static dict gate_cost = { - { "$_BUF_", 1 }, - { "$_NOT_", 2 }, - { "$_AND_", 4 }, - { "$_NAND_", 4 }, - { "$_OR_", 4 }, - { "$_NOR_", 4 }, - { "$_ANDNOT_", 4 }, - { "$_ORNOT_", 4 }, - { "$_XOR_", 8 }, - { "$_XNOR_", 8 }, - { "$_AOI3_", 6 }, - { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, - { "$_MUX_", 4 }, - { "$_NMUX_", 4 } - }; - - // match costs in "stat -tech cmos" - static dict cmos_gate_cost = { - { "$_BUF_", 1 }, - { "$_NOT_", 2 }, - { "$_AND_", 6 }, - { "$_NAND_", 4 }, - { "$_OR_", 6 }, - { "$_NOR_", 4 }, - { "$_ANDNOT_", 6 }, - { "$_ORNOT_", 6 }, - { "$_XOR_", 12 }, - { "$_XNOR_", 12 }, - { "$_AOI3_", 6 }, - { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, - { "$_MUX_", 12 }, - { "$_NMUX_", 10 } - }; - - if (cmos_cost && cmos_gate_cost.count(type)) - return cmos_gate_cost.at(type); - - if (gate_cost.count(type)) - return gate_cost.at(type); - - if (parameters.empty() && design && design->module(type)) + static const dict& default_gate_cost() { + static const dict db = { + { "$_BUF_", 1 }, + { "$_NOT_", 2 }, + { "$_AND_", 4 }, + { "$_NAND_", 4 }, + { "$_OR_", 4 }, + { "$_NOR_", 4 }, + { "$_ANDNOT_", 4 }, + { "$_ORNOT_", 4 }, + { "$_XOR_", 6 }, + { "$_XNOR_", 6 }, + { "$_AOI3_", 6 }, + { "$_OAI3_", 6 }, + { "$_AOI4_", 8 }, + { "$_OAI4_", 8 }, + { "$_MUX_", 4 }, + { "$_NMUX_", 4 } + }; + return db; + } + + static const dict& cmos_gate_cost() { + static const dict db = { + { "$_BUF_", 1 }, + { "$_NOT_", 2 }, + { "$_AND_", 6 }, + { "$_NAND_", 4 }, + { "$_OR_", 6 }, + { "$_NOR_", 4 }, + { "$_ANDNOT_", 6 }, + { "$_ORNOT_", 6 }, + { "$_XOR_", 12 }, + { "$_XNOR_", 12 }, + { "$_AOI3_", 6 }, + { "$_OAI3_", 6 }, + { "$_AOI4_", 8 }, + { "$_OAI4_", 8 }, + { "$_MUX_", 12 }, + { "$_NMUX_", 10 } + }; + return db; + } + + dict mod_cost_cache; + const dict *gate_cost = nullptr; + Design *design = nullptr; + + int get(RTLIL::IdString type) const { - RTLIL::Module *mod = design->module(type); + if (gate_cost && gate_cost->count(type)) + return gate_cost->at(type); - if (mod->attributes.count("\\cost")) - return mod->attributes.at("\\cost").as_int(); + log_warning("Can't determine cost of %s cell.\n", log_id(type)); + return 1; + } - dict local_mod_cost_cache; - if (mod_cost_cache == nullptr) - mod_cost_cache = &local_mod_cost_cache; + int get(RTLIL::Cell *cell) + { + if (gate_cost && gate_cost->count(cell->type)) + return gate_cost->at(cell->type); - if (mod_cost_cache->count(mod->name)) - return mod_cost_cache->at(mod->name); + if (design && design->module(cell->type) && cell->parameters.empty()) + { + RTLIL::Module *mod = design->module(cell->type); - int module_cost = 1; - for (auto c : mod->cells()) - module_cost += get_cell_cost(c, mod_cost_cache); + if (mod->attributes.count("\\cost")) + return mod->attributes.at("\\cost").as_int(); - (*mod_cost_cache)[mod->name] = module_cost; - return module_cost; - } + if (mod_cost_cache.count(mod->name)) + return mod_cost_cache.at(mod->name); - log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters)); - return 1; -} + int module_cost = 1; + for (auto c : mod->cells()) + module_cost += get(c); -inline int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache, bool cmos_cost) -{ - return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache, cmos_cost); -} + mod_cost_cache[mod->name] = module_cost; + return module_cost; + } + + log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters)); + return 1; + } +}; YOSYS_NAMESPACE_END -- cgit v1.2.3 From 338f6765ebeb6bd07197dbef8e22fa077bf2d043 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 7 Aug 2019 10:25:51 +0200 Subject: Tweak default gate costs, cleanup "stat -tech cmos" Signed-off-by: Clifford Wolf --- kernel/cost.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/cost.h b/kernel/cost.h index 7ff11eba2..10fa50fb3 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -36,12 +36,12 @@ struct CellCosts { "$_NOR_", 4 }, { "$_ANDNOT_", 4 }, { "$_ORNOT_", 4 }, - { "$_XOR_", 6 }, - { "$_XNOR_", 6 }, + { "$_XOR_", 5 }, + { "$_XNOR_", 5 }, { "$_AOI3_", 6 }, { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, + { "$_AOI4_", 7 }, + { "$_OAI4_", 7 }, { "$_MUX_", 4 }, { "$_NMUX_", 4 } }; -- cgit v1.2.3