From 483c99fe46d6b1cd35abddd38a629d30e13289b4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Feb 2014 23:28:59 +0100 Subject: Added "design -push" and "design -pop" --- kernel/register.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'kernel') diff --git a/kernel/register.h b/kernel/register.h index 83e1059c6..b582f98c9 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -40,6 +40,10 @@ std::string rewrite_yosys_exe(std::string exe); std::string get_share_file_name(std::string file); const char *create_prompt(RTLIL::Design *design, int recursion_counter); +// from passes/cmds/design.cc +extern std::map saved_designs; +extern std::vector pushed_designs; + struct Pass { std::string pass_name, short_help; -- cgit v1.2.3 From b76528d8a557dc324b1dfaa366e2b620795f582d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 23 Feb 2014 01:28:29 +0100 Subject: Fixed small memory leak in Pass::call() --- kernel/register.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 325709664..ee14ffbad 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -133,8 +133,10 @@ void Pass::call(RTLIL::Design *design, std::string command) std::vector args; char *s = strdup(command.c_str()), *sstart = s, *saveptr; s += strspn(s, " \t\r\n"); - if (*s == 0 || *s == '#') + if (*s == 0 || *s == '#') { + free(sstart); return; + } if (*s == '!') { for (s++; *s == ' ' || *s == '\t'; s++) { } char *p = s + strlen(s) - 1; @@ -144,6 +146,7 @@ void Pass::call(RTLIL::Design *design, std::string command) int retCode = system(s); if (retCode != 0) log_cmd_error("Shell command returned error code %d.\n", retCode); + free(sstart); return; } for (char *p = strtok_r(s, " \t\r\n", &saveptr); p; p = strtok_r(NULL, " \t\r\n", &saveptr)) { -- cgit v1.2.3 From dab1612f81212d1bc1c07ee77b265167861ec883 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 23 Feb 2014 01:35:59 +0100 Subject: Added support for Minisat::SimpSolver + ezSAT frezze() API --- kernel/satgen.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index 840700cbd..539210442 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -72,6 +72,7 @@ struct SatGen } else { std::string name = pf + stringf(c.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset); vec.push_back(ez->literal(name)); + ez->freeze(vec.back()); } return vec; } -- cgit v1.2.3 From aaaa604853caaecf8dcbfa928914495efb5556c6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 26 Feb 2014 21:31:34 +0100 Subject: Added support for $bu0 to SatGen --- kernel/satgen.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index 539210442..d9bcb4250 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -385,7 +385,7 @@ struct SatGen return true; } - if (cell->type == "$pos" || cell->type == "$neg") + if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") { std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); @@ -393,7 +393,7 @@ struct SatGen std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == "$pos") { + if (cell->type == "$pos" || cell->type == "$bu0") { ez->assume(ez->vec_eq(a, yy)); } else { std::vector zero(a.size(), ez->FALSE); @@ -404,9 +404,9 @@ struct SatGen { std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); - extendSignalWidthUnary(undef_a, undef_y, cell, true); + extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0"); - if (cell->type == "$pos") { + if (cell->type == "$pos" || cell->type == "$bu0") { ez->assume(ez->vec_eq(undef_a, undef_y)); } else { int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); -- cgit v1.2.3 From 9e9998433616f438cb0185519bb5b7f8e1a8f543 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 27 Feb 2014 04:09:32 +0100 Subject: Fixed const folding of $bu0 cells --- kernel/celltypes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 34a6e56fa..4a600af9d 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -216,7 +216,7 @@ struct CellTypes type = "$shl"; if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && - type != "$pos" && type != "$neg" && type != "$not") { + type != "$pos" && type != "$neg" && type != "$not" && type != "$bu0") { if (!signed1 || !signed2) signed1 = false, signed2 = false; } -- cgit v1.2.3 From a1bfde8c5ea0d5c9778579bf78165637ac6c9b25 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 6 Mar 2014 11:53:37 +0100 Subject: Strictly zero-extend unsigned A-inputs of shift operations --- kernel/calc.cc | 4 ++-- kernel/satgen.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/calc.cc b/kernel/calc.cc index a56db93aa..749589f20 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -305,14 +305,14 @@ static RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &ar RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; - extend(arg1_ext, result_len, signed1); + extend_u0(arg1_ext, result_len, signed1); return const_shift(arg1_ext, arg2, false, -1, result_len); } RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; - extend(arg1_ext, result_len, signed1); + extend_u0(arg1_ext, result_len, signed1); return const_shift(arg1_ext, arg2, false, +1, result_len); } diff --git a/kernel/satgen.h b/kernel/satgen.h index d9bcb4250..3ae9502f8 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -634,7 +634,7 @@ struct SatGen while (undef_y.size() < undef_a.size()) undef_y.push_back(ez->literal()); while (undef_y.size() > undef_a.size()) - undef_a.push_back(undef_a.back()); + undef_a.push_back(cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE); tmp = undef_a; for (size_t i = 0; i < b.size(); i++) -- cgit v1.2.3 From 97710ffad5d4750b538dac5f08b77dce37e3cda4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 6 Mar 2014 13:08:44 +0100 Subject: Fixed use of frozen literals in SatGen --- kernel/satgen.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index 3ae9502f8..bf72a31cb 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -66,13 +66,12 @@ struct SatGen if (c.wire == NULL) { RTLIL::State bit = c.data.bits.at(0); if (model_undef && dup_undef && bit == RTLIL::State::Sx) - vec.push_back(ez->literal()); + vec.push_back(ez->frozen_literal()); else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->TRUE : ez->FALSE); } else { std::string name = pf + stringf(c.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset); - vec.push_back(ez->literal(name)); - ez->freeze(vec.back()); + vec.push_back(ez->frozen_literal(name)); } return vec; } -- cgit v1.2.3 From fdef064b1d8bbaff8d8f3f2dbf728132ef463010 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 10 Mar 2014 03:02:27 +0100 Subject: Added RTLIL::Module::add... helper methods --- kernel/rtlil.cc | 236 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/rtlil.h | 57 ++++++++++++++ 2 files changed, 293 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 396eaf110..811289a4d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -844,6 +844,242 @@ void RTLIL::Module::fixup_ports() all_ports[i]->port_id = i+1; } + +#define DEF_METHOD(_func, _type) \ + RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->parameters["\\A_SIGNED"] = is_signed; \ + cell->parameters["\\A_WIDTH"] = sig_a.width; \ + cell->parameters["\\Y_WIDTH"] = sig_y.width; \ + cell->connections["\\A"] = sig_a; \ + cell->connections["\\Y"] = sig_y; \ + add(cell); \ + return cell; \ + } +DEF_METHOD(addNot, "$not") +DEF_METHOD(addPos, "$pos") +DEF_METHOD(addBu0, "$bu0") +DEF_METHOD(addNeg, "$neg") +DEF_METHOD(addReduceAnd, "$redcue_and") +DEF_METHOD(addReduceOr, "$redcue_or") +DEF_METHOD(addReduceXor, "$redcue_xor") +DEF_METHOD(addReduceXnor, "$redcue_xnor") +DEF_METHOD(addReduceBool, "$redcue_bool") +DEF_METHOD(addLogicNot, "$logic_not") +#undef DEF_METHOD + +#define DEF_METHOD(_func, _type) \ + RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->parameters["\\A_SIGNED"] = is_signed; \ + cell->parameters["\\B_SIGNED"] = is_signed; \ + cell->parameters["\\A_WIDTH"] = sig_a.width; \ + cell->parameters["\\B_WIDTH"] = sig_b.width; \ + cell->parameters["\\Y_WIDTH"] = sig_y.width; \ + cell->connections["\\A"] = sig_a; \ + cell->connections["\\B"] = sig_b; \ + cell->connections["\\Y"] = sig_y; \ + add(cell); \ + return cell; \ + } +DEF_METHOD(addAnd, "$and") +DEF_METHOD(addOr, "$or") +DEF_METHOD(addXor, "$xor") +DEF_METHOD(addXnor, "$xnor") +DEF_METHOD(addShl, "$shl") +DEF_METHOD(addShr, "$shr") +DEF_METHOD(addSshl, "$Sshl") +DEF_METHOD(addSshr, "$Sshr") +DEF_METHOD(addLt, "$lt") +DEF_METHOD(addLe, "$le") +DEF_METHOD(addEq, "$eq") +DEF_METHOD(addNe, "$ne") +DEF_METHOD(addEqx, "$eqx") +DEF_METHOD(addNex, "$nex") +DEF_METHOD(addGe, "$ge") +DEF_METHOD(addGt, "$gt") +DEF_METHOD(addAdd, "$add") +DEF_METHOD(addSub, "$sub") +DEF_METHOD(addMul, "$mul") +DEF_METHOD(addDiv, "$div") +DEF_METHOD(addMod, "$mod") +DEF_METHOD(addLogicAnd, "$logic_and") +DEF_METHOD(addLogicOr, "$logic_or") +#undef DEF_METHOD + +#define DEF_METHOD(_func, _type, _pmux) \ + RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->parameters["\\WIDTH"] = sig_a.width; \ + cell->parameters["\\WIDTH"] = sig_b.width; \ + if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.width; \ + cell->connections["\\A"] = sig_a; \ + cell->connections["\\B"] = sig_b; \ + cell->connections["\\S"] = sig_s; \ + cell->connections["\\Y"] = sig_y; \ + add(cell); \ + return cell; \ + } +DEF_METHOD(addMux, "$mux", 0) +DEF_METHOD(addPmux, "$pmux", 1) +DEF_METHOD(addSafePmux, "$safe_pmux", 1) +#undef DEF_METHOD + +RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$pow"; + cell->parameters["\\A_SIGNED"] = a_signed; + cell->parameters["\\B_SIGNED"] = b_signed; + cell->parameters["\\A_WIDTH"] = sig_a.width; + cell->parameters["\\B_WIDTH"] = sig_b.width; + cell->parameters["\\Y_WIDTH"] = sig_y.width; + cell->connections["\\A"] = sig_a; + cell->connections["\\B"] = sig_b; + cell->connections["\\Y"] = sig_y; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$slice"; + cell->parameters["\\A_WIDTH"] = sig_a.width; + cell->parameters["\\Y_WIDTH"] = sig_y.width; + cell->parameters["\\OFFSET"] = offset; + cell->connections["\\A"] = sig_a; + cell->connections["\\Y"] = sig_y; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$concat"; + cell->parameters["\\A_WIDTH"] = sig_a.width; + cell->parameters["\\B_WIDTH"] = sig_b.width; + cell->connections["\\A"] = sig_a; + cell->connections["\\B"] = sig_b; + cell->connections["\\Y"] = sig_y; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$lut"; + cell->parameters["\\LUT"] = lut; + cell->parameters["\\WIDTH"] = sig_i.width; + cell->connections["\\I"] = sig_i; + cell->connections["\\O"] = sig_o; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$assert"; + cell->connections["\\A"] = sig_a; + cell->connections["\\EN"] = sig_en; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$sr"; + cell->parameters["\\SET_POLARITY"] = set_polarity; + cell->parameters["\\CLR_POLARITY"] = clr_polarity; + cell->parameters["\\WIDTH"] = sig_q.width; + cell->connections["\\SET"] = sig_set; + cell->connections["\\CLR"] = sig_clr; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$dff"; + cell->parameters["\\CLK_POLARITY"] = clk_polarity; + cell->parameters["\\WIDTH"] = sig_q.width; + cell->connections["\\CLK"] = sig_clk; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, + RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$dffsr"; + cell->parameters["\\CLK_POLARITY"] = clk_polarity; + cell->parameters["\\SET_POLARITY"] = set_polarity; + cell->parameters["\\CLR_POLARITY"] = clr_polarity; + cell->parameters["\\WIDTH"] = sig_q.width; + cell->connections["\\CLK"] = sig_clk; + cell->connections["\\SET"] = sig_set; + cell->connections["\\CLR"] = sig_clr; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, + RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$dffsr"; + cell->parameters["\\CLK_POLARITY"] = clk_polarity; + cell->parameters["\\ARST_POLARITY"] = arst_polarity; + cell->parameters["\\ARST_VALUE"] = arst_value; + cell->parameters["\\WIDTH"] = sig_q.width; + cell->connections["\\CLK"] = sig_clk; + cell->connections["\\ARST"] = sig_arst; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addDlatch (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$dffsr"; + cell->parameters["\\EN_POLARITY"] = en_polarity; + cell->parameters["\\WIDTH"] = sig_q.width; + cell->connections["\\EN"] = sig_en; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + RTLIL::Wire::Wire() { width = 1; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index caadf1981..48f3e3921 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -294,6 +294,63 @@ struct RTLIL::Module { void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; + RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addBu0 (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + + RTLIL::Cell* addAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addXor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + + RTLIL::Cell* addReduceAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addReduceOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addReduceXor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + + RTLIL::Cell* addShl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addShr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addSshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addSshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + + RTLIL::Cell* addLt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addLe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addEq (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addNe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addEqx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addNex (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addGe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addGt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + + RTLIL::Cell* addAdd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addSub (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addMul (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addDiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addMod (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addPow (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false); + + RTLIL::Cell* addLogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addLogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addLogicOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + + RTLIL::Cell* addMux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); + RTLIL::Cell* addPmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); + RTLIL::Cell* addSafePmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); + + RTLIL::Cell* addSlice (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset); + RTLIL::Cell* addConcat (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); + RTLIL::Cell* addLut (RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut); + RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); + + RTLIL::Cell* addSr (RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true); + RTLIL::Cell* addDff (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true); + RTLIL::Cell* addDffsr (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, + RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true); + RTLIL::Cell* addAdff (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, + RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true); + RTLIL::Cell* addDlatch (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true); }; struct RTLIL::Wire { -- cgit v1.2.3 From 78c64a64017dbc3e15aeac3246d5fc159555fbe2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 10 Mar 2014 12:07:26 +0100 Subject: Fixed a typo in RTLIL::Module::addReduce... --- kernel/rtlil.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 811289a4d..21fcae2b5 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -862,11 +862,11 @@ DEF_METHOD(addNot, "$not") DEF_METHOD(addPos, "$pos") DEF_METHOD(addBu0, "$bu0") DEF_METHOD(addNeg, "$neg") -DEF_METHOD(addReduceAnd, "$redcue_and") -DEF_METHOD(addReduceOr, "$redcue_or") -DEF_METHOD(addReduceXor, "$redcue_xor") -DEF_METHOD(addReduceXnor, "$redcue_xnor") -DEF_METHOD(addReduceBool, "$redcue_bool") +DEF_METHOD(addReduceAnd, "$reduce_and") +DEF_METHOD(addReduceOr, "$reduce_or") +DEF_METHOD(addReduceXor, "$reduce_xor") +DEF_METHOD(addReduceXnor, "$reduce_xnor") +DEF_METHOD(addReduceBool, "$reduce_bool") DEF_METHOD(addLogicNot, "$logic_not") #undef DEF_METHOD -- cgit v1.2.3 From 91704a78531bec2e3eea3ddf90eaedb28e1d696d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 11 Mar 2014 14:24:24 +0100 Subject: Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28) --- kernel/driver.cc | 1 + kernel/log.h | 16 ++++++++++++++++ kernel/register.cc | 1 + 3 files changed, 18 insertions(+) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 00a61ec0f..ce95cad4f 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -24,6 +24,7 @@ #include #include #include +#include #include diff --git a/kernel/log.h b/kernel/log.h index c4c03352a..fbc3c1c39 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -23,6 +23,8 @@ #include "kernel/rtlil.h" #include #include +#include +#include #include extern std::vector log_files; @@ -65,9 +67,23 @@ struct PerformanceTimer } static int64_t query() { +#if defined(_POSIX_TIMERS) && (_POSIX_TIMERS > 0) struct timespec ts; clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &ts); return int64_t(ts.tv_sec)*1000000000 + ts.tv_nsec; +#elif defined(RUSAGE_SELF) + struct rusage rusage; + int64_t t; + if (getrusage(RUSAGE_SELF, &rusage) == -1) { + log_cmd_error("getrusage failed!\n"); + log_abort(); + } + t = 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL; + t += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL; + return t; +#else + #error Dont know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?). +#endif } void reset() { diff --git a/kernel/register.cc b/kernel/register.cc index ee14ffbad..ab5cba11b 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -23,6 +23,7 @@ #include #include #include +#include using namespace REGISTER_INTERN; #define MAX_REG_COUNT 1000 -- cgit v1.2.3 From 94c1307c262e4b14f4a91b1bbcf9099ee6202bab Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 12 Mar 2014 10:17:51 +0100 Subject: Added libs/minisat (copy of minisat git master) --- kernel/satgen.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index bf72a31cb..81d029295 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -24,13 +24,8 @@ #include "kernel/sigtools.h" #include "kernel/celltypes.h" -#ifdef YOSYS_ENABLE_MINISAT -# include "libs/ezsat/ezminisat.h" +#include "libs/ezsat/ezminisat.h" typedef ezMiniSAT ezDefaultSAT; -#else -# include "libs/ezsat/ezsat.h" -typedef ezSAT ezDefaultSAT; -#endif struct SatGen { -- cgit v1.2.3 From 8127d5e8c35da6610dc9fd43cca66ff9ca41f078 Mon Sep 17 00:00:00 2001 From: Siesh1oo Date: Wed, 12 Mar 2014 18:33:37 +0100 Subject: - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics. --- kernel/driver.cc | 69 +++++++++++++++++++++++++++++-------------------------- kernel/register.h | 4 ++-- 2 files changed, 39 insertions(+), 34 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index ce95cad4f..da4962b82 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -427,42 +428,46 @@ extern RTLIL::Design *yosys_get_design() return yosys_design; } -std::string rewrite_yosys_exe(std::string exe) +#if defined(__linux__) +std::string proc_self_dirname () { - char buffer[1024]; - ssize_t buflen = readlink("/proc/self/exe", buffer, sizeof(buffer)-1); - - if (buflen < 0) - return exe; - - buffer[buflen] = 0; - std::string newexe = stringf("%s/%s", dirname(buffer), exe.c_str()); - if (access(newexe.c_str(), X_OK) == 0) - return newexe; - - return exe; + char path [PATH_MAX]; + ssize_t buflen = readlink("/proc/self/exe", path, sizeof(path)); + if (buflen < 0) { + log_cmd_error("readlink(\"/proc/self/exe\") failed: %s", strerror(errno)); + log_abort(); + } + while (buflen > 0 && path[buflen-1] != '/') + buflen--; + return std::string(path, buflen); } - -std::string get_share_file_name(std::string file) +#elif defined(__APPLE__) +#include +std::string proc_self_dirname () { - char buffer[1024]; - ssize_t buflen = readlink("/proc/self/exe", buffer, sizeof(buffer)-1); - - if (buflen < 0) - log_error("Can't find file `%s': reading of /proc/self/exe failed!\n", file.c_str()); - - buffer[buflen] = 0; - const char *dir = dirname(buffer); - - std::string newfile_inplace = stringf("%s/share/%s", dir, file.c_str()); - if (access(newfile_inplace.c_str(), F_OK) == 0) - return newfile_inplace; - - std::string newfile_system = stringf("%s/../share/yosys/%s", dir, file.c_str()); - if (access(newfile_system.c_str(), F_OK) == 0) - return newfile_system; + char * path = NULL; + uint32_t buflen = 0; + while (_NSGetExecutablePath(path, &buflen) != 0) + path = (char *) realloc((void *) path, buflen); + while (buflen > 0 && path[buflen-1] != '/') + buflen--; + return std::string(path, buflen); +} +#else + #error Dont know how to determine process executable base path! +#endif - log_error("Can't find file `%s': no `%s' and no `%s' found!\n", file.c_str(), newfile_inplace.c_str(), newfile_system.c_str()); +std::string proc_share_dirname () +{ + std::string proc_self_path = proc_self_dirname(); + std::string proc_share_path = proc_self_path + "share/"; + if (access(proc_share_path.c_str(), X_OK) == 0) + return proc_share_path; + proc_share_path = proc_self_path + "../share/yosys/"; + if (access(proc_share_path.c_str(), X_OK) == 0) + return proc_share_path; + log_cmd_error("proc_share_dirname: unable to determine share/ directory!"); + log_abort(); } int main(int argc, char **argv) diff --git a/kernel/register.h b/kernel/register.h index b582f98c9..f3d3f70ae 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -36,8 +36,8 @@ extern const char *yosys_version_str; // implemented in driver.cc extern RTLIL::Design *yosys_get_design(); -std::string rewrite_yosys_exe(std::string exe); -std::string get_share_file_name(std::string file); +extern std::string proc_self_dirname(); +extern std::string proc_share_dirname(); const char *create_prompt(RTLIL::Design *design, int recursion_counter); // from passes/cmds/design.cc -- cgit v1.2.3 From fad8558eb5ecbd62e2032a48c537bfecfad3dfc4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Mar 2014 12:48:10 +0100 Subject: Merged OSX fixes from Siesh1oo with some modifications --- kernel/compatibility.cc | 135 ++++++++++++++++++++++++++++++++++++++++++++++++ kernel/compatibility.h | 36 +++++++++++++ kernel/log.cc | 1 + kernel/register.cc | 5 +- kernel/rtlil.cc | 1 + 5 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 kernel/compatibility.cc create mode 100644 kernel/compatibility.h (limited to 'kernel') diff --git a/kernel/compatibility.cc b/kernel/compatibility.cc new file mode 100644 index 000000000..2ef023eb3 --- /dev/null +++ b/kernel/compatibility.cc @@ -0,0 +1,135 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/** + * POSIX.2008 fake implementation for pre-POSIX.2008 systems. (OSX, BSD, MINGW, CYGWIN, older Linux &c.) + */ + +#include +#include +#include +#include + +#if !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) + +typedef struct memstream { + off_t pos; + off_t size; + char * buffer; + char ** bufp; + size_t * sizep; + bool realloc; +} memstream_t; + +static int memstream_read (void * cookie, char * buf, int size) +{ + memstream_t * mem = (memstream_t *) cookie; + off_t available = mem->size - mem->pos; + if (available < 0) + available = 0; + if (size > available) + size = available; + memcpy(buf, mem->buffer + mem->pos, size); + mem->pos += size; + return size; +} + +static int memstream_write (void * cookie, const char * buf, int size) +{ + memstream_t * mem = (memstream_t *) cookie; + off_t available = mem->size - mem->pos; + if (size > available) { + if (mem->realloc) { + mem->buffer = (char *) realloc(mem->buffer, mem->pos + size + 1); + memset(mem->buffer + mem->size, 0, mem->pos + size + 1 - mem->size); + mem->size = mem->pos + size; + if (mem->bufp) + *(mem->bufp) = mem->buffer; + if (mem->sizep) + *(mem->sizep) = mem->size; + } else { + size = available; + } + } + memcpy(mem->buffer + mem->pos, buf, sizeof(char) * size); + mem->pos += size; + return size; +} + +static fpos_t memstream_seek (void * cookie, fpos_t offset, int whence) +{ + memstream_t * mem = (memstream_t *) cookie; + switch (whence) { + case SEEK_SET: + if (offset < 0) + goto error_inval; + mem->pos = offset; + return 0; + case SEEK_CUR: + if (mem->pos + offset < 0) + goto error_inval; + mem->pos += offset; + return 0; + case SEEK_END: + if (mem->size + offset < 0) + goto error_inval; + mem->pos = mem->size + offset; + break; + default: + goto error_inval; + } + return mem->pos; +error_inval: + errno = EINVAL; + return -1; +} + +static int memstream_close (void * cookie) +{ + memstream_t * mem = (memstream_t *) cookie; + if (mem->bufp) + *(mem->bufp) = mem->buffer; + if (mem->sizep) + *(mem->sizep) = mem->size; + free(cookie); + return 0; +} + +FILE * compat_fmemopen (void * buf, size_t size, const char * mode) +{ + memstream_t * mem = (memstream_t *) malloc(sizeof(memstream_t)); + memset(mem, 0, sizeof(memstream_t)); + mem->size = size; + mem->buffer = (char *) buf; + (void) mode; + return funopen(mem, memstream_read, memstream_write, memstream_seek, memstream_close); +} + +FILE * compat_open_memstream (char ** bufp, size_t * sizep) +{ + memstream_t * mem = (memstream_t *) malloc(sizeof(memstream_t)); + memset(mem, 0, sizeof(memstream_t)); + mem->bufp = bufp; + mem->sizep = sizep; + mem->realloc = true; + return funopen(mem, memstream_read, memstream_write, memstream_seek, memstream_close); +} + +#endif /* !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) */ + diff --git a/kernel/compatibility.h b/kernel/compatibility.h new file mode 100644 index 000000000..58e0b52e9 --- /dev/null +++ b/kernel/compatibility.h @@ -0,0 +1,36 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef COMPATIBILITY_H +#define COMPATIBILITY_H + +#if !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) +#include +#include + +#define open_memstream compat_open_memstream +#define fmemopen compat_fmemopen + +FILE * compat_open_memstream (char ** bufp, size_t * sizep); +FILE * compat_fmemopen (void * buf, size_t size, const char * mode); + +#endif /* !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) */ + +#endif /* COMPATIBILITY_H */ + diff --git a/kernel/log.cc b/kernel/log.cc index 779f93737..b2c92e4e1 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -18,6 +18,7 @@ */ #include "kernel/log.h" +#include "kernel/compatibility.h" #include "backends/ilang/ilang_backend.h" #include diff --git a/kernel/register.cc b/kernel/register.cc index ab5cba11b..511afaac0 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -17,8 +17,9 @@ * */ -#include "register.h" -#include "log.h" +#include "kernel/compatibility.h" +#include "kernel/register.h" +#include "kernel/log.h" #include #include #include diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 21fcae2b5..7259845a0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -17,6 +17,7 @@ * */ +#include "kernel/compatibility.h" #include "kernel/rtlil.h" #include "kernel/log.h" #include "frontends/verilog/verilog_frontend.h" -- cgit v1.2.3 From 542afc562fa8b828f3c87e9dbe47a373ac09f147 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Mar 2014 12:55:15 +0100 Subject: Hotfix for kernel/compatibility.h --- kernel/compatibility.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/compatibility.h b/kernel/compatibility.h index 58e0b52e9..c7603c8a5 100644 --- a/kernel/compatibility.h +++ b/kernel/compatibility.h @@ -20,10 +20,11 @@ #ifndef COMPATIBILITY_H #define COMPATIBILITY_H -#if !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) #include #include +#if !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) + #define open_memstream compat_open_memstream #define fmemopen compat_fmemopen -- cgit v1.2.3 From 77e5968323e76dd8f5dec431cadd95c69d77dc94 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Mar 2014 11:45:44 +0100 Subject: Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API --- kernel/rtlil.cc | 42 ++++++++++++++++++++++++++++++++++++++++++ kernel/rtlil.h | 6 ++++++ 2 files changed, 48 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7259845a0..420f528a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -932,6 +932,48 @@ DEF_METHOD(addPmux, "$pmux", 1) DEF_METHOD(addSafePmux, "$safe_pmux", 1) #undef DEF_METHOD +#define DEF_METHOD_2(_func, _type, _P1, _P2) \ + RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->connections["\\" #_P1] = sig1; \ + cell->connections["\\" #_P2] = sig2; \ + add(cell); \ + return cell; \ + } +#define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \ + RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->connections["\\" #_P1] = sig1; \ + cell->connections["\\" #_P2] = sig2; \ + cell->connections["\\" #_P3] = sig3; \ + add(cell); \ + return cell; \ + } +#define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \ + RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->connections["\\" #_P1] = sig1; \ + cell->connections["\\" #_P2] = sig2; \ + cell->connections["\\" #_P3] = sig3; \ + cell->connections["\\" #_P4] = sig4; \ + add(cell); \ + return cell; \ + } +DEF_METHOD_2(addInvGate, "$_INV_", A, Y) +DEF_METHOD_3(addAndGate, "$_AND_", A, B, Y) +DEF_METHOD_3(addOrGate, "$_OR_", A, B, Y) +DEF_METHOD_3(addXorGate, "$_XOR_", A, B, Y) +DEF_METHOD_4(addMuxGate, "$_MUX_", A, B, S, Y) +#undef DEF_METHOD_2 +#undef DEF_METHOD_3 +#undef DEF_METHOD_4 + RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed) { RTLIL::Cell *cell = new RTLIL::Cell; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 48f3e3921..e55a88eba 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -351,6 +351,12 @@ struct RTLIL::Module { RTLIL::Cell* addAdff (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true); RTLIL::Cell* addDlatch (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true); + + RTLIL::Cell* addInvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y); + RTLIL::Cell* addAndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); + RTLIL::Cell* addOrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); + RTLIL::Cell* addXorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); + RTLIL::Cell* addMuxGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); }; struct RTLIL::Wire { -- cgit v1.2.3 From 0ac915a757a10f50fd74e18365cbcf351885c162 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Mar 2014 11:46:13 +0100 Subject: Progress in Verific bindings --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 420f528a3..ee73ebe44 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -718,7 +718,7 @@ void RTLIL::Module::check() for (auto &it2 : it.second->parameters) { assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); } - if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod") { + if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod" && it.second->type.substr(0, 9) != "$verific$") { InternalCellChecker checker(this, it.second); checker.check(); } -- cgit v1.2.3 From 5da9558fa8a6be6e98eb0a7a7d0c6dd8bd86347f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Mar 2014 16:39:50 +0100 Subject: Added log_dump() support for generic pointers --- kernel/log.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index fbc3c1c39..5fbd2fc68 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -128,6 +128,9 @@ static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); } static inline void log_dump_val_worker(RTLIL::SigSpec v) { log("%s", log_signal(v)); } static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); } +template +static inline void log_dump_val_worker(T *ptr) { log("%p", ptr); } + template void log_dump_args_worker(const char *p, T first, Args ... args) { -- cgit v1.2.3 From b7c71d92f6003dcd626f58a0cf06f43c6a3b8d4c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 15 Mar 2014 14:35:29 +0100 Subject: Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API --- kernel/rtlil.cc | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- kernel/rtlil.h | 7 +++++++ 2 files changed, 61 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ee73ebe44..072910e30 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1109,7 +1109,7 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk return cell; } -RTLIL::Cell* RTLIL::Module::addDlatch (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity) +RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; @@ -1123,6 +1123,59 @@ RTLIL::Cell* RTLIL::Module::addDlatch (RTLIL::IdString name, RTLIL::SigSpec sig_ return cell; } +RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'); + cell->connections["\\C"] = sig_clk; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, + RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'); + cell->connections["\\C"] = sig_clk; + cell->connections["\\S"] = sig_set; + cell->connections["\\R"] = sig_clr; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, + bool arst_value, bool clk_polarity, bool arst_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'); + cell->connections["\\C"] = sig_clk; + cell->connections["\\R"] = sig_arst; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'); + cell->connections["\\E"] = sig_en; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + RTLIL::Wire::Wire() { width = 1; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e55a88eba..44142bf29 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -357,6 +357,13 @@ struct RTLIL::Module { RTLIL::Cell* addOrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); RTLIL::Cell* addXorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); RTLIL::Cell* addMuxGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); + + RTLIL::Cell* addDffGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true); + RTLIL::Cell* addDffsrGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, + RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true); + RTLIL::Cell* addAdffGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, + bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true); + RTLIL::Cell* addDlatchGate (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true); }; struct RTLIL::Wire { -- cgit v1.2.3 From ef1795a1e8df76873074a891f9132948181febcc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 15 Mar 2014 22:52:10 +0100 Subject: Fixed typo in RTLIL::Module::{addSshl,addSshr} --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 072910e30..2b28f3232 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -893,8 +893,8 @@ DEF_METHOD(addXor, "$xor") DEF_METHOD(addXnor, "$xnor") DEF_METHOD(addShl, "$shl") DEF_METHOD(addShr, "$shr") -DEF_METHOD(addSshl, "$Sshl") -DEF_METHOD(addSshr, "$Sshr") +DEF_METHOD(addSshl, "$sshl") +DEF_METHOD(addSshr, "$sshr") DEF_METHOD(addLt, "$lt") DEF_METHOD(addLe, "$le") DEF_METHOD(addEq, "$eq") -- cgit v1.2.3 From e164edc8d11356c0999c44dfdb52d0b2b337f212 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 17 Mar 2014 14:41:41 +0100 Subject: Fixed typo in RTLIL::Module::addAdff() --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2b28f3232..1d53bc79b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1096,7 +1096,7 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; - cell->type = "$dffsr"; + cell->type = "$adff"; cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\ARST_POLARITY"] = arst_polarity; cell->parameters["\\ARST_VALUE"] = arst_value; -- cgit v1.2.3 From d4a1b0af5b41d1360c74a73fb2ae92ee5f6c3bd0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 31 Mar 2014 14:14:40 +0200 Subject: Added support for dlatchsr cells --- kernel/celltypes.h | 9 +++++++++ kernel/rtlil.cc | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++- kernel/rtlil.h | 4 ++++ 3 files changed, 71 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 4a600af9d..769145838 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -108,6 +108,7 @@ struct CellTypes cell_types.insert("$dffsr"); cell_types.insert("$adff"); cell_types.insert("$dlatch"); + cell_types.insert("$dlatchsr"); cell_types.insert("$memrd"); cell_types.insert("$memwr"); cell_types.insert("$mem"); @@ -149,6 +150,14 @@ struct CellTypes cell_types.insert("$_DFFSR_PPP_"); cell_types.insert("$_DLATCH_N_"); cell_types.insert("$_DLATCH_P_"); + cell_types.insert("$_DLATCHSR_NNN_"); + cell_types.insert("$_DLATCHSR_NNP_"); + cell_types.insert("$_DLATCHSR_NPN_"); + cell_types.insert("$_DLATCHSR_NPP_"); + cell_types.insert("$_DLATCHSR_PNN_"); + cell_types.insert("$_DLATCHSR_PNP_"); + cell_types.insert("$_DLATCHSR_PPN_"); + cell_types.insert("$_DLATCHSR_PPP_"); } void clear() diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1d53bc79b..1168102a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -569,6 +569,19 @@ namespace { return; } + if (cell->type == "$dlatchsr") { + param_bool("\\EN_POLARITY"); + param_bool("\\SET_POLARITY"); + param_bool("\\CLR_POLARITY"); + port("\\EN", 1); + port("\\SET", param("\\WIDTH")); + port("\\CLR", param("\\WIDTH")); + port("\\D", param("\\WIDTH")); + port("\\Q", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$fsm") { param("\\NAME"); param_bool("\\CLK_POLARITY"); @@ -675,6 +688,15 @@ namespace { if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; } if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; } + if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; } + if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; } + if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; } + if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; } + if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; } + if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; } + if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; } + if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; } + error(__LINE__); } }; @@ -1113,7 +1135,7 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; - cell->type = "$dffsr"; + cell->type = "$dlatch"; cell->parameters["\\EN_POLARITY"] = en_polarity; cell->parameters["\\WIDTH"] = sig_q.width; cell->connections["\\EN"] = sig_en; @@ -1123,6 +1145,25 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e return cell; } +RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, + RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = "$dlatchsr"; + cell->parameters["\\EN_POLARITY"] = en_polarity; + cell->parameters["\\SET_POLARITY"] = set_polarity; + cell->parameters["\\CLR_POLARITY"] = clr_polarity; + cell->parameters["\\WIDTH"] = sig_q.width; + cell->connections["\\EN"] = sig_en; + cell->connections["\\SET"] = sig_set; + cell->connections["\\CLR"] = sig_clr; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity) { RTLIL::Cell *cell = new RTLIL::Cell; @@ -1176,6 +1217,22 @@ RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec s return cell; } +RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, + RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'); + cell->connections["\\E"] = sig_en; + cell->connections["\\S"] = sig_set; + cell->connections["\\R"] = sig_clr; + cell->connections["\\D"] = sig_d; + cell->connections["\\Q"] = sig_q; + add(cell); + return cell; +} + + RTLIL::Wire::Wire() { width = 1; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 44142bf29..b95a04422 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -351,6 +351,8 @@ struct RTLIL::Module { RTLIL::Cell* addAdff (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true); RTLIL::Cell* addDlatch (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true); + RTLIL::Cell* addDlatchsr (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, + RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true); RTLIL::Cell* addInvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y); RTLIL::Cell* addAndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); @@ -364,6 +366,8 @@ struct RTLIL::Module { RTLIL::Cell* addAdffGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true); RTLIL::Cell* addDlatchGate (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true); + RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, + RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true); }; struct RTLIL::Wire { -- cgit v1.2.3 From 75a5d6bd1ec6f23e508a52d04a6e384d247efd90 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 May 2014 13:22:26 +0200 Subject: workaround for OpenBSD 'stdin' implementation --- kernel/register.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 511afaac0..cb8ad473c 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -306,7 +306,8 @@ void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filenam if (f != NULL) { frontend_register[args[0]]->execute(f, filename, args, design); } else if (filename == "-") { - frontend_register[args[0]]->execute(stdin, "", args, design); + FILE *f_stdin = stdin; // workaround for OpenBSD 'stdin' implementation + frontend_register[args[0]]->execute(f_stdin, "", args, design); } else { if (!filename.empty()) args.push_back(filename); -- cgit v1.2.3 From a5a519a9d15f188b93723c84890d6005d2e9c4be Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 3 May 2014 12:55:56 +0200 Subject: workaround for OpenBSD 'stdout' implementation --- kernel/register.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index cb8ad473c..5d882ab43 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -400,7 +400,8 @@ void Backend::backend_call(RTLIL::Design *design, FILE *f, std::string filename, if (f != NULL) { backend_register[args[0]]->execute(f, filename, args, design); } else if (filename == "-") { - backend_register[args[0]]->execute(stdout, "", args, design); + FILE *f_stdout = stdout; // workaround for OpenBSD 'stdout' implementation + backend_register[args[0]]->execute(f_stdout, "", args, design); } else { if (!filename.empty()) args.push_back(filename); -- cgit v1.2.3 From f9c1cd5edba5acb4d9b9dd287c7265111cf22087 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Jun 2014 09:10:50 +0200 Subject: Improved error message for options after front-end filename arguments --- kernel/register.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 5d882ab43..8da5a725f 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -270,6 +270,10 @@ void Frontend::extra_args(FILE *&f, std::string &filename, std::vector Date: Sat, 7 Jun 2014 11:48:50 +0200 Subject: Add support for cell arrays --- kernel/rtlil.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1168102a3..028cd6d81 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -740,7 +740,8 @@ void RTLIL::Module::check() for (auto &it2 : it.second->parameters) { assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); } - if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod" && it.second->type.substr(0, 9) != "$verific$") { + if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod" && + it.second->type.substr(0, 9) != "$verific$" && it.second->type.substr(0, 7) != "$array:") { InternalCellChecker checker(this, it.second); checker.check(); } -- cgit v1.2.3 From 847e2ee4a130559f7ee002542560a9fcbe1dfc71 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 11 Jul 2014 13:10:51 +0200 Subject: Use "verilog -sv" to parse .sv files --- kernel/driver.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index da4962b82..577fbe3d9 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -54,6 +54,8 @@ static void run_frontend(std::string filename, std::string command, RTLIL::Desig if (command == "auto") { if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") command = "verilog"; + else if (filename.size() > 2 && filename.substr(filename.size()-3) == ".sv") + command = "verilog -sv"; else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") command = "ilang"; else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".ys") -- cgit v1.2.3 From 73e0e13d2f1b959a05d69ed715c8fdde84894d6f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Jul 2014 11:38:02 +0200 Subject: Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 028cd6d81..c4c08d5b8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -619,7 +619,7 @@ namespace { param_bool("\\CLK_POLARITY"); param("\\PRIORITY"); port("\\CLK", 1); - port("\\EN", 1); + port("\\EN", param("\\WIDTH")); port("\\ADDR", param("\\ABITS")); port("\\DATA", param("\\WIDTH")); check_expected(); @@ -639,7 +639,7 @@ namespace { port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS")); port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH")); port("\\WR_CLK", param("\\WR_PORTS")); - port("\\WR_EN", param("\\WR_PORTS")); + port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH")); port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS")); port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH")); check_expected(); -- cgit v1.2.3 From 274c51487937e3ca37c3520e98e996cb5918e982 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jul 2014 12:10:57 +0200 Subject: Fixed RTLIL::SigSpec::append_bit() for appending constants --- kernel/rtlil.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c4c08d5b8..c232dadd2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1716,9 +1716,10 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) chunks.push_back(bit); else if (bit.wire == NULL) - if (chunks.back().wire == NULL) + if (chunks.back().wire == NULL) { chunks.back().data.bits.push_back(bit.data); - else + chunks.back().width++; + } else chunks.push_back(bit); else if (chunks.back().wire == bit.wire && chunks.back().offset + chunks.back().width == bit.offset) -- cgit v1.2.3 From a8cedb225709171b97e31c35dcac52d13c47b94f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 10:26:01 +0200 Subject: Added log_id() helper function --- kernel/log.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index 5fbd2fc68..3e280a6f6 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -52,6 +52,14 @@ void log_flush(); const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); +static inline const char *log_id(std::string id) { + return RTLIL::id2cstr(id); +} + +template static inline const char *log_id(T *obj) { + return RTLIL::id2cstr(obj->name); +} + #define log_abort() log_error("Abort in %s:%d.\n", __FILE__, __LINE__) #define log_assert(_assert_expr_) do { if (_assert_expr_) break; log_error("Assert `%s' failed in %s:%d.\n", #_assert_expr_, __FILE__, __LINE__); } while (0) -- cgit v1.2.3 From 2d69c309f9d4d3093eead620684a59e3804b3894 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 10:27:06 +0200 Subject: Added function-like cell creation helpers --- kernel/rtlil.cc | 176 +++++++++++++++++++++++++++++++++----------------------- kernel/rtlil.h | 55 ++++++++++++++++++ 2 files changed, 158 insertions(+), 73 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c232dadd2..dea0e1050 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -869,8 +869,8 @@ void RTLIL::Module::fixup_ports() } -#define DEF_METHOD(_func, _type) \ - RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ +#define DEF_METHOD(_func, _y_size, _type) \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ @@ -881,21 +881,26 @@ void RTLIL::Module::fixup_ports() cell->connections["\\Y"] = sig_y; \ add(cell); \ return cell; \ + } \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \ + RTLIL::SigSpec sig_y = new_wire(_y_size, NEW_ID); \ + add ## _func(name, sig_a, sig_y, is_signed); \ + return sig_y; \ } -DEF_METHOD(addNot, "$not") -DEF_METHOD(addPos, "$pos") -DEF_METHOD(addBu0, "$bu0") -DEF_METHOD(addNeg, "$neg") -DEF_METHOD(addReduceAnd, "$reduce_and") -DEF_METHOD(addReduceOr, "$reduce_or") -DEF_METHOD(addReduceXor, "$reduce_xor") -DEF_METHOD(addReduceXnor, "$reduce_xnor") -DEF_METHOD(addReduceBool, "$reduce_bool") -DEF_METHOD(addLogicNot, "$logic_not") +DEF_METHOD(Not, sig_a.width, "$not") +DEF_METHOD(Pos, sig_a.width, "$pos") +DEF_METHOD(Bu0, sig_a.width, "$bu0") +DEF_METHOD(Neg, sig_a.width, "$neg") +DEF_METHOD(ReduceAnd, 1, "$reduce_and") +DEF_METHOD(ReduceOr, 1, "$reduce_or") +DEF_METHOD(ReduceXor, 1, "$reduce_xor") +DEF_METHOD(ReduceXnor, 1, "$reduce_xnor") +DEF_METHOD(ReduceBool, 1, "$reduce_bool") +DEF_METHOD(LogicNot, 1, "$logic_not") #undef DEF_METHOD -#define DEF_METHOD(_func, _type) \ - RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \ +#define DEF_METHOD(_func, _y_size, _type) \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \ RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ @@ -909,34 +914,39 @@ DEF_METHOD(addLogicNot, "$logic_not") cell->connections["\\Y"] = sig_y; \ add(cell); \ return cell; \ + } \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \ + RTLIL::SigSpec sig_y = new_wire(_y_size, NEW_ID); \ + add ## _func(name, sig_a, sig_b, sig_y, is_signed); \ + return sig_y; \ } -DEF_METHOD(addAnd, "$and") -DEF_METHOD(addOr, "$or") -DEF_METHOD(addXor, "$xor") -DEF_METHOD(addXnor, "$xnor") -DEF_METHOD(addShl, "$shl") -DEF_METHOD(addShr, "$shr") -DEF_METHOD(addSshl, "$sshl") -DEF_METHOD(addSshr, "$sshr") -DEF_METHOD(addLt, "$lt") -DEF_METHOD(addLe, "$le") -DEF_METHOD(addEq, "$eq") -DEF_METHOD(addNe, "$ne") -DEF_METHOD(addEqx, "$eqx") -DEF_METHOD(addNex, "$nex") -DEF_METHOD(addGe, "$ge") -DEF_METHOD(addGt, "$gt") -DEF_METHOD(addAdd, "$add") -DEF_METHOD(addSub, "$sub") -DEF_METHOD(addMul, "$mul") -DEF_METHOD(addDiv, "$div") -DEF_METHOD(addMod, "$mod") -DEF_METHOD(addLogicAnd, "$logic_and") -DEF_METHOD(addLogicOr, "$logic_or") +DEF_METHOD(And, std::max(sig_a.width, sig_b.width), "$and") +DEF_METHOD(Or, std::max(sig_a.width, sig_b.width), "$or") +DEF_METHOD(Xor, std::max(sig_a.width, sig_b.width), "$xor") +DEF_METHOD(Xnor, std::max(sig_a.width, sig_b.width), "$xnor") +DEF_METHOD(Shl, sig_a.width, "$shl") +DEF_METHOD(Shr, sig_a.width, "$shr") +DEF_METHOD(Sshl, sig_a.width, "$sshl") +DEF_METHOD(Sshr, sig_a.width, "$sshr") +DEF_METHOD(Lt, 1, "$lt") +DEF_METHOD(Le, 1, "$le") +DEF_METHOD(Eq, 1, "$eq") +DEF_METHOD(Ne, 1, "$ne") +DEF_METHOD(Eqx, 1, "$eqx") +DEF_METHOD(Nex, 1, "$nex") +DEF_METHOD(Ge, 1, "$ge") +DEF_METHOD(Gt, 1, "$gt") +DEF_METHOD(Add, std::max(sig_a.width, sig_b.width), "$add") +DEF_METHOD(Sub, std::max(sig_a.width, sig_b.width), "$sub") +DEF_METHOD(Mul, std::max(sig_a.width, sig_b.width), "$mul") +DEF_METHOD(Div, std::max(sig_a.width, sig_b.width), "$div") +DEF_METHOD(Mod, std::max(sig_a.width, sig_b.width), "$mod") +DEF_METHOD(LogicAnd, 1, "$logic_and") +DEF_METHOD(LogicOr, 1, "$logic_or") #undef DEF_METHOD #define DEF_METHOD(_func, _type, _pmux) \ - RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \ RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ @@ -949,50 +959,70 @@ DEF_METHOD(addLogicOr, "$logic_or") cell->connections["\\Y"] = sig_y; \ add(cell); \ return cell; \ + } \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \ + RTLIL::SigSpec sig_y = new_wire(sig_a.width, NEW_ID); \ + add ## _func(name, sig_a, sig_b, sig_s, sig_y); \ + return sig_y; \ } -DEF_METHOD(addMux, "$mux", 0) -DEF_METHOD(addPmux, "$pmux", 1) -DEF_METHOD(addSafePmux, "$safe_pmux", 1) +DEF_METHOD(Mux, "$mux", 0) +DEF_METHOD(Pmux, "$pmux", 1) +DEF_METHOD(SafePmux, "$safe_pmux", 1) #undef DEF_METHOD #define DEF_METHOD_2(_func, _type, _P1, _P2) \ - RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ - cell->connections["\\" #_P1] = sig1; \ - cell->connections["\\" #_P2] = sig2; \ - add(cell); \ - return cell; \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->connections["\\" #_P1] = sig1; \ + cell->connections["\\" #_P2] = sig2; \ + add(cell); \ + return cell; \ + } \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \ + RTLIL::SigSpec sig2 = new_wire(1, NEW_ID); \ + add ## _func(name, sig1, sig2); \ + return sig2; \ } #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \ - RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ - cell->connections["\\" #_P1] = sig1; \ - cell->connections["\\" #_P2] = sig2; \ - cell->connections["\\" #_P3] = sig3; \ - add(cell); \ - return cell; \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->connections["\\" #_P1] = sig1; \ + cell->connections["\\" #_P2] = sig2; \ + cell->connections["\\" #_P3] = sig3; \ + add(cell); \ + return cell; \ + } \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ + RTLIL::SigSpec sig3 = new_wire(1, NEW_ID); \ + add ## _func(name, sig1, sig2, sig3); \ + return sig3; \ } #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \ - RTLIL::Cell* RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ - cell->connections["\\" #_P1] = sig1; \ - cell->connections["\\" #_P2] = sig2; \ - cell->connections["\\" #_P3] = sig3; \ - cell->connections["\\" #_P4] = sig4; \ - add(cell); \ - return cell; \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \ + RTLIL::Cell *cell = new RTLIL::Cell; \ + cell->name = name; \ + cell->type = _type; \ + cell->connections["\\" #_P1] = sig1; \ + cell->connections["\\" #_P2] = sig2; \ + cell->connections["\\" #_P3] = sig3; \ + cell->connections["\\" #_P4] = sig4; \ + add(cell); \ + return cell; \ + } \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ + RTLIL::SigSpec sig4 = new_wire(1, NEW_ID); \ + add ## _func(name, sig1, sig2, sig3, sig4); \ + return sig4; \ } -DEF_METHOD_2(addInvGate, "$_INV_", A, Y) -DEF_METHOD_3(addAndGate, "$_AND_", A, B, Y) -DEF_METHOD_3(addOrGate, "$_OR_", A, B, Y) -DEF_METHOD_3(addXorGate, "$_XOR_", A, B, Y) -DEF_METHOD_4(addMuxGate, "$_MUX_", A, B, S, Y) +DEF_METHOD_2(InvGate, "$_INV_", A, Y) +DEF_METHOD_3(AndGate, "$_AND_", A, B, Y) +DEF_METHOD_3(OrGate, "$_OR_", A, B, Y) +DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y) +DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y) #undef DEF_METHOD_2 #undef DEF_METHOD_3 #undef DEF_METHOD_4 diff --git a/kernel/rtlil.h b/kernel/rtlil.h index b95a04422..17406d5d6 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -294,6 +294,8 @@ struct RTLIL::Module { void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; + // The add* methods create a cell and return the created cell. All signals must exist in advance. + RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addBu0 (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); @@ -368,6 +370,59 @@ struct RTLIL::Module { RTLIL::Cell* addDlatchGate (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true); RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true); + + // The methods without the add* prefix create a cell and an output signal. They return the newly created output signal. + + RTLIL::SigSpec Not (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + RTLIL::SigSpec Pos (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + RTLIL::SigSpec Bu0 (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + RTLIL::SigSpec Neg (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + + RTLIL::SigSpec And (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Or (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Xor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Xnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + + RTLIL::SigSpec ReduceAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + RTLIL::SigSpec ReduceOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + RTLIL::SigSpec ReduceXor (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + RTLIL::SigSpec ReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + + RTLIL::SigSpec Shl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Shr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Sshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Sshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + + RTLIL::SigSpec Lt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Le (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Eq (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Ne (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Eqx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Nex (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Ge (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Gt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + + RTLIL::SigSpec Add (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Sub (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Mul (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Div (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Mod (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Pow (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool a_signed = false, bool b_signed = false); + + RTLIL::SigSpec LogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); + RTLIL::SigSpec LogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec LogicOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + + RTLIL::SigSpec Mux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); + RTLIL::SigSpec Pmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); + RTLIL::SigSpec SafePmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); + + RTLIL::SigSpec InvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a); + RTLIL::SigSpec AndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); + RTLIL::SigSpec OrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); + RTLIL::SigSpec XorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); + RTLIL::SigSpec MuxGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); }; struct RTLIL::Wire { -- cgit v1.2.3 From a721f7d768feb3ce68cb384805ea7f1fde3e08ed Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 11:36:34 +0200 Subject: Added automatic conversion from RTLIL::SigSpec to std::vector --- kernel/rtlil.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 17406d5d6..3a22d1371 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -542,6 +542,7 @@ struct RTLIL::SigSpec { static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + operator std::vector() const { return to_sigbit_vector(); } }; inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { -- cgit v1.2.3 From 1c288adcc03db49375dd0e214bbbc0b8b9099436 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 19 Jul 2014 15:32:39 +0200 Subject: Some "const" cleanups in SigMap --- kernel/sigtools.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/sigtools.h b/kernel/sigtools.h index ae6a00f8e..56497bb83 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -407,12 +407,12 @@ struct SigMap } // internal helper function - void map_bit(RTLIL::SigChunk &c) + void map_bit(RTLIL::SigChunk &c) const { assert(c.width == 1); bitDef_t bit(c.wire, c.offset); if (c.wire && bits.count(bit) > 0) - c = bits[bit]->chunk; + c = bits.at(bit)->chunk; } void add(RTLIL::SigSpec from, RTLIL::SigSpec to) @@ -459,7 +459,7 @@ struct SigMap unregister_bit(c); } - void apply(RTLIL::SigSpec &sig) + void apply(RTLIL::SigSpec &sig) const { sig.expand(); for (auto &c : sig.chunks) @@ -467,7 +467,7 @@ struct SigMap sig.optimize(); } - RTLIL::SigSpec operator()(RTLIL::SigSpec sig) + RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const { apply(sig); return sig; -- cgit v1.2.3 From 35edac0b31ff826c60d864febefc294263613716 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 19 Jul 2014 15:33:00 +0200 Subject: Added ModWalker helper class --- kernel/modwalker.h | 298 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 298 insertions(+) create mode 100644 kernel/modwalker.h (limited to 'kernel') diff --git a/kernel/modwalker.h b/kernel/modwalker.h new file mode 100644 index 000000000..6c3da5dd0 --- /dev/null +++ b/kernel/modwalker.h @@ -0,0 +1,298 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef MODWALKER_H +#define MODWALKER_H + +#include "kernel/sigtools.h" +#include "kernel/celltypes.h" + +struct ModWalker +{ + struct PortBit + { + RTLIL::Cell *cell; + RTLIL::IdString port; + int offset; + + bool operator<(const PortBit &other) const { + if (cell != other.cell) + return cell < other.cell; + if (port != other.port) + return port < other.port; + return offset < other.offset; + } + }; + + RTLIL::Design *design; + RTLIL::Module *module; + + CellTypes ct; + SigMap sigmap; + + std::map> signal_drivers; + std::map> signal_consumers; + std::set signal_inputs, signal_outputs; + + std::map> cell_outputs, cell_inputs; + + void add_wire(RTLIL::Wire *wire) + { + if (wire->port_input) { + std::vector bits = sigmap(wire); + for (auto bit : bits) + if (bit.wire != NULL) + signal_inputs.insert(bit); + } + + if (wire->port_output) { + std::vector bits = sigmap(wire); + for (auto bit : bits) + if (bit.wire != NULL) + signal_outputs.insert(bit); + } + } + + void add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector bits, bool is_output, bool is_input) + { + for (int i = 0; i < int(bits.size()); i++) + if (bits[i].wire != NULL) { + PortBit pbit = { cell, port, i }; + if (is_output) { + signal_drivers[bits[i]].insert(pbit); + cell_outputs[cell].insert(bits[i]); + } + if (is_input) { + signal_consumers[bits[i]].insert(pbit); + cell_inputs[cell].insert(bits[i]); + } + } + } + + void add_cell(RTLIL::Cell *cell) + { + if (ct.cell_known(cell->type)) { + for (auto &conn : cell->connections) + add_cell_port(cell, conn.first, sigmap(conn.second), + ct.cell_output(cell->type, conn.first), + ct.cell_input(cell->type, conn.first)); + } else { + for (auto &conn : cell->connections) + add_cell_port(cell, conn.first, sigmap(conn.second), true, true); + } + } + + ModWalker() : design(NULL), module(NULL) + { + } + + ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) + { + setup(design, module, filter_ct); + } + + void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) + { + this->design = design; + this->module = module; + + ct.clear(); + ct.setup(design); + sigmap.set(module); + + signal_drivers.clear(); + signal_consumers.clear(); + signal_inputs.clear(); + signal_outputs.clear(); + + for (auto &it : module->wires) + add_wire(it.second); + for (auto &it : module->cells) + if (filter_ct == NULL || filter_ct->cell_known(it.second->type)) + add_cell(it.second); + } + + // get_* methods -- single RTLIL::SigBit + + template + inline bool get_drivers(std::set &result, RTLIL::SigBit bit) const + { + bool found = false; + if (signal_drivers.count(bit)) { + const std::set &r = signal_drivers.at(bit); + result.insert(r.begin(), r.end()); + found = true; + } + return found; + } + + template + inline bool get_consumers(std::set &result, RTLIL::SigBit bit) const + { + bool found = false; + if (signal_consumers.count(bit)) { + const std::set &r = signal_consumers.at(bit); + result.insert(r.begin(), r.end()); + found = true; + } + return found; + } + + template + inline bool get_inputs(std::set &result, RTLIL::SigBit bit) const + { + bool found = false; + if (signal_inputs.count(bit)) + result.insert(bit), found = true; + return found; + } + + template + inline bool get_outputs(std::set &result, RTLIL::SigBit bit) const + { + bool found = false; + if (signal_outputs.count(bit)) + result.insert(bit), found = true; + return found; + } + + // get_* methods -- container of RTLIL::SigBit's (always by reference) + + template + inline bool get_drivers(std::set &result, const T &bits) const + { + bool found = false; + for (RTLIL::SigBit bit : bits) + if (signal_drivers.count(bit)) { + const std::set &r = signal_drivers.at(bit); + result.insert(r.begin(), r.end()); + found = true; + } + return found; + } + + template + inline bool get_consumers(std::set &result, const T &bits) const + { + bool found = false; + for (RTLIL::SigBit bit : bits) + if (signal_consumers.count(bit)) { + const std::set &r = signal_consumers.at(bit); + result.insert(r.begin(), r.end()); + found = true; + } + return found; + } + + template + inline bool get_inputs(std::set &result, const T &bits) const + { + bool found = false; + for (RTLIL::SigBit bit : bits) + if (signal_inputs.count(bit)) + result.insert(bit), found = true; + return found; + } + + template + inline bool get_outputs(std::set &result, const T &bits) const + { + bool found = false; + for (RTLIL::SigBit bit : bits) + if (signal_outputs.count(bit)) + result.insert(bit), found = true; + return found; + } + + // get_* methods -- call by RTLIL::SigSpec (always by value) + + bool get_drivers(std::set &result, RTLIL::SigSpec signal) const + { + std::vector bits = sigmap(signal); + return get_drivers(result, bits); + } + + bool get_consumers(std::set &result, RTLIL::SigSpec signal) const + { + std::vector bits = sigmap(signal); + return get_consumers(result, bits); + } + + bool get_inputs(std::set &result, RTLIL::SigSpec signal) const + { + std::vector bits = sigmap(signal); + return get_inputs(result, bits); + } + + bool get_outputs(std::set &result, RTLIL::SigSpec signal) const + { + std::vector bits = sigmap(signal); + return get_outputs(result, bits); + } + + // has_* methods -- call by reference + + template + inline bool has_drivers(const T &sig) const { + std::set result; + return get_drivers(result, sig); + } + + template + inline bool has_consumers(const T &sig) const { + std::set result; + return get_consumers(result, sig); + } + + template + inline bool has_inputs(const T &sig) const { + std::set result; + return get_inputs(result, sig); + } + + template + inline bool has_outputs(const T &sig) const { + std::set result; + return get_outputs(result, sig); + } + + // has_* methods -- call by value + + inline bool has_drivers(RTLIL::SigSpec sig) const { + std::set result; + return get_drivers(result, sig); + } + + inline bool has_consumers(RTLIL::SigSpec sig) const { + std::set result; + return get_consumers(result, sig); + } + + inline bool has_inputs(RTLIL::SigSpec sig) const { + std::set result; + return get_inputs(result, sig); + } + + inline bool has_outputs(RTLIL::SigSpec sig) const { + std::set result; + return get_outputs(result, sig); + } +}; + +#endif -- cgit v1.2.3 From 02f0acb3bce05f3af036495aa36049c67ffbdb52 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 19 Jul 2014 20:53:29 +0200 Subject: Fixed log_id() memory corruption --- kernel/log.cc | 8 ++++++++ kernel/log.h | 7 ++----- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index b2c92e4e1..3108bddfe 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -205,3 +205,11 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) return string_buf.back().c_str(); } +const char *log_id(std::string str) +{ + if (str.size() > 1 && str[0] == '\\' && str[1] != '$') + string_buf.push_back(str.substr(1)); + else + string_buf.push_back(str); + return string_buf.back().c_str(); +} diff --git a/kernel/log.h b/kernel/log.h index 3e280a6f6..2c3597c9a 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -51,13 +51,10 @@ void log_reset_stack(); void log_flush(); const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); - -static inline const char *log_id(std::string id) { - return RTLIL::id2cstr(id); -} +const char *log_id(std::string id); template static inline const char *log_id(T *obj) { - return RTLIL::id2cstr(obj->name); + return log_id(obj->name); } #define log_abort() log_error("Abort in %s:%d.\n", __FILE__, __LINE__) -- cgit v1.2.3 From a6174aaf5eec37f1d1713afa978ae16286fc0b74 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 10:35:47 +0200 Subject: Added log_cell() --- kernel/log.cc | 15 +++++++++++++++ kernel/log.h | 2 ++ 2 files changed, 17 insertions(+) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 3108bddfe..949bf4327 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -213,3 +213,18 @@ const char *log_id(std::string str) string_buf.push_back(str); return string_buf.back().c_str(); } + +void log_cell(RTLIL::Cell *cell, std::string indent) +{ + char *ptr; + size_t size; + + FILE *f = open_memstream(&ptr, &size); + ILANG_BACKEND::dump_cell(f, indent, cell); + fputc(0, f); + fclose(f); + + log("%s", ptr); + free(ptr); +} + diff --git a/kernel/log.h b/kernel/log.h index 2c3597c9a..f6dcc0ac2 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -57,6 +57,8 @@ template static inline const char *log_id(T *obj) { return log_id(obj->name); } +void log_cell(RTLIL::Cell *cell, std::string indent = ""); + #define log_abort() log_error("Abort in %s:%d.\n", __FILE__, __LINE__) #define log_assert(_assert_expr_) do { if (_assert_expr_) break; log_error("Assert `%s' failed in %s:%d.\n", #_assert_expr_, __FILE__, __LINE__); } while (0) -- cgit v1.2.3 From efa78840261871616f9af15e5ad9a5bc89f95857 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 10:36:14 +0200 Subject: Added SIZE() macro --- kernel/rtlil.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 3a22d1371..6290db21d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -26,7 +26,9 @@ #include #include +// various helpers (unrelated to RTLIL) std::string stringf(const char *fmt, ...); +#define SIZE(__obj) int(__obj.size()) namespace RTLIL { -- cgit v1.2.3 From e57db5e9b256d801c1d4337e44e1a7173a115d07 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 11:00:09 +0200 Subject: Added std::set to RTLIL::SigSpec conversion --- kernel/rtlil.cc | 13 ++++++++++--- kernel/rtlil.h | 1 + 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index dea0e1050..748deae3e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1451,10 +1451,17 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) RTLIL::SigSpec::SigSpec(std::vector bits) { - chunks.reserve(bits.size()); + this->width = 0; for (auto &bit : bits) - chunks.push_back(bit); - this->width = bits.size(); + append_bit(bit); + check(); +} + +RTLIL::SigSpec::SigSpec(std::set bits) +{ + this->width = 0; + for (auto &bit : bits) + append_bit(bit); check(); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6290db21d..64136de04 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -505,6 +505,7 @@ struct RTLIL::SigSpec { SigSpec(RTLIL::State bit, int width = 1); SigSpec(RTLIL::SigBit bit, int width = 1); SigSpec(std::vector bits); + SigSpec(std::set bits); void expand(); void optimize(); RTLIL::SigSpec optimized() const; -- cgit v1.2.3 From 8d04ca7d22e375fbe075dee1f189669046ee8906 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 15:16:10 +0200 Subject: Added call_on_selection() and call_on_module() API --- kernel/register.cc | 34 ++++++++++++++++++++++++++++++---- kernel/register.h | 7 +++++-- 2 files changed, 35 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 8da5a725f..84051948f 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -198,11 +198,11 @@ void Pass::call(RTLIL::Design *design, std::vector args) design->check(); } -void Pass::call_newsel(RTLIL::Design *design, std::string command) +void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command) { std::string backup_selected_active_module = design->selected_active_module; design->selected_active_module.clear(); - design->selection_stack.push_back(RTLIL::Selection()); + design->selection_stack.push_back(selection); Pass::call(design, command); @@ -210,11 +210,37 @@ void Pass::call_newsel(RTLIL::Design *design, std::string command) design->selected_active_module = backup_selected_active_module; } -void Pass::call_newsel(RTLIL::Design *design, std::vector args) +void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector args) { std::string backup_selected_active_module = design->selected_active_module; design->selected_active_module.clear(); - design->selection_stack.push_back(RTLIL::Selection()); + design->selection_stack.push_back(selection); + + Pass::call(design, args); + + design->selection_stack.pop_back(); + design->selected_active_module = backup_selected_active_module; +} + +void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command) +{ + std::string backup_selected_active_module = design->selected_active_module; + design->selected_active_module = module->name; + design->selection_stack.push_back(RTLIL::Selection(false)); + design->selection_stack.back().select(module); + + Pass::call(design, command); + + design->selection_stack.pop_back(); + design->selected_active_module = backup_selected_active_module; +} + +void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector args) +{ + std::string backup_selected_active_module = design->selected_active_module; + design->selected_active_module = module->name; + design->selection_stack.push_back(RTLIL::Selection(false)); + design->selection_stack.back().select(module); Pass::call(design, args); diff --git a/kernel/register.h b/kernel/register.h index f3d3f70ae..b07c46177 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -60,8 +60,11 @@ struct Pass static void call(RTLIL::Design *design, std::string command); static void call(RTLIL::Design *design, std::vector args); - static void call_newsel(RTLIL::Design *design, std::string command); - static void call_newsel(RTLIL::Design *design, std::vector args); + static void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command); + static void call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector args); + + static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command); + static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector args); static void init_register(); static void done_register(); -- cgit v1.2.3 From caae6e19dffde4d76b30af3fd1f9751f4ec37fdc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:01:45 +0200 Subject: Added log_ping() --- kernel/log.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index f6dcc0ac2..00265dbe0 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -61,6 +61,7 @@ void log_cell(RTLIL::Cell *cell, std::string indent = ""); #define log_abort() log_error("Abort in %s:%d.\n", __FILE__, __LINE__) #define log_assert(_assert_expr_) do { if (_assert_expr_) break; log_error("Assert `%s' failed in %s:%d.\n", #_assert_expr_, __FILE__, __LINE__); } while (0) +#define log_ping() log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__) // simple timer for performance measurements // toggle the '#if 1' to get a baseline for the perormance penalty added by the measurement -- cgit v1.2.3 From 54b0f2e659ac0c34c69b0c251c72b2a90fe8e6b6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:02:55 +0200 Subject: Added module->remove(), module->addWire(), module->addCell(), cell->check() --- kernel/rtlil.cc | 47 +++++++++++++++++++++++++++++++++++++++-------- kernel/rtlil.h | 5 +++++ 2 files changed, 44 insertions(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 748deae3e..b16b62ca1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -316,9 +316,9 @@ namespace { fputc(0, f); fclose(f); - log_error("Found error in internal cell %s.%s (%s) at %s:%d:\n%s", - module->name.c_str(), cell->name.c_str(), cell->type.c_str(), - __FILE__, linenr, ptr); + log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s", + module ? module->name.c_str() : "", module ? "." : "", + cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr); } int param(const char *name) @@ -395,6 +395,10 @@ namespace { void check() { + if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || + cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:") + return; + if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); @@ -740,11 +744,8 @@ void RTLIL::Module::check() for (auto &it2 : it.second->parameters) { assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); } - if (it.second->type[0] == '$' && it.second->type.substr(0, 3) != "$__" && it.second->type.substr(0, 8) != "$paramod" && - it.second->type.substr(0, 9) != "$verific$" && it.second->type.substr(0, 7) != "$array:") { - InternalCellChecker checker(this, it.second); - checker.check(); - } + InternalCellChecker checker(this, it.second); + checker.check(); } for (auto &it : processes) { @@ -841,6 +842,13 @@ void RTLIL::Module::add(RTLIL::Cell *cell) cells[cell->name] = cell; } +void RTLIL::Module::remove(RTLIL::Cell *cell) +{ + assert(cells.count(cell->name) != 0); + cells.erase(cell->name); + delete cell; +} + static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) { if (a->port_id && !b->port_id) @@ -868,6 +876,23 @@ void RTLIL::Module::fixup_ports() all_ports[i]->port_id = i+1; } +RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width) +{ + RTLIL::Wire *wire = new RTLIL::Wire; + wire->name = name; + wire->width = width; + add(wire); + return wire; +} + +RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) +{ + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = name; + cell->type = type; + add(cell); + return cell; +} #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ @@ -1285,6 +1310,12 @@ void RTLIL::Cell::optimize() it.second.optimize(); } +void RTLIL::Cell::check() +{ + InternalCellChecker checker(NULL, this); + checker.check(); +} + RTLIL::SigChunk::SigChunk() { wire = NULL; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 64136de04..19666481d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -290,12 +290,16 @@ struct RTLIL::Module { RTLIL::Wire *new_wire(int width, RTLIL::IdString name); void add(RTLIL::Wire *wire); void add(RTLIL::Cell *cell); + void remove(RTLIL::Cell *cell); void fixup_ports(); template void rewrite_sigspecs(T functor); void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; + RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + // The add* methods create a cell and return the created cell. All signals must exist in advance. RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); @@ -449,6 +453,7 @@ struct RTLIL::Cell { std::map parameters; RTLIL_ATTRIBUTE_MEMBERS void optimize(); + void check(); template void rewrite_sigspecs(T functor); }; -- cgit v1.2.3 From c54d1f2ad1a781363f9c35e4f7266f4560a6aba8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:03:41 +0200 Subject: Bugfix in satgen for cells with wider in- than outputs. --- kernel/satgen.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index 81d029295..281d2b26f 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -166,7 +166,15 @@ struct SatGen void undefGating(std::vector &vec_y, std::vector &vec_yy, std::vector &vec_undef) { assert(model_undef); - ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy)))); + assert(vec_y.size() == vec_yy.size()); + if (vec_y.size() > vec_undef.size()) { + std::vector trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size()); + std::vector trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size()); + ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy)))); + } else { + assert(vec_y.size() == vec_undef.size()); + ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy)))); + } } bool importCell(RTLIL::Cell *cell, int timestep = -1) -- cgit v1.2.3 From 1d88f1cf9f2088de7825f5292db5b40d4f73d036 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:35:06 +0200 Subject: Removed deprecated module->new_wire() --- kernel/rtlil.cc | 21 ++++++--------------- kernel/rtlil.h | 10 +++++----- 2 files changed, 11 insertions(+), 20 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b16b62ca1..d3d830d67 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -819,15 +819,6 @@ RTLIL::Module *RTLIL::Module::clone() const return new_mod; } -RTLIL::Wire *RTLIL::Module::new_wire(int width, RTLIL::IdString name) -{ - RTLIL::Wire *wire = new RTLIL::Wire; - wire->width = width; - wire->name = name; - add(wire); - return wire; -} - void RTLIL::Module::add(RTLIL::Wire *wire) { assert(!wire->name.empty()); @@ -908,7 +899,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \ - RTLIL::SigSpec sig_y = new_wire(_y_size, NEW_ID); \ + RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ add ## _func(name, sig_a, sig_y, is_signed); \ return sig_y; \ } @@ -941,7 +932,7 @@ DEF_METHOD(LogicNot, 1, "$logic_not") return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \ - RTLIL::SigSpec sig_y = new_wire(_y_size, NEW_ID); \ + RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ add ## _func(name, sig_a, sig_b, sig_y, is_signed); \ return sig_y; \ } @@ -986,7 +977,7 @@ DEF_METHOD(LogicOr, 1, "$logic_or") return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \ - RTLIL::SigSpec sig_y = new_wire(sig_a.width, NEW_ID); \ + RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.width); \ add ## _func(name, sig_a, sig_b, sig_s, sig_y); \ return sig_y; \ } @@ -1006,7 +997,7 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \ - RTLIL::SigSpec sig2 = new_wire(1, NEW_ID); \ + RTLIL::SigSpec sig2 = addWire(NEW_ID); \ add ## _func(name, sig1, sig2); \ return sig2; \ } @@ -1022,7 +1013,7 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ - RTLIL::SigSpec sig3 = new_wire(1, NEW_ID); \ + RTLIL::SigSpec sig3 = addWire(NEW_ID); \ add ## _func(name, sig1, sig2, sig3); \ return sig3; \ } @@ -1039,7 +1030,7 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ - RTLIL::SigSpec sig4 = new_wire(1, NEW_ID); \ + RTLIL::SigSpec sig4 = addWire(NEW_ID); \ add ## _func(name, sig1, sig2, sig3, sig4); \ return sig4; \ } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 19666481d..3c6c97242 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -142,7 +142,7 @@ namespace RTLIL RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) #define NEW_WIRE(_mod, _width) \ - (_mod)->new_wire(_width, NEW_ID) + (_mod)->addWire(NEW_ID, _width) template struct sort_by_name { bool operator()(T *a, T *b) const { @@ -287,16 +287,16 @@ struct RTLIL::Module { virtual size_t count_id(RTLIL::IdString id); virtual void check(); virtual void optimize(); - RTLIL::Wire *new_wire(int width, RTLIL::IdString name); - void add(RTLIL::Wire *wire); - void add(RTLIL::Cell *cell); - void remove(RTLIL::Cell *cell); void fixup_ports(); template void rewrite_sigspecs(T functor); void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; + void add(RTLIL::Wire *wire); + void add(RTLIL::Cell *cell); + void remove(RTLIL::Cell *cell); + RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); -- cgit v1.2.3 From 361e0d62ffd90b87c94bfc98ed3cbee1a745cd8f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:41:29 +0200 Subject: Replaced depricated NEW_WIRE macro with module->addWire() calls --- kernel/rtlil.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 3c6c97242..9b3e44179 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -141,9 +141,6 @@ namespace RTLIL #define NEW_ID \ RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) -#define NEW_WIRE(_mod, _width) \ - (_mod)->addWire(NEW_ID, _width) - template struct sort_by_name { bool operator()(T *a, T *b) const { return a->name < b->name; -- cgit v1.2.3 From 550ac3587302c6c95892c66db2cfa3788b2b5c42 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 13:28:12 +0200 Subject: Added support for scripts with labels --- kernel/driver.cc | 85 ++++++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 74 insertions(+), 11 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 577fbe3d9..e365e67c3 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -49,7 +49,30 @@ bool fgetline(FILE *f, std::string &buffer) } } -static void run_frontend(std::string filename, std::string command, RTLIL::Design *design, std::string *backend_command) +static void handle_label(std::string &command, bool &from_to_active, const std::string &run_from, const std::string &run_to) +{ + int pos = 0; + std::string label; + + while (pos < SIZE(command) && (command[pos] == ' ' || command[pos] == '\t')) + pos++; + + while (pos < SIZE(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n') + label += command[pos++]; + + if (label.back() == ':' && SIZE(label) > 1) + { + label = label.substr(0, SIZE(label)-1); + command = command.substr(pos); + + if (label == run_from) + from_to_active = true; + else if (label == run_to || (run_from == run_to && !run_from.empty())) + from_to_active = false; + } +} + +static void run_frontend(std::string filename, std::string command, RTLIL::Design *design, std::string *backend_command, std::string *from_to_label) { if (command == "auto") { if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") @@ -66,13 +89,33 @@ static void run_frontend(std::string filename, std::string command, RTLIL::Desig log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str()); } - if (command == "script") { + if (command == "script") + { + std::string run_from, run_to; + bool from_to_active = true; + + if (from_to_label != NULL) { + size_t pos = from_to_label->find(':'); + if (pos == std::string::npos) { + run_from = *from_to_label; + run_to = *from_to_label; + } else { + run_from = from_to_label->substr(0, pos); + run_to = from_to_label->substr(pos+1); + } + from_to_active = run_from.empty(); + } + log("\n-- Executing script file `%s' --\n", filename.c_str()); + FILE *f = stdin; + if (filename != "-") f = fopen(filename.c_str(), "r"); + if (f == NULL) log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); + std::string command; while (fgetline(f, command)) { while (!command.empty() && command[command.size()-1] == '\\') { @@ -82,14 +125,23 @@ static void run_frontend(std::string filename, std::string command, RTLIL::Desig command.resize(command.size()-1); command += next_line; } - Pass::call(design, command); + handle_label(command, from_to_active, run_from, run_to); + if (from_to_active) + Pass::call(design, command); } - if (!command.empty()) - Pass::call(design, command); + + if (!command.empty()) { + handle_label(command, from_to_active, run_from, run_to); + if (from_to_active) + Pass::call(design, command); + } + if (filename != "-") fclose(f); + if (backend_command != NULL && *backend_command == "auto") *backend_command = ""; + return; } @@ -340,17 +392,28 @@ struct ScriptPass : public Pass { ScriptPass() : Pass("script", "execute commands from script file") { } virtual void help() { log("\n"); - log(" script \n"); + log(" script [:]\n"); log("\n"); log("This command executes the yosys commands in the specified file.\n"); log("\n"); + log("The 2nd argument can be used to only execute the section of the\n"); + log("file between the specified labels. An empty from label is synonymous\n"); + log("for the beginning of the file and an empty to label is synonymous\n"); + log("for the end of the file.\n"); + log("\n"); + log("If only one label is specified (without ':') then only the block\n"); + log("marked with that label (until the next label) is executed.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { if (args.size() < 2) log_cmd_error("Missing script file.\n"); - if (args.size() > 2) - extra_args(args, 1, design, false); - run_frontend(args[1], "script", design, NULL); + else if (args.size() == 2) + run_frontend(args[1], "script", design, NULL, NULL); + else if (args.size() == 3) + run_frontend(args[1], "script", design, NULL, &args[2]); + else + extra_args(args, 2, design, false); } } ScriptPass; @@ -663,7 +726,7 @@ int main(int argc, char **argv) } while (optind < argc) - run_frontend(argv[optind++], frontend_command, yosys_design, output_filename == "-" ? &backend_command : NULL); + run_frontend(argv[optind++], frontend_command, yosys_design, output_filename == "-" ? &backend_command : NULL, NULL); if (!scriptfile.empty()) { if (scriptfile_tcl) { @@ -674,7 +737,7 @@ int main(int argc, char **argv) log_error("Can't exectue TCL script: this version of yosys is not built with TCL support enabled.\n"); #endif } else - run_frontend(scriptfile, "script", yosys_design, output_filename == "-" ? &backend_command : NULL); + run_frontend(scriptfile, "script", yosys_design, output_filename == "-" ? &backend_command : NULL, NULL); } for (auto it = passes_commands.begin(); it != passes_commands.end(); it++) -- cgit v1.2.3 From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- kernel/bitpattern.h | 12 +- kernel/consteval.h | 18 +-- kernel/rtlil.cc | 386 ++++++++++++++++++++++++++-------------------------- kernel/rtlil.h | 11 +- kernel/satgen.h | 14 +- kernel/sigtools.h | 50 +++---- 6 files changed, 247 insertions(+), 244 deletions(-) (limited to 'kernel') diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index aaefa50fc..0ca26bb34 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -31,16 +31,16 @@ struct BitPatternPool BitPatternPool(RTLIL::SigSpec sig) { - width = sig.width; + width = sig.__width; if (width > 0) { std::vector pattern(width); sig.optimize(); for (int i = 0; i < width; i++) { RTLIL::SigSpec s = sig.extract(i, 1); s.optimize(); - assert(s.chunks.size() == 1); - if (s.chunks[0].wire == NULL && s.chunks[0].data.bits[0] <= RTLIL::State::S1) - pattern[i] = s.chunks[0].data.bits[0]; + assert(s.__chunks.size() == 1); + if (s.__chunks[0].wire == NULL && s.__chunks[0].data.bits[0] <= RTLIL::State::S1) + pattern[i] = s.__chunks[0].data.bits[0]; else pattern[i] = RTLIL::State::Sa; } @@ -63,8 +63,8 @@ struct BitPatternPool { sig.optimize(); assert(sig.is_fully_const()); - assert(sig.chunks.size() == 1); - bits_t bits = sig.chunks[0].data.bits; + assert(sig.__chunks.size() == 1); + bits_t bits = sig.__chunks[0].data.bits; for (auto &b : bits) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; diff --git a/kernel/consteval.h b/kernel/consteval.h index 10116ccfe..fa079e14e 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -72,8 +72,8 @@ struct ConstEval #ifndef NDEBUG RTLIL::SigSpec current_val = values_map(sig); current_val.expand(); - for (size_t i = 0; i < current_val.chunks.size(); i++) { - RTLIL::SigChunk &chunk = current_val.chunks[i]; + for (size_t i = 0; i < current_val.__chunks.size(); i++) { + RTLIL::SigChunk &chunk = current_val.__chunks[i]; assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]); } #endif @@ -113,10 +113,10 @@ struct ConstEval int count_maybe_set_s_bits = 0; int count_set_s_bits = 0; - for (int i = 0; i < sig_s.width; i++) + for (int i = 0; i < sig_s.__width; i++) { RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0); - RTLIL::SigSpec b_slice = sig_b.extract(sig_y.width*i, sig_y.width); + RTLIL::SigSpec b_slice = sig_b.extract(sig_y.__width*i, sig_y.__width); if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1) y_candidates.push_back(b_slice); @@ -162,9 +162,9 @@ struct ConstEval } else { - if (sig_a.width > 0 && !eval(sig_a, undef, cell)) + if (sig_a.__width > 0 && !eval(sig_a, undef, cell)) return false; - if (sig_b.width > 0 && !eval(sig_b, undef, cell)) + if (sig_b.__width > 0 && !eval(sig_b, undef, cell)) return false; set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const())); } @@ -210,9 +210,9 @@ struct ConstEval if (sig.is_fully_const()) return true; - for (size_t i = 0; i < sig.chunks.size(); i++) - if (sig.chunks[i].wire != NULL) - undef.append(sig.chunks[i]); + for (size_t i = 0; i < sig.__chunks.size(); i++) + if (sig.__chunks[i].wire != NULL) + undef.append(sig.__chunks[i]); return false; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d3d830d67..3a646dc62 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -350,7 +350,7 @@ namespace { { if (cell->connections.count(name) == 0) error(__LINE__); - if (cell->connections.at(name).width != width) + if (cell->connections.at(name).__width != width) error(__LINE__); expected_ports.insert(name); } @@ -381,7 +381,7 @@ namespace { char portname[3] = { '\\', *p, 0 }; if (cell->connections.count(portname) == 0) error(__LINE__); - if (cell->connections.at(portname).width != 1) + if (cell->connections.at(portname).__width != 1) error(__LINE__); } @@ -755,7 +755,7 @@ void RTLIL::Module::check() } for (auto &it : connections) { - assert(it.first.width == it.second.width); + assert(it.first.__width == it.second.__width); it.first.check(); it.second.check(); } @@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const RTLIL::Module *mod; void operator()(RTLIL::SigSpec &sig) { - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (c.wire != NULL) c.wire = mod->wires.at(c.wire->name); } @@ -891,8 +891,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) cell->name = name; \ cell->type = _type; \ cell->parameters["\\A_SIGNED"] = is_signed; \ - cell->parameters["\\A_WIDTH"] = sig_a.width; \ - cell->parameters["\\Y_WIDTH"] = sig_y.width; \ + cell->parameters["\\A_WIDTH"] = sig_a.__width; \ + cell->parameters["\\Y_WIDTH"] = sig_y.__width; \ cell->connections["\\A"] = sig_a; \ cell->connections["\\Y"] = sig_y; \ add(cell); \ @@ -903,10 +903,10 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) add ## _func(name, sig_a, sig_y, is_signed); \ return sig_y; \ } -DEF_METHOD(Not, sig_a.width, "$not") -DEF_METHOD(Pos, sig_a.width, "$pos") -DEF_METHOD(Bu0, sig_a.width, "$bu0") -DEF_METHOD(Neg, sig_a.width, "$neg") +DEF_METHOD(Not, sig_a.__width, "$not") +DEF_METHOD(Pos, sig_a.__width, "$pos") +DEF_METHOD(Bu0, sig_a.__width, "$bu0") +DEF_METHOD(Neg, sig_a.__width, "$neg") DEF_METHOD(ReduceAnd, 1, "$reduce_and") DEF_METHOD(ReduceOr, 1, "$reduce_or") DEF_METHOD(ReduceXor, 1, "$reduce_xor") @@ -922,9 +922,9 @@ DEF_METHOD(LogicNot, 1, "$logic_not") cell->type = _type; \ cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\B_SIGNED"] = is_signed; \ - cell->parameters["\\A_WIDTH"] = sig_a.width; \ - cell->parameters["\\B_WIDTH"] = sig_b.width; \ - cell->parameters["\\Y_WIDTH"] = sig_y.width; \ + cell->parameters["\\A_WIDTH"] = sig_a.__width; \ + cell->parameters["\\B_WIDTH"] = sig_b.__width; \ + cell->parameters["\\Y_WIDTH"] = sig_y.__width; \ cell->connections["\\A"] = sig_a; \ cell->connections["\\B"] = sig_b; \ cell->connections["\\Y"] = sig_y; \ @@ -936,14 +936,14 @@ DEF_METHOD(LogicNot, 1, "$logic_not") add ## _func(name, sig_a, sig_b, sig_y, is_signed); \ return sig_y; \ } -DEF_METHOD(And, std::max(sig_a.width, sig_b.width), "$and") -DEF_METHOD(Or, std::max(sig_a.width, sig_b.width), "$or") -DEF_METHOD(Xor, std::max(sig_a.width, sig_b.width), "$xor") -DEF_METHOD(Xnor, std::max(sig_a.width, sig_b.width), "$xnor") -DEF_METHOD(Shl, sig_a.width, "$shl") -DEF_METHOD(Shr, sig_a.width, "$shr") -DEF_METHOD(Sshl, sig_a.width, "$sshl") -DEF_METHOD(Sshr, sig_a.width, "$sshr") +DEF_METHOD(And, std::max(sig_a.__width, sig_b.__width), "$and") +DEF_METHOD(Or, std::max(sig_a.__width, sig_b.__width), "$or") +DEF_METHOD(Xor, std::max(sig_a.__width, sig_b.__width), "$xor") +DEF_METHOD(Xnor, std::max(sig_a.__width, sig_b.__width), "$xnor") +DEF_METHOD(Shl, sig_a.__width, "$shl") +DEF_METHOD(Shr, sig_a.__width, "$shr") +DEF_METHOD(Sshl, sig_a.__width, "$sshl") +DEF_METHOD(Sshr, sig_a.__width, "$sshr") DEF_METHOD(Lt, 1, "$lt") DEF_METHOD(Le, 1, "$le") DEF_METHOD(Eq, 1, "$eq") @@ -952,11 +952,11 @@ DEF_METHOD(Eqx, 1, "$eqx") DEF_METHOD(Nex, 1, "$nex") DEF_METHOD(Ge, 1, "$ge") DEF_METHOD(Gt, 1, "$gt") -DEF_METHOD(Add, std::max(sig_a.width, sig_b.width), "$add") -DEF_METHOD(Sub, std::max(sig_a.width, sig_b.width), "$sub") -DEF_METHOD(Mul, std::max(sig_a.width, sig_b.width), "$mul") -DEF_METHOD(Div, std::max(sig_a.width, sig_b.width), "$div") -DEF_METHOD(Mod, std::max(sig_a.width, sig_b.width), "$mod") +DEF_METHOD(Add, std::max(sig_a.__width, sig_b.__width), "$add") +DEF_METHOD(Sub, std::max(sig_a.__width, sig_b.__width), "$sub") +DEF_METHOD(Mul, std::max(sig_a.__width, sig_b.__width), "$mul") +DEF_METHOD(Div, std::max(sig_a.__width, sig_b.__width), "$div") +DEF_METHOD(Mod, std::max(sig_a.__width, sig_b.__width), "$mod") DEF_METHOD(LogicAnd, 1, "$logic_and") DEF_METHOD(LogicOr, 1, "$logic_or") #undef DEF_METHOD @@ -966,9 +966,9 @@ DEF_METHOD(LogicOr, 1, "$logic_or") RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->parameters["\\WIDTH"] = sig_a.width; \ - cell->parameters["\\WIDTH"] = sig_b.width; \ - if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.width; \ + cell->parameters["\\WIDTH"] = sig_a.__width; \ + cell->parameters["\\WIDTH"] = sig_b.__width; \ + if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.__width; \ cell->connections["\\A"] = sig_a; \ cell->connections["\\B"] = sig_b; \ cell->connections["\\S"] = sig_s; \ @@ -977,7 +977,7 @@ DEF_METHOD(LogicOr, 1, "$logic_or") return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.width); \ + RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.__width); \ add ## _func(name, sig_a, sig_b, sig_s, sig_y); \ return sig_y; \ } @@ -1050,9 +1050,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R cell->type = "$pow"; cell->parameters["\\A_SIGNED"] = a_signed; cell->parameters["\\B_SIGNED"] = b_signed; - cell->parameters["\\A_WIDTH"] = sig_a.width; - cell->parameters["\\B_WIDTH"] = sig_b.width; - cell->parameters["\\Y_WIDTH"] = sig_y.width; + cell->parameters["\\A_WIDTH"] = sig_a.__width; + cell->parameters["\\B_WIDTH"] = sig_b.__width; + cell->parameters["\\Y_WIDTH"] = sig_y.__width; cell->connections["\\A"] = sig_a; cell->connections["\\B"] = sig_b; cell->connections["\\Y"] = sig_y; @@ -1065,8 +1065,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = "$slice"; - cell->parameters["\\A_WIDTH"] = sig_a.width; - cell->parameters["\\Y_WIDTH"] = sig_y.width; + cell->parameters["\\A_WIDTH"] = sig_a.__width; + cell->parameters["\\Y_WIDTH"] = sig_y.__width; cell->parameters["\\OFFSET"] = offset; cell->connections["\\A"] = sig_a; cell->connections["\\Y"] = sig_y; @@ -1079,8 +1079,8 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = "$concat"; - cell->parameters["\\A_WIDTH"] = sig_a.width; - cell->parameters["\\B_WIDTH"] = sig_b.width; + cell->parameters["\\A_WIDTH"] = sig_a.__width; + cell->parameters["\\B_WIDTH"] = sig_b.__width; cell->connections["\\A"] = sig_a; cell->connections["\\B"] = sig_b; cell->connections["\\Y"] = sig_y; @@ -1094,7 +1094,7 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R cell->name = name; cell->type = "$lut"; cell->parameters["\\LUT"] = lut; - cell->parameters["\\WIDTH"] = sig_i.width; + cell->parameters["\\WIDTH"] = sig_i.__width; cell->connections["\\I"] = sig_i; cell->connections["\\O"] = sig_o; add(cell); @@ -1119,7 +1119,7 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, cell->type = "$sr"; cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.width; + cell->parameters["\\WIDTH"] = sig_q.__width; cell->connections["\\SET"] = sig_set; cell->connections["\\CLR"] = sig_clr; cell->connections["\\Q"] = sig_q; @@ -1133,7 +1133,7 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, cell->name = name; cell->type = "$dff"; cell->parameters["\\CLK_POLARITY"] = clk_polarity; - cell->parameters["\\WIDTH"] = sig_q.width; + cell->parameters["\\WIDTH"] = sig_q.__width; cell->connections["\\CLK"] = sig_clk; cell->connections["\\D"] = sig_d; cell->connections["\\Q"] = sig_q; @@ -1150,7 +1150,7 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.width; + cell->parameters["\\WIDTH"] = sig_q.__width; cell->connections["\\CLK"] = sig_clk; cell->connections["\\SET"] = sig_set; cell->connections["\\CLR"] = sig_clr; @@ -1169,7 +1169,7 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\ARST_POLARITY"] = arst_polarity; cell->parameters["\\ARST_VALUE"] = arst_value; - cell->parameters["\\WIDTH"] = sig_q.width; + cell->parameters["\\WIDTH"] = sig_q.__width; cell->connections["\\CLK"] = sig_clk; cell->connections["\\ARST"] = sig_arst; cell->connections["\\D"] = sig_d; @@ -1184,7 +1184,7 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e cell->name = name; cell->type = "$dlatch"; cell->parameters["\\EN_POLARITY"] = en_polarity; - cell->parameters["\\WIDTH"] = sig_q.width; + cell->parameters["\\WIDTH"] = sig_q.__width; cell->connections["\\EN"] = sig_en; cell->connections["\\D"] = sig_d; cell->connections["\\Q"] = sig_q; @@ -1201,7 +1201,7 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig cell->parameters["\\EN_POLARITY"] = en_polarity; cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.width; + cell->parameters["\\WIDTH"] = sig_q.__width; cell->connections["\\EN"] = sig_en; cell->connections["\\SET"] = sig_set; cell->connections["\\CLR"] = sig_clr; @@ -1415,65 +1415,65 @@ bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const RTLIL::SigSpec::SigSpec() { - width = 0; + __width = 0; } RTLIL::SigSpec::SigSpec(const RTLIL::Const &data) { - chunks.push_back(RTLIL::SigChunk(data)); - width = chunks.back().width; + __chunks.push_back(RTLIL::SigChunk(data)); + __width = __chunks.back().width; check(); } RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) { - chunks.push_back(chunk); - width = chunks.back().width; + __chunks.push_back(chunk); + __width = __chunks.back().width; check(); } RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset) { - chunks.push_back(RTLIL::SigChunk(wire, width, offset)); - this->width = chunks.back().width; + __chunks.push_back(RTLIL::SigChunk(wire, width, offset)); + __width = __chunks.back().width; check(); } RTLIL::SigSpec::SigSpec(const std::string &str) { - chunks.push_back(RTLIL::SigChunk(str)); - width = chunks.back().width; + __chunks.push_back(RTLIL::SigChunk(str)); + __width = __chunks.back().width; check(); } RTLIL::SigSpec::SigSpec(int val, int width) { - chunks.push_back(RTLIL::SigChunk(val, width)); - this->width = width; + __chunks.push_back(RTLIL::SigChunk(val, width)); + __width = width; check(); } RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) { - chunks.push_back(RTLIL::SigChunk(bit, width)); - this->width = width; + __chunks.push_back(RTLIL::SigChunk(bit, width)); + __width = width; check(); } RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) { if (bit.wire == NULL) - chunks.push_back(RTLIL::SigChunk(bit.data, width)); + __chunks.push_back(RTLIL::SigChunk(bit.data, width)); else for (int i = 0; i < width; i++) - chunks.push_back(bit); - this->width = width; + __chunks.push_back(bit); + __width = width; check(); } RTLIL::SigSpec::SigSpec(std::vector bits) { - this->width = 0; + __width = 0; for (auto &bit : bits) append_bit(bit); check(); @@ -1481,7 +1481,7 @@ RTLIL::SigSpec::SigSpec(std::vector bits) RTLIL::SigSpec::SigSpec(std::set bits) { - this->width = 0; + __width = 0; for (auto &bit : bits) append_bit(bit); check(); @@ -1490,18 +1490,18 @@ RTLIL::SigSpec::SigSpec(std::set bits) void RTLIL::SigSpec::expand() { std::vector new_chunks; - for (size_t i = 0; i < chunks.size(); i++) { - for (int j = 0; j < chunks[i].width; j++) - new_chunks.push_back(chunks[i].extract(j, 1)); + for (size_t i = 0; i < __chunks.size(); i++) { + for (int j = 0; j < __chunks[i].width; j++) + new_chunks.push_back(__chunks[i].extract(j, 1)); } - chunks.swap(new_chunks); + __chunks.swap(new_chunks); check(); } void RTLIL::SigSpec::optimize() { std::vector new_chunks; - for (auto &c : chunks) + for (auto &c : __chunks) if (new_chunks.size() == 0) { new_chunks.push_back(c); } else { @@ -1513,7 +1513,7 @@ void RTLIL::SigSpec::optimize() else new_chunks.push_back(c); } - chunks.swap(new_chunks); + __chunks.swap(new_chunks); check(); } @@ -1544,20 +1544,20 @@ bool RTLIL::SigChunk::compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b void RTLIL::SigSpec::sort() { expand(); - std::sort(chunks.begin(), chunks.end(), RTLIL::SigChunk::compare); + std::sort(__chunks.begin(), __chunks.end(), RTLIL::SigChunk::compare); optimize(); } void RTLIL::SigSpec::sort_and_unify() { expand(); - std::sort(chunks.begin(), chunks.end(), RTLIL::SigChunk::compare); - for (size_t i = 1; i < chunks.size(); i++) { - RTLIL::SigChunk &ch1 = chunks[i-1]; - RTLIL::SigChunk &ch2 = chunks[i]; + std::sort(__chunks.begin(), __chunks.end(), RTLIL::SigChunk::compare); + for (size_t i = 1; i < __chunks.size(); i++) { + RTLIL::SigChunk &ch1 = __chunks[i-1]; + RTLIL::SigChunk &ch2 = __chunks[i]; if (!RTLIL::SigChunk::compare(ch1, ch2) && !RTLIL::SigChunk::compare(ch2, ch1)) { - chunks.erase(chunks.begin()+i); - width -= chunks[i].width; + __chunks.erase(__chunks.begin()+i); + __width -= __chunks[i].width; i--; } } @@ -1572,13 +1572,13 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const { int pos = 0, restart_pos = 0; - assert(other == NULL || width == other->width); - for (size_t i = 0; i < chunks.size(); i++) { + assert(other == NULL || __width == other->__width); + for (size_t i = 0; i < __chunks.size(); i++) { restart: - const RTLIL::SigChunk &ch1 = chunks[i]; - if (chunks[i].wire != NULL && pos >= restart_pos) - for (size_t j = 0, poff = 0; j < pattern.chunks.size(); j++) { - const RTLIL::SigChunk &ch2 = pattern.chunks[j]; + const RTLIL::SigChunk &ch1 = __chunks[i]; + if (__chunks[i].wire != NULL && pos >= restart_pos) + for (size_t j = 0, poff = 0; j < pattern.__chunks.size(); j++) { + const RTLIL::SigChunk &ch2 = pattern.__chunks[j]; assert(ch2.wire != NULL); if (ch1.wire == ch2.wire) { int lower = std::max(ch1.offset, ch2.offset); @@ -1591,7 +1591,7 @@ restart: } poff += ch2.width; } - pos += chunks[i].width; + pos += __chunks[i].width; } check(); } @@ -1610,13 +1610,13 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) { int pos = 0; - assert(other == NULL || width == other->width); - for (size_t i = 0; i < chunks.size(); i++) { + assert(other == NULL || __width == other->__width); + for (size_t i = 0; i < __chunks.size(); i++) { restart: - const RTLIL::SigChunk &ch1 = chunks[i]; - if (chunks[i].wire != NULL) - for (size_t j = 0; j < pattern.chunks.size(); j++) { - const RTLIL::SigChunk &ch2 = pattern.chunks[j]; + const RTLIL::SigChunk &ch1 = __chunks[i]; + if (__chunks[i].wire != NULL) + for (size_t j = 0; j < pattern.__chunks.size(); j++) { + const RTLIL::SigChunk &ch2 = pattern.__chunks[j]; assert(ch2.wire != NULL); if (ch1.wire == ch2.wire) { int lower = std::max(ch1.offset, ch2.offset); @@ -1625,20 +1625,20 @@ restart: if (other) other->remove(pos+lower-ch1.offset, upper-lower); remove(pos+lower-ch1.offset, upper-lower); - if (i == chunks.size()) + if (i == __chunks.size()) break; goto restart; } } } - pos += chunks[i].width; + pos += __chunks[i].width; } check(); } RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other) const { - assert(other == NULL || width == other->width); + assert(other == NULL || __width == other->__width); std::set pat = pattern.to_sigbit_set(); std::vector bits_match = to_sigbit_vector(); @@ -1646,11 +1646,11 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o if (other) { std::vector bits_other = other ? other->to_sigbit_vector() : bits_match; - for (int i = 0; i < width; i++) + for (int i = 0; i < __width; i++) if (bits_match[i].wire && pat.count(bits_match[i])) ret.append_bit(bits_other[i]); } else { - for (int i = 0; i < width; i++) + for (int i = 0; i < __width; i++) if (bits_match[i].wire && pat.count(bits_match[i])) ret.append_bit(bits_match[i]); } @@ -1663,31 +1663,31 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) { int pos = 0; assert(offset >= 0); - assert(with.width >= 0); - assert(offset+with.width <= width); - remove(offset, with.width); - for (size_t i = 0; i < chunks.size(); i++) { + assert(with.__width >= 0); + assert(offset+with.__width <= __width); + remove(offset, with.__width); + for (size_t i = 0; i < __chunks.size(); i++) { if (pos == offset) { - chunks.insert(chunks.begin()+i, with.chunks.begin(), with.chunks.end()); - width += with.width; + __chunks.insert(__chunks.begin()+i, with.__chunks.begin(), with.__chunks.end()); + __width += with.__width; check(); return; } - pos += chunks[i].width; + pos += __chunks[i].width; } assert(pos == offset); - chunks.insert(chunks.end(), with.chunks.begin(), with.chunks.end()); - width += with.width; + __chunks.insert(__chunks.end(), with.__chunks.begin(), with.__chunks.end()); + __width += with.__width; check(); } void RTLIL::SigSpec::remove_const() { - for (size_t i = 0; i < chunks.size(); i++) { - if (chunks[i].wire != NULL) + for (size_t i = 0; i < __chunks.size(); i++) { + if (__chunks[i].wire != NULL) continue; - width -= chunks[i].width; - chunks.erase(chunks.begin() + (i--)); + __width -= __chunks[i].width; + __chunks.erase(__chunks.begin() + (i--)); } check(); } @@ -1697,34 +1697,34 @@ void RTLIL::SigSpec::remove(int offset, int length) int pos = 0; assert(offset >= 0); assert(length >= 0); - assert(offset+length <= width); - for (size_t i = 0; i < chunks.size(); i++) { - int orig_width = chunks[i].width; - if (pos+chunks[i].width > offset && pos < offset+length) { + assert(offset+length <= __width); + for (size_t i = 0; i < __chunks.size(); i++) { + int orig_width = __chunks[i].width; + if (pos+__chunks[i].width > offset && pos < offset+length) { int off = offset - pos; int len = length; if (off < 0) { len += off; off = 0; } - if (len > chunks[i].width-off) - len = chunks[i].width-off; - RTLIL::SigChunk lsb_chunk = chunks[i].extract(0, off); - RTLIL::SigChunk msb_chunk = chunks[i].extract(off+len, chunks[i].width-off-len); + if (len > __chunks[i].width-off) + len = __chunks[i].width-off; + RTLIL::SigChunk lsb_chunk = __chunks[i].extract(0, off); + RTLIL::SigChunk msb_chunk = __chunks[i].extract(off+len, __chunks[i].width-off-len); if (lsb_chunk.width == 0 && msb_chunk.width == 0) { - chunks.erase(chunks.begin()+i); + __chunks.erase(__chunks.begin()+i); i--; } else if (lsb_chunk.width == 0 && msb_chunk.width != 0) { - chunks[i] = msb_chunk; + __chunks[i] = msb_chunk; } else if (lsb_chunk.width != 0 && msb_chunk.width == 0) { - chunks[i] = lsb_chunk; + __chunks[i] = lsb_chunk; } else if (lsb_chunk.width != 0 && msb_chunk.width != 0) { - chunks[i] = lsb_chunk; - chunks.insert(chunks.begin()+i+1, msb_chunk); + __chunks[i] = lsb_chunk; + __chunks.insert(__chunks.begin()+i+1, msb_chunk); i++; } else assert(0); - width -= len; + __width -= len; } pos += orig_width; } @@ -1737,23 +1737,23 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const RTLIL::SigSpec ret; assert(offset >= 0); assert(length >= 0); - assert(offset+length <= width); - for (size_t i = 0; i < chunks.size(); i++) { - if (pos+chunks[i].width > offset && pos < offset+length) { + assert(offset+length <= __width); + for (size_t i = 0; i < __chunks.size(); i++) { + if (pos+__chunks[i].width > offset && pos < offset+length) { int off = offset - pos; int len = length; if (off < 0) { len += off; off = 0; } - if (len > chunks[i].width-off) - len = chunks[i].width-off; - ret.chunks.push_back(chunks[i].extract(off, len)); - ret.width += len; + if (len > __chunks[i].width-off) + len = __chunks[i].width-off; + ret.__chunks.push_back(__chunks[i].extract(off, len)); + ret.__width += len; offset += len; length -= len; } - pos += chunks[i].width; + pos += __chunks[i].width; } assert(length == 0); ret.check(); @@ -1762,30 +1762,30 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) { - for (size_t i = 0; i < signal.chunks.size(); i++) { - chunks.push_back(signal.chunks[i]); - width += signal.chunks[i].width; + for (size_t i = 0; i < signal.__chunks.size(); i++) { + __chunks.push_back(signal.__chunks[i]); + __width += signal.__chunks[i].width; } // check(); } void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) { - if (chunks.size() == 0) - chunks.push_back(bit); + if (__chunks.size() == 0) + __chunks.push_back(bit); else if (bit.wire == NULL) - if (chunks.back().wire == NULL) { - chunks.back().data.bits.push_back(bit.data); - chunks.back().width++; + if (__chunks.back().wire == NULL) { + __chunks.back().data.bits.push_back(bit.data); + __chunks.back().width++; } else - chunks.push_back(bit); + __chunks.push_back(bit); else - if (chunks.back().wire == bit.wire && chunks.back().offset + chunks.back().width == bit.offset) - chunks.back().width++; + if (__chunks.back().wire == bit.wire && __chunks.back().offset + __chunks.back().width == bit.offset) + __chunks.back().width++; else - chunks.push_back(bit); - width++; + __chunks.push_back(bit); + __width++; // check(); } @@ -1793,22 +1793,22 @@ bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool { bool no_collisions = true; - assert(width == signal.width); + assert(__width == signal.__width); expand(); signal.expand(); - for (size_t i = 0; i < chunks.size(); i++) { - bool self_free = chunks[i].wire == NULL && chunks[i].data.bits[0] == freeState; - bool other_free = signal.chunks[i].wire == NULL && signal.chunks[i].data.bits[0] == freeState; + for (size_t i = 0; i < __chunks.size(); i++) { + bool self_free = __chunks[i].wire == NULL && __chunks[i].data.bits[0] == freeState; + bool other_free = signal.__chunks[i].wire == NULL && signal.__chunks[i].data.bits[0] == freeState; if (!self_free && !other_free) { if (override) - chunks[i] = signal.chunks[i]; + __chunks[i] = signal.__chunks[i]; else - chunks[i] = RTLIL::SigChunk(RTLIL::State::Sx, 1); + __chunks[i] = RTLIL::SigChunk(RTLIL::State::Sx, 1); no_collisions = false; } if (self_free && !other_free) - chunks[i] = signal.chunks[i]; + __chunks[i] = signal.__chunks[i]; } optimize(); @@ -1817,15 +1817,15 @@ bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool void RTLIL::SigSpec::extend(int width, bool is_signed) { - if (this->width > width) - remove(width, this->width - width); + if (__width > width) + remove(width, __width - width); - if (this->width < width) { - RTLIL::SigSpec padding = this->width > 0 ? extract(this->width - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); + if (__width < width) { + RTLIL::SigSpec padding = __width > 0 ? extract(__width - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) && padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm)) padding = RTLIL::SigSpec(RTLIL::State::S0); - while (this->width < width) + while (__width < width) append(padding); } @@ -1834,14 +1834,14 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { - if (this->width > width) - remove(width, this->width - width); + if (__width > width) + remove(width, __width - width); - if (this->width < width) { - RTLIL::SigSpec padding = this->width > 0 ? extract(this->width - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); + if (__width < width) { + RTLIL::SigSpec padding = __width > 0 ? extract(__width - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); if (!is_signed) padding = RTLIL::SigSpec(RTLIL::State::S0); - while (this->width < width) + while (__width < width) append(padding); } @@ -1851,8 +1851,8 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) void RTLIL::SigSpec::check() const { int w = 0; - for (size_t i = 0; i < chunks.size(); i++) { - const RTLIL::SigChunk chunk = chunks[i]; + for (size_t i = 0; i < __chunks.size(); i++) { + const RTLIL::SigChunk chunk = __chunks[i]; if (chunk.wire == NULL) { assert(chunk.offset == 0); assert(chunk.data.bits.size() == (size_t)chunk.width); @@ -1864,42 +1864,42 @@ void RTLIL::SigSpec::check() const } w += chunk.width; } - assert(w == width); + assert(w == __width); } bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const { - if (width != other.width) - return width < other.width; + if (__width != other.__width) + return __width < other.__width; RTLIL::SigSpec a = *this, b = other; a.optimize(); b.optimize(); - if (a.chunks.size() != b.chunks.size()) - return a.chunks.size() < b.chunks.size(); + if (a.__chunks.size() != b.__chunks.size()) + return a.__chunks.size() < b.__chunks.size(); - for (size_t i = 0; i < a.chunks.size(); i++) - if (a.chunks[i] != b.chunks[i]) - return a.chunks[i] < b.chunks[i]; + for (size_t i = 0; i < a.__chunks.size(); i++) + if (a.__chunks[i] != b.__chunks[i]) + return a.__chunks[i] < b.__chunks[i]; return false; } bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const { - if (width != other.width) + if (__width != other.__width) return false; RTLIL::SigSpec a = *this, b = other; a.optimize(); b.optimize(); - if (a.chunks.size() != b.chunks.size()) + if (a.__chunks.size() != b.__chunks.size()) return false; - for (size_t i = 0; i < a.chunks.size(); i++) - if (a.chunks[i] != b.chunks[i]) + for (size_t i = 0; i < a.__chunks.size(); i++) + if (a.__chunks[i] != b.__chunks[i]) return false; return true; @@ -1914,7 +1914,7 @@ bool RTLIL::SigSpec::operator !=(const RTLIL::SigSpec &other) const bool RTLIL::SigSpec::is_fully_const() const { - for (auto it = chunks.begin(); it != chunks.end(); it++) + for (auto it = __chunks.begin(); it != __chunks.end(); it++) if (it->width > 0 && it->wire != NULL) return false; return true; @@ -1922,7 +1922,7 @@ bool RTLIL::SigSpec::is_fully_const() const bool RTLIL::SigSpec::is_fully_def() const { - for (auto it = chunks.begin(); it != chunks.end(); it++) { + for (auto it = __chunks.begin(); it != __chunks.end(); it++) { if (it->width > 0 && it->wire != NULL) return false; for (size_t i = 0; i < it->data.bits.size(); i++) @@ -1934,7 +1934,7 @@ bool RTLIL::SigSpec::is_fully_def() const bool RTLIL::SigSpec::is_fully_undef() const { - for (auto it = chunks.begin(); it != chunks.end(); it++) { + for (auto it = __chunks.begin(); it != __chunks.end(); it++) { if (it->width > 0 && it->wire != NULL) return false; for (size_t i = 0; i < it->data.bits.size(); i++) @@ -1946,7 +1946,7 @@ bool RTLIL::SigSpec::is_fully_undef() const bool RTLIL::SigSpec::has_marked_bits() const { - for (auto it = chunks.begin(); it != chunks.end(); it++) + for (auto it = __chunks.begin(); it != __chunks.end(); it++) if (it->width > 0 && it->wire == NULL) { for (size_t i = 0; i < it->data.bits.size(); i++) if (it->data.bits[i] == RTLIL::State::Sm) @@ -1960,8 +1960,8 @@ bool RTLIL::SigSpec::as_bool() const assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); - if (sig.width) - return sig.chunks[0].data.as_bool(); + if (sig.__width) + return sig.__chunks[0].data.as_bool(); return false; } @@ -1970,16 +1970,16 @@ int RTLIL::SigSpec::as_int() const assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); - if (sig.width) - return sig.chunks[0].data.as_int(); + if (sig.__width) + return sig.__chunks[0].data.as_int(); return 0; } std::string RTLIL::SigSpec::as_string() const { std::string str; - for (size_t i = chunks.size(); i > 0; i--) { - const RTLIL::SigChunk &chunk = chunks[i-1]; + for (size_t i = __chunks.size(); i > 0; i--) { + const RTLIL::SigChunk &chunk = __chunks[i-1]; if (chunk.wire != NULL) for (int j = 0; j < chunk.width; j++) str += "?"; @@ -1994,8 +1994,8 @@ RTLIL::Const RTLIL::SigSpec::as_const() const assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); - if (sig.width) - return sig.chunks[0].data; + if (sig.__width) + return sig.__chunks[0].data; return RTLIL::Const(); } @@ -2022,7 +2022,7 @@ bool RTLIL::SigSpec::match(std::string pattern) const std::set RTLIL::SigSpec::to_sigbit_set() const { std::set sigbits; - for (auto &c : chunks) + for (auto &c : __chunks) for (int i = 0; i < c.width; i++) sigbits.insert(RTLIL::SigBit(c, i)); return sigbits; @@ -2031,8 +2031,8 @@ std::set RTLIL::SigSpec::to_sigbit_set() const std::vector RTLIL::SigSpec::to_sigbit_vector() const { std::vector sigbits; - sigbits.reserve(width); - for (auto &c : chunks) + sigbits.reserve(__width); + for (auto &c : __chunks) for (int i = 0; i < c.width; i++) sigbits.push_back(RTLIL::SigBit(c, i)); return sigbits; @@ -2040,8 +2040,8 @@ std::vector RTLIL::SigSpec::to_sigbit_vector() const RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const { - log_assert(width == 1); - for (auto &c : chunks) + log_assert(__width == 1); + for (auto &c : __chunks) if (c.width) return RTLIL::SigBit(c); log_abort(); @@ -2155,20 +2155,20 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str) { if (str == "0") { - sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width); + sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.__width); return true; } if (str == "~0") { - sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width); + sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.__width); return true; } - if (lhs.chunks.size() == 1) { + if (lhs.__chunks.size() == 1) { char *p = (char*)str.c_str(), *endptr; long long int val = strtoll(p, &endptr, 10); if (endptr && endptr != p && *endptr == 0) { - sig = RTLIL::SigSpec(val, lhs.width); + sig = RTLIL::SigSpec(val, lhs.__width); return true; } } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9b3e44179..0919b3926 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -496,8 +496,11 @@ struct RTLIL::SigBit { }; struct RTLIL::SigSpec { - std::vector chunks; // LSB at index 0 - int width; +public: + std::vector __chunks; // LSB at index 0 + int __width; + +public: SigSpec(); SigSpec(const RTLIL::Const &data); SigSpec(const RTLIL::SigChunk &chunk); @@ -551,8 +554,8 @@ struct RTLIL::SigSpec { }; inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { - assert(sig.width == 1 && sig.chunks.size() == 1); - *this = SigBit(sig.chunks[0]); + assert(sig.__width == 1 && sig.__chunks.size() == 1); + *this = SigBit(sig.__chunks[0]); } struct RTLIL::CaseRule { diff --git a/kernel/satgen.h b/kernel/satgen.h index 281d2b26f..012b6ab89 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -55,9 +55,9 @@ struct SatGen sig.expand(); std::vector vec; - vec.reserve(sig.chunks.size()); + vec.reserve(sig.__chunks.size()); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (c.wire == NULL) { RTLIL::State bit = c.data.bits.at(0); if (model_undef && dup_undef && bit == RTLIL::State::Sx) @@ -118,7 +118,7 @@ struct SatGen if (timestep_rhs < 0) timestep_rhs = timestep_lhs; - assert(lhs.width == rhs.width); + assert(lhs.__width == rhs.__width); std::vector vec_lhs = importSigSpec(lhs, timestep_lhs); std::vector vec_rhs = importSigSpec(rhs, timestep_rhs); @@ -130,7 +130,7 @@ struct SatGen std::vector undef_rhs = importUndefSigSpec(rhs, timestep_rhs); std::vector eq_bits; - for (int i = 0; i < lhs.width; i++) + for (int i = 0; i < lhs.__width; i++) eq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)), ez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i))))); return ez->expression(ezSAT::OpAnd, eq_bits); @@ -742,11 +742,11 @@ struct SatGen only_first_one.at(0) = ez->TRUE; div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones); } else { - div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").width, ez->TRUE); + div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").__width, ez->TRUE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE); } } else { - int copy_a_bits = std::min(cell->connections.at("\\A").width, cell->connections.at("\\B").width); + int copy_a_bits = std::min(cell->connections.at("\\A").__width, cell->connections.at("\\B").__width); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); @@ -768,7 +768,7 @@ struct SatGen { RTLIL::SigSpec a = cell->connections.at("\\A"); RTLIL::SigSpec y = cell->connections.at("\\Y"); - ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.width), y, timestep)); + ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.__width), y, timestep)); return true; } diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 56497bb83..c886ff168 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -38,7 +38,7 @@ struct SigPool void add(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -56,7 +56,7 @@ struct SigPool void del(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -75,10 +75,10 @@ struct SigPool { from.expand(); to.expand(); - assert(from.chunks.size() == to.chunks.size()); - for (size_t i = 0; i < from.chunks.size(); i++) { - bitDef_t bit_from(from.chunks[i].wire, from.chunks[i].offset); - bitDef_t bit_to(to.chunks[i].wire, to.chunks[i].offset); + assert(from.__chunks.size() == to.__chunks.size()); + for (size_t i = 0; i < from.__chunks.size(); i++) { + bitDef_t bit_from(from.__chunks[i].wire, from.__chunks[i].offset); + bitDef_t bit_to(to.__chunks[i].wire, to.__chunks[i].offset); if (bit_from.first == NULL || bit_to.first == NULL) continue; if (bits.count(bit_from) > 0) @@ -90,7 +90,7 @@ struct SigPool { RTLIL::SigSpec result; sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; bitDef_t bit(c.wire, c.offset); @@ -104,7 +104,7 @@ struct SigPool { RTLIL::SigSpec result; sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; bitDef_t bit(c.wire, c.offset); @@ -117,7 +117,7 @@ struct SigPool bool check_any(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; bitDef_t bit(c.wire, c.offset); @@ -130,7 +130,7 @@ struct SigPool bool check_all(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; bitDef_t bit(c.wire, c.offset); @@ -179,7 +179,7 @@ struct SigSet void insert(RTLIL::SigSpec sig, T data) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -191,7 +191,7 @@ struct SigSet void insert(RTLIL::SigSpec sig, const std::set &data) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -203,7 +203,7 @@ struct SigSet void erase(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -215,7 +215,7 @@ struct SigSet void erase(RTLIL::SigSpec sig, T data) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -227,7 +227,7 @@ struct SigSet void erase(RTLIL::SigSpec sig, const std::set &data) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -239,7 +239,7 @@ struct SigSet void find(RTLIL::SigSpec sig, std::set &result) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -259,7 +259,7 @@ struct SigSet bool has(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -420,11 +420,11 @@ struct SigMap from.expand(); to.expand(); - assert(from.chunks.size() == to.chunks.size()); - for (size_t i = 0; i < from.chunks.size(); i++) + assert(from.__chunks.size() == to.__chunks.size()); + for (size_t i = 0; i < from.__chunks.size(); i++) { - RTLIL::SigChunk &cf = from.chunks[i]; - RTLIL::SigChunk &ct = to.chunks[i]; + RTLIL::SigChunk &cf = from.__chunks[i]; + RTLIL::SigChunk &ct = to.__chunks[i]; if (cf.wire == NULL) continue; @@ -442,9 +442,9 @@ struct SigMap void add(RTLIL::SigSpec sig) { sig.expand(); - for (size_t i = 0; i < sig.chunks.size(); i++) + for (size_t i = 0; i < sig.__chunks.size(); i++) { - RTLIL::SigChunk &c = sig.chunks[i]; + RTLIL::SigChunk &c = sig.__chunks[i]; if (c.wire != NULL) { register_bit(c); set_bit(c, c); @@ -455,14 +455,14 @@ struct SigMap void del(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) unregister_bit(c); } void apply(RTLIL::SigSpec &sig) const { sig.expand(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) map_bit(c); sig.optimize(); } -- cgit v1.2.3 From 16e5ae0b92ac4b7568cb11a769e612e152c0042e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:12:15 +0200 Subject: SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions --- kernel/rtlil.cc | 298 ++++++++++++++++++++++++++++---------------------------- kernel/rtlil.h | 12 ++- 2 files changed, 158 insertions(+), 152 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3a646dc62..043323095 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1415,65 +1415,65 @@ bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const RTLIL::SigSpec::SigSpec() { - __width = 0; + width_ = 0; } RTLIL::SigSpec::SigSpec(const RTLIL::Const &data) { - __chunks.push_back(RTLIL::SigChunk(data)); - __width = __chunks.back().width; + chunks_.push_back(RTLIL::SigChunk(data)); + width_ = chunks_.back().width; check(); } RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) { - __chunks.push_back(chunk); - __width = __chunks.back().width; + chunks_.push_back(chunk); + width_ = chunks_.back().width; check(); } RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset) { - __chunks.push_back(RTLIL::SigChunk(wire, width, offset)); - __width = __chunks.back().width; + chunks_.push_back(RTLIL::SigChunk(wire, width, offset)); + width_ = chunks_.back().width; check(); } RTLIL::SigSpec::SigSpec(const std::string &str) { - __chunks.push_back(RTLIL::SigChunk(str)); - __width = __chunks.back().width; + chunks_.push_back(RTLIL::SigChunk(str)); + width_ = chunks_.back().width; check(); } RTLIL::SigSpec::SigSpec(int val, int width) { - __chunks.push_back(RTLIL::SigChunk(val, width)); - __width = width; + chunks_.push_back(RTLIL::SigChunk(val, width)); + width_ = width; check(); } RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) { - __chunks.push_back(RTLIL::SigChunk(bit, width)); - __width = width; + chunks_.push_back(RTLIL::SigChunk(bit, width)); + width_ = width; check(); } RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) { if (bit.wire == NULL) - __chunks.push_back(RTLIL::SigChunk(bit.data, width)); + chunks_.push_back(RTLIL::SigChunk(bit.data, width)); else for (int i = 0; i < width; i++) - __chunks.push_back(bit); - __width = width; + chunks_.push_back(bit); + width_ = width; check(); } RTLIL::SigSpec::SigSpec(std::vector bits) { - __width = 0; + width_ = 0; for (auto &bit : bits) append_bit(bit); check(); @@ -1481,7 +1481,7 @@ RTLIL::SigSpec::SigSpec(std::vector bits) RTLIL::SigSpec::SigSpec(std::set bits) { - __width = 0; + width_ = 0; for (auto &bit : bits) append_bit(bit); check(); @@ -1490,18 +1490,18 @@ RTLIL::SigSpec::SigSpec(std::set bits) void RTLIL::SigSpec::expand() { std::vector new_chunks; - for (size_t i = 0; i < __chunks.size(); i++) { - for (int j = 0; j < __chunks[i].width; j++) - new_chunks.push_back(__chunks[i].extract(j, 1)); + for (size_t i = 0; i < chunks_.size(); i++) { + for (int j = 0; j < chunks_[i].width; j++) + new_chunks.push_back(chunks_[i].extract(j, 1)); } - __chunks.swap(new_chunks); + chunks_.swap(new_chunks); check(); } void RTLIL::SigSpec::optimize() { std::vector new_chunks; - for (auto &c : __chunks) + for (auto &c : chunks_) if (new_chunks.size() == 0) { new_chunks.push_back(c); } else { @@ -1513,7 +1513,7 @@ void RTLIL::SigSpec::optimize() else new_chunks.push_back(c); } - __chunks.swap(new_chunks); + chunks_.swap(new_chunks); check(); } @@ -1544,20 +1544,20 @@ bool RTLIL::SigChunk::compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b void RTLIL::SigSpec::sort() { expand(); - std::sort(__chunks.begin(), __chunks.end(), RTLIL::SigChunk::compare); + std::sort(chunks_.begin(), chunks_.end(), RTLIL::SigChunk::compare); optimize(); } void RTLIL::SigSpec::sort_and_unify() { expand(); - std::sort(__chunks.begin(), __chunks.end(), RTLIL::SigChunk::compare); - for (size_t i = 1; i < __chunks.size(); i++) { - RTLIL::SigChunk &ch1 = __chunks[i-1]; - RTLIL::SigChunk &ch2 = __chunks[i]; + std::sort(chunks_.begin(), chunks_.end(), RTLIL::SigChunk::compare); + for (size_t i = 1; i < chunks_.size(); i++) { + RTLIL::SigChunk &ch1 = chunks_[i-1]; + RTLIL::SigChunk &ch2 = chunks_[i]; if (!RTLIL::SigChunk::compare(ch1, ch2) && !RTLIL::SigChunk::compare(ch2, ch1)) { - __chunks.erase(__chunks.begin()+i); - __width -= __chunks[i].width; + chunks_.erase(chunks_.begin()+i); + width_ -= chunks_[i].width; i--; } } @@ -1572,13 +1572,13 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const { int pos = 0, restart_pos = 0; - assert(other == NULL || __width == other->__width); - for (size_t i = 0; i < __chunks.size(); i++) { + assert(other == NULL || width_ == other->width_); + for (size_t i = 0; i < chunks_.size(); i++) { restart: - const RTLIL::SigChunk &ch1 = __chunks[i]; - if (__chunks[i].wire != NULL && pos >= restart_pos) - for (size_t j = 0, poff = 0; j < pattern.__chunks.size(); j++) { - const RTLIL::SigChunk &ch2 = pattern.__chunks[j]; + const RTLIL::SigChunk &ch1 = chunks_[i]; + if (chunks_[i].wire != NULL && pos >= restart_pos) + for (size_t j = 0, poff = 0; j < pattern.chunks_.size(); j++) { + const RTLIL::SigChunk &ch2 = pattern.chunks_[j]; assert(ch2.wire != NULL); if (ch1.wire == ch2.wire) { int lower = std::max(ch1.offset, ch2.offset); @@ -1591,7 +1591,7 @@ restart: } poff += ch2.width; } - pos += __chunks[i].width; + pos += chunks_[i].width; } check(); } @@ -1610,13 +1610,13 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) { int pos = 0; - assert(other == NULL || __width == other->__width); - for (size_t i = 0; i < __chunks.size(); i++) { + assert(other == NULL || width_ == other->width_); + for (size_t i = 0; i < chunks_.size(); i++) { restart: - const RTLIL::SigChunk &ch1 = __chunks[i]; - if (__chunks[i].wire != NULL) - for (size_t j = 0; j < pattern.__chunks.size(); j++) { - const RTLIL::SigChunk &ch2 = pattern.__chunks[j]; + const RTLIL::SigChunk &ch1 = chunks_[i]; + if (chunks_[i].wire != NULL) + for (size_t j = 0; j < pattern.chunks_.size(); j++) { + const RTLIL::SigChunk &ch2 = pattern.chunks_[j]; assert(ch2.wire != NULL); if (ch1.wire == ch2.wire) { int lower = std::max(ch1.offset, ch2.offset); @@ -1625,20 +1625,20 @@ restart: if (other) other->remove(pos+lower-ch1.offset, upper-lower); remove(pos+lower-ch1.offset, upper-lower); - if (i == __chunks.size()) + if (i == chunks_.size()) break; goto restart; } } } - pos += __chunks[i].width; + pos += chunks_[i].width; } check(); } RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other) const { - assert(other == NULL || __width == other->__width); + assert(other == NULL || width_ == other->width_); std::set pat = pattern.to_sigbit_set(); std::vector bits_match = to_sigbit_vector(); @@ -1646,11 +1646,11 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o if (other) { std::vector bits_other = other ? other->to_sigbit_vector() : bits_match; - for (int i = 0; i < __width; i++) + for (int i = 0; i < width_; i++) if (bits_match[i].wire && pat.count(bits_match[i])) ret.append_bit(bits_other[i]); } else { - for (int i = 0; i < __width; i++) + for (int i = 0; i < width_; i++) if (bits_match[i].wire && pat.count(bits_match[i])) ret.append_bit(bits_match[i]); } @@ -1663,31 +1663,31 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) { int pos = 0; assert(offset >= 0); - assert(with.__width >= 0); - assert(offset+with.__width <= __width); - remove(offset, with.__width); - for (size_t i = 0; i < __chunks.size(); i++) { + assert(with.width_ >= 0); + assert(offset+with.width_ <= width_); + remove(offset, with.width_); + for (size_t i = 0; i < chunks_.size(); i++) { if (pos == offset) { - __chunks.insert(__chunks.begin()+i, with.__chunks.begin(), with.__chunks.end()); - __width += with.__width; + chunks_.insert(chunks_.begin()+i, with.chunks_.begin(), with.chunks_.end()); + width_ += with.width_; check(); return; } - pos += __chunks[i].width; + pos += chunks_[i].width; } assert(pos == offset); - __chunks.insert(__chunks.end(), with.__chunks.begin(), with.__chunks.end()); - __width += with.__width; + chunks_.insert(chunks_.end(), with.chunks_.begin(), with.chunks_.end()); + width_ += with.width_; check(); } void RTLIL::SigSpec::remove_const() { - for (size_t i = 0; i < __chunks.size(); i++) { - if (__chunks[i].wire != NULL) + for (size_t i = 0; i < chunks_.size(); i++) { + if (chunks_[i].wire != NULL) continue; - __width -= __chunks[i].width; - __chunks.erase(__chunks.begin() + (i--)); + width_ -= chunks_[i].width; + chunks_.erase(chunks_.begin() + (i--)); } check(); } @@ -1697,34 +1697,34 @@ void RTLIL::SigSpec::remove(int offset, int length) int pos = 0; assert(offset >= 0); assert(length >= 0); - assert(offset+length <= __width); - for (size_t i = 0; i < __chunks.size(); i++) { - int orig_width = __chunks[i].width; - if (pos+__chunks[i].width > offset && pos < offset+length) { + assert(offset+length <= width_); + for (size_t i = 0; i < chunks_.size(); i++) { + int orig_width = chunks_[i].width; + if (pos+chunks_[i].width > offset && pos < offset+length) { int off = offset - pos; int len = length; if (off < 0) { len += off; off = 0; } - if (len > __chunks[i].width-off) - len = __chunks[i].width-off; - RTLIL::SigChunk lsb_chunk = __chunks[i].extract(0, off); - RTLIL::SigChunk msb_chunk = __chunks[i].extract(off+len, __chunks[i].width-off-len); + if (len > chunks_[i].width-off) + len = chunks_[i].width-off; + RTLIL::SigChunk lsb_chunk = chunks_[i].extract(0, off); + RTLIL::SigChunk msb_chunk = chunks_[i].extract(off+len, chunks_[i].width-off-len); if (lsb_chunk.width == 0 && msb_chunk.width == 0) { - __chunks.erase(__chunks.begin()+i); + chunks_.erase(chunks_.begin()+i); i--; } else if (lsb_chunk.width == 0 && msb_chunk.width != 0) { - __chunks[i] = msb_chunk; + chunks_[i] = msb_chunk; } else if (lsb_chunk.width != 0 && msb_chunk.width == 0) { - __chunks[i] = lsb_chunk; + chunks_[i] = lsb_chunk; } else if (lsb_chunk.width != 0 && msb_chunk.width != 0) { - __chunks[i] = lsb_chunk; - __chunks.insert(__chunks.begin()+i+1, msb_chunk); + chunks_[i] = lsb_chunk; + chunks_.insert(chunks_.begin()+i+1, msb_chunk); i++; } else assert(0); - __width -= len; + width_ -= len; } pos += orig_width; } @@ -1737,23 +1737,23 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const RTLIL::SigSpec ret; assert(offset >= 0); assert(length >= 0); - assert(offset+length <= __width); - for (size_t i = 0; i < __chunks.size(); i++) { - if (pos+__chunks[i].width > offset && pos < offset+length) { + assert(offset+length <= width_); + for (size_t i = 0; i < chunks_.size(); i++) { + if (pos+chunks_[i].width > offset && pos < offset+length) { int off = offset - pos; int len = length; if (off < 0) { len += off; off = 0; } - if (len > __chunks[i].width-off) - len = __chunks[i].width-off; - ret.__chunks.push_back(__chunks[i].extract(off, len)); - ret.__width += len; + if (len > chunks_[i].width-off) + len = chunks_[i].width-off; + ret.chunks_.push_back(chunks_[i].extract(off, len)); + ret.width_ += len; offset += len; length -= len; } - pos += __chunks[i].width; + pos += chunks_[i].width; } assert(length == 0); ret.check(); @@ -1762,30 +1762,30 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) { - for (size_t i = 0; i < signal.__chunks.size(); i++) { - __chunks.push_back(signal.__chunks[i]); - __width += signal.__chunks[i].width; + for (size_t i = 0; i < signal.chunks_.size(); i++) { + chunks_.push_back(signal.chunks_[i]); + width_ += signal.chunks_[i].width; } // check(); } void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) { - if (__chunks.size() == 0) - __chunks.push_back(bit); + if (chunks_.size() == 0) + chunks_.push_back(bit); else if (bit.wire == NULL) - if (__chunks.back().wire == NULL) { - __chunks.back().data.bits.push_back(bit.data); - __chunks.back().width++; + if (chunks_.back().wire == NULL) { + chunks_.back().data.bits.push_back(bit.data); + chunks_.back().width++; } else - __chunks.push_back(bit); + chunks_.push_back(bit); else - if (__chunks.back().wire == bit.wire && __chunks.back().offset + __chunks.back().width == bit.offset) - __chunks.back().width++; + if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset) + chunks_.back().width++; else - __chunks.push_back(bit); - __width++; + chunks_.push_back(bit); + width_++; // check(); } @@ -1793,22 +1793,22 @@ bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool { bool no_collisions = true; - assert(__width == signal.__width); + assert(width_ == signal.width_); expand(); signal.expand(); - for (size_t i = 0; i < __chunks.size(); i++) { - bool self_free = __chunks[i].wire == NULL && __chunks[i].data.bits[0] == freeState; - bool other_free = signal.__chunks[i].wire == NULL && signal.__chunks[i].data.bits[0] == freeState; + for (size_t i = 0; i < chunks_.size(); i++) { + bool self_free = chunks_[i].wire == NULL && chunks_[i].data.bits[0] == freeState; + bool other_free = signal.chunks_[i].wire == NULL && signal.chunks_[i].data.bits[0] == freeState; if (!self_free && !other_free) { if (override) - __chunks[i] = signal.__chunks[i]; + chunks_[i] = signal.chunks_[i]; else - __chunks[i] = RTLIL::SigChunk(RTLIL::State::Sx, 1); + chunks_[i] = RTLIL::SigChunk(RTLIL::State::Sx, 1); no_collisions = false; } if (self_free && !other_free) - __chunks[i] = signal.__chunks[i]; + chunks_[i] = signal.chunks_[i]; } optimize(); @@ -1817,15 +1817,15 @@ bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool void RTLIL::SigSpec::extend(int width, bool is_signed) { - if (__width > width) - remove(width, __width - width); + if (width_ > width) + remove(width, width_ - width); - if (__width < width) { - RTLIL::SigSpec padding = __width > 0 ? extract(__width - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); + if (width_ < width) { + RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) && padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm)) padding = RTLIL::SigSpec(RTLIL::State::S0); - while (__width < width) + while (width_ < width) append(padding); } @@ -1834,14 +1834,14 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { - if (__width > width) - remove(width, __width - width); + if (width_ > width) + remove(width, width_ - width); - if (__width < width) { - RTLIL::SigSpec padding = __width > 0 ? extract(__width - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); + if (width_ < width) { + RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0); if (!is_signed) padding = RTLIL::SigSpec(RTLIL::State::S0); - while (__width < width) + while (width_ < width) append(padding); } @@ -1851,8 +1851,8 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) void RTLIL::SigSpec::check() const { int w = 0; - for (size_t i = 0; i < __chunks.size(); i++) { - const RTLIL::SigChunk chunk = __chunks[i]; + for (size_t i = 0; i < chunks_.size(); i++) { + const RTLIL::SigChunk chunk = chunks_[i]; if (chunk.wire == NULL) { assert(chunk.offset == 0); assert(chunk.data.bits.size() == (size_t)chunk.width); @@ -1864,42 +1864,42 @@ void RTLIL::SigSpec::check() const } w += chunk.width; } - assert(w == __width); + assert(w == width_); } bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const { - if (__width != other.__width) - return __width < other.__width; + if (width_ != other.width_) + return width_ < other.width_; RTLIL::SigSpec a = *this, b = other; a.optimize(); b.optimize(); - if (a.__chunks.size() != b.__chunks.size()) - return a.__chunks.size() < b.__chunks.size(); + if (a.chunks_.size() != b.chunks_.size()) + return a.chunks_.size() < b.chunks_.size(); - for (size_t i = 0; i < a.__chunks.size(); i++) - if (a.__chunks[i] != b.__chunks[i]) - return a.__chunks[i] < b.__chunks[i]; + for (size_t i = 0; i < a.chunks_.size(); i++) + if (a.chunks_[i] != b.chunks_[i]) + return a.chunks_[i] < b.chunks_[i]; return false; } bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const { - if (__width != other.__width) + if (width_ != other.width_) return false; RTLIL::SigSpec a = *this, b = other; a.optimize(); b.optimize(); - if (a.__chunks.size() != b.__chunks.size()) + if (a.chunks_.size() != b.chunks_.size()) return false; - for (size_t i = 0; i < a.__chunks.size(); i++) - if (a.__chunks[i] != b.__chunks[i]) + for (size_t i = 0; i < a.chunks_.size(); i++) + if (a.chunks_[i] != b.chunks_[i]) return false; return true; @@ -1914,7 +1914,7 @@ bool RTLIL::SigSpec::operator !=(const RTLIL::SigSpec &other) const bool RTLIL::SigSpec::is_fully_const() const { - for (auto it = __chunks.begin(); it != __chunks.end(); it++) + for (auto it = chunks_.begin(); it != chunks_.end(); it++) if (it->width > 0 && it->wire != NULL) return false; return true; @@ -1922,7 +1922,7 @@ bool RTLIL::SigSpec::is_fully_const() const bool RTLIL::SigSpec::is_fully_def() const { - for (auto it = __chunks.begin(); it != __chunks.end(); it++) { + for (auto it = chunks_.begin(); it != chunks_.end(); it++) { if (it->width > 0 && it->wire != NULL) return false; for (size_t i = 0; i < it->data.bits.size(); i++) @@ -1934,7 +1934,7 @@ bool RTLIL::SigSpec::is_fully_def() const bool RTLIL::SigSpec::is_fully_undef() const { - for (auto it = __chunks.begin(); it != __chunks.end(); it++) { + for (auto it = chunks_.begin(); it != chunks_.end(); it++) { if (it->width > 0 && it->wire != NULL) return false; for (size_t i = 0; i < it->data.bits.size(); i++) @@ -1946,7 +1946,7 @@ bool RTLIL::SigSpec::is_fully_undef() const bool RTLIL::SigSpec::has_marked_bits() const { - for (auto it = __chunks.begin(); it != __chunks.end(); it++) + for (auto it = chunks_.begin(); it != chunks_.end(); it++) if (it->width > 0 && it->wire == NULL) { for (size_t i = 0; i < it->data.bits.size(); i++) if (it->data.bits[i] == RTLIL::State::Sm) @@ -1960,8 +1960,8 @@ bool RTLIL::SigSpec::as_bool() const assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); - if (sig.__width) - return sig.__chunks[0].data.as_bool(); + if (sig.width_) + return sig.chunks_[0].data.as_bool(); return false; } @@ -1970,16 +1970,16 @@ int RTLIL::SigSpec::as_int() const assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); - if (sig.__width) - return sig.__chunks[0].data.as_int(); + if (sig.width_) + return sig.chunks_[0].data.as_int(); return 0; } std::string RTLIL::SigSpec::as_string() const { std::string str; - for (size_t i = __chunks.size(); i > 0; i--) { - const RTLIL::SigChunk &chunk = __chunks[i-1]; + for (size_t i = chunks_.size(); i > 0; i--) { + const RTLIL::SigChunk &chunk = chunks_[i-1]; if (chunk.wire != NULL) for (int j = 0; j < chunk.width; j++) str += "?"; @@ -1994,8 +1994,8 @@ RTLIL::Const RTLIL::SigSpec::as_const() const assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); - if (sig.__width) - return sig.__chunks[0].data; + if (sig.width_) + return sig.chunks_[0].data; return RTLIL::Const(); } @@ -2022,7 +2022,7 @@ bool RTLIL::SigSpec::match(std::string pattern) const std::set RTLIL::SigSpec::to_sigbit_set() const { std::set sigbits; - for (auto &c : __chunks) + for (auto &c : chunks_) for (int i = 0; i < c.width; i++) sigbits.insert(RTLIL::SigBit(c, i)); return sigbits; @@ -2031,8 +2031,8 @@ std::set RTLIL::SigSpec::to_sigbit_set() const std::vector RTLIL::SigSpec::to_sigbit_vector() const { std::vector sigbits; - sigbits.reserve(__width); - for (auto &c : __chunks) + sigbits.reserve(width_); + for (auto &c : chunks_) for (int i = 0; i < c.width; i++) sigbits.push_back(RTLIL::SigBit(c, i)); return sigbits; @@ -2040,8 +2040,8 @@ std::vector RTLIL::SigSpec::to_sigbit_vector() const RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const { - log_assert(__width == 1); - for (auto &c : __chunks) + log_assert(width_ == 1); + for (auto &c : chunks_) if (c.width) return RTLIL::SigBit(c); log_abort(); @@ -2155,20 +2155,20 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str) { if (str == "0") { - sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.__width); + sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_); return true; } if (str == "~0") { - sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.__width); + sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_); return true; } - if (lhs.__chunks.size() == 1) { + if (lhs.chunks_.size() == 1) { char *p = (char*)str.c_str(), *endptr; long long int val = strtoll(p, &endptr, 10); if (endptr && endptr != p && *endptr == 0) { - sig = RTLIL::SigSpec(val, lhs.__width); + sig = RTLIL::SigSpec(val, lhs.width_); return true; } } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0919b3926..7fb416f1f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -496,11 +496,17 @@ struct RTLIL::SigBit { }; struct RTLIL::SigSpec { -public: - std::vector __chunks; // LSB at index 0 - int __width; +private: + std::vector chunks_; // LSB at index 0 + int width_; public: + std::vector &chunks() { return chunks_; } + const std::vector &chunks() const { return chunks_; } + + int &size() { return width_; } + const int &size() const { return width_; } + SigSpec(); SigSpec(const RTLIL::Const &data); SigSpec(const RTLIL::SigChunk &chunk); -- cgit v1.2.3 From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- kernel/bitpattern.h | 12 ++++---- kernel/consteval.h | 18 +++++------ kernel/rtlil.cc | 88 ++++++++++++++++++++++++++--------------------------- kernel/rtlil.h | 4 +-- kernel/satgen.h | 14 ++++----- kernel/sigtools.h | 50 +++++++++++++++--------------- 6 files changed, 93 insertions(+), 93 deletions(-) (limited to 'kernel') diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 0ca26bb34..934796d24 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -31,16 +31,16 @@ struct BitPatternPool BitPatternPool(RTLIL::SigSpec sig) { - width = sig.__width; + width = sig.size(); if (width > 0) { std::vector pattern(width); sig.optimize(); for (int i = 0; i < width; i++) { RTLIL::SigSpec s = sig.extract(i, 1); s.optimize(); - assert(s.__chunks.size() == 1); - if (s.__chunks[0].wire == NULL && s.__chunks[0].data.bits[0] <= RTLIL::State::S1) - pattern[i] = s.__chunks[0].data.bits[0]; + assert(s.chunks().size() == 1); + if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1) + pattern[i] = s.chunks()[0].data.bits[0]; else pattern[i] = RTLIL::State::Sa; } @@ -63,8 +63,8 @@ struct BitPatternPool { sig.optimize(); assert(sig.is_fully_const()); - assert(sig.__chunks.size() == 1); - bits_t bits = sig.__chunks[0].data.bits; + assert(sig.chunks().size() == 1); + bits_t bits = sig.chunks()[0].data.bits; for (auto &b : bits) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; diff --git a/kernel/consteval.h b/kernel/consteval.h index fa079e14e..564098c6a 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -72,8 +72,8 @@ struct ConstEval #ifndef NDEBUG RTLIL::SigSpec current_val = values_map(sig); current_val.expand(); - for (size_t i = 0; i < current_val.__chunks.size(); i++) { - RTLIL::SigChunk &chunk = current_val.__chunks[i]; + for (size_t i = 0; i < current_val.chunks().size(); i++) { + RTLIL::SigChunk &chunk = current_val.chunks()[i]; assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]); } #endif @@ -113,10 +113,10 @@ struct ConstEval int count_maybe_set_s_bits = 0; int count_set_s_bits = 0; - for (int i = 0; i < sig_s.__width; i++) + for (int i = 0; i < sig_s.size(); i++) { RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0); - RTLIL::SigSpec b_slice = sig_b.extract(sig_y.__width*i, sig_y.__width); + RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size()); if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1) y_candidates.push_back(b_slice); @@ -162,9 +162,9 @@ struct ConstEval } else { - if (sig_a.__width > 0 && !eval(sig_a, undef, cell)) + if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) return false; - if (sig_b.__width > 0 && !eval(sig_b, undef, cell)) + if (sig_b.size() > 0 && !eval(sig_b, undef, cell)) return false; set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const())); } @@ -210,9 +210,9 @@ struct ConstEval if (sig.is_fully_const()) return true; - for (size_t i = 0; i < sig.__chunks.size(); i++) - if (sig.__chunks[i].wire != NULL) - undef.append(sig.__chunks[i]); + for (size_t i = 0; i < sig.chunks().size(); i++) + if (sig.chunks()[i].wire != NULL) + undef.append(sig.chunks()[i]); return false; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 043323095..43511304e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -350,7 +350,7 @@ namespace { { if (cell->connections.count(name) == 0) error(__LINE__); - if (cell->connections.at(name).__width != width) + if (cell->connections.at(name).size() != width) error(__LINE__); expected_ports.insert(name); } @@ -381,7 +381,7 @@ namespace { char portname[3] = { '\\', *p, 0 }; if (cell->connections.count(portname) == 0) error(__LINE__); - if (cell->connections.at(portname).__width != 1) + if (cell->connections.at(portname).size() != 1) error(__LINE__); } @@ -755,7 +755,7 @@ void RTLIL::Module::check() } for (auto &it : connections) { - assert(it.first.__width == it.second.__width); + assert(it.first.size() == it.second.size()); it.first.check(); it.second.check(); } @@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const RTLIL::Module *mod; void operator()(RTLIL::SigSpec &sig) { - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire != NULL) c.wire = mod->wires.at(c.wire->name); } @@ -891,8 +891,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) cell->name = name; \ cell->type = _type; \ cell->parameters["\\A_SIGNED"] = is_signed; \ - cell->parameters["\\A_WIDTH"] = sig_a.__width; \ - cell->parameters["\\Y_WIDTH"] = sig_y.__width; \ + cell->parameters["\\A_WIDTH"] = sig_a.size(); \ + cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ cell->connections["\\A"] = sig_a; \ cell->connections["\\Y"] = sig_y; \ add(cell); \ @@ -903,10 +903,10 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) add ## _func(name, sig_a, sig_y, is_signed); \ return sig_y; \ } -DEF_METHOD(Not, sig_a.__width, "$not") -DEF_METHOD(Pos, sig_a.__width, "$pos") -DEF_METHOD(Bu0, sig_a.__width, "$bu0") -DEF_METHOD(Neg, sig_a.__width, "$neg") +DEF_METHOD(Not, sig_a.size(), "$not") +DEF_METHOD(Pos, sig_a.size(), "$pos") +DEF_METHOD(Bu0, sig_a.size(), "$bu0") +DEF_METHOD(Neg, sig_a.size(), "$neg") DEF_METHOD(ReduceAnd, 1, "$reduce_and") DEF_METHOD(ReduceOr, 1, "$reduce_or") DEF_METHOD(ReduceXor, 1, "$reduce_xor") @@ -922,9 +922,9 @@ DEF_METHOD(LogicNot, 1, "$logic_not") cell->type = _type; \ cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\B_SIGNED"] = is_signed; \ - cell->parameters["\\A_WIDTH"] = sig_a.__width; \ - cell->parameters["\\B_WIDTH"] = sig_b.__width; \ - cell->parameters["\\Y_WIDTH"] = sig_y.__width; \ + cell->parameters["\\A_WIDTH"] = sig_a.size(); \ + cell->parameters["\\B_WIDTH"] = sig_b.size(); \ + cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ cell->connections["\\A"] = sig_a; \ cell->connections["\\B"] = sig_b; \ cell->connections["\\Y"] = sig_y; \ @@ -936,14 +936,14 @@ DEF_METHOD(LogicNot, 1, "$logic_not") add ## _func(name, sig_a, sig_b, sig_y, is_signed); \ return sig_y; \ } -DEF_METHOD(And, std::max(sig_a.__width, sig_b.__width), "$and") -DEF_METHOD(Or, std::max(sig_a.__width, sig_b.__width), "$or") -DEF_METHOD(Xor, std::max(sig_a.__width, sig_b.__width), "$xor") -DEF_METHOD(Xnor, std::max(sig_a.__width, sig_b.__width), "$xnor") -DEF_METHOD(Shl, sig_a.__width, "$shl") -DEF_METHOD(Shr, sig_a.__width, "$shr") -DEF_METHOD(Sshl, sig_a.__width, "$sshl") -DEF_METHOD(Sshr, sig_a.__width, "$sshr") +DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and") +DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or") +DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor") +DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor") +DEF_METHOD(Shl, sig_a.size(), "$shl") +DEF_METHOD(Shr, sig_a.size(), "$shr") +DEF_METHOD(Sshl, sig_a.size(), "$sshl") +DEF_METHOD(Sshr, sig_a.size(), "$sshr") DEF_METHOD(Lt, 1, "$lt") DEF_METHOD(Le, 1, "$le") DEF_METHOD(Eq, 1, "$eq") @@ -952,11 +952,11 @@ DEF_METHOD(Eqx, 1, "$eqx") DEF_METHOD(Nex, 1, "$nex") DEF_METHOD(Ge, 1, "$ge") DEF_METHOD(Gt, 1, "$gt") -DEF_METHOD(Add, std::max(sig_a.__width, sig_b.__width), "$add") -DEF_METHOD(Sub, std::max(sig_a.__width, sig_b.__width), "$sub") -DEF_METHOD(Mul, std::max(sig_a.__width, sig_b.__width), "$mul") -DEF_METHOD(Div, std::max(sig_a.__width, sig_b.__width), "$div") -DEF_METHOD(Mod, std::max(sig_a.__width, sig_b.__width), "$mod") +DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add") +DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub") +DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul") +DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div") +DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod") DEF_METHOD(LogicAnd, 1, "$logic_and") DEF_METHOD(LogicOr, 1, "$logic_or") #undef DEF_METHOD @@ -966,9 +966,9 @@ DEF_METHOD(LogicOr, 1, "$logic_or") RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->parameters["\\WIDTH"] = sig_a.__width; \ - cell->parameters["\\WIDTH"] = sig_b.__width; \ - if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.__width; \ + cell->parameters["\\WIDTH"] = sig_a.size(); \ + cell->parameters["\\WIDTH"] = sig_b.size(); \ + if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ cell->connections["\\A"] = sig_a; \ cell->connections["\\B"] = sig_b; \ cell->connections["\\S"] = sig_s; \ @@ -977,7 +977,7 @@ DEF_METHOD(LogicOr, 1, "$logic_or") return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \ - RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.__width); \ + RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \ add ## _func(name, sig_a, sig_b, sig_s, sig_y); \ return sig_y; \ } @@ -1050,9 +1050,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R cell->type = "$pow"; cell->parameters["\\A_SIGNED"] = a_signed; cell->parameters["\\B_SIGNED"] = b_signed; - cell->parameters["\\A_WIDTH"] = sig_a.__width; - cell->parameters["\\B_WIDTH"] = sig_b.__width; - cell->parameters["\\Y_WIDTH"] = sig_y.__width; + cell->parameters["\\A_WIDTH"] = sig_a.size(); + cell->parameters["\\B_WIDTH"] = sig_b.size(); + cell->parameters["\\Y_WIDTH"] = sig_y.size(); cell->connections["\\A"] = sig_a; cell->connections["\\B"] = sig_b; cell->connections["\\Y"] = sig_y; @@ -1065,8 +1065,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = "$slice"; - cell->parameters["\\A_WIDTH"] = sig_a.__width; - cell->parameters["\\Y_WIDTH"] = sig_y.__width; + cell->parameters["\\A_WIDTH"] = sig_a.size(); + cell->parameters["\\Y_WIDTH"] = sig_y.size(); cell->parameters["\\OFFSET"] = offset; cell->connections["\\A"] = sig_a; cell->connections["\\Y"] = sig_y; @@ -1079,8 +1079,8 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = "$concat"; - cell->parameters["\\A_WIDTH"] = sig_a.__width; - cell->parameters["\\B_WIDTH"] = sig_b.__width; + cell->parameters["\\A_WIDTH"] = sig_a.size(); + cell->parameters["\\B_WIDTH"] = sig_b.size(); cell->connections["\\A"] = sig_a; cell->connections["\\B"] = sig_b; cell->connections["\\Y"] = sig_y; @@ -1094,7 +1094,7 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R cell->name = name; cell->type = "$lut"; cell->parameters["\\LUT"] = lut; - cell->parameters["\\WIDTH"] = sig_i.__width; + cell->parameters["\\WIDTH"] = sig_i.size(); cell->connections["\\I"] = sig_i; cell->connections["\\O"] = sig_o; add(cell); @@ -1119,7 +1119,7 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, cell->type = "$sr"; cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.__width; + cell->parameters["\\WIDTH"] = sig_q.size(); cell->connections["\\SET"] = sig_set; cell->connections["\\CLR"] = sig_clr; cell->connections["\\Q"] = sig_q; @@ -1133,7 +1133,7 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, cell->name = name; cell->type = "$dff"; cell->parameters["\\CLK_POLARITY"] = clk_polarity; - cell->parameters["\\WIDTH"] = sig_q.__width; + cell->parameters["\\WIDTH"] = sig_q.size(); cell->connections["\\CLK"] = sig_clk; cell->connections["\\D"] = sig_d; cell->connections["\\Q"] = sig_q; @@ -1150,7 +1150,7 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.__width; + cell->parameters["\\WIDTH"] = sig_q.size(); cell->connections["\\CLK"] = sig_clk; cell->connections["\\SET"] = sig_set; cell->connections["\\CLR"] = sig_clr; @@ -1169,7 +1169,7 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\ARST_POLARITY"] = arst_polarity; cell->parameters["\\ARST_VALUE"] = arst_value; - cell->parameters["\\WIDTH"] = sig_q.__width; + cell->parameters["\\WIDTH"] = sig_q.size(); cell->connections["\\CLK"] = sig_clk; cell->connections["\\ARST"] = sig_arst; cell->connections["\\D"] = sig_d; @@ -1184,7 +1184,7 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e cell->name = name; cell->type = "$dlatch"; cell->parameters["\\EN_POLARITY"] = en_polarity; - cell->parameters["\\WIDTH"] = sig_q.__width; + cell->parameters["\\WIDTH"] = sig_q.size(); cell->connections["\\EN"] = sig_en; cell->connections["\\D"] = sig_d; cell->connections["\\Q"] = sig_q; @@ -1201,7 +1201,7 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig cell->parameters["\\EN_POLARITY"] = en_polarity; cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.__width; + cell->parameters["\\WIDTH"] = sig_q.size(); cell->connections["\\EN"] = sig_en; cell->connections["\\SET"] = sig_set; cell->connections["\\CLR"] = sig_clr; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7fb416f1f..88ed2f6a2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -560,8 +560,8 @@ public: }; inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { - assert(sig.__width == 1 && sig.__chunks.size() == 1); - *this = SigBit(sig.__chunks[0]); + assert(sig.size() == 1 && sig.chunks().size() == 1); + *this = SigBit(sig.chunks()[0]); } struct RTLIL::CaseRule { diff --git a/kernel/satgen.h b/kernel/satgen.h index 012b6ab89..9e2277076 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -55,9 +55,9 @@ struct SatGen sig.expand(); std::vector vec; - vec.reserve(sig.__chunks.size()); + vec.reserve(sig.chunks().size()); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire == NULL) { RTLIL::State bit = c.data.bits.at(0); if (model_undef && dup_undef && bit == RTLIL::State::Sx) @@ -118,7 +118,7 @@ struct SatGen if (timestep_rhs < 0) timestep_rhs = timestep_lhs; - assert(lhs.__width == rhs.__width); + assert(lhs.size() == rhs.size()); std::vector vec_lhs = importSigSpec(lhs, timestep_lhs); std::vector vec_rhs = importSigSpec(rhs, timestep_rhs); @@ -130,7 +130,7 @@ struct SatGen std::vector undef_rhs = importUndefSigSpec(rhs, timestep_rhs); std::vector eq_bits; - for (int i = 0; i < lhs.__width; i++) + for (int i = 0; i < lhs.size(); i++) eq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)), ez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i))))); return ez->expression(ezSAT::OpAnd, eq_bits); @@ -742,11 +742,11 @@ struct SatGen only_first_one.at(0) = ez->TRUE; div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones); } else { - div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").__width, ez->TRUE); + div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").size(), ez->TRUE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE); } } else { - int copy_a_bits = std::min(cell->connections.at("\\A").__width, cell->connections.at("\\B").__width); + int copy_a_bits = std::min(cell->connections.at("\\A").size(), cell->connections.at("\\B").size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); @@ -768,7 +768,7 @@ struct SatGen { RTLIL::SigSpec a = cell->connections.at("\\A"); RTLIL::SigSpec y = cell->connections.at("\\Y"); - ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.__width), y, timestep)); + ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep)); return true; } diff --git a/kernel/sigtools.h b/kernel/sigtools.h index c886ff168..27abd8670 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -38,7 +38,7 @@ struct SigPool void add(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -56,7 +56,7 @@ struct SigPool void del(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -75,10 +75,10 @@ struct SigPool { from.expand(); to.expand(); - assert(from.__chunks.size() == to.__chunks.size()); - for (size_t i = 0; i < from.__chunks.size(); i++) { - bitDef_t bit_from(from.__chunks[i].wire, from.__chunks[i].offset); - bitDef_t bit_to(to.__chunks[i].wire, to.__chunks[i].offset); + assert(from.chunks().size() == to.chunks().size()); + for (size_t i = 0; i < from.chunks().size(); i++) { + bitDef_t bit_from(from.chunks()[i].wire, from.chunks()[i].offset); + bitDef_t bit_to(to.chunks()[i].wire, to.chunks()[i].offset); if (bit_from.first == NULL || bit_to.first == NULL) continue; if (bits.count(bit_from) > 0) @@ -90,7 +90,7 @@ struct SigPool { RTLIL::SigSpec result; sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; bitDef_t bit(c.wire, c.offset); @@ -104,7 +104,7 @@ struct SigPool { RTLIL::SigSpec result; sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; bitDef_t bit(c.wire, c.offset); @@ -117,7 +117,7 @@ struct SigPool bool check_any(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; bitDef_t bit(c.wire, c.offset); @@ -130,7 +130,7 @@ struct SigPool bool check_all(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; bitDef_t bit(c.wire, c.offset); @@ -179,7 +179,7 @@ struct SigSet void insert(RTLIL::SigSpec sig, T data) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -191,7 +191,7 @@ struct SigSet void insert(RTLIL::SigSpec sig, const std::set &data) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -203,7 +203,7 @@ struct SigSet void erase(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -215,7 +215,7 @@ struct SigSet void erase(RTLIL::SigSpec sig, T data) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -227,7 +227,7 @@ struct SigSet void erase(RTLIL::SigSpec sig, const std::set &data) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -239,7 +239,7 @@ struct SigSet void find(RTLIL::SigSpec sig, std::set &result) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -259,7 +259,7 @@ struct SigSet bool has(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL) continue; assert(c.width == 1); @@ -420,11 +420,11 @@ struct SigMap from.expand(); to.expand(); - assert(from.__chunks.size() == to.__chunks.size()); - for (size_t i = 0; i < from.__chunks.size(); i++) + assert(from.chunks().size() == to.chunks().size()); + for (size_t i = 0; i < from.chunks().size(); i++) { - RTLIL::SigChunk &cf = from.__chunks[i]; - RTLIL::SigChunk &ct = to.__chunks[i]; + RTLIL::SigChunk &cf = from.chunks()[i]; + RTLIL::SigChunk &ct = to.chunks()[i]; if (cf.wire == NULL) continue; @@ -442,9 +442,9 @@ struct SigMap void add(RTLIL::SigSpec sig) { sig.expand(); - for (size_t i = 0; i < sig.__chunks.size(); i++) + for (size_t i = 0; i < sig.chunks().size(); i++) { - RTLIL::SigChunk &c = sig.__chunks[i]; + RTLIL::SigChunk &c = sig.chunks()[i]; if (c.wire != NULL) { register_bit(c); set_bit(c, c); @@ -455,14 +455,14 @@ struct SigMap void del(RTLIL::SigSpec sig) { sig.expand(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) unregister_bit(c); } void apply(RTLIL::SigSpec &sig) const { sig.expand(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) map_bit(c); sig.optimize(); } -- cgit v1.2.3 From 7bffde6abdaf6fc2ed090946442f90b2438e6126 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:39:13 +0200 Subject: SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only --- kernel/rtlil.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 88ed2f6a2..6bbf69602 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -504,8 +504,7 @@ public: std::vector &chunks() { return chunks_; } const std::vector &chunks() const { return chunks_; } - int &size() { return width_; } - const int &size() const { return width_; } + int size() const { return width_; } SigSpec(); SigSpec(const RTLIL::Const &data); -- cgit v1.2.3 From 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:58:44 +0200 Subject: SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() --- kernel/consteval.h | 2 +- kernel/rtlil.cc | 2 +- kernel/rtlil.h | 2 +- kernel/sigtools.h | 8 ++++---- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 564098c6a..5836cdd5b 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -73,7 +73,7 @@ struct ConstEval RTLIL::SigSpec current_val = values_map(sig); current_val.expand(); for (size_t i = 0; i < current_val.chunks().size(); i++) { - RTLIL::SigChunk &chunk = current_val.chunks()[i]; + const RTLIL::SigChunk &chunk = current_val.chunks()[i]; assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]); } #endif diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 43511304e..361cd5f04 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const RTLIL::Module *mod; void operator()(RTLIL::SigSpec &sig) { - for (auto &c : sig.chunks()) + for (auto &c : sig.chunks_rw()) if (c.wire != NULL) c.wire = mod->wires.at(c.wire->name); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6bbf69602..9d5b3b304 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -501,7 +501,7 @@ private: int width_; public: - std::vector &chunks() { return chunks_; } + std::vector &chunks_rw() { return chunks_; } const std::vector &chunks() const { return chunks_; } int size() const { return width_; } diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 27abd8670..826f84179 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -423,8 +423,8 @@ struct SigMap assert(from.chunks().size() == to.chunks().size()); for (size_t i = 0; i < from.chunks().size(); i++) { - RTLIL::SigChunk &cf = from.chunks()[i]; - RTLIL::SigChunk &ct = to.chunks()[i]; + const RTLIL::SigChunk &cf = from.chunks()[i]; + const RTLIL::SigChunk &ct = to.chunks()[i]; if (cf.wire == NULL) continue; @@ -444,7 +444,7 @@ struct SigMap sig.expand(); for (size_t i = 0; i < sig.chunks().size(); i++) { - RTLIL::SigChunk &c = sig.chunks()[i]; + const RTLIL::SigChunk &c = sig.chunks()[i]; if (c.wire != NULL) { register_bit(c); set_bit(c, c); @@ -462,7 +462,7 @@ struct SigMap void apply(RTLIL::SigSpec &sig) const { sig.expand(); - for (auto &c : sig.chunks()) + for (auto &c : sig.chunks_rw()) map_bit(c); sig.optimize(); } -- cgit v1.2.3 From 08e1e251698edfec7e0634a8ccdc321f42e8f27f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 21:33:52 +0200 Subject: SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api --- kernel/rtlil.cc | 111 ++++++++++++++++++++++++++++++++++++++++++++++++++++---- kernel/rtlil.h | 42 ++++++++++++++++----- 2 files changed, 135 insertions(+), 18 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 361cd5f04..8058f69cf 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1487,8 +1487,48 @@ RTLIL::SigSpec::SigSpec(std::set bits) check(); } +void RTLIL::SigSpec::pack() const +{ + RTLIL::SigSpec *that = (RTLIL::SigSpec*)this; + + if (that->bits_.empty()) + return; + + log_assert(that->chunks_.empty()); + + std::vector old_bits; + old_bits.swap(that->bits_); + + that->width_ = 0; + for (auto &bit : old_bits) + that->append_bit(bit); +} + +void RTLIL::SigSpec::unpack() const +{ + RTLIL::SigSpec *that = (RTLIL::SigSpec*)this; + + if (that->chunks_.empty()) + return; + + log_assert(that->bits_.empty()); + + that->bits_.reserve(that->width_); + for (auto &c : that->chunks_) + for (int i = 0; i < c.width; i++) + that->bits_.push_back(RTLIL::SigBit(c, i)); + + that->chunks_.clear(); +} + +bool RTLIL::SigSpec::packed() const +{ + return bits_.empty(); +} + void RTLIL::SigSpec::expand() { + pack(); std::vector new_chunks; for (size_t i = 0; i < chunks_.size(); i++) { for (int j = 0; j < chunks_[i].width; j++) @@ -1500,6 +1540,7 @@ void RTLIL::SigSpec::expand() void RTLIL::SigSpec::optimize() { + pack(); std::vector new_chunks; for (auto &c : chunks_) if (new_chunks.size() == 0) { @@ -1519,6 +1560,7 @@ void RTLIL::SigSpec::optimize() RTLIL::SigSpec RTLIL::SigSpec::optimized() const { + pack(); RTLIL::SigSpec ret = *this; ret.optimize(); return ret; @@ -1543,6 +1585,7 @@ bool RTLIL::SigChunk::compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b void RTLIL::SigSpec::sort() { + pack(); expand(); std::sort(chunks_.begin(), chunks_.end(), RTLIL::SigChunk::compare); optimize(); @@ -1550,6 +1593,7 @@ void RTLIL::SigSpec::sort() void RTLIL::SigSpec::sort_and_unify() { + pack(); expand(); std::sort(chunks_.begin(), chunks_.end(), RTLIL::SigChunk::compare); for (size_t i = 1; i < chunks_.size(); i++) { @@ -1571,6 +1615,13 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const { + pack(); + pattern.pack(); + with.pack(); + + if (other != NULL) + other->pack(); + int pos = 0, restart_pos = 0; assert(other == NULL || width_ == other->width_); for (size_t i = 0; i < chunks_.size(); i++) { @@ -1609,6 +1660,12 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) { + pack(); + pattern.pack(); + + if (other != NULL) + other->pack(); + int pos = 0; assert(other == NULL || width_ == other->width_); for (size_t i = 0; i < chunks_.size(); i++) { @@ -1638,6 +1695,12 @@ restart: RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other) const { + pack(); + pattern.pack(); + + if (other != NULL) + other->pack(); + assert(other == NULL || width_ == other->width_); std::set pat = pattern.to_sigbit_set(); @@ -1661,6 +1724,9 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) { + pack(); + with.pack(); + int pos = 0; assert(offset >= 0); assert(with.width_ >= 0); @@ -1683,6 +1749,7 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) void RTLIL::SigSpec::remove_const() { + pack(); for (size_t i = 0; i < chunks_.size(); i++) { if (chunks_[i].wire != NULL) continue; @@ -1694,6 +1761,7 @@ void RTLIL::SigSpec::remove_const() void RTLIL::SigSpec::remove(int offset, int length) { + pack(); int pos = 0; assert(offset >= 0); assert(length >= 0); @@ -1733,6 +1801,7 @@ void RTLIL::SigSpec::remove(int offset, int length) RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { + pack(); int pos = 0; RTLIL::SigSpec ret; assert(offset >= 0); @@ -1762,6 +1831,9 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) { + pack(); + signal.pack(); + for (size_t i = 0; i < signal.chunks_.size(); i++) { chunks_.push_back(signal.chunks_[i]); width_ += signal.chunks_[i].width; @@ -1771,6 +1843,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) { + pack(); if (chunks_.size() == 0) chunks_.push_back(bit); else @@ -1789,8 +1862,11 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) // check(); } -bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool override) +bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool do_override) { + pack(); + signal.pack(); + bool no_collisions = true; assert(width_ == signal.width_); @@ -1801,7 +1877,7 @@ bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool bool self_free = chunks_[i].wire == NULL && chunks_[i].data.bits[0] == freeState; bool other_free = signal.chunks_[i].wire == NULL && signal.chunks_[i].data.bits[0] == freeState; if (!self_free && !other_free) { - if (override) + if (do_override) chunks_[i] = signal.chunks_[i]; else chunks_[i] = RTLIL::SigChunk(RTLIL::State::Sx, 1); @@ -1817,6 +1893,8 @@ bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool void RTLIL::SigSpec::extend(int width, bool is_signed) { + pack(); + if (width_ > width) remove(width, width_ - width); @@ -1834,6 +1912,8 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { + pack(); + if (width_ > width) remove(width, width_ - width); @@ -1850,6 +1930,8 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) void RTLIL::SigSpec::check() const { + pack(); + int w = 0; for (size_t i = 0; i < chunks_.size(); i++) { const RTLIL::SigChunk chunk = chunks_[i]; @@ -1869,6 +1951,9 @@ void RTLIL::SigSpec::check() const bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const { + pack(); + other.pack(); + if (width_ != other.width_) return width_ < other.width_; @@ -1888,6 +1973,9 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const { + pack(); + other.pack(); + if (width_ != other.width_) return false; @@ -1914,6 +2002,7 @@ bool RTLIL::SigSpec::operator !=(const RTLIL::SigSpec &other) const bool RTLIL::SigSpec::is_fully_const() const { + pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) if (it->width > 0 && it->wire != NULL) return false; @@ -1922,6 +2011,7 @@ bool RTLIL::SigSpec::is_fully_const() const bool RTLIL::SigSpec::is_fully_def() const { + pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) { if (it->width > 0 && it->wire != NULL) return false; @@ -1934,6 +2024,7 @@ bool RTLIL::SigSpec::is_fully_def() const bool RTLIL::SigSpec::is_fully_undef() const { + pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) { if (it->width > 0 && it->wire != NULL) return false; @@ -1946,6 +2037,7 @@ bool RTLIL::SigSpec::is_fully_undef() const bool RTLIL::SigSpec::has_marked_bits() const { + pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) if (it->width > 0 && it->wire == NULL) { for (size_t i = 0; i < it->data.bits.size(); i++) @@ -1957,6 +2049,7 @@ bool RTLIL::SigSpec::has_marked_bits() const bool RTLIL::SigSpec::as_bool() const { + pack(); assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); @@ -1967,6 +2060,7 @@ bool RTLIL::SigSpec::as_bool() const int RTLIL::SigSpec::as_int() const { + pack(); assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); @@ -1977,6 +2071,7 @@ int RTLIL::SigSpec::as_int() const std::string RTLIL::SigSpec::as_string() const { + pack(); std::string str; for (size_t i = chunks_.size(); i > 0; i--) { const RTLIL::SigChunk &chunk = chunks_[i-1]; @@ -1991,6 +2086,7 @@ std::string RTLIL::SigSpec::as_string() const RTLIL::Const RTLIL::SigSpec::as_const() const { + pack(); assert(is_fully_const()); SigSpec sig = *this; sig.optimize(); @@ -2001,6 +2097,7 @@ RTLIL::Const RTLIL::SigSpec::as_const() const bool RTLIL::SigSpec::match(std::string pattern) const { + pack(); std::string str = as_string(); assert(pattern.size() == str.size()); @@ -2021,6 +2118,7 @@ bool RTLIL::SigSpec::match(std::string pattern) const std::set RTLIL::SigSpec::to_sigbit_set() const { + pack(); std::set sigbits; for (auto &c : chunks_) for (int i = 0; i < c.width; i++) @@ -2030,16 +2128,13 @@ std::set RTLIL::SigSpec::to_sigbit_set() const std::vector RTLIL::SigSpec::to_sigbit_vector() const { - std::vector sigbits; - sigbits.reserve(width_); - for (auto &c : chunks_) - for (int i = 0; i < c.width; i++) - sigbits.push_back(RTLIL::SigBit(c, i)); - return sigbits; + unpack(); + return bits_; } RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const { + pack(); log_assert(width_ == 1); for (auto &c : chunks_) if (c.width) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9d5b3b304..1d84dd3bb 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -498,14 +498,14 @@ struct RTLIL::SigBit { struct RTLIL::SigSpec { private: std::vector chunks_; // LSB at index 0 + std::vector bits_; // LSB at index 0 int width_; -public: - std::vector &chunks_rw() { return chunks_; } - const std::vector &chunks() const { return chunks_; } - - int size() const { return width_; } + void pack() const; + void unpack() const; + bool packed() const; +public: SigSpec(); SigSpec(const RTLIL::Const &data); SigSpec(const RTLIL::SigChunk &chunk); @@ -516,46 +516,68 @@ public: SigSpec(RTLIL::SigBit bit, int width = 1); SigSpec(std::vector bits); SigSpec(std::set bits); + + std::vector &chunks_rw() { pack(); return chunks_; } + const std::vector &chunks() const { pack(); return chunks_; } + const std::vector &bits() const { unpack(); return bits_; } + + int size() const { return width_; } + void expand(); void optimize(); RTLIL::SigSpec optimized() const; + void sort(); void sort_and_unify(); + void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; + void replace(int offset, const RTLIL::SigSpec &with); + void remove(const RTLIL::SigSpec &pattern); void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); - RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const; - void replace(int offset, const RTLIL::SigSpec &with); + void remove(int offset, int length = 1); void remove_const(); - void remove(int offset, int length); + + RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(int offset, int length) const; + void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); - bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool override = false); + + bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool do_override = false); + void extend(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false); - void check() const; + bool operator <(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const; bool operator !=(const RTLIL::SigSpec &other) const; + bool is_fully_const() const; bool is_fully_def() const; bool is_fully_undef() const; bool has_marked_bits() const; + bool as_bool() const; int as_int() const; std::string as_string() const; RTLIL::Const as_const() const; + bool match(std::string pattern) const; + std::set to_sigbit_set() const; std::vector to_sigbit_vector() const; RTLIL::SigBit to_single_sigbit() const; + static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + operator std::vector() const { return to_sigbit_vector(); } + + void check() const; }; inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { -- cgit v1.2.3 From a97be0828a3998d1eb5128e8e24c75af2016f27b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 21:40:52 +0200 Subject: Removed RTLIL::SigChunk::compare() --- kernel/rtlil.cc | 29 +++++------------------------ kernel/rtlil.h | 1 - 2 files changed, 5 insertions(+), 25 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8058f69cf..937dcbce5 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1382,6 +1382,7 @@ bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const if (wire && other.wire) if (wire->name != other.wire->name) return wire->name < other.wire->name; + if (wire != other.wire) return wire < other.wire; @@ -1391,10 +1392,7 @@ bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const if (width != other.width) return width < other.width; - if (data.bits != other.data.bits) - return data.bits < other.data.bits; - - return false; + return data.bits < other.data.bits; } bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const @@ -1566,28 +1564,11 @@ RTLIL::SigSpec RTLIL::SigSpec::optimized() const return ret; } -bool RTLIL::SigChunk::compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b) -{ - if (a.wire != b.wire) { - if (a.wire == NULL || b.wire == NULL) - return a.wire < b.wire; - else if (a.wire->name != b.wire->name) - return a.wire->name < b.wire->name; - else - return a.wire < b.wire; - } - if (a.offset != b.offset) - return a.offset < b.offset; - if (a.width != b.width) - return a.width < b.width; - return a.data.bits < b.data.bits; -} - void RTLIL::SigSpec::sort() { pack(); expand(); - std::sort(chunks_.begin(), chunks_.end(), RTLIL::SigChunk::compare); + std::sort(chunks_.begin(), chunks_.end()); optimize(); } @@ -1595,11 +1576,11 @@ void RTLIL::SigSpec::sort_and_unify() { pack(); expand(); - std::sort(chunks_.begin(), chunks_.end(), RTLIL::SigChunk::compare); + std::sort(chunks_.begin(), chunks_.end()); for (size_t i = 1; i < chunks_.size(); i++) { RTLIL::SigChunk &ch1 = chunks_[i-1]; RTLIL::SigChunk &ch2 = chunks_[i]; - if (!RTLIL::SigChunk::compare(ch1, ch2) && !RTLIL::SigChunk::compare(ch2, ch1)) { + if (ch1 == ch2) { chunks_.erase(chunks_.begin()+i); width_ -= chunks_[i].width; i--; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1d84dd3bb..facd43db4 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -470,7 +470,6 @@ struct RTLIL::SigChunk { bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; bool operator !=(const RTLIL::SigChunk &other) const; - static bool compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b); }; struct RTLIL::SigBit { -- cgit v1.2.3 From fd4cbe627527561fb08bc77467f2b6a250d5dc4d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 22:26:30 +0200 Subject: SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form --- kernel/rtlil.cc | 295 ++++++++++++++++++++++---------------------------------- 1 file changed, 113 insertions(+), 182 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 937dcbce5..d46014050 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1566,27 +1566,13 @@ RTLIL::SigSpec RTLIL::SigSpec::optimized() const void RTLIL::SigSpec::sort() { - pack(); - expand(); - std::sort(chunks_.begin(), chunks_.end()); - optimize(); + unpack(); + std::sort(bits_.begin(), bits_.end()); } void RTLIL::SigSpec::sort_and_unify() { - pack(); - expand(); - std::sort(chunks_.begin(), chunks_.end()); - for (size_t i = 1; i < chunks_.size(); i++) { - RTLIL::SigChunk &ch1 = chunks_[i-1]; - RTLIL::SigChunk &ch2 = chunks_[i]; - if (ch1 == ch2) { - chunks_.erase(chunks_.begin()+i); - width_ -= chunks_[i].width; - i--; - } - } - optimize(); + *this = this->to_sigbit_set(); } void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with) @@ -1596,36 +1582,26 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const { - pack(); - pattern.pack(); - with.pack(); + unpack(); + pattern.unpack(); + with.unpack(); - if (other != NULL) - other->pack(); + assert(other != NULL); + assert(width_ == other->width_); + other->unpack(); - int pos = 0, restart_pos = 0; - assert(other == NULL || width_ == other->width_); - for (size_t i = 0; i < chunks_.size(); i++) { -restart: - const RTLIL::SigChunk &ch1 = chunks_[i]; - if (chunks_[i].wire != NULL && pos >= restart_pos) - for (size_t j = 0, poff = 0; j < pattern.chunks_.size(); j++) { - const RTLIL::SigChunk &ch2 = pattern.chunks_[j]; - assert(ch2.wire != NULL); - if (ch1.wire == ch2.wire) { - int lower = std::max(ch1.offset, ch2.offset); - int upper = std::min(ch1.offset + ch1.width, ch2.offset + ch2.width); - if (lower < upper) { - restart_pos = pos+upper-ch1.offset; - other->replace(pos+lower-ch1.offset, with.extract(poff+lower-ch2.offset, upper-lower)); - goto restart; - } - } - poff += ch2.width; - } - pos += chunks_[i].width; - } - check(); + assert(pattern.width_ == with.width_); + + std::map pattern_map; + for (int i = 0; i < SIZE(pattern.bits_); i++) + if (pattern.bits_[i].wire != NULL) + pattern_map[pattern.bits_[i]] = with.bits_[i]; + + for (int i = 0; i < SIZE(bits_); i++) + if (pattern_map.count(bits_[i])) + other->bits_[i] = pattern_map.at(bits_[i]); + + other->check(); } void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern) @@ -1641,36 +1617,32 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) { - pack(); - pattern.pack(); + unpack(); - if (other != NULL) - other->pack(); + if (other != NULL) { + assert(width_ == other->width_); + other->unpack(); + } - int pos = 0; - assert(other == NULL || width_ == other->width_); - for (size_t i = 0; i < chunks_.size(); i++) { -restart: - const RTLIL::SigChunk &ch1 = chunks_[i]; - if (chunks_[i].wire != NULL) - for (size_t j = 0; j < pattern.chunks_.size(); j++) { - const RTLIL::SigChunk &ch2 = pattern.chunks_[j]; - assert(ch2.wire != NULL); - if (ch1.wire == ch2.wire) { - int lower = std::max(ch1.offset, ch2.offset); - int upper = std::min(ch1.offset + ch1.width, ch2.offset + ch2.width); - if (lower < upper) { - if (other) - other->remove(pos+lower-ch1.offset, upper-lower); - remove(pos+lower-ch1.offset, upper-lower); - if (i == chunks_.size()) - break; - goto restart; - } - } - } - pos += chunks_[i].width; + std::set pattern_bits = pattern.to_sigbit_set(); + std::vector new_bits, new_other_bits; + + for (int i = 0; i < SIZE(bits_); i++) { + if (bits_[i].wire != NULL && pattern_bits.count(bits_[i])) + continue; + if (other != NULL) + new_other_bits.push_back(other->bits_[i]); + new_bits.push_back(bits_[i]); } + + bits_.swap(new_bits); + width_ = SIZE(bits_); + + if (other != NULL) { + other->bits_.swap(new_other_bits); + other->width_ = SIZE(other->bits_); + } + check(); } @@ -1705,109 +1677,54 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) { - pack(); - with.pack(); + unpack(); + with.unpack(); - int pos = 0; assert(offset >= 0); assert(with.width_ >= 0); assert(offset+with.width_ <= width_); - remove(offset, with.width_); - for (size_t i = 0; i < chunks_.size(); i++) { - if (pos == offset) { - chunks_.insert(chunks_.begin()+i, with.chunks_.begin(), with.chunks_.end()); - width_ += with.width_; - check(); - return; - } - pos += chunks_[i].width; - } - assert(pos == offset); - chunks_.insert(chunks_.end(), with.chunks_.begin(), with.chunks_.end()); - width_ += with.width_; + + for (int i = 0; i < with.width_; i++) + bits_.at(offset + i) = with.bits_.at(i); + check(); } void RTLIL::SigSpec::remove_const() { - pack(); - for (size_t i = 0; i < chunks_.size(); i++) { - if (chunks_[i].wire != NULL) - continue; - width_ -= chunks_[i].width; - chunks_.erase(chunks_.begin() + (i--)); - } + unpack(); + + std::vector new_bits; + new_bits.reserve(width_); + + for (auto &bit : bits_) + if (bit.wire != NULL) + new_bits.push_back(bit); + + bits_.swap(new_bits); + width_ = bits_.size(); + check(); } void RTLIL::SigSpec::remove(int offset, int length) { - pack(); - int pos = 0; + unpack(); + assert(offset >= 0); assert(length >= 0); - assert(offset+length <= width_); - for (size_t i = 0; i < chunks_.size(); i++) { - int orig_width = chunks_[i].width; - if (pos+chunks_[i].width > offset && pos < offset+length) { - int off = offset - pos; - int len = length; - if (off < 0) { - len += off; - off = 0; - } - if (len > chunks_[i].width-off) - len = chunks_[i].width-off; - RTLIL::SigChunk lsb_chunk = chunks_[i].extract(0, off); - RTLIL::SigChunk msb_chunk = chunks_[i].extract(off+len, chunks_[i].width-off-len); - if (lsb_chunk.width == 0 && msb_chunk.width == 0) { - chunks_.erase(chunks_.begin()+i); - i--; - } else if (lsb_chunk.width == 0 && msb_chunk.width != 0) { - chunks_[i] = msb_chunk; - } else if (lsb_chunk.width != 0 && msb_chunk.width == 0) { - chunks_[i] = lsb_chunk; - } else if (lsb_chunk.width != 0 && msb_chunk.width != 0) { - chunks_[i] = lsb_chunk; - chunks_.insert(chunks_.begin()+i+1, msb_chunk); - i++; - } else - assert(0); - width_ -= len; - } - pos += orig_width; - } + assert(offset + length <= width_); + + bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length); + width_ = bits_.size(); + check(); } RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { - pack(); - int pos = 0; - RTLIL::SigSpec ret; - assert(offset >= 0); - assert(length >= 0); - assert(offset+length <= width_); - for (size_t i = 0; i < chunks_.size(); i++) { - if (pos+chunks_[i].width > offset && pos < offset+length) { - int off = offset - pos; - int len = length; - if (off < 0) { - len += off; - off = 0; - } - if (len > chunks_[i].width-off) - len = chunks_[i].width-off; - ret.chunks_.push_back(chunks_[i].extract(off, len)); - ret.width_ += len; - offset += len; - length -= len; - } - pos += chunks_[i].width; - } - assert(length == 0); - ret.check(); - return ret; + unpack(); + return std::vector(bits_.begin() + offset, bits_.begin() + offset + length); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) @@ -1819,27 +1736,34 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) chunks_.push_back(signal.chunks_[i]); width_ += signal.chunks_[i].width; } + // check(); } void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) { - pack(); - if (chunks_.size() == 0) - chunks_.push_back(bit); - else - if (bit.wire == NULL) - if (chunks_.back().wire == NULL) { - chunks_.back().data.bits.push_back(bit.data); - chunks_.back().width++; - } else - chunks_.push_back(bit); + if (packed()) + { + if (chunks_.size() == 0) + chunks_.push_back(bit); else - if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset) - chunks_.back().width++; + if (bit.wire == NULL) + if (chunks_.back().wire == NULL) { + chunks_.back().data.bits.push_back(bit.data); + chunks_.back().width++; + } else + chunks_.push_back(bit); else - chunks_.push_back(bit); + if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset) + chunks_.back().width++; + else + chunks_.push_back(bit); + } + else + bits_.push_back(bit); + width_++; + // check(); } @@ -1911,23 +1835,30 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) void RTLIL::SigSpec::check() const { - pack(); - - int w = 0; - for (size_t i = 0; i < chunks_.size(); i++) { - const RTLIL::SigChunk chunk = chunks_[i]; - if (chunk.wire == NULL) { - assert(chunk.offset == 0); - assert(chunk.data.bits.size() == (size_t)chunk.width); - } else { - assert(chunk.offset >= 0); - assert(chunk.width >= 0); - assert(chunk.offset + chunk.width <= chunk.wire->width); - assert(chunk.data.bits.size() == 0); + if (packed()) + { + int w = 0; + for (size_t i = 0; i < chunks_.size(); i++) { + const RTLIL::SigChunk chunk = chunks_[i]; + if (chunk.wire == NULL) { + assert(chunk.offset == 0); + assert(chunk.data.bits.size() == (size_t)chunk.width); + } else { + assert(chunk.offset >= 0); + assert(chunk.width >= 0); + assert(chunk.offset + chunk.width <= chunk.wire->width); + assert(chunk.data.bits.size() == 0); + } + w += chunk.width; } - w += chunk.width; + assert(w == width_); + assert(bits_.empty()); + } + else + { + assert(width_ == SIZE(bits_)); + assert(chunks_.empty()); } - assert(w == width_); } bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const -- cgit v1.2.3 From f80da7b41dd9c12d3bd65ceab6c0c6748a70a78c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 22:54:03 +0200 Subject: SigSpec refactoring: added RTLIL::SigSpec::operator[] --- kernel/rtlil.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index facd43db4..da3a2661e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -522,6 +522,9 @@ public: int size() const { return width_; } + RTLIL::SigBit &operator[](int index) { unpack(); return bits_.at(index); } + const RTLIL::SigBit &operator[](int index) const { unpack(); return bits_.at(index); } + void expand(); void optimize(); RTLIL::SigSpec optimized() const; @@ -540,7 +543,7 @@ public: void remove_const(); RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const; - RTLIL::SigSpec extract(int offset, int length) const; + RTLIL::SigSpec extract(int offset, int length = 1) const; void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); -- cgit v1.2.3 From 9e94f41b89bca54f8a3ce2e8e54c0467a7e8c43d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 23:49:26 +0200 Subject: SigSpec refactoring: Added RTLIL::SigSpecIterator --- kernel/rtlil.h | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index da3a2661e..53770088b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -69,6 +69,7 @@ namespace RTLIL struct Cell; struct SigChunk; struct SigBit; + struct SigSpecIterator; struct SigSpec; struct CaseRule; struct SwitchRule; @@ -494,6 +495,14 @@ struct RTLIL::SigBit { } }; +struct RTLIL::SigSpecIterator { + RTLIL::SigSpec *sig_p; + int index; + inline RTLIL::SigBit &operator*() const; + inline bool operator!=(const RTLIL::SigSpecIterator &other) { return index != other.index; } + inline void operator++() { index++; } +}; + struct RTLIL::SigSpec { private: std::vector chunks_; // LSB at index 0 @@ -504,6 +513,11 @@ private: void unpack() const; bool packed() const; + inline void inline_unpack() const { + if (!chunks_.empty()) + unpack(); + } + public: SigSpec(); SigSpec(const RTLIL::Const &data); @@ -513,17 +527,21 @@ public: SigSpec(int val, int width = 32); SigSpec(RTLIL::State bit, int width = 1); SigSpec(RTLIL::SigBit bit, int width = 1); + SigSpec(std::vector chunks); SigSpec(std::vector bits); SigSpec(std::set bits); - std::vector &chunks_rw() { pack(); return chunks_; } - const std::vector &chunks() const { pack(); return chunks_; } - const std::vector &bits() const { unpack(); return bits_; } + inline std::vector &chunks_rw() { pack(); return chunks_; } + inline const std::vector &chunks() const { pack(); return chunks_; } + inline const std::vector &bits() const { inline_unpack(); return bits_; } - int size() const { return width_; } + inline int size() const { return width_; } - RTLIL::SigBit &operator[](int index) { unpack(); return bits_.at(index); } - const RTLIL::SigBit &operator[](int index) const { unpack(); return bits_.at(index); } + inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); } + inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); } + + inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } + inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } void expand(); void optimize(); @@ -582,6 +600,10 @@ public: void check() const; }; +inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const { + return (*sig_p)[index]; +} + inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { assert(sig.size() == 1 && sig.chunks().size() == 1); *this = SigBit(sig.chunks()[0]); -- cgit v1.2.3 From 115dd959d9dbf68aa30f8374df0e62fba8646f1e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 23:50:21 +0200 Subject: SigSpec refactoring: More cleanups of old SigSpec use pattern --- kernel/rtlil.cc | 12 ++++++- kernel/sigtools.h | 93 +++++++++++++++++++++++-------------------------------- 2 files changed, 50 insertions(+), 55 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d46014050..6757d5dc3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -801,9 +801,11 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const RTLIL::Module *mod; void operator()(RTLIL::SigSpec &sig) { - for (auto &c : sig.chunks_rw()) + std::vector chunks = sig.chunks(); + for (auto &c : chunks) if (c.wire != NULL) c.wire = mod->wires.at(c.wire->name); + sig = chunks; } }; @@ -1469,6 +1471,14 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) check(); } +RTLIL::SigSpec::SigSpec(std::vector chunks) +{ + width_ = 0; + for (auto &c : chunks) + append(c); + check(); +} + RTLIL::SigSpec::SigSpec(std::vector bits) { width_ = 0; diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 826f84179..e93780b49 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -276,7 +276,7 @@ struct SigMap typedef std::pair bitDef_t; struct shared_bit_data_t { - RTLIL::SigChunk chunk; + RTLIL::SigBit map_to; std::set bits; }; @@ -304,7 +304,7 @@ struct SigMap clear(); for (auto &bit : other.bits) { bits[bit.first] = new shared_bit_data_t; - bits[bit.first]->chunk = bit.second->chunk; + bits[bit.first]->map_to = bit.second->map_to; bits[bit.first]->bits = bit.second->bits; } } @@ -337,24 +337,22 @@ struct SigMap } // internal helper function - void register_bit(const RTLIL::SigChunk &c) + void register_bit(const RTLIL::SigBit &b) { - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - if (c.wire && bits.count(bit) == 0) { + bitDef_t bit(b.wire, b.offset); + if (b.wire && bits.count(bit) == 0) { shared_bit_data_t *bd = new shared_bit_data_t; - bd->chunk = c; + bd->map_to = b; bd->bits.insert(bit); bits[bit] = bd; } } // internal helper function - void unregister_bit(const RTLIL::SigChunk &c) + void unregister_bit(const RTLIL::SigBit &b) { - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - if (c.wire && bits.count(bit) > 0) { + bitDef_t bit(b.wire, b.offset); + if (b.wire && bits.count(bit) > 0) { shared_bit_data_t *bd = bits[bit]; bd->bits.erase(bit); if (bd->bits.size() == 0) @@ -364,13 +362,12 @@ struct SigMap } // internal helper function - void merge_bit(const RTLIL::SigChunk &c1, const RTLIL::SigChunk &c2) + void merge_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2) { - assert(c1.wire != NULL && c2.wire != NULL); - assert(c1.width == 1 && c2.width == 1); + assert(bit1.wire != NULL && bit2.wire != NULL); - bitDef_t b1(c1.wire, c1.offset); - bitDef_t b2(c2.wire, c2.offset); + bitDef_t b1(bit1.wire, bit1.offset); + bitDef_t b2(bit2.wire, bit2.offset); shared_bit_data_t *bd1 = bits[b1]; shared_bit_data_t *bd2 = bits[b2]; @@ -388,7 +385,7 @@ struct SigMap } else { - bd1->chunk = bd2->chunk; + bd1->map_to = bd2->map_to; for (auto &bit : bd2->bits) bits[bit] = bd1; bd1->bits.insert(bd2->bits.begin(), bd2->bits.end()); @@ -397,74 +394,62 @@ struct SigMap } // internal helper function - void set_bit(const RTLIL::SigChunk &c1, const RTLIL::SigChunk &c2) + void set_bit(const RTLIL::SigBit &b1, const RTLIL::SigBit &b2) { - assert(c1.wire != NULL); - assert(c1.width == 1 && c2.width == 1); - bitDef_t bit(c1.wire, c1.offset); + assert(b1.wire != NULL); + bitDef_t bit(b1.wire, b1.offset); assert(bits.count(bit) > 0); - bits[bit]->chunk = c2; + bits[bit]->map_to = b2; } // internal helper function - void map_bit(RTLIL::SigChunk &c) const + void map_bit(RTLIL::SigBit &b) const { - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - if (c.wire && bits.count(bit) > 0) - c = bits.at(bit)->chunk; + bitDef_t bit(b.wire, b.offset); + if (b.wire && bits.count(bit) > 0) + b = bits.at(bit)->map_to; } void add(RTLIL::SigSpec from, RTLIL::SigSpec to) { - from.expand(); - to.expand(); + assert(SIZE(from) == SIZE(to)); - assert(from.chunks().size() == to.chunks().size()); - for (size_t i = 0; i < from.chunks().size(); i++) + for (int i = 0; i < SIZE(from); i++) { - const RTLIL::SigChunk &cf = from.chunks()[i]; - const RTLIL::SigChunk &ct = to.chunks()[i]; + RTLIL::SigBit &bf = from[i]; + RTLIL::SigBit &bt = to[i]; - if (cf.wire == NULL) + if (bf.wire == NULL) continue; - register_bit(cf); - register_bit(ct); + register_bit(bf); + register_bit(bt); - if (ct.wire != NULL) - merge_bit(cf, ct); + if (bt.wire != NULL) + merge_bit(bf, bt); else - set_bit(cf, ct); + set_bit(bf, bt); } } void add(RTLIL::SigSpec sig) { - sig.expand(); - for (size_t i = 0; i < sig.chunks().size(); i++) - { - const RTLIL::SigChunk &c = sig.chunks()[i]; - if (c.wire != NULL) { - register_bit(c); - set_bit(c, c); - } + for (auto &bit : sig) { + register_bit(bit); + set_bit(bit, bit); } } void del(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) - unregister_bit(c); + for (auto &bit : sig) + unregister_bit(bit); } void apply(RTLIL::SigSpec &sig) const { - sig.expand(); - for (auto &c : sig.chunks_rw()) - map_bit(c); - sig.optimize(); + for (auto &bit : sig) + map_bit(bit); } RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const -- cgit v1.2.3 From c61467a32c4bd3ec4b9e0cb6d36d602f0e4dea81 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 08:59:54 +0200 Subject: Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) --- kernel/rtlil.cc | 8 ++++---- kernel/rtlil.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6757d5dc3..2ab4a8c6e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1316,10 +1316,10 @@ RTLIL::SigChunk::SigChunk() offset = 0; } -RTLIL::SigChunk::SigChunk(const RTLIL::Const &data) +RTLIL::SigChunk::SigChunk(const RTLIL::Const &value) { wire = NULL; - this->data = data; + data = value; width = data.bits.size(); offset = 0; } @@ -1418,9 +1418,9 @@ RTLIL::SigSpec::SigSpec() width_ = 0; } -RTLIL::SigSpec::SigSpec(const RTLIL::Const &data) +RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) { - chunks_.push_back(RTLIL::SigChunk(data)); + chunks_.push_back(RTLIL::SigChunk(value)); width_ = chunks_.back().width; check(); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 53770088b..0e74c958a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -461,7 +461,7 @@ struct RTLIL::SigChunk { RTLIL::Const data; // only used if wire == NULL, LSB at index 0 int width, offset; SigChunk(); - SigChunk(const RTLIL::Const &data); + SigChunk(const RTLIL::Const &value); SigChunk(RTLIL::Wire *wire, int width, int offset); SigChunk(const std::string &str); SigChunk(int val, int width = 32); @@ -520,7 +520,7 @@ private: public: SigSpec(); - SigSpec(const RTLIL::Const &data); + SigSpec(const RTLIL::Const &value); SigSpec(const RTLIL::SigChunk &chunk); SigSpec(RTLIL::Wire *wire, int width = -1, int offset = 0); SigSpec(const std::string &str); -- cgit v1.2.3 From 260c19ec5a3adb292158658dd69a352b9325ab64 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 09:00:16 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 --- kernel/rtlil.cc | 32 ++++++++++++++++++++++++++++++++ kernel/rtlil.h | 10 ++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2ab4a8c6e..acfba057f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1324,6 +1324,13 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value) offset = 0; } +RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire) +{ + this->wire = wire; + this->width = wire->width; + this->offset = 0; +} + RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset) { this->wire = wire; @@ -1331,6 +1338,15 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset) this->offset = offset; } +RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width) +{ + RTLIL::SigChunk chunk; + chunk.wire = wire; + chunk.width = width; + chunk.offset = offset; + return chunk; +} + RTLIL::SigChunk::SigChunk(const std::string &str) { wire = NULL; @@ -1432,6 +1448,13 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) check(); } +RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) +{ + chunks_.push_back(RTLIL::SigChunk(wire)); + width_ = chunks_.back().width; + check(); +} + RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset) { chunks_.push_back(RTLIL::SigChunk(wire, width, offset)); @@ -1439,6 +1462,15 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset) check(); } +RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width) +{ + RTLIL::SigSpec sig; + sig.chunks_.push_back(RTLIL::SigChunk::grml(wire, offset, width)); + sig.width_ = sig.chunks_.back().width; + sig.check(); + return sig; +} + RTLIL::SigSpec::SigSpec(const std::string &str) { chunks_.push_back(RTLIL::SigChunk(str)); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0e74c958a..542e685de 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -462,7 +462,10 @@ struct RTLIL::SigChunk { int width, offset; SigChunk(); SigChunk(const RTLIL::Const &value); - SigChunk(RTLIL::Wire *wire, int width, int offset); + SigChunk(RTLIL::Wire *wire); + SigChunk(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error + SigChunk(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated)); + static SigChunk grml(RTLIL::Wire *wire, int offset, int width = 1); SigChunk(const std::string &str); SigChunk(int val, int width = 32); SigChunk(RTLIL::State bit, int width = 1); @@ -522,7 +525,10 @@ public: SigSpec(); SigSpec(const RTLIL::Const &value); SigSpec(const RTLIL::SigChunk &chunk); - SigSpec(RTLIL::Wire *wire, int width = -1, int offset = 0); + SigSpec(RTLIL::Wire *wire); + SigSpec(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error + SigSpec(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated)); + static SigSpec grml(RTLIL::Wire *wire, int offset, int width = 1); SigSpec(const std::string &str); SigSpec(int val, int width = 32); SigSpec(RTLIL::State bit, int width = 1); -- cgit v1.2.3 From a8d3a68971ccc4e47c54a906aae374a9a54b1415 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 08:40:31 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 --- kernel/rtlil.cc | 18 ++---------------- kernel/sigtools.h | 4 ++-- 2 files changed, 4 insertions(+), 18 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index acfba057f..f5b84bc66 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1331,13 +1331,6 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire) this->offset = 0; } -RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset) -{ - this->wire = wire; - this->width = width >= 0 ? width : wire->width; - this->offset = offset; -} - RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width) { RTLIL::SigChunk chunk; @@ -1455,13 +1448,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) check(); } -RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset) -{ - chunks_.push_back(RTLIL::SigChunk(wire, width, offset)); - width_ = chunks_.back().width; - check(); -} - RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width) { RTLIL::SigSpec sig; @@ -2166,7 +2152,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri std::vector index_tokens; sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); if (index_tokens.size() == 1) - sig.append(RTLIL::SigSpec(wire, 1, atoi(index_tokens.at(0).c_str()))); + sig.append(RTLIL::SigSpec::grml(wire, atoi(index_tokens.at(0).c_str()))); else { int a = atoi(index_tokens.at(0).c_str()); int b = atoi(index_tokens.at(1).c_str()); @@ -2174,7 +2160,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri int tmp = a; a = b, b = tmp; } - sig.append(RTLIL::SigSpec(wire, b-a+1, a)); + sig.append(RTLIL::SigSpec::grml(wire, a, b-a+1)); } } else sig.append(wire); diff --git a/kernel/sigtools.h b/kernel/sigtools.h index e93780b49..d011b0ef5 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -144,7 +144,7 @@ struct SigPool { RTLIL::SigSpec sig; for (auto &bit : bits) { - sig.append(RTLIL::SigSpec(bit.first, 1, bit.second)); + sig.append(RTLIL::SigSpec::grml(bit.first, bit.second)); break; } return sig; @@ -154,7 +154,7 @@ struct SigPool { RTLIL::SigSpec sig; for (auto &bit : bits) - sig.append(RTLIL::SigSpec(bit.first, 1, bit.second)); + sig.append(RTLIL::SigSpec::grml(bit.first, bit.second)); sig.sort_and_unify(); return sig; } -- cgit v1.2.3 From ec923652e2eb721aa16657e54a67666f855c3d65 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 09:48:26 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 --- kernel/rtlil.cc | 24 ++++++++++-------------- kernel/rtlil.h | 8 ++------ kernel/sigtools.h | 4 ++-- 3 files changed, 14 insertions(+), 22 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f5b84bc66..6bb3e6126 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1331,13 +1331,11 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire) this->offset = 0; } -RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width) +RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width) { - RTLIL::SigChunk chunk; - chunk.wire = wire; - chunk.width = width; - chunk.offset = offset; - return chunk; + this->wire = wire; + this->width = width; + this->offset = offset; } RTLIL::SigChunk::SigChunk(const std::string &str) @@ -1448,13 +1446,11 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) check(); } -RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width) +RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width) { - RTLIL::SigSpec sig; - sig.chunks_.push_back(RTLIL::SigChunk::grml(wire, offset, width)); - sig.width_ = sig.chunks_.back().width; - sig.check(); - return sig; + chunks_.push_back(RTLIL::SigChunk(wire, offset, width)); + width_ = chunks_.back().width; + check(); } RTLIL::SigSpec::SigSpec(const std::string &str) @@ -2152,7 +2148,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri std::vector index_tokens; sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); if (index_tokens.size() == 1) - sig.append(RTLIL::SigSpec::grml(wire, atoi(index_tokens.at(0).c_str()))); + sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str()))); else { int a = atoi(index_tokens.at(0).c_str()); int b = atoi(index_tokens.at(1).c_str()); @@ -2160,7 +2156,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri int tmp = a; a = b, b = tmp; } - sig.append(RTLIL::SigSpec::grml(wire, a, b-a+1)); + sig.append(RTLIL::SigSpec(wire, a, b-a+1)); } } else sig.append(wire); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 542e685de..832146594 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -463,9 +463,7 @@ struct RTLIL::SigChunk { SigChunk(); SigChunk(const RTLIL::Const &value); SigChunk(RTLIL::Wire *wire); - SigChunk(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error - SigChunk(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated)); - static SigChunk grml(RTLIL::Wire *wire, int offset, int width = 1); + SigChunk(RTLIL::Wire *wire, int offset, int width = 1); SigChunk(const std::string &str); SigChunk(int val, int width = 32); SigChunk(RTLIL::State bit, int width = 1); @@ -526,9 +524,7 @@ public: SigSpec(const RTLIL::Const &value); SigSpec(const RTLIL::SigChunk &chunk); SigSpec(RTLIL::Wire *wire); - SigSpec(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error - SigSpec(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated)); - static SigSpec grml(RTLIL::Wire *wire, int offset, int width = 1); + SigSpec(RTLIL::Wire *wire, int offset, int width = 1); SigSpec(const std::string &str); SigSpec(int val, int width = 32); SigSpec(RTLIL::State bit, int width = 1); diff --git a/kernel/sigtools.h b/kernel/sigtools.h index d011b0ef5..cd179ebf0 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -144,7 +144,7 @@ struct SigPool { RTLIL::SigSpec sig; for (auto &bit : bits) { - sig.append(RTLIL::SigSpec::grml(bit.first, bit.second)); + sig.append(RTLIL::SigSpec(bit.first, bit.second)); break; } return sig; @@ -154,7 +154,7 @@ struct SigPool { RTLIL::SigSpec sig; for (auto &bit : bits) - sig.append(RTLIL::SigSpec::grml(bit.first, bit.second)); + sig.append(RTLIL::SigSpec(bit.first, bit.second)); sig.sort_and_unify(); return sig; } -- cgit v1.2.3 From 85db102e13bbd6decda3f99ef640d0991ee24b33 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 15:35:09 +0200 Subject: Replaced RTLIL::SigSpec::operator!=() with inline version --- kernel/rtlil.cc | 7 ------- kernel/rtlil.h | 2 +- 2 files changed, 1 insertion(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6bb3e6126..f907ff642 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1929,13 +1929,6 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const return true; } -bool RTLIL::SigSpec::operator !=(const RTLIL::SigSpec &other) const -{ - if (*this == other) - return false; - return true; -} - bool RTLIL::SigSpec::is_fully_const() const { pack(); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 832146594..80007ab8c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -575,7 +575,7 @@ public: bool operator <(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const; - bool operator !=(const RTLIL::SigSpec &other) const; + inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } bool is_fully_const() const; bool is_fully_def() const; -- cgit v1.2.3 From 4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 15:36:09 +0200 Subject: Fixed all users of SigSpec::chunks_rw() and removed it --- kernel/rtlil.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 80007ab8c..e1c5b1a6b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -533,7 +533,6 @@ public: SigSpec(std::vector bits); SigSpec(std::set bits); - inline std::vector &chunks_rw() { pack(); return chunks_; } inline const std::vector &chunks() const { pack(); return chunks_; } inline const std::vector &bits() const { inline_unpack(); return bits_; } @@ -597,7 +596,8 @@ public: static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); - operator std::vector() const { return to_sigbit_vector(); } + operator std::vector() const { return chunks(); } + operator std::vector() const { return bits(); } void check() const; }; -- cgit v1.2.3 From a62c21c9c64ad5b3e0dae5d4ee4857425f73068e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 16:09:27 +0200 Subject: Removed RTLIL::SigSpec::expand() method --- kernel/consteval.h | 7 +- kernel/rtlil.cc | 41 ---------- kernel/rtlil.h | 3 - kernel/satgen.h | 10 +-- kernel/sigtools.h | 225 +++++++++++++++++++---------------------------------- 5 files changed, 86 insertions(+), 200 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 5836cdd5b..3a8ef44a0 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -71,11 +71,8 @@ struct ConstEval assign_map.apply(sig); #ifndef NDEBUG RTLIL::SigSpec current_val = values_map(sig); - current_val.expand(); - for (size_t i = 0; i < current_val.chunks().size(); i++) { - const RTLIL::SigChunk &chunk = current_val.chunks()[i]; - assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]); - } + for (int i = 0; i < SIZE(current_val); i++) + assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]); #endif values_map.add(sig, RTLIL::SigSpec(value)); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f907ff642..7dcf32b7e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1548,18 +1548,6 @@ bool RTLIL::SigSpec::packed() const return bits_.empty(); } -void RTLIL::SigSpec::expand() -{ - pack(); - std::vector new_chunks; - for (size_t i = 0; i < chunks_.size(); i++) { - for (int j = 0; j < chunks_[i].width; j++) - new_chunks.push_back(chunks_[i].extract(j, 1)); - } - chunks_.swap(new_chunks); - check(); -} - void RTLIL::SigSpec::optimize() { pack(); @@ -1791,35 +1779,6 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) // check(); } -bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool do_override) -{ - pack(); - signal.pack(); - - bool no_collisions = true; - - assert(width_ == signal.width_); - expand(); - signal.expand(); - - for (size_t i = 0; i < chunks_.size(); i++) { - bool self_free = chunks_[i].wire == NULL && chunks_[i].data.bits[0] == freeState; - bool other_free = signal.chunks_[i].wire == NULL && signal.chunks_[i].data.bits[0] == freeState; - if (!self_free && !other_free) { - if (do_override) - chunks_[i] = signal.chunks_[i]; - else - chunks_[i] = RTLIL::SigChunk(RTLIL::State::Sx, 1); - no_collisions = false; - } - if (self_free && !other_free) - chunks_[i] = signal.chunks_[i]; - } - - optimize(); - return no_collisions; -} - void RTLIL::SigSpec::extend(int width, bool is_signed) { pack(); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e1c5b1a6b..6c0a7b66f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -544,7 +544,6 @@ public: inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } - void expand(); void optimize(); RTLIL::SigSpec optimized() const; @@ -567,8 +566,6 @@ public: void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); - bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool do_override = false); - void extend(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false); diff --git a/kernel/satgen.h b/kernel/satgen.h index 9e2277076..ea04cb409 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -52,20 +52,18 @@ struct SatGen { log_assert(!undef_mode || model_undef); sigmap->apply(sig); - sig.expand(); std::vector vec; - vec.reserve(sig.chunks().size()); + vec.reserve(SIZE(sig)); - for (auto &c : sig.chunks()) - if (c.wire == NULL) { - RTLIL::State bit = c.data.bits.at(0); + for (auto &bit : sig) + if (bit.wire == NULL) { if (model_undef && dup_undef && bit == RTLIL::State::Sx) vec.push_back(ez->frozen_literal()); else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->TRUE : ez->FALSE); } else { - std::string name = pf + stringf(c.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset); + std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset); vec.push_back(ez->frozen_literal(name)); } return vec; diff --git a/kernel/sigtools.h b/kernel/sigtools.h index cd179ebf0..1a84194ee 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -27,7 +27,11 @@ struct SigPool { - typedef std::pair bitDef_t; + struct bitDef_t : public std::pair { + bitDef_t() : std::pair(NULL, 0) { } + bitDef_t(const RTLIL::SigBit &bit) : std::pair(bit.wire, bit.offset) { } + }; + std::set bits; void clear() @@ -37,14 +41,9 @@ struct SigPool void add(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits.insert(bit); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits.insert(bit); } void add(const SigPool &other) @@ -55,14 +54,9 @@ struct SigPool void del(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits.erase(bit); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits.erase(bit); } void del(const SigPool &other) @@ -73,15 +67,10 @@ struct SigPool void expand(RTLIL::SigSpec from, RTLIL::SigSpec to) { - from.expand(); - to.expand(); - assert(from.chunks().size() == to.chunks().size()); - for (size_t i = 0; i < from.chunks().size(); i++) { - bitDef_t bit_from(from.chunks()[i].wire, from.chunks()[i].offset); - bitDef_t bit_to(to.chunks()[i].wire, to.chunks()[i].offset); - if (bit_from.first == NULL || bit_to.first == NULL) - continue; - if (bits.count(bit_from) > 0) + assert(SIZE(from) == SIZE(to)); + for (int i = 0; i < SIZE(from); i++) { + bitDef_t bit_from(from[i]), bit_to(to[i]); + if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0) bits.insert(bit_to); } } @@ -89,73 +78,49 @@ struct SigPool RTLIL::SigSpec extract(RTLIL::SigSpec sig) { RTLIL::SigSpec result; - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit) > 0) - result.append(c); - } + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit)) + result.append_bit(bit); return result; } RTLIL::SigSpec remove(RTLIL::SigSpec sig) { RTLIL::SigSpec result; - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit) == 0) - result.append(c); - } + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit) == 0) + result.append(bit); return result; } bool check_any(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit) != 0) + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit)) return true; - } return false; } bool check_all(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit) == 0) + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit) == 0) return false; - } return true; } RTLIL::SigSpec export_one() { - RTLIL::SigSpec sig; - for (auto &bit : bits) { - sig.append(RTLIL::SigSpec(bit.first, bit.second)); - break; - } - return sig; + for (auto &bit : bits) + return RTLIL::SigSpec(bit.first, bit.second); + return RTLIL::SigSpec(); } RTLIL::SigSpec export_all() { - RTLIL::SigSpec sig; + std::set sig; for (auto &bit : bits) - sig.append(RTLIL::SigSpec(bit.first, bit.second)); - sig.sort_and_unify(); + sig.insert(RTLIL::SigBit(bit.first, bit.second)); return sig; } @@ -168,7 +133,11 @@ struct SigPool template > struct SigSet { - typedef std::pair bitDef_t; + struct bitDef_t : public std::pair { + bitDef_t() : std::pair(NULL, 0) { } + bitDef_t(const RTLIL::SigBit &bit) : std::pair(bit.wire, bit.offset) { } + }; + std::map> bits; void clear() @@ -178,75 +147,46 @@ struct SigSet void insert(RTLIL::SigSpec sig, T data) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].insert(data); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].insert(data); } void insert(RTLIL::SigSpec sig, const std::set &data) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].insert(data.begin(), data.end()); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].insert(data.begin(), data.end()); } void erase(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].clear(); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].clear(); } void erase(RTLIL::SigSpec sig, T data) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].erase(data); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].erase(data); } void erase(RTLIL::SigSpec sig, const std::set &data) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].erase(data.begin(), data.end()); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].erase(data.begin(), data.end()); } void find(RTLIL::SigSpec sig, std::set &result) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - for (auto &data : bits[bit]) - result.insert(data); - } + for (auto &bit : sig) + if (bit.wire != NULL) { + auto &data = bits[bit]; + result.insert(data.begin(), data.end()); + } } std::set find(RTLIL::SigSpec sig) @@ -258,22 +198,19 @@ struct SigSet bool has(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit)) + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit)) return true; - } return false; } }; struct SigMap { - typedef std::pair bitDef_t; + struct bitDef_t : public std::pair { + bitDef_t() : std::pair(NULL, 0) { } + bitDef_t(const RTLIL::SigBit &bit) : std::pair(bit.wire, bit.offset) { } + }; struct shared_bit_data_t { RTLIL::SigBit map_to; @@ -337,22 +274,20 @@ struct SigMap } // internal helper function - void register_bit(const RTLIL::SigBit &b) + void register_bit(const RTLIL::SigBit &bit) { - bitDef_t bit(b.wire, b.offset); - if (b.wire && bits.count(bit) == 0) { + if (bit.wire && bits.count(bit) == 0) { shared_bit_data_t *bd = new shared_bit_data_t; - bd->map_to = b; + bd->map_to = bit; bd->bits.insert(bit); bits[bit] = bd; } } // internal helper function - void unregister_bit(const RTLIL::SigBit &b) + void unregister_bit(const RTLIL::SigBit &bit) { - bitDef_t bit(b.wire, b.offset); - if (b.wire && bits.count(bit) > 0) { + if (bit.wire && bits.count(bit) > 0) { shared_bit_data_t *bd = bits[bit]; bd->bits.erase(bit); if (bd->bits.size() == 0) @@ -366,11 +301,8 @@ struct SigMap { assert(bit1.wire != NULL && bit2.wire != NULL); - bitDef_t b1(bit1.wire, bit1.offset); - bitDef_t b2(bit2.wire, bit2.offset); - - shared_bit_data_t *bd1 = bits[b1]; - shared_bit_data_t *bd2 = bits[b2]; + shared_bit_data_t *bd1 = bits[bit1]; + shared_bit_data_t *bd2 = bits[bit2]; assert(bd1 != NULL && bd2 != NULL); if (bd1 == bd2) @@ -394,20 +326,18 @@ struct SigMap } // internal helper function - void set_bit(const RTLIL::SigBit &b1, const RTLIL::SigBit &b2) + void set_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2) { - assert(b1.wire != NULL); - bitDef_t bit(b1.wire, b1.offset); - assert(bits.count(bit) > 0); - bits[bit]->map_to = b2; + assert(bit1.wire != NULL); + assert(bits.count(bit1) > 0); + bits[bit1]->map_to = bit2; } // internal helper function - void map_bit(RTLIL::SigBit &b) const + void map_bit(RTLIL::SigBit &bit) const { - bitDef_t bit(b.wire, b.offset); - if (b.wire && bits.count(bit) > 0) - b = bits.at(bit)->map_to; + if (bit.wire && bits.count(bit) > 0) + bit = bits.at(bit)->map_to; } void add(RTLIL::SigSpec from, RTLIL::SigSpec to) @@ -446,6 +376,11 @@ struct SigMap unregister_bit(bit); } + void apply(RTLIL::SigBit &bit) const + { + map_bit(bit); + } + void apply(RTLIL::SigSpec &sig) const { for (auto &bit : sig) -- cgit v1.2.3 From 8fd8e4a468fb650fe5dcbe892c07010f627e2c2b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:11:55 +0200 Subject: Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized --- kernel/rtlil.cc | 49 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7dcf32b7e..32a6b2775 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1550,6 +1550,7 @@ bool RTLIL::SigSpec::packed() const void RTLIL::SigSpec::optimize() { +#if 0 pack(); std::vector new_chunks; for (auto &c : chunks_) @@ -1566,14 +1567,19 @@ void RTLIL::SigSpec::optimize() } chunks_.swap(new_chunks); check(); +#endif } RTLIL::SigSpec RTLIL::SigSpec::optimized() const { +#if 0 pack(); RTLIL::SigSpec ret = *this; ret.optimize(); return ret; +#else + return *this; +#endif } void RTLIL::SigSpec::sort() @@ -1741,15 +1747,40 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) { - pack(); - signal.pack(); + if (signal.width_ == 0) + return; - for (size_t i = 0; i < signal.chunks_.size(); i++) { - chunks_.push_back(signal.chunks_[i]); - width_ += signal.chunks_[i].width; + if (width_ == 0) { + *this = signal; + return; + } + + if (packed() != signal.packed()) { + pack(); + signal.pack(); } - // check(); + if (packed()) + for (auto &other_c : signal.chunks_) + { + auto &my_last_c = chunks_.back(); + if (my_last_c.wire == NULL && other_c.wire == NULL) { + auto &this_data = my_last_c.data.bits; + auto &other_data = other_c.data.bits; + this_data.insert(this_data.end(), other_data.begin(), other_data.end()); + my_last_c.width += other_c.width; + } else + if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) { + my_last_c.width += other_c.width; + } else + chunks_.push_back(other_c); + } + else + bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end()); + + width_ += signal.width_; + + check(); } void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) @@ -1776,7 +1807,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) width_++; - // check(); + check(); } void RTLIL::SigSpec::extend(int width, bool is_signed) @@ -1824,9 +1855,13 @@ void RTLIL::SigSpec::check() const for (size_t i = 0; i < chunks_.size(); i++) { const RTLIL::SigChunk chunk = chunks_[i]; if (chunk.wire == NULL) { + if (i > 0) + assert(chunks_[i-1].wire != NULL); assert(chunk.offset == 0); assert(chunk.data.bits.size() == (size_t)chunk.width); } else { + if (i > 0 && chunks_[i-1].wire == chunk.wire) + assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width); assert(chunk.offset >= 0); assert(chunk.width >= 0); assert(chunk.offset + chunk.width <= chunk.wire->width); -- cgit v1.2.3 From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:32:28 +0200 Subject: Removed RTLIL::SigSpec::optimize() --- kernel/bitpattern.h | 3 -- kernel/rtlil.cc | 114 +++++----------------------------------------------- kernel/rtlil.h | 7 ---- 3 files changed, 9 insertions(+), 115 deletions(-) (limited to 'kernel') diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 934796d24..4f4bc37a0 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -34,10 +34,8 @@ struct BitPatternPool width = sig.size(); if (width > 0) { std::vector pattern(width); - sig.optimize(); for (int i = 0; i < width; i++) { RTLIL::SigSpec s = sig.extract(i, 1); - s.optimize(); assert(s.chunks().size() == 1); if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1) pattern[i] = s.chunks()[0].data.bits[0]; @@ -61,7 +59,6 @@ struct BitPatternPool bits_t sig2bits(RTLIL::SigSpec sig) { - sig.optimize(); assert(sig.is_fully_const()); assert(sig.chunks().size() == 1); bits_t bits = sig.chunks()[0].data.bits; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 32a6b2775..7d031e174 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -768,14 +768,6 @@ void RTLIL::Module::check() void RTLIL::Module::optimize() { - for (auto &it : cells) - it.second->optimize(); - for (auto &it : processes) - it.second->optimize(); - for (auto &it : connections) { - it.first.optimize(); - it.second.optimize(); - } } void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const @@ -1297,12 +1289,6 @@ RTLIL::Memory::Memory() size = 0; } -void RTLIL::Cell::optimize() -{ - for (auto &it : connections) - it.second.optimize(); -} - void RTLIL::Cell::check() { InternalCellChecker checker(NULL, this); @@ -1548,40 +1534,6 @@ bool RTLIL::SigSpec::packed() const return bits_.empty(); } -void RTLIL::SigSpec::optimize() -{ -#if 0 - pack(); - std::vector new_chunks; - for (auto &c : chunks_) - if (new_chunks.size() == 0) { - new_chunks.push_back(c); - } else { - RTLIL::SigChunk &cc = new_chunks.back(); - if (c.wire == NULL && cc.wire == NULL) - cc.data.bits.insert(cc.data.bits.end(), c.data.bits.begin(), c.data.bits.end()); - if (c.wire == cc.wire && (c.wire == NULL || cc.offset + cc.width == c.offset)) - cc.width += c.width; - else - new_chunks.push_back(c); - } - chunks_.swap(new_chunks); - check(); -#endif -} - -RTLIL::SigSpec RTLIL::SigSpec::optimized() const -{ -#if 0 - pack(); - RTLIL::SigSpec ret = *this; - ret.optimize(); - return ret; -#else - return *this; -#endif -} - void RTLIL::SigSpec::sort() { unpack(); @@ -1825,8 +1777,6 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) while (width_ < width) append(padding); } - - optimize(); } void RTLIL::SigSpec::extend_u0(int width, bool is_signed) @@ -1844,7 +1794,6 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) append(padding); } - optimize(); } void RTLIL::SigSpec::check() const @@ -1888,8 +1837,6 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const return width_ < other.width_; RTLIL::SigSpec a = *this, b = other; - a.optimize(); - b.optimize(); if (a.chunks_.size() != b.chunks_.size()) return a.chunks_.size() < b.chunks_.size(); @@ -1910,8 +1857,6 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const return false; RTLIL::SigSpec a = *this, b = other; - a.optimize(); - b.optimize(); if (a.chunks_.size() != b.chunks_.size()) return false; @@ -1973,22 +1918,18 @@ bool RTLIL::SigSpec::has_marked_bits() const bool RTLIL::SigSpec::as_bool() const { pack(); - assert(is_fully_const()); - SigSpec sig = *this; - sig.optimize(); - if (sig.width_) - return sig.chunks_[0].data.as_bool(); + assert(is_fully_const() && SIZE(chunks_) <= 1); + if (width_) + return chunks_[0].data.as_bool(); return false; } int RTLIL::SigSpec::as_int() const { pack(); - assert(is_fully_const()); - SigSpec sig = *this; - sig.optimize(); - if (sig.width_) - return sig.chunks_[0].data.as_int(); + assert(is_fully_const() && SIZE(chunks_) <= 1); + if (width_) + return chunks_[0].data.as_int(); return 0; } @@ -2010,11 +1951,9 @@ std::string RTLIL::SigSpec::as_string() const RTLIL::Const RTLIL::SigSpec::as_const() const { pack(); - assert(is_fully_const()); - SigSpec sig = *this; - sig.optimize(); - if (sig.width_) - return sig.chunks_[0].data; + assert(is_fully_const() && SIZE(chunks_) <= 1); + if (width_) + return chunks_[0].data; return RTLIL::Const(); } @@ -2200,18 +2139,6 @@ RTLIL::CaseRule::~CaseRule() delete *it; } -void RTLIL::CaseRule::optimize() -{ - for (auto it : switches) - it->optimize(); - for (auto &it : compare) - it.optimize(); - for (auto &it : actions) { - it.first.optimize(); - it.second.optimize(); - } -} - RTLIL::CaseRule *RTLIL::CaseRule::clone() const { RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule; @@ -2228,13 +2155,6 @@ RTLIL::SwitchRule::~SwitchRule() delete *it; } -void RTLIL::SwitchRule::optimize() -{ - signal.optimize(); - for (auto it : cases) - it->optimize(); -} - RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const { RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule; @@ -2246,15 +2166,6 @@ RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const } -void RTLIL::SyncRule::optimize() -{ - signal.optimize(); - for (auto &it : actions) { - it.first.optimize(); - it.second.optimize(); - } -} - RTLIL::SyncRule *RTLIL::SyncRule::clone() const { RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule; @@ -2270,13 +2181,6 @@ RTLIL::Process::~Process() delete *it; } -void RTLIL::Process::optimize() -{ - root_case.optimize(); - for (auto it : syncs) - it->optimize(); -} - RTLIL::Process *RTLIL::Process::clone() const { RTLIL::Process *new_proc = new RTLIL::Process; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6c0a7b66f..a13164c37 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -450,7 +450,6 @@ struct RTLIL::Cell { std::map connections; std::map parameters; RTLIL_ATTRIBUTE_MEMBERS - void optimize(); void check(); template void rewrite_sigspecs(T functor); @@ -544,9 +543,6 @@ public: inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } - void optimize(); - RTLIL::SigSpec optimized() const; - void sort(); void sort_and_unify(); @@ -624,7 +620,6 @@ struct RTLIL::SwitchRule { RTLIL_ATTRIBUTE_MEMBERS std::vector cases; ~SwitchRule(); - void optimize(); template void rewrite_sigspecs(T functor); RTLIL::SwitchRule *clone() const; @@ -634,7 +629,6 @@ struct RTLIL::SyncRule { RTLIL::SyncType type; RTLIL::SigSpec signal; std::vector actions; - void optimize(); template void rewrite_sigspecs(T functor); RTLIL::SyncRule *clone() const; @@ -646,7 +640,6 @@ struct RTLIL::Process { RTLIL::CaseRule root_case; std::vector syncs; ~Process(); - void optimize(); template void rewrite_sigspecs(T functor); RTLIL::Process *clone() const; -- cgit v1.2.3 From 2a41afb7b2415f824ea1f60337050c9f41c0e33f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 21:34:14 +0200 Subject: Added RTLIL::SigSpec::repeat() --- kernel/rtlil.cc | 8 ++++++++ kernel/rtlil.h | 2 ++ 2 files changed, 10 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d031e174..d2f37cec4 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1796,6 +1796,14 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) } +RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const +{ + RTLIL::SigSpec sig; + for (int i = 0; i < num; i++) + sig.append(*this); + return sig; +} + void RTLIL::SigSpec::check() const { if (packed()) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a13164c37..95de5f8c6 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -565,6 +565,8 @@ public: void extend(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false); + RTLIL::SigSpec repeat(int num) const; + bool operator <(const RTLIL::SigSpec &other) const; bool operator ==(const RTLIL::SigSpec &other) const; inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } -- cgit v1.2.3 From 95ac484548d4a4550568de09343964150806042d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 21:38:18 +0200 Subject: Fixed release build --- kernel/rtlil.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d2f37cec4..7d630b352 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1291,8 +1291,10 @@ RTLIL::Memory::Memory() void RTLIL::Cell::check() { +#ifndef NDEBUG InternalCellChecker checker(NULL, this); checker.check(); +#endif } RTLIL::SigChunk::SigChunk() -- cgit v1.2.3 From f368d792fbe6a4430dbf710b11e89cbf58439542 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 21:42:44 +0200 Subject: Disabled RTLIL::SigSpec::check() in release builds --- kernel/rtlil.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d630b352..b0958bd0d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1808,6 +1808,7 @@ RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const void RTLIL::SigSpec::check() const { +#ifndef NDEBUG if (packed()) { int w = 0; @@ -1836,6 +1837,7 @@ void RTLIL::SigSpec::check() const assert(width_ == SIZE(bits_)); assert(chunks_.empty()); } +#endif } bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const -- cgit v1.2.3 From 82fa3560372bd89ad0985644a76cdd14f6701ec2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 23:58:03 +0200 Subject: Added hashing to RTLIL::SigSpec relational and equal operators --- kernel/rtlil.cc | 79 ++++++++++++++++++++++++++++++++++++++++++++++----------- kernel/rtlil.h | 9 +++++-- 2 files changed, 71 insertions(+), 17 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b0958bd0d..87c9cd04c 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1411,12 +1411,14 @@ bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const RTLIL::SigSpec::SigSpec() { width_ = 0; + hash_ = 0; } RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) { chunks_.push_back(RTLIL::SigChunk(value)); width_ = chunks_.back().width; + hash_ = 0; check(); } @@ -1424,6 +1426,7 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) { chunks_.push_back(chunk); width_ = chunks_.back().width; + hash_ = 0; check(); } @@ -1431,6 +1434,7 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) { chunks_.push_back(RTLIL::SigChunk(wire)); width_ = chunks_.back().width; + hash_ = 0; check(); } @@ -1438,6 +1442,7 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width) { chunks_.push_back(RTLIL::SigChunk(wire, offset, width)); width_ = chunks_.back().width; + hash_ = 0; check(); } @@ -1445,6 +1450,7 @@ RTLIL::SigSpec::SigSpec(const std::string &str) { chunks_.push_back(RTLIL::SigChunk(str)); width_ = chunks_.back().width; + hash_ = 0; check(); } @@ -1452,6 +1458,7 @@ RTLIL::SigSpec::SigSpec(int val, int width) { chunks_.push_back(RTLIL::SigChunk(val, width)); width_ = width; + hash_ = 0; check(); } @@ -1459,6 +1466,7 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) { chunks_.push_back(RTLIL::SigChunk(bit, width)); width_ = width; + hash_ = 0; check(); } @@ -1470,12 +1478,14 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) for (int i = 0; i < width; i++) chunks_.push_back(bit); width_ = width; + hash_ = 0; check(); } RTLIL::SigSpec::SigSpec(std::vector chunks) { width_ = 0; + hash_ = 0; for (auto &c : chunks) append(c); check(); @@ -1484,6 +1494,7 @@ RTLIL::SigSpec::SigSpec(std::vector chunks) RTLIL::SigSpec::SigSpec(std::vector bits) { width_ = 0; + hash_ = 0; for (auto &bit : bits) append_bit(bit); check(); @@ -1492,6 +1503,7 @@ RTLIL::SigSpec::SigSpec(std::vector bits) RTLIL::SigSpec::SigSpec(std::set bits) { width_ = 0; + hash_ = 0; for (auto &bit : bits) append_bit(bit); check(); @@ -1529,11 +1541,34 @@ void RTLIL::SigSpec::unpack() const that->bits_.push_back(RTLIL::SigBit(c, i)); that->chunks_.clear(); + that->hash_ = 0; } -bool RTLIL::SigSpec::packed() const +#define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0) + +void RTLIL::SigSpec::hash() const { - return bits_.empty(); + RTLIL::SigSpec *that = (RTLIL::SigSpec*)this; + + if (that->hash_ != 0) + return; + + that->pack(); + that->hash_ = 5381; + + for (auto &c : that->chunks_) + if (c.wire == NULL) { + for (auto &v : c.data.bits) + DJB2(that->hash_, v); + } else { + for (auto &v : c.wire->name) + DJB2(that->hash_, v); + DJB2(that->hash_, c.offset); + DJB2(that->hash_, c.width); + } + + if (that->hash_ == 0) + that->hash_ = 1; } void RTLIL::SigSpec::sort() @@ -1842,39 +1877,53 @@ void RTLIL::SigSpec::check() const bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const { - pack(); - other.pack(); + if (this == &other) + return false; if (width_ != other.width_) return width_ < other.width_; - RTLIL::SigSpec a = *this, b = other; + pack(); + other.pack(); + + if (chunks_.size() != other.chunks_.size()) + return chunks_.size() < other.chunks_.size(); + + hash(); + other.hash(); - if (a.chunks_.size() != b.chunks_.size()) - return a.chunks_.size() < b.chunks_.size(); + if (hash_ != other.hash_) + return hash_ < other.hash_; - for (size_t i = 0; i < a.chunks_.size(); i++) - if (a.chunks_[i] != b.chunks_[i]) - return a.chunks_[i] < b.chunks_[i]; + for (size_t i = 0; i < chunks_.size(); i++) + if (chunks_[i] != other.chunks_[i]) + return chunks_[i] < other.chunks_[i]; return false; } bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const { + if (this == &other) + return true; + + if (width_ != other.width_) + return false; + pack(); other.pack(); - if (width_ != other.width_) + if (chunks_.size() != chunks_.size()) return false; - RTLIL::SigSpec a = *this, b = other; + hash(); + other.hash(); - if (a.chunks_.size() != b.chunks_.size()) + if (hash_ != other.hash_) return false; - for (size_t i = 0; i < a.chunks_.size(); i++) - if (a.chunks_[i] != b.chunks_[i]) + for (size_t i = 0; i < chunks_.size(); i++) + if (chunks_[i] != other.chunks_[i]) return false; return true; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 95de5f8c6..c25f71855 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -505,13 +505,18 @@ struct RTLIL::SigSpecIterator { struct RTLIL::SigSpec { private: + int width_; + unsigned long hash_; std::vector chunks_; // LSB at index 0 std::vector bits_; // LSB at index 0 - int width_; void pack() const; void unpack() const; - bool packed() const; + void hash() const; + + inline bool packed() const { + return bits_.empty(); + } inline void inline_unpack() const { if (!chunks_.empty()) -- cgit v1.2.3 From 6b1018314c130ffa12df2e8c73f1c0cd5853b6f7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 03:48:38 +0200 Subject: Added cover() API --- kernel/log.cc | 2 ++ kernel/log.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 949bf4327..26414d493 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -29,6 +29,8 @@ #include #include +CoverAgent *CoverAgent::first_cover_agent = NULL; + std::vector log_files; FILE *log_errfile = NULL; bool log_time = false; diff --git a/kernel/log.h b/kernel/log.h index 00265dbe0..517808061 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -63,6 +63,39 @@ void log_cell(RTLIL::Cell *cell, std::string indent = ""); #define log_assert(_assert_expr_) do { if (_assert_expr_) break; log_error("Assert `%s' failed in %s:%d.\n", #_assert_expr_, __FILE__, __LINE__); } while (0) #define log_ping() log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__) +#ifndef NDEBUG +# define cover(_id) do { \ + static CoverAgent _cover_agent(__FILE__, __LINE__, __FUNCTION__, _id); \ + _cover_agent.ticks++; \ + } while (0) +#else +# define cover(_id) do { } while (0) +#endif + +struct CoverAgent +{ + static struct CoverAgent *first_cover_agent; + struct CoverAgent *next_cover_agent; + + const char *file; + int line; + const char *func; + const char *id; + int ticks; + + CoverAgent(const char *file, int line, const char *func, const char *id) : + file(file), line(line), func(func), id(id), ticks(0) + { + next_cover_agent = first_cover_agent; + first_cover_agent = this; + }; +}; + + +// ------------------------------------------------------------ +// everything below this line are utilities for troubleshooting +// ------------------------------------------------------------ + // simple timer for performance measurements // toggle the '#if 1' to get a baseline for the perormance penalty added by the measurement struct PerformanceTimer -- cgit v1.2.3 From 9cf12570ba639ca23e1d611a27160fb46b3c46d1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 03:49:32 +0200 Subject: Added support for YOSYS_COVER_DIR env variable --- kernel/driver.cc | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index e365e67c3..4992686bd 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -749,6 +749,32 @@ int main(int argc, char **argv) delete yosys_design; yosys_design = NULL; +#ifndef NDEBUG + if (getenv("YOSYS_COVER_DIR")) + { + char filename_buffer[4096]; + snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", getenv("YOSYS_COVER_DIR"), getpid()); + FILE *f = fdopen(mkstemps(filename_buffer, 4), "w"); + + if (f == NULL) + log_error("Can't create coverage file `%s'.\n", filename_buffer); + + log("\n", filename_buffer); + + std::map> coverage_data; + for (CoverAgent *p = CoverAgent::first_cover_agent; p; p = p->next_cover_agent) { + if (coverage_data.count(p->id)) + log("WARNING: found duplicate coverage id \"%s\".\n", p->id); + coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func); + coverage_data[p->id].second += p->ticks; + } + + for (auto &it : coverage_data) + fprintf(f, "%-40s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); + fclose(f); + } +#endif + log("\nREADY.\n"); log_pop(); -- cgit v1.2.3 From 1b0d5fc22d1a1e590cb8f2252956ef1b0a38dda0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 03:50:28 +0200 Subject: Added cover() calls to RTLIL::SigSpec methods --- kernel/rtlil.cc | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 93 insertions(+), 5 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 87c9cd04c..4a0ac60f0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1516,6 +1516,7 @@ void RTLIL::SigSpec::pack() const if (that->bits_.empty()) return; + cover("kernel.rtlil.sigspec.pack"); log_assert(that->chunks_.empty()); std::vector old_bits; @@ -1533,6 +1534,7 @@ void RTLIL::SigSpec::unpack() const if (that->chunks_.empty()) return; + cover("kernel.rtlil.sigspec.unpack"); log_assert(that->bits_.empty()); that->bits_.reserve(that->width_); @@ -1553,9 +1555,10 @@ void RTLIL::SigSpec::hash() const if (that->hash_ != 0) return; + cover("kernel.rtlil.sigspec.hash"); that->pack(); - that->hash_ = 5381; + that->hash_ = 5381; for (auto &c : that->chunks_) if (c.wire == NULL) { for (auto &v : c.data.bits) @@ -1574,11 +1577,13 @@ void RTLIL::SigSpec::hash() const void RTLIL::SigSpec::sort() { unpack(); + cover("kernel.rtlil.sigspec.sort"); std::sort(bits_.begin(), bits_.end()); } void RTLIL::SigSpec::sort_and_unify() { + cover("kernel.rtlil.sigspec.sort_and_unify"); *this = this->to_sigbit_set(); } @@ -1589,6 +1594,11 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const { + if (other) + cover("kernel.rtlil.sigspec.replace_other"); + else + cover("kernel.rtlil.sigspec.replace"); + unpack(); pattern.unpack(); with.unpack(); @@ -1624,6 +1634,11 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) { + if (other) + cover("kernel.rtlil.sigspec.remove_other"); + else + cover("kernel.rtlil.sigspec.remove"); + unpack(); if (other != NULL) { @@ -1655,6 +1670,11 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other) const { + if (other) + cover("kernel.rtlil.sigspec.extract_other"); + else + cover("kernel.rtlil.sigspec.extract"); + pack(); pattern.pack(); @@ -1684,6 +1704,8 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) { + cover("kernel.rtlil.sigspec.replace"); + unpack(); with.unpack(); @@ -1699,6 +1721,8 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) void RTLIL::SigSpec::remove_const() { + cover("kernel.rtlil.sigspec.remove_const"); + unpack(); std::vector new_bits; @@ -1716,6 +1740,8 @@ void RTLIL::SigSpec::remove_const() void RTLIL::SigSpec::remove(int offset, int length) { + cover("kernel.rtlil.sigspec.remove_pos"); + unpack(); assert(offset >= 0); @@ -1731,6 +1757,7 @@ void RTLIL::SigSpec::remove(int offset, int length) RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); + cover("kernel.rtlil.sigspec.extract_pos"); return std::vector(bits_.begin() + offset, bits_.begin() + offset + length); } @@ -1744,6 +1771,8 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) return; } + cover("kernel.rtlil.sigspec.append"); + if (packed() != signal.packed()) { pack(); signal.pack(); @@ -1776,6 +1805,8 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) { if (packed()) { + cover("kernel.rtlil.sigspec.append_bit.packed"); + if (chunks_.size() == 0) chunks_.push_back(bit); else @@ -1792,7 +1823,10 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) chunks_.push_back(bit); } else + { + cover("kernel.rtlil.sigspec.append_bit.unpacked"); bits_.push_back(bit); + } width_++; @@ -1801,6 +1835,8 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) void RTLIL::SigSpec::extend(int width, bool is_signed) { + cover("kernel.rtlil.sigspec.extend"); + pack(); if (width_ > width) @@ -1818,6 +1854,8 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { + cover("kernel.rtlil.sigspec.extend_0"); + pack(); if (width_ > width) @@ -1835,6 +1873,8 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const { + cover("kernel.rtlil.sigspec.repeat"); + RTLIL::SigSpec sig; for (int i = 0; i < num; i++) sig.append(*this); @@ -1846,6 +1886,8 @@ void RTLIL::SigSpec::check() const #ifndef NDEBUG if (packed()) { + cover("kernel.rtlil.sigspec.check.packed"); + int w = 0; for (size_t i = 0; i < chunks_.size(); i++) { const RTLIL::SigChunk chunk = chunks_[i]; @@ -1869,6 +1911,8 @@ void RTLIL::SigSpec::check() const } else { + cover("kernel.rtlil.sigspec.check.unpacked"); + assert(width_ == SIZE(bits_)); assert(chunks_.empty()); } @@ -1877,6 +1921,8 @@ void RTLIL::SigSpec::check() const bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const { + cover("kernel.rtlil.sigspec.comp_lt"); + if (this == &other) return false; @@ -1896,14 +1942,18 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const return hash_ < other.hash_; for (size_t i = 0; i < chunks_.size(); i++) - if (chunks_[i] != other.chunks_[i]) + if (chunks_[i] != other.chunks_[i]) { + cover("kernel.rtlil.sigspec.comp_lt.hash_collision"); return chunks_[i] < other.chunks_[i]; + } return false; } bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const { + cover("kernel.rtlil.sigspec.comp_eq"); + if (this == &other) return true; @@ -1923,14 +1973,18 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const return false; for (size_t i = 0; i < chunks_.size(); i++) - if (chunks_[i] != other.chunks_[i]) + if (chunks_[i] != other.chunks_[i]) { + cover("kernel.rtlil.sigspec.comp_eq.hash_collision"); return false; + } return true; } bool RTLIL::SigSpec::is_fully_const() const { + cover("kernel.rtlil.sigspec.is_fully_const"); + pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) if (it->width > 0 && it->wire != NULL) @@ -1940,6 +1994,8 @@ bool RTLIL::SigSpec::is_fully_const() const bool RTLIL::SigSpec::is_fully_def() const { + cover("kernel.rtlil.sigspec.is_fully_def"); + pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) { if (it->width > 0 && it->wire != NULL) @@ -1953,6 +2009,8 @@ bool RTLIL::SigSpec::is_fully_def() const bool RTLIL::SigSpec::is_fully_undef() const { + cover("kernel.rtlil.sigspec.is_fully_undef"); + pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) { if (it->width > 0 && it->wire != NULL) @@ -1966,6 +2024,8 @@ bool RTLIL::SigSpec::is_fully_undef() const bool RTLIL::SigSpec::has_marked_bits() const { + cover("kernel.rtlil.sigspec.has_marked_bits"); + pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) if (it->width > 0 && it->wire == NULL) { @@ -1978,6 +2038,8 @@ bool RTLIL::SigSpec::has_marked_bits() const bool RTLIL::SigSpec::as_bool() const { + cover("kernel.rtlil.sigspec.as_bool"); + pack(); assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) @@ -1987,6 +2049,8 @@ bool RTLIL::SigSpec::as_bool() const int RTLIL::SigSpec::as_int() const { + cover("kernel.rtlil.sigspec.as_int"); + pack(); assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) @@ -1996,6 +2060,8 @@ int RTLIL::SigSpec::as_int() const std::string RTLIL::SigSpec::as_string() const { + cover("kernel.rtlil.sigspec.as_string"); + pack(); std::string str; for (size_t i = chunks_.size(); i > 0; i--) { @@ -2011,6 +2077,8 @@ std::string RTLIL::SigSpec::as_string() const RTLIL::Const RTLIL::SigSpec::as_const() const { + cover("kernel.rtlil.sigspec.as_const"); + pack(); assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) @@ -2020,6 +2088,8 @@ RTLIL::Const RTLIL::SigSpec::as_const() const bool RTLIL::SigSpec::match(std::string pattern) const { + cover("kernel.rtlil.sigspec.match"); + pack(); std::string str = as_string(); assert(pattern.size() == str.size()); @@ -2041,6 +2111,8 @@ bool RTLIL::SigSpec::match(std::string pattern) const std::set RTLIL::SigSpec::to_sigbit_set() const { + cover("kernel.rtlil.sigspec.to_sigbit_set"); + pack(); std::set sigbits; for (auto &c : chunks_) @@ -2051,12 +2123,16 @@ std::set RTLIL::SigSpec::to_sigbit_set() const std::vector RTLIL::SigSpec::to_sigbit_vector() const { + cover("kernel.rtlil.sigspec.to_sigbit_vector"); + unpack(); return bits_; } RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const { + cover("kernel.rtlil.sigspec.to_single_sigbit"); + pack(); log_assert(width_ == 1); for (auto &c : chunks_) @@ -2082,6 +2158,8 @@ static int sigspec_parse_get_dummy_line_num() bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str) { + cover("kernel.rtlil.sigspec.parse"); + std::vector tokens; sigspec_parse_split(tokens, str, ','); @@ -2095,6 +2173,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri continue; if ('0' <= netname[0] && netname[0] <= '9') { + cover("kernel.rtlil.sigspec.parse.const"); AST::get_line_num = sigspec_parse_get_dummy_line_num; AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname); if (ast == NULL) @@ -2107,6 +2186,8 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri if (module == NULL) return false; + cover("kernel.rtlil.sigspec.parse.net"); + if (netname[0] != '$' && netname[0] != '\\') netname = "\\" + netname; @@ -2134,9 +2215,11 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri if (!indices.empty()) { std::vector index_tokens; sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); - if (index_tokens.size() == 1) + if (index_tokens.size() == 1) { + cover("kernel.rtlil.sigspec.parse.bit_sel"); sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str()))); - else { + } else { + cover("kernel.rtlil.sigspec.parse.part_sel"); int a = atoi(index_tokens.at(0).c_str()); int b = atoi(index_tokens.at(1).c_str()); if (a > b) { @@ -2157,6 +2240,8 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL if (str.empty() || str[0] != '@') return parse(sig, module, str); + cover("kernel.rtlil.sigspec.parse.sel"); + str = RTLIL::escape_id(str.substr(1)); if (design->selection_vars.count(str) == 0) return false; @@ -2173,11 +2258,13 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str) { if (str == "0") { + cover("kernel.rtlil.sigspec.parse.rhs_zeros"); sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_); return true; } if (str == "~0") { + cover("kernel.rtlil.sigspec.parse.rhs_ones"); sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_); return true; } @@ -2187,6 +2274,7 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R long long int val = strtoll(p, &endptr, 10); if (endptr && endptr != p && *endptr == 0) { sig = RTLIL::SigSpec(val, lhs.width_); + cover("kernel.rtlil.sigspec.parse.rhs_dec"); return true; } } -- cgit v1.2.3 From 798f71362975c625f4e24b0c981b15b5684ab33d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 04:16:32 +0200 Subject: Added support for YOSYS_COVER_FILE env variable --- kernel/driver.cc | 13 ++++++++++--- kernel/rtlil.cc | 2 ++ 2 files changed, 12 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 4992686bd..9749ff305 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -750,11 +750,18 @@ int main(int argc, char **argv) yosys_design = NULL; #ifndef NDEBUG - if (getenv("YOSYS_COVER_DIR")) + if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE")) { char filename_buffer[4096]; - snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", getenv("YOSYS_COVER_DIR"), getpid()); - FILE *f = fdopen(mkstemps(filename_buffer, 4), "w"); + FILE *f; + + if (getenv("YOSYS_COVER_DIR")) { + snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", getenv("YOSYS_COVER_DIR"), getpid()); + f = fdopen(mkstemps(filename_buffer, 4), "w"); + } else { + snprintf(filename_buffer, 4096, "%s", getenv("YOSYS_COVER_FILE")); + f = fopen(filename_buffer, "w"); + } if (f == NULL) log_error("Can't create coverage file `%s'.\n", filename_buffer); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 4a0ac60f0..ca8e9b6d8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1947,6 +1947,7 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const return chunks_[i] < other.chunks_[i]; } + cover("kernel.rtlil.sigspec.comp_lt.equal"); return false; } @@ -1978,6 +1979,7 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const return false; } + cover("kernel.rtlil.sigspec.comp_eq.equal"); return true; } -- cgit v1.2.3 From 22ede43b3f5016784b2e22c0ea95b7f718d7598e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 04:46:36 +0200 Subject: Small changes regarding cover() and check() in SigSpec --- kernel/rtlil.cc | 15 +++++---------- kernel/rtlil.h | 4 ++++ 2 files changed, 9 insertions(+), 10 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ca8e9b6d8..5194b5f7d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1594,10 +1594,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const { - if (other) - cover("kernel.rtlil.sigspec.replace_other"); - else - cover("kernel.rtlil.sigspec.replace"); + cover("kernel.rtlil.sigspec.replace"); unpack(); pattern.unpack(); @@ -1797,8 +1794,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end()); width_ += signal.width_; - - check(); + // check(); } void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) @@ -1829,8 +1825,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) } width_++; - - check(); + // check(); } void RTLIL::SigSpec::extend(int width, bool is_signed) @@ -1881,9 +1876,9 @@ RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const return sig; } +#ifndef NDEBUG void RTLIL::SigSpec::check() const { -#ifndef NDEBUG if (packed()) { cover("kernel.rtlil.sigspec.check.packed"); @@ -1916,8 +1911,8 @@ void RTLIL::SigSpec::check() const assert(width_ == SIZE(bits_)); assert(chunks_.empty()); } -#endif } +#endif bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c25f71855..68eee46ea 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -599,7 +599,11 @@ public: operator std::vector() const { return chunks(); } operator std::vector() const { return bits(); } +#ifndef NDEBUG void check() const; +#else + inline void check() const { } +#endif }; inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const { -- cgit v1.2.3 From 7679000673f7a5c07037dfd3373162cbbcdb0624 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 15:05:05 +0200 Subject: Now using a dedicated ELF section for all coverage counters --- kernel/driver.cc | 6 +++--- kernel/log.cc | 2 -- kernel/log.h | 39 ++++++++++++++++++--------------------- 3 files changed, 21 insertions(+), 26 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 9749ff305..64165737e 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -760,7 +760,7 @@ int main(int argc, char **argv) f = fdopen(mkstemps(filename_buffer, 4), "w"); } else { snprintf(filename_buffer, 4096, "%s", getenv("YOSYS_COVER_FILE")); - f = fopen(filename_buffer, "w"); + f = fopen(filename_buffer, "a+"); } if (f == NULL) @@ -769,11 +769,11 @@ int main(int argc, char **argv) log("\n", filename_buffer); std::map> coverage_data; - for (CoverAgent *p = CoverAgent::first_cover_agent; p; p = p->next_cover_agent) { + for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) { if (coverage_data.count(p->id)) log("WARNING: found duplicate coverage id \"%s\".\n", p->id); coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func); - coverage_data[p->id].second += p->ticks; + coverage_data[p->id].second += p->counter; } for (auto &it : coverage_data) diff --git a/kernel/log.cc b/kernel/log.cc index 26414d493..949bf4327 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -29,8 +29,6 @@ #include #include -CoverAgent *CoverAgent::first_cover_agent = NULL; - std::vector log_files; FILE *log_errfile = NULL; bool log_time = false; diff --git a/kernel/log.h b/kernel/log.h index 517808061..804175909 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -63,34 +63,31 @@ void log_cell(RTLIL::Cell *cell, std::string indent = ""); #define log_assert(_assert_expr_) do { if (_assert_expr_) break; log_error("Assert `%s' failed in %s:%d.\n", #_assert_expr_, __FILE__, __LINE__); } while (0) #define log_ping() log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__) + +// --------------------------------------------------- +// This is the magic behind the code coverage counters +// --------------------------------------------------- + +struct CoverData { + const char *file, *func, *id; + int line, counter; +} __attribute__ ((packed)); + +// this two symbols are created by the linker for the "yosys_cover_list" ELF section +#ifndef NDEBUG +extern "C" struct CoverData __start_yosys_cover_list[]; +extern "C" struct CoverData __stop_yosys_cover_list[]; +#endif + #ifndef NDEBUG # define cover(_id) do { \ - static CoverAgent _cover_agent(__FILE__, __LINE__, __FUNCTION__, _id); \ - _cover_agent.ticks++; \ + static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1))) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \ + __d.counter++; \ } while (0) #else # define cover(_id) do { } while (0) #endif -struct CoverAgent -{ - static struct CoverAgent *first_cover_agent; - struct CoverAgent *next_cover_agent; - - const char *file; - int line; - const char *func; - const char *id; - int ticks; - - CoverAgent(const char *file, int line, const char *func, const char *id) : - file(file), line(line), func(func), id(id), ticks(0) - { - next_cover_agent = first_cover_agent; - first_cover_agent = this; - }; -}; - // ------------------------------------------------------------ // everything below this line are utilities for troubleshooting -- cgit v1.2.3 From e589289df7662f076d12f7237321b429401952e2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 15:05:41 +0200 Subject: Some improvements in SigSpec packing/unpacking and checking --- kernel/rtlil.cc | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5194b5f7d..8e509f360 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1516,15 +1516,32 @@ void RTLIL::SigSpec::pack() const if (that->bits_.empty()) return; - cover("kernel.rtlil.sigspec.pack"); + cover("kernel.rtlil.sigspec.convert.pack"); log_assert(that->chunks_.empty()); std::vector old_bits; old_bits.swap(that->bits_); - that->width_ = 0; + RTLIL::SigChunk *last_const = NULL; + RTLIL::SigChunk *last_wire = NULL; + int last_wire_end = 0; + for (auto &bit : old_bits) - that->append_bit(bit); + if (bit.wire == NULL && last_const) { + last_const->data.bits.push_back(bit.data); + last_const->width++; + } else + if (bit.wire && last_wire && last_wire->wire == bit.wire && last_wire_end == bit.offset) { + last_wire->width++; + last_wire_end++; + } else { + that->chunks_.push_back(bit); + last_const = bit.wire ? NULL : &that->chunks_.back(); + last_wire = bit.wire ? &that->chunks_.back() : NULL; + last_wire_end = bit.offset + 1; + } + + check(); } void RTLIL::SigSpec::unpack() const @@ -1534,7 +1551,7 @@ void RTLIL::SigSpec::unpack() const if (that->chunks_.empty()) return; - cover("kernel.rtlil.sigspec.unpack"); + cover("kernel.rtlil.sigspec.convert.unpack"); log_assert(that->bits_.empty()); that->bits_.reserve(that->width_); @@ -1701,7 +1718,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) { - cover("kernel.rtlil.sigspec.replace"); + cover("kernel.rtlil.sigspec.replace_pos"); unpack(); with.unpack(); @@ -1794,7 +1811,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end()); width_ += signal.width_; - // check(); + check(); } void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) @@ -1825,7 +1842,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) } width_++; - // check(); + check(); } void RTLIL::SigSpec::extend(int width, bool is_signed) @@ -1879,7 +1896,11 @@ RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const #ifndef NDEBUG void RTLIL::SigSpec::check() const { - if (packed()) + if (width_ > 64) + { + cover("kernel.rtlil.sigspec.check.skip"); + } + else if (packed()) { cover("kernel.rtlil.sigspec.check.packed"); -- cgit v1.2.3 From 2f54345cff3aea768bb89754654127a3b0ee58e9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 15:06:45 +0200 Subject: Added "cover" command --- kernel/driver.cc | 11 ++--------- kernel/log.h | 41 ++++++++++++++++++++++++++++++++++------- kernel/register.cc | 28 ++++++++++++++++------------ kernel/register.h | 9 +++++---- 4 files changed, 57 insertions(+), 32 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 64165737e..a4556fb1b 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -768,16 +768,9 @@ int main(int argc, char **argv) log("\n", filename_buffer); - std::map> coverage_data; - for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) { - if (coverage_data.count(p->id)) - log("WARNING: found duplicate coverage id \"%s\".\n", p->id); - coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func); - coverage_data[p->id].second += p->counter; - } + for (auto &it : get_coverage_data()) + fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); - for (auto &it : coverage_data) - fprintf(f, "%-40s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); fclose(f); } #endif diff --git a/kernel/log.h b/kernel/log.h index 804175909..0e8d08272 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -21,7 +21,10 @@ #define LOG_H #include "kernel/rtlil.h" +#include "kernel/register.h" + #include +#include #include #include #include @@ -68,22 +71,46 @@ void log_cell(RTLIL::Cell *cell, std::string indent = ""); // This is the magic behind the code coverage counters // --------------------------------------------------- +#ifndef NDEBUG + +#define cover(_id) do { \ + static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1))) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \ + __d.counter++; \ +} while (0) + struct CoverData { const char *file, *func, *id; int line, counter; } __attribute__ ((packed)); // this two symbols are created by the linker for the "yosys_cover_list" ELF section -#ifndef NDEBUG extern "C" struct CoverData __start_yosys_cover_list[]; extern "C" struct CoverData __stop_yosys_cover_list[]; -#endif -#ifndef NDEBUG -# define cover(_id) do { \ - static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1))) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \ - __d.counter++; \ - } while (0) +static inline std::map> get_coverage_data() +{ + std::map> coverage_data; + + for (auto &it : REGISTER_INTERN::pass_register) { + std::string key = stringf("passes.%s", it.first.c_str()); + coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__); + coverage_data[key].second += it.second->call_counter; + } + + for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) { + if (coverage_data.count(p->id)) + log("WARNING: found duplicate coverage id \"%s\".\n", p->id); + coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func); + coverage_data[p->id].second += p->counter; + } + + for (auto &it : coverage_data) + if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/")) + it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/")); + + return coverage_data; +} + #else # define cover(_id) do { } while (0) #endif diff --git a/kernel/register.cc b/kernel/register.cc index 84051948f..e7ad7ef05 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -32,9 +32,7 @@ using namespace REGISTER_INTERN; namespace REGISTER_INTERN { bool echo_mode = false; - int raw_register_count = 0; - bool raw_register_done = false; - Pass *raw_register_array[MAX_REG_COUNT]; + Pass *first_queued_pass; std::map frontend_register; std::map pass_register; @@ -45,9 +43,9 @@ std::vector Frontend::next_args; Pass::Pass(std::string name, std::string short_help) : pass_name(name), short_help(short_help) { - assert(!raw_register_done); - assert(raw_register_count < MAX_REG_COUNT); - raw_register_array[raw_register_count++] = this; + next_queued_pass = first_queued_pass; + first_queued_pass = this; + call_counter = 0; } void Pass::run_register() @@ -58,11 +56,10 @@ void Pass::run_register() void Pass::init_register() { - if (raw_register_done) - done_register(); - while (raw_register_count > 0) - raw_register_array[--raw_register_count]->run_register(); - raw_register_done = true; + while (first_queued_pass) { + first_queued_pass->run_register(); + first_queued_pass = first_queued_pass->next_queued_pass; + } } void Pass::done_register() @@ -70,7 +67,7 @@ void Pass::done_register() frontend_register.clear(); pass_register.clear(); backend_register.clear(); - raw_register_done = false; + assert(first_queued_pass == NULL); } Pass::~Pass() @@ -191,6 +188,7 @@ void Pass::call(RTLIL::Design *design, std::vector args) log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str()); size_t orig_sel_stack_pos = design->selection_stack.size(); + pass_register[args[0]]->call_counter++; pass_register[args[0]]->execute(args, design); while (design->selection_stack.size() > orig_sel_stack_pos) design->selection_stack.pop_back(); @@ -271,6 +269,7 @@ void Frontend::execute(std::vector args, RTLIL::Design *design) do { FILE *f = NULL; next_args.clear(); + call_counter++; execute(f, std::string(), args, design); args = next_args; fclose(f); @@ -334,9 +333,11 @@ void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filenam log_cmd_error("No such frontend: %s\n", args[0].c_str()); if (f != NULL) { + frontend_register[args[0]]->call_counter++; frontend_register[args[0]]->execute(f, filename, args, design); } else if (filename == "-") { FILE *f_stdin = stdin; // workaround for OpenBSD 'stdin' implementation + frontend_register[args[0]]->call_counter++; frontend_register[args[0]]->execute(f_stdin, "", args, design); } else { if (!filename.empty()) @@ -367,6 +368,7 @@ Backend::~Backend() void Backend::execute(std::vector args, RTLIL::Design *design) { FILE *f = NULL; + call_counter++; execute(f, std::string(), args, design); if (f != stdout) fclose(f); @@ -428,9 +430,11 @@ void Backend::backend_call(RTLIL::Design *design, FILE *f, std::string filename, size_t orig_sel_stack_pos = design->selection_stack.size(); if (f != NULL) { + backend_register[args[0]]->call_counter++; backend_register[args[0]]->execute(f, filename, args, design); } else if (filename == "-") { FILE *f_stdout = stdout; // workaround for OpenBSD 'stdout' implementation + backend_register[args[0]]->call_counter++; backend_register[args[0]]->execute(f_stdout, "", args, design); } else { if (!filename.empty()) diff --git a/kernel/register.h b/kernel/register.h index b07c46177..fd073cbe7 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -47,9 +47,11 @@ extern std::vector pushed_designs; struct Pass { std::string pass_name, short_help; + int call_counter; + Pass(std::string name, std::string short_help = "** document me **"); - virtual void run_register(); virtual ~Pass(); + virtual void help(); virtual void execute(std::vector args, RTLIL::Design *design) = 0; @@ -66,6 +68,8 @@ struct Pass static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command); static void call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector args); + Pass *next_queued_pass; + virtual void run_register(); static void init_register(); static void done_register(); }; @@ -105,9 +109,6 @@ struct Backend : Pass extern void handle_extra_select_args(Pass *pass, std::vector args, size_t argidx, size_t args_size, RTLIL::Design *design); namespace REGISTER_INTERN { - extern int raw_register_count; - extern bool raw_register_done; - extern Pass *raw_register_array[]; extern std::map pass_register; extern std::map frontend_register; extern std::map backend_register; -- cgit v1.2.3 From 10d2402e2f3cd49bd8c4e0cddb01c90c5615bb05 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 19:36:20 +0200 Subject: Added cover_list() API --- kernel/log.cc | 3 +++ kernel/log.h | 45 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 46 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 949bf4327..63a0a84dd 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -29,6 +29,9 @@ #include #include +// declared extern in log.h +std::map> extra_coverage_data; + std::vector log_files; FILE *log_errfile = NULL; bool log_time = false; diff --git a/kernel/log.h b/kernel/log.h index 0e8d08272..18ea528a0 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -30,6 +30,10 @@ #include #include +#define S__LINE__sub2(x) #x +#define S__LINE__sub1(x) S__LINE__sub2(x) +#define S__LINE__ S__LINE__sub1(__LINE__) + extern std::vector log_files; extern FILE *log_errfile; extern bool log_time; @@ -87,6 +91,19 @@ struct CoverData { extern "C" struct CoverData __start_yosys_cover_list[]; extern "C" struct CoverData __stop_yosys_cover_list[]; +extern std::map> extra_coverage_data; + +static inline void cover_extra(std::string parent, std::string id, bool increment = true) { + if (extra_coverage_data.count(id) == 0) { + for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) + if (p->id == parent) + extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func); + log_assert(extra_coverage_data.count(id)); + } + if (increment) + extra_coverage_data[id].second++; +} + static inline std::map> get_coverage_data() { std::map> coverage_data; @@ -97,6 +114,13 @@ static inline std::map> get_coverage_da coverage_data[key].second += it.second->call_counter; } + for (auto &it : extra_coverage_data) { + if (coverage_data.count(it.first)) + log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str()); + coverage_data[it.first].first = it.second.first; + coverage_data[it.first].second += it.second.second; + } + for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) { if (coverage_data.count(p->id)) log("WARNING: found duplicate coverage id \"%s\".\n", p->id); @@ -111,8 +135,25 @@ static inline std::map> get_coverage_da return coverage_data; } +#define cover_list(_id, ...) do { cover(_id); \ + std::string r = cover_list_worker(_id, __VA_ARGS__); \ + log_assert(r.empty()); \ +} while (0) + +static inline std::string cover_list_worker(std::string, std::string last) { + return last; +} + +template +std::string cover_list_worker(std::string prefix, std::string first, T... rest) { + std::string selected = cover_list_worker(prefix, rest...); + cover_extra(prefix, prefix + "." + first, first == selected); + return first == selected ? "" : selected; +} + #else -# define cover(_id) do { } while (0) +# define cover(...) do { } while (0) +# define cover_list(...) do { } while (0) #endif @@ -196,7 +237,7 @@ static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); } template static inline void log_dump_val_worker(T *ptr) { log("%p", ptr); } -template +template void log_dump_args_worker(const char *p, T first, Args ... args) { int next_p_state = 0; -- cgit v1.2.3 From 6aa792c864444324a1b140c2b63bd860f0cc3914 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 22:47:57 +0200 Subject: Replaced more old SigChunk programming patterns --- kernel/bitpattern.h | 10 +++------- kernel/consteval.h | 6 +++--- kernel/rtlil.cc | 17 +++++++++++++++++ kernel/rtlil.h | 4 +++- 4 files changed, 26 insertions(+), 11 deletions(-) (limited to 'kernel') diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 4f4bc37a0..05b2bbc24 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -35,10 +35,8 @@ struct BitPatternPool if (width > 0) { std::vector pattern(width); for (int i = 0; i < width; i++) { - RTLIL::SigSpec s = sig.extract(i, 1); - assert(s.chunks().size() == 1); - if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1) - pattern[i] = s.chunks()[0].data.bits[0]; + if (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1) + pattern[i] = sig[i].data; else pattern[i] = RTLIL::State::Sa; } @@ -59,9 +57,7 @@ struct BitPatternPool bits_t sig2bits(RTLIL::SigSpec sig) { - assert(sig.is_fully_const()); - assert(sig.chunks().size() == 1); - bits_t bits = sig.chunks()[0].data.bits; + bits_t bits = sig.as_const().bits; for (auto &b : bits) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; diff --git a/kernel/consteval.h b/kernel/consteval.h index 3a8ef44a0..7b1b798c8 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -207,9 +207,9 @@ struct ConstEval if (sig.is_fully_const()) return true; - for (size_t i = 0; i < sig.chunks().size(); i++) - if (sig.chunks()[i].wire != NULL) - undef.append(sig.chunks()[i]); + for (auto &c : sig.chunks()) + if (c.wire != NULL) + undef.append(c); return false; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8e509f360..f741e2a34 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1999,6 +1999,14 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const return true; } +bool RTLIL::SigSpec::is_wire() const +{ + cover("kernel.rtlil.sigspec.is_wire"); + + pack(); + return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_; +} + bool RTLIL::SigSpec::is_fully_const() const { cover("kernel.rtlil.sigspec.is_fully_const"); @@ -2104,6 +2112,15 @@ RTLIL::Const RTLIL::SigSpec::as_const() const return RTLIL::Const(); } +RTLIL::Wire *RTLIL::SigSpec::as_wire() const +{ + cover("kernel.rtlil.sigspec.as_wire"); + + pack(); + assert(is_wire()); + return chunks_[0].wire; +} + bool RTLIL::SigSpec::match(std::string pattern) const { cover("kernel.rtlil.sigspec.match"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 68eee46ea..a4b7e8492 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -576,6 +576,7 @@ public: bool operator ==(const RTLIL::SigSpec &other) const; inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } + bool is_wire() const; bool is_fully_const() const; bool is_fully_def() const; bool is_fully_undef() const; @@ -585,6 +586,7 @@ public: int as_int() const; std::string as_string() const; RTLIL::Const as_const() const; + RTLIL::Wire *as_wire() const; bool match(std::string pattern) const; @@ -612,7 +614,7 @@ inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const { inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { assert(sig.size() == 1 && sig.chunks().size() == 1); - *this = SigBit(sig.chunks()[0]); + *this = SigBit(sig.chunks().front()); } struct RTLIL::CaseRule { -- cgit v1.2.3 From 7f1789ad1bb978132e8e09fee54ded81b370fcb3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 03:17:35 +0200 Subject: Fixed typo in cover id --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f741e2a34..6bb395ec2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1866,7 +1866,7 @@ void RTLIL::SigSpec::extend(int width, bool is_signed) void RTLIL::SigSpec::extend_u0(int width, bool is_signed) { - cover("kernel.rtlil.sigspec.extend_0"); + cover("kernel.rtlil.sigspec.extend_u0"); pack(); -- cgit v1.2.3 From c4e4f79a2a2fd5530fa2677245f9361c7b04df70 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 12:22:37 +0200 Subject: Disabled cover() for non-linux builds --- kernel/driver.cc | 2 +- kernel/log.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index a4556fb1b..3c185e44b 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -749,7 +749,7 @@ int main(int argc, char **argv) delete yosys_design; yosys_design = NULL; -#ifndef NDEBUG +#ifdef COVER_ACTIVE if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE")) { char filename_buffer[4096]; diff --git a/kernel/log.h b/kernel/log.h index 18ea528a0..1658800dd 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -75,7 +75,8 @@ void log_cell(RTLIL::Cell *cell, std::string indent = ""); // This is the magic behind the code coverage counters // --------------------------------------------------- -#ifndef NDEBUG +#if defined(__linux__) && !defined(NDEBUG) +#define COVER_ACTIVE #define cover(_id) do { \ static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1))) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \ -- cgit v1.2.3 From c762050e7fc2c733210f8cd2b147e6084af0afe1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 14:23:10 +0200 Subject: Added RTLIL::SigSpec is_chunk()/as_chunk() API --- kernel/rtlil.cc | 17 +++++++++++++++++ kernel/rtlil.h | 3 +++ 2 files changed, 20 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6bb395ec2..83524d796 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2007,6 +2007,14 @@ bool RTLIL::SigSpec::is_wire() const return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_; } +bool RTLIL::SigSpec::is_chunk() const +{ + cover("kernel.rtlil.sigspec.is_chunk"); + + pack(); + return SIZE(chunks_) == 1; +} + bool RTLIL::SigSpec::is_fully_const() const { cover("kernel.rtlil.sigspec.is_fully_const"); @@ -2121,6 +2129,15 @@ RTLIL::Wire *RTLIL::SigSpec::as_wire() const return chunks_[0].wire; } +RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const +{ + cover("kernel.rtlil.sigspec.as_chunk"); + + pack(); + assert(is_chunk()); + return chunks_[0]; +} + bool RTLIL::SigSpec::match(std::string pattern) const { cover("kernel.rtlil.sigspec.match"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a4b7e8492..59db099fb 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -577,6 +577,8 @@ public: inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); } bool is_wire() const; + bool is_chunk() const; + bool is_fully_const() const; bool is_fully_def() const; bool is_fully_undef() const; @@ -587,6 +589,7 @@ public: std::string as_string() const; RTLIL::Const as_const() const; RTLIL::Wire *as_wire() const; + RTLIL::SigChunk as_chunk() const; bool match(std::string pattern) const; -- cgit v1.2.3 From 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 15:05:18 +0200 Subject: Use only module->addCell() and module->remove() to create and delete cells --- kernel/rtlil.cc | 37 +++++++++++++++++++++++++++++++++++-- kernel/rtlil.h | 21 +++++++++++++++++++-- 2 files changed, 54 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 83524d796..17e4a2733 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -782,8 +782,14 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const for (auto &it : memories) new_mod->memories[it.first] = new RTLIL::Memory(*it.second); - for (auto &it : cells) - new_mod->cells[it.first] = new RTLIL::Cell(*it.second); + for (auto &it : cells) { + new_mod->cells[it.first] = new RTLIL::Cell; + new_mod->cells[it.first]->name = it.second->name; + new_mod->cells[it.first]->type = it.second->type; + new_mod->cells[it.first]->connections = it.second->connections; + new_mod->cells[it.first]->parameters = it.second->parameters; + new_mod->cells[it.first]->attributes = it.second->attributes; + } for (auto &it : processes) new_mod->processes[it.first] = it.second->clone(); @@ -834,6 +840,33 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) delete cell; } +void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) +{ + assert(wires[wire->name] == wire); + wires.erase(wire->name); + wire->name = new_name; + add(wire); +} + +void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name) +{ + assert(cells[cell->name] == cell); + cells.erase(cell->name); + cell->name = new_name; + add(cell); +} + +void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name) +{ + assert(count_id(old_name) != 0); + if (wires.count(old_name)) + rename(wires.at(old_name), new_name); + else if (cells.count(old_name)) + rename(cells.at(old_name), new_name); + else + log_abort(); +} + static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) { if (a->port_id && !b->port_id) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 59db099fb..e1e4a54bc 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -271,7 +271,8 @@ struct RTLIL::Design { return attributes.at(id).as_bool(); \ } -struct RTLIL::Module { +struct RTLIL::Module +{ RTLIL::IdString name; std::set avail_parameters; std::map wires; @@ -295,6 +296,10 @@ struct RTLIL::Module { void add(RTLIL::Cell *cell); void remove(RTLIL::Cell *cell); + void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); + void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); + void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); @@ -444,7 +449,19 @@ struct RTLIL::Memory { Memory(); }; -struct RTLIL::Cell { +struct RTLIL::Cell +{ +protected: + // Use module->addCell() and module->remove() to create or destroy modules. + friend struct RTLIL::Module; + Cell() { }; + ~Cell() { }; + +public: + // do not copy simply cells + Cell(RTLIL::Cell &other) = delete; + void operator=(RTLIL::Cell &other) = delete; + RTLIL::IdString name; RTLIL::IdString type; std::map connections; -- cgit v1.2.3 From 4755e14e7b9ba57ea21bec4c0d0b3ac6080307e4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 00:38:44 +0200 Subject: Added copy-constructor-like module->addCell(name, other) method --- kernel/rtlil.cc | 19 +++++++++++-------- kernel/rtlil.h | 1 + 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 17e4a2733..1a6e386ff 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -782,14 +782,8 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const for (auto &it : memories) new_mod->memories[it.first] = new RTLIL::Memory(*it.second); - for (auto &it : cells) { - new_mod->cells[it.first] = new RTLIL::Cell; - new_mod->cells[it.first]->name = it.second->name; - new_mod->cells[it.first]->type = it.second->type; - new_mod->cells[it.first]->connections = it.second->connections; - new_mod->cells[it.first]->parameters = it.second->parameters; - new_mod->cells[it.first]->attributes = it.second->attributes; - } + for (auto &it : cells) + new_mod->addCell(it.first, it.second); for (auto &it : processes) new_mod->processes[it.first] = it.second->clone(); @@ -912,6 +906,15 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) return cell; } +RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other) +{ + RTLIL::Cell *cell = addCell(name, other->type); + cell->connections = other->connections; + cell->parameters = other->parameters; + cell->attributes = other->attributes; + return cell; +} + #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ RTLIL::Cell *cell = new RTLIL::Cell; \ diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e1e4a54bc..fbd6e719d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -302,6 +302,7 @@ struct RTLIL::Module RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); // The add* methods create a cell and return the created cell. All signals must exist in advance. -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- kernel/consteval.h | 18 +++--- kernel/modwalker.h | 4 +- kernel/rtlil.cc | 171 +++++++++++++++++++++++++++-------------------------- kernel/rtlil.h | 36 +++++++---- kernel/satgen.h | 170 ++++++++++++++++++++++++++-------------------------- kernel/sigtools.h | 2 +- 6 files changed, 211 insertions(+), 190 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 7b1b798c8..5469fa80f 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -43,7 +43,7 @@ struct ConstEval for (auto &it : module->cells) { if (!ct.cell_known(it.second->type)) continue; - for (auto &it2 : it.second->connections) + for (auto &it2 : it.second->connections_) if (ct.cell_output(it.second->type, it2.first)) sig2driver.insert(assign_map(it2.second), it.second); } @@ -87,22 +87,22 @@ struct ConstEval { RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - assert(cell->connections.count("\\Y") > 0); - sig_y = values_map(assign_map(cell->connections["\\Y"])); + assert(cell->connections_.count("\\Y") > 0); + sig_y = values_map(assign_map(cell->connections_["\\Y"])); if (sig_y.is_fully_const()) return true; - if (cell->connections.count("\\S") > 0) { - sig_s = cell->connections["\\S"]; + if (cell->connections_.count("\\S") > 0) { + sig_s = cell->connections_["\\S"]; if (!eval(sig_s, undef, cell)) return false; } - if (cell->connections.count("\\A") > 0) - sig_a = cell->connections["\\A"]; + if (cell->connections_.count("\\A") > 0) + sig_a = cell->connections_["\\A"]; - if (cell->connections.count("\\B") > 0) - sig_b = cell->connections["\\B"]; + if (cell->connections_.count("\\B") > 0) + sig_b = cell->connections_["\\B"]; if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_") { diff --git a/kernel/modwalker.h b/kernel/modwalker.h index 6c3da5dd0..efd97379c 100644 --- a/kernel/modwalker.h +++ b/kernel/modwalker.h @@ -88,12 +88,12 @@ struct ModWalker void add_cell(RTLIL::Cell *cell) { if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) add_cell_port(cell, conn.first, sigmap(conn.second), ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first)); } else { - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) add_cell_port(cell, conn.first, sigmap(conn.second), true, true); } } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1a6e386ff..4d0aadbb5 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -348,9 +348,9 @@ namespace { void port(const char *name, int width) { - if (cell->connections.count(name) == 0) + if (cell->connections_.count(name) == 0) error(__LINE__); - if (cell->connections.at(name).size() != width) + if (cell->connections_.at(name).size() != width) error(__LINE__); expected_ports.insert(name); } @@ -360,7 +360,7 @@ namespace { for (auto ¶ : cell->parameters) if (expected_params.count(para.first) == 0) error(__LINE__); - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) if (expected_ports.count(conn.first) == 0) error(__LINE__); @@ -379,13 +379,13 @@ namespace { for (const char *p = ports; *p; p++) { char portname[3] = { '\\', *p, 0 }; - if (cell->connections.count(portname) == 0) + if (cell->connections_.count(portname) == 0) error(__LINE__); - if (cell->connections.at(portname).size() != 1) + if (cell->connections_.at(portname).size() != 1) error(__LINE__); } - for (auto &conn : cell->connections) { + for (auto &conn : cell->connections_) { if (conn.first.size() != 2 || conn.first.at(0) != '\\') error(__LINE__); if (strchr(ports, conn.first.at(1)) == NULL) @@ -734,7 +734,7 @@ void RTLIL::Module::check() assert(it.first == it.second->name); assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$')); - for (auto &it2 : it.second->connections) { + for (auto &it2 : it.second->connections_) { assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); it2.second.check(); } @@ -754,7 +754,7 @@ void RTLIL::Module::check() // FIXME: More checks here.. } - for (auto &it : connections) { + for (auto &it : connections_) { assert(it.first.size() == it.second.size()); it.first.check(); it.second.check(); @@ -773,7 +773,7 @@ void RTLIL::Module::optimize() void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const { new_mod->name = name; - new_mod->connections = connections; + new_mod->connections_ = connections_; new_mod->attributes = attributes; for (auto &it : wires) @@ -873,6 +873,11 @@ static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) return a->port_id < b->port_id; } +void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs) +{ + connections_.push_back(RTLIL::SigSig(lhs, rhs)); +} + void RTLIL::Module::fixup_ports() { std::vector all_ports; @@ -909,7 +914,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other) { RTLIL::Cell *cell = addCell(name, other->type); - cell->connections = other->connections; + cell->connections_ = other->connections_; cell->parameters = other->parameters; cell->attributes = other->attributes; return cell; @@ -923,8 +928,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->connections["\\A"] = sig_a; \ - cell->connections["\\Y"] = sig_y; \ + cell->connections_["\\A"] = sig_a; \ + cell->connections_["\\Y"] = sig_y; \ add(cell); \ return cell; \ } \ @@ -955,9 +960,9 @@ DEF_METHOD(LogicNot, 1, "$logic_not") cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\B_WIDTH"] = sig_b.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->connections["\\A"] = sig_a; \ - cell->connections["\\B"] = sig_b; \ - cell->connections["\\Y"] = sig_y; \ + cell->connections_["\\A"] = sig_a; \ + cell->connections_["\\B"] = sig_b; \ + cell->connections_["\\Y"] = sig_y; \ add(cell); \ return cell; \ } \ @@ -999,10 +1004,10 @@ DEF_METHOD(LogicOr, 1, "$logic_or") cell->parameters["\\WIDTH"] = sig_a.size(); \ cell->parameters["\\WIDTH"] = sig_b.size(); \ if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ - cell->connections["\\A"] = sig_a; \ - cell->connections["\\B"] = sig_b; \ - cell->connections["\\S"] = sig_s; \ - cell->connections["\\Y"] = sig_y; \ + cell->connections_["\\A"] = sig_a; \ + cell->connections_["\\B"] = sig_b; \ + cell->connections_["\\S"] = sig_s; \ + cell->connections_["\\Y"] = sig_y; \ add(cell); \ return cell; \ } \ @@ -1021,8 +1026,8 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections["\\" #_P1] = sig1; \ - cell->connections["\\" #_P2] = sig2; \ + cell->connections_["\\" #_P1] = sig1; \ + cell->connections_["\\" #_P2] = sig2; \ add(cell); \ return cell; \ } \ @@ -1036,9 +1041,9 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections["\\" #_P1] = sig1; \ - cell->connections["\\" #_P2] = sig2; \ - cell->connections["\\" #_P3] = sig3; \ + cell->connections_["\\" #_P1] = sig1; \ + cell->connections_["\\" #_P2] = sig2; \ + cell->connections_["\\" #_P3] = sig3; \ add(cell); \ return cell; \ } \ @@ -1052,10 +1057,10 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections["\\" #_P1] = sig1; \ - cell->connections["\\" #_P2] = sig2; \ - cell->connections["\\" #_P3] = sig3; \ - cell->connections["\\" #_P4] = sig4; \ + cell->connections_["\\" #_P1] = sig1; \ + cell->connections_["\\" #_P2] = sig2; \ + cell->connections_["\\" #_P3] = sig3; \ + cell->connections_["\\" #_P4] = sig4; \ add(cell); \ return cell; \ } \ @@ -1083,9 +1088,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\B_WIDTH"] = sig_b.size(); cell->parameters["\\Y_WIDTH"] = sig_y.size(); - cell->connections["\\A"] = sig_a; - cell->connections["\\B"] = sig_b; - cell->connections["\\Y"] = sig_y; + cell->connections_["\\A"] = sig_a; + cell->connections_["\\B"] = sig_b; + cell->connections_["\\Y"] = sig_y; add(cell); return cell; } @@ -1098,8 +1103,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig_y.size(); cell->parameters["\\OFFSET"] = offset; - cell->connections["\\A"] = sig_a; - cell->connections["\\Y"] = sig_y; + cell->connections_["\\A"] = sig_a; + cell->connections_["\\Y"] = sig_y; add(cell); return cell; } @@ -1111,9 +1116,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a cell->type = "$concat"; cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\B_WIDTH"] = sig_b.size(); - cell->connections["\\A"] = sig_a; - cell->connections["\\B"] = sig_b; - cell->connections["\\Y"] = sig_y; + cell->connections_["\\A"] = sig_a; + cell->connections_["\\B"] = sig_b; + cell->connections_["\\Y"] = sig_y; add(cell); return cell; } @@ -1125,8 +1130,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R cell->type = "$lut"; cell->parameters["\\LUT"] = lut; cell->parameters["\\WIDTH"] = sig_i.size(); - cell->connections["\\I"] = sig_i; - cell->connections["\\O"] = sig_o; + cell->connections_["\\I"] = sig_i; + cell->connections_["\\O"] = sig_o; add(cell); return cell; } @@ -1136,8 +1141,8 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = "$assert"; - cell->connections["\\A"] = sig_a; - cell->connections["\\EN"] = sig_en; + cell->connections_["\\A"] = sig_a; + cell->connections_["\\EN"] = sig_en; add(cell); return cell; } @@ -1150,9 +1155,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections["\\SET"] = sig_set; - cell->connections["\\CLR"] = sig_clr; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\SET"] = sig_set; + cell->connections_["\\CLR"] = sig_clr; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1164,9 +1169,9 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, cell->type = "$dff"; cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections["\\CLK"] = sig_clk; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\CLK"] = sig_clk; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1181,11 +1186,11 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections["\\CLK"] = sig_clk; - cell->connections["\\SET"] = sig_set; - cell->connections["\\CLR"] = sig_clr; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\CLK"] = sig_clk; + cell->connections_["\\SET"] = sig_set; + cell->connections_["\\CLR"] = sig_clr; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1200,10 +1205,10 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk cell->parameters["\\ARST_POLARITY"] = arst_polarity; cell->parameters["\\ARST_VALUE"] = arst_value; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections["\\CLK"] = sig_clk; - cell->connections["\\ARST"] = sig_arst; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\CLK"] = sig_clk; + cell->connections_["\\ARST"] = sig_arst; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1215,9 +1220,9 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e cell->type = "$dlatch"; cell->parameters["\\EN_POLARITY"] = en_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections["\\EN"] = sig_en; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\EN"] = sig_en; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1232,11 +1237,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections["\\EN"] = sig_en; - cell->connections["\\SET"] = sig_set; - cell->connections["\\CLR"] = sig_clr; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\EN"] = sig_en; + cell->connections_["\\SET"] = sig_set; + cell->connections_["\\CLR"] = sig_clr; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1246,9 +1251,9 @@ RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_ RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'); - cell->connections["\\C"] = sig_clk; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\C"] = sig_clk; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1259,11 +1264,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'); - cell->connections["\\C"] = sig_clk; - cell->connections["\\S"] = sig_set; - cell->connections["\\R"] = sig_clr; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\C"] = sig_clk; + cell->connections_["\\S"] = sig_set; + cell->connections_["\\R"] = sig_clr; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1274,10 +1279,10 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'); - cell->connections["\\C"] = sig_clk; - cell->connections["\\R"] = sig_arst; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\C"] = sig_clk; + cell->connections_["\\R"] = sig_arst; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1287,9 +1292,9 @@ RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec s RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'); - cell->connections["\\E"] = sig_en; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\E"] = sig_en; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } @@ -1300,11 +1305,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'); - cell->connections["\\E"] = sig_en; - cell->connections["\\S"] = sig_set; - cell->connections["\\R"] = sig_clr; - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; + cell->connections_["\\E"] = sig_en; + cell->connections_["\\S"] = sig_set; + cell->connections_["\\R"] = sig_clr; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; add(cell); return cell; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fbd6e719d..96bda7530 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -279,13 +279,16 @@ struct RTLIL::Module std::map memories; std::map cells; std::map processes; - std::vector connections; + std::vector connections_; RTLIL_ATTRIBUTE_MEMBERS + virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters); virtual size_t count_id(RTLIL::IdString id); virtual void check(); virtual void optimize(); + + void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); void fixup_ports(); template void rewrite_sigspecs(T functor); @@ -435,37 +438,50 @@ struct RTLIL::Module RTLIL::SigSpec MuxGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); }; -struct RTLIL::Wire { +struct RTLIL::Wire +{ +//protected: + // use module->addWire() and module->remove() to create or destroy wires + friend struct RTLIL::Module; + Wire(); + ~Wire() { }; + +public: + // do not simply copy wires + //Wire(RTLIL::Wire &other) = delete; + //void operator=(RTLIL::Wire &other) = delete; + RTLIL::IdString name; int width, start_offset, port_id; bool port_input, port_output; RTLIL_ATTRIBUTE_MEMBERS - Wire(); }; -struct RTLIL::Memory { +struct RTLIL::Memory +{ + Memory(); + RTLIL::IdString name; int width, start_offset, size; RTLIL_ATTRIBUTE_MEMBERS - Memory(); }; struct RTLIL::Cell { protected: - // Use module->addCell() and module->remove() to create or destroy modules. + // use module->addCell() and module->remove() to create or destroy cells friend struct RTLIL::Module; Cell() { }; ~Cell() { }; public: - // do not copy simply cells + // do not simply copy cells Cell(RTLIL::Cell &other) = delete; void operator=(RTLIL::Cell &other) = delete; RTLIL::IdString name; RTLIL::IdString type; - std::map connections; + std::map connections_; std::map parameters; RTLIL_ATTRIBUTE_MEMBERS void check(); @@ -686,7 +702,7 @@ void RTLIL::Module::rewrite_sigspecs(T functor) it.second->rewrite_sigspecs(functor); for (auto &it : processes) it.second->rewrite_sigspecs(functor); - for (auto &it : connections) { + for (auto &it : connections_) { functor(it.first); functor(it.second); } @@ -694,7 +710,7 @@ void RTLIL::Module::rewrite_sigspecs(T functor) template void RTLIL::Cell::rewrite_sigspecs(T functor) { - for (auto &it : connections) + for (auto &it : connections_) functor(it.second); } diff --git a/kernel/satgen.h b/kernel/satgen.h index ea04cb409..ec4480c36 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -182,9 +182,9 @@ struct SatGen if (model_undef && (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || is_arith_compare)) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); if (is_arith_compare) extendSignalWidth(undef_a, undef_b, cell, true); else @@ -195,7 +195,7 @@ struct SatGen int undef_y_bit = ez->OR(undef_any_a, undef_any_b); if (cell->type == "$div" || cell->type == "$mod") { - std::vector b = importSigSpec(cell->connections.at("\\B"), timestep); + std::vector b = importSigSpec(cell->connections_.at("\\B"), timestep); undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b))); } @@ -215,9 +215,9 @@ struct SatGen cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$sub") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -237,9 +237,9 @@ struct SatGen if (model_undef && !arith_undef_handled) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell, false); if (cell->type == "$and" || cell->type == "$_AND_") { @@ -265,7 +265,7 @@ struct SatGen } else if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -273,16 +273,16 @@ struct SatGen if (cell->type == "$_INV_" || cell->type == "$not") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_not(a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, true); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -292,20 +292,20 @@ struct SatGen if (cell->type == "$_MUX_" || cell->type == "$mux") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections.at("\\B"), timestep); - std::vector s = importDefSigSpec(cell->connections.at("\\S"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector s = importDefSigSpec(cell->connections_.at("\\S"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); - std::vector undef_s = importUndefSigSpec(cell->connections.at("\\S"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_s = importUndefSigSpec(cell->connections_.at("\\S"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); std::vector unequal_ab = ez->vec_not(ez->vec_iff(a, b)); std::vector undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b)); @@ -318,10 +318,10 @@ struct SatGen if (cell->type == "$pmux" || cell->type == "$safe_pmux") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections.at("\\B"), timestep); - std::vector s = importDefSigSpec(cell->connections.at("\\S"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector s = importDefSigSpec(cell->connections_.at("\\S"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -336,10 +336,10 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); - std::vector undef_s = importUndefSigSpec(cell->connections.at("\\S"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_s = importUndefSigSpec(cell->connections_.at("\\S"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); int maybe_one_hot = ez->FALSE; int maybe_many_hot = ez->FALSE; @@ -387,8 +387,8 @@ struct SatGen if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -402,8 +402,8 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0"); if (cell->type == "$pos" || cell->type == "$bu0") { @@ -422,8 +422,8 @@ struct SatGen if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -442,8 +442,8 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); int aX = ez->expression(ezSAT::OpOr, undef_a); if (cell->type == "$reduce_and") { @@ -469,12 +469,12 @@ struct SatGen if (cell->type == "$logic_and" || cell->type == "$logic_or") { - std::vector vec_a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector vec_b = importDefSigSpec(cell->connections.at("\\B"), timestep); + std::vector vec_a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector vec_b = importDefSigSpec(cell->connections_.at("\\B"), timestep); int a = ez->expression(ez->OpOr, vec_a); int b = ez->expression(ez->OpOr, vec_b); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -487,9 +487,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a))); int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b))); @@ -516,16 +516,16 @@ struct SatGen if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") { bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool(); - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidth(a, b, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); a = ez->vec_or(a, undef_a); b = ez->vec_or(b, undef_b); @@ -548,9 +548,9 @@ struct SatGen if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); if (cell->type == "$eqx") @@ -565,9 +565,9 @@ struct SatGen } else if (model_undef && (cell->type == "$eq" || cell->type == "$ne")) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); @@ -589,7 +589,7 @@ struct SatGen else { if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); undefGating(y, yy, undef_y); } log_assert(!model_undef || arith_undef_handled); @@ -599,9 +599,9 @@ struct SatGen if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); char shift_left = cell->type == "$shl" || cell->type == "$sshl"; bool sign_extend = cell->type == "$sshr" && cell->parameters["\\A_SIGNED"].as_bool(); @@ -627,9 +627,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); while (undef_y.size() < undef_a.size()) undef_y.push_back(ez->literal()); @@ -657,9 +657,9 @@ struct SatGen if (cell->type == "$mul") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -676,7 +676,7 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -684,9 +684,9 @@ struct SatGen if (cell->type == "$div" || cell->type == "$mod") { - std::vector a = importDefSigSpec(cell->connections.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); + std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -740,11 +740,11 @@ struct SatGen only_first_one.at(0) = ez->TRUE; div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones); } else { - div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").size(), ez->TRUE); + div_zero_result.insert(div_zero_result.end(), cell->connections_.at("\\A").size(), ez->TRUE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE); } } else { - int copy_a_bits = std::min(cell->connections.at("\\A").size(), cell->connections.at("\\B").size()); + int copy_a_bits = std::min(cell->connections_.at("\\A").size(), cell->connections_.at("\\B").size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); @@ -756,7 +756,7 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -764,17 +764,17 @@ struct SatGen if (cell->type == "$slice") { - RTLIL::SigSpec a = cell->connections.at("\\A"); - RTLIL::SigSpec y = cell->connections.at("\\Y"); + RTLIL::SigSpec a = cell->connections_.at("\\A"); + RTLIL::SigSpec y = cell->connections_.at("\\Y"); ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep)); return true; } if (cell->type == "$concat") { - RTLIL::SigSpec a = cell->connections.at("\\A"); - RTLIL::SigSpec b = cell->connections.at("\\B"); - RTLIL::SigSpec y = cell->connections.at("\\Y"); + RTLIL::SigSpec a = cell->connections_.at("\\A"); + RTLIL::SigSpec b = cell->connections_.at("\\B"); + RTLIL::SigSpec y = cell->connections_.at("\\Y"); RTLIL::SigSpec ab = a; ab.append(b); @@ -787,20 +787,20 @@ struct SatGen { if (timestep == 1) { - initial_state.add((*sigmap)(cell->connections.at("\\Q"))); + initial_state.add((*sigmap)(cell->connections_.at("\\Q"))); } else { - std::vector d = importDefSigSpec(cell->connections.at("\\D"), timestep-1); - std::vector q = importDefSigSpec(cell->connections.at("\\Q"), timestep); + std::vector d = importDefSigSpec(cell->connections_.at("\\D"), timestep-1); + std::vector q = importDefSigSpec(cell->connections_.at("\\Q"), timestep); std::vector qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector undef_d = importUndefSigSpec(cell->connections.at("\\D"), timestep-1); - std::vector undef_q = importUndefSigSpec(cell->connections.at("\\Q"), timestep); + std::vector undef_d = importUndefSigSpec(cell->connections_.at("\\D"), timestep-1); + std::vector undef_q = importUndefSigSpec(cell->connections_.at("\\Q"), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -812,8 +812,8 @@ struct SatGen if (cell->type == "$assert") { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - asserts_a[pf].append((*sigmap)(cell->connections.at("\\A"))); - asserts_en[pf].append((*sigmap)(cell->connections.at("\\EN"))); + asserts_a[pf].append((*sigmap)(cell->connections_.at("\\A"))); + asserts_en[pf].append((*sigmap)(cell->connections_.at("\\EN"))); return true; } diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 1a84194ee..ea95e06ee 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -269,7 +269,7 @@ struct SigMap void set(RTLIL::Module *module) { clear(); - for (auto &it : module->connections) + for (auto &it : module->connections_) add(it.first, it.second); } -- cgit v1.2.3 From e75e495c2bddb62634c6d50f90e09e0ff358faa5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 12:22:58 +0200 Subject: Added new RTLIL::Cell port access methods --- kernel/rtlil.cc | 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/rtlil.h | 8 ++++++++ 2 files changed, 71 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 4d0aadbb5..27063aeac 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1330,6 +1330,26 @@ RTLIL::Memory::Memory() size = 0; } +void RTLIL::Cell::unset(RTLIL::IdString portname) +{ + connections_.erase(portname); +} + +void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal) +{ + connections_[portname] = signal; +} + +RTLIL::SigSpec RTLIL::Cell::get(RTLIL::IdString portname) const +{ + return connections_.at(portname); +} + +const std::map &RTLIL::Cell::connections() +{ + return connections_; +} + void RTLIL::Cell::check() { #ifndef NDEBUG @@ -1338,6 +1358,49 @@ void RTLIL::Cell::check() #endif } +void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) +{ + if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || + type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:") + return; + + if (type == "$mux" || type == "$pmux" || type == "$safe_pmux") + { + parameters["\\WIDTH"] = SIZE(connections_["\\Y"]); + if (type == "$pmux" || type == "$safe_pmux") + parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]); + check(); + return; + } + + bool signedness_ab = type != "$slice" && type != "$concat"; + + if (connections_.count("\\A")) { + if (signedness_ab) { + if (set_a_signed) + parameters["\\A_SIGNED"] = true; + else if (parameters.count("\\A_SIGNED") == 0) + parameters["\\A_SIGNED"] = false; + } + parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]); + } + + if (connections_.count("\\B")) { + if (signedness_ab) { + if (set_b_signed) + parameters["\\B_SIGNED"] = true; + else if (parameters.count("\\B_SIGNED") == 0) + parameters["\\B_SIGNED"] = false; + } + parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]); + } + + if (connections_.count("\\Y")) + parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]); + + check(); +} + RTLIL::SigChunk::SigChunk() { wire = NULL; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 96bda7530..0b92405e8 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -484,7 +484,15 @@ public: std::map connections_; std::map parameters; RTLIL_ATTRIBUTE_MEMBERS + + // access cell ports + void unset(RTLIL::IdString portname); + void set(RTLIL::IdString portname, RTLIL::SigSpec signal); + RTLIL::SigSpec get(RTLIL::IdString portname) const; + const std::map &connections(); + void check(); + void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); template void rewrite_sigspecs(T functor); }; -- cgit v1.2.3 From 3719281ed44aa9d8b2ac11eb936b750c4642be38 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 13:59:30 +0200 Subject: Automatically pack SigSpec on copy/assign --- kernel/rtlil.cc | 77 ++++++++++++++++++++++++++++++++++++++++++++------------- kernel/rtlil.h | 3 +++ 2 files changed, 63 insertions(+), 17 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 27063aeac..2378e95c5 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1518,6 +1518,48 @@ RTLIL::SigSpec::SigSpec() hash_ = 0; } +RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other) +{ + *this = other; +} + +const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other) +{ + cover("kernel.rtlil.sigspec.assign"); + + width_ = other.width_; + hash_ = other.hash_; + chunks_ = other.chunks_; + bits_.clear(); + + if (!other.bits_.empty()) + { + RTLIL::SigChunk *last = NULL; + int last_end_offset = 0; + + for (auto &bit : other.bits_) { + if (last && bit.wire == last->wire) { + if (bit.wire == NULL) { + last->data.bits.push_back(bit.data); + last->width++; + continue; + } else if (last_end_offset == bit.offset) { + last_end_offset++; + last->width++; + continue; + } + } + chunks_.push_back(bit); + last = &chunks_.back(); + last_end_offset = bit.offset + 1; + } + + check(); + } + + return *this; +} + RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) { chunks_.push_back(RTLIL::SigChunk(value)); @@ -1626,24 +1668,25 @@ void RTLIL::SigSpec::pack() const std::vector old_bits; old_bits.swap(that->bits_); - RTLIL::SigChunk *last_const = NULL; - RTLIL::SigChunk *last_wire = NULL; - int last_wire_end = 0; - - for (auto &bit : old_bits) - if (bit.wire == NULL && last_const) { - last_const->data.bits.push_back(bit.data); - last_const->width++; - } else - if (bit.wire && last_wire && last_wire->wire == bit.wire && last_wire_end == bit.offset) { - last_wire->width++; - last_wire_end++; - } else { - that->chunks_.push_back(bit); - last_const = bit.wire ? NULL : &that->chunks_.back(); - last_wire = bit.wire ? &that->chunks_.back() : NULL; - last_wire_end = bit.offset + 1; + RTLIL::SigChunk *last = NULL; + int last_end_offset = 0; + + for (auto &bit : old_bits) { + if (last && bit.wire == last->wire) { + if (bit.wire == NULL) { + last->data.bits.push_back(bit.data); + last->width++; + continue; + } else if (last_end_offset == bit.offset) { + last_end_offset++; + last->width++; + continue; + } } + that->chunks_.push_back(bit); + last = &that->chunks_.back(); + last_end_offset = bit.offset + 1; + } check(); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0b92405e8..a2320873a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -567,6 +567,9 @@ private: public: SigSpec(); + SigSpec(const RTLIL::SigSpec &other); + const RTLIL::SigSpec &operator=(const RTLIL::SigSpec &other); + SigSpec(const RTLIL::Const &value); SigSpec(const RTLIL::SigChunk &chunk); SigSpec(RTLIL::Wire *wire); -- cgit v1.2.3 From b03aec6e3212a387e3d255583476d472d16663f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:31:47 +0200 Subject: Added RTLIL::Module::connect(const RTLIL::SigSig&) --- kernel/rtlil.cc | 5 +++++ kernel/rtlil.h | 1 + 2 files changed, 6 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2378e95c5..ce4ecea6f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -873,6 +873,11 @@ static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) return a->port_id < b->port_id; } +void RTLIL::Module::connect(const RTLIL::SigSig &conn) +{ + connections_.push_back(conn); +} + void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs) { connections_.push_back(RTLIL::SigSig(lhs, rhs)); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a2320873a..4f91b720d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -288,6 +288,7 @@ struct RTLIL::Module virtual void check(); virtual void optimize(); + void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); void fixup_ports(); -- cgit v1.2.3 From 7ac9dc7f6eab40b3853583848933c4a8a94df9c9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:38:33 +0200 Subject: Added RTLIL::Module::connections() --- kernel/rtlil.cc | 5 +++++ kernel/rtlil.h | 1 + 2 files changed, 6 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ce4ecea6f..1638682c1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -883,6 +883,11 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs connections_.push_back(RTLIL::SigSig(lhs, rhs)); } +const std::vector &RTLIL::Module::connections() +{ + return connections_; +} + void RTLIL::Module::fixup_ports() { std::vector all_ports; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4f91b720d..1775975d5 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -290,6 +290,7 @@ struct RTLIL::Module void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + const std::vector &connections(); void fixup_ports(); template void rewrite_sigspecs(T functor); -- cgit v1.2.3 From cd6574ecf652901573cbc6b89e1a59dd383ec496 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:27 +0200 Subject: Added some missing "const" in rtlil.h --- kernel/rtlil.cc | 10 +++++----- kernel/rtlil.h | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1638682c1..73f5d71f9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -883,7 +883,7 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs connections_.push_back(RTLIL::SigSig(lhs, rhs)); } -const std::vector &RTLIL::Module::connections() +const std::vector &RTLIL::Module::connections() const { return connections_; } @@ -1350,12 +1350,12 @@ void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal) connections_[portname] = signal; } -RTLIL::SigSpec RTLIL::Cell::get(RTLIL::IdString portname) const +const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const { return connections_.at(portname); } -const std::map &RTLIL::Cell::connections() +const std::map &RTLIL::Cell::connections() const { return connections_; } @@ -1839,7 +1839,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe check(); } -RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other) const +RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const { if (other) cover("kernel.rtlil.sigspec.extract_other"); @@ -1859,7 +1859,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *o RTLIL::SigSpec ret; if (other) { - std::vector bits_other = other ? other->to_sigbit_vector() : bits_match; + std::vector bits_other = other->to_sigbit_vector(); for (int i = 0; i < width_; i++) if (bits_match[i].wire && pat.count(bits_match[i])) ret.append_bit(bits_other[i]); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1775975d5..25d0a8309 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -290,7 +290,7 @@ struct RTLIL::Module void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); - const std::vector &connections(); + const std::vector &connections() const; void fixup_ports(); template void rewrite_sigspecs(T functor); @@ -490,8 +490,8 @@ public: // access cell ports void unset(RTLIL::IdString portname); void set(RTLIL::IdString portname, RTLIL::SigSpec signal); - RTLIL::SigSpec get(RTLIL::IdString portname) const; - const std::map &connections(); + const RTLIL::SigSpec &get(RTLIL::IdString portname) const; + const std::map &connections() const; void check(); void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); @@ -608,7 +608,7 @@ public: void remove(int offset, int length = 1); void remove_const(); - RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const; + RTLIL::SigSpec extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(int offset, int length = 1) const; void append(const RTLIL::SigSpec &signal); -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- kernel/consteval.h | 18 +++--- kernel/modwalker.h | 4 +- kernel/rtlil.cc | 164 +++++++++++++++++++++++++-------------------------- kernel/satgen.h | 170 ++++++++++++++++++++++++++--------------------------- kernel/sigtools.h | 2 +- 5 files changed, 179 insertions(+), 179 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 5469fa80f..4050d2dcf 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -43,7 +43,7 @@ struct ConstEval for (auto &it : module->cells) { if (!ct.cell_known(it.second->type)) continue; - for (auto &it2 : it.second->connections_) + for (auto &it2 : it.second->connections()) if (ct.cell_output(it.second->type, it2.first)) sig2driver.insert(assign_map(it2.second), it.second); } @@ -87,22 +87,22 @@ struct ConstEval { RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - assert(cell->connections_.count("\\Y") > 0); - sig_y = values_map(assign_map(cell->connections_["\\Y"])); + assert(cell->connections().count("\\Y") > 0); + sig_y = values_map(assign_map(cell->get("\\Y"))); if (sig_y.is_fully_const()) return true; - if (cell->connections_.count("\\S") > 0) { - sig_s = cell->connections_["\\S"]; + if (cell->connections().count("\\S") > 0) { + sig_s = cell->get("\\S"); if (!eval(sig_s, undef, cell)) return false; } - if (cell->connections_.count("\\A") > 0) - sig_a = cell->connections_["\\A"]; + if (cell->connections().count("\\A") > 0) + sig_a = cell->get("\\A"); - if (cell->connections_.count("\\B") > 0) - sig_b = cell->connections_["\\B"]; + if (cell->connections().count("\\B") > 0) + sig_b = cell->get("\\B"); if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_") { diff --git a/kernel/modwalker.h b/kernel/modwalker.h index efd97379c..a3983a2c1 100644 --- a/kernel/modwalker.h +++ b/kernel/modwalker.h @@ -88,12 +88,12 @@ struct ModWalker void add_cell(RTLIL::Cell *cell) { if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) add_cell_port(cell, conn.first, sigmap(conn.second), ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first)); } else { - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) add_cell_port(cell, conn.first, sigmap(conn.second), true, true); } } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 73f5d71f9..9781fa32b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -348,9 +348,9 @@ namespace { void port(const char *name, int width) { - if (cell->connections_.count(name) == 0) + if (cell->connections().count(name) == 0) error(__LINE__); - if (cell->connections_.at(name).size() != width) + if (cell->connections().at(name).size() != width) error(__LINE__); expected_ports.insert(name); } @@ -360,7 +360,7 @@ namespace { for (auto ¶ : cell->parameters) if (expected_params.count(para.first) == 0) error(__LINE__); - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) if (expected_ports.count(conn.first) == 0) error(__LINE__); @@ -379,13 +379,13 @@ namespace { for (const char *p = ports; *p; p++) { char portname[3] = { '\\', *p, 0 }; - if (cell->connections_.count(portname) == 0) + if (cell->connections().count(portname) == 0) error(__LINE__); - if (cell->connections_.at(portname).size() != 1) + if (cell->connections().at(portname).size() != 1) error(__LINE__); } - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { if (conn.first.size() != 2 || conn.first.at(0) != '\\') error(__LINE__); if (strchr(ports, conn.first.at(1)) == NULL) @@ -734,7 +734,7 @@ void RTLIL::Module::check() assert(it.first == it.second->name); assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$')); - for (auto &it2 : it.second->connections_) { + for (auto &it2 : it.second->connections()) { assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); it2.second.check(); } @@ -773,7 +773,7 @@ void RTLIL::Module::optimize() void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const { new_mod->name = name; - new_mod->connections_ = connections_; + new_mod->connections() = connections_; new_mod->attributes = attributes; for (auto &it : wires) @@ -924,7 +924,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other) { RTLIL::Cell *cell = addCell(name, other->type); - cell->connections_ = other->connections_; + cell->connections() = other->connections(); cell->parameters = other->parameters; cell->attributes = other->attributes; return cell; @@ -938,8 +938,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->connections_["\\A"] = sig_a; \ - cell->connections_["\\Y"] = sig_y; \ + cell->set("\\A", sig_a); \ + cell->set("\\Y", sig_y); \ add(cell); \ return cell; \ } \ @@ -970,9 +970,9 @@ DEF_METHOD(LogicNot, 1, "$logic_not") cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\B_WIDTH"] = sig_b.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->connections_["\\A"] = sig_a; \ - cell->connections_["\\B"] = sig_b; \ - cell->connections_["\\Y"] = sig_y; \ + cell->set("\\A", sig_a); \ + cell->set("\\B", sig_b); \ + cell->set("\\Y", sig_y); \ add(cell); \ return cell; \ } \ @@ -1014,10 +1014,10 @@ DEF_METHOD(LogicOr, 1, "$logic_or") cell->parameters["\\WIDTH"] = sig_a.size(); \ cell->parameters["\\WIDTH"] = sig_b.size(); \ if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ - cell->connections_["\\A"] = sig_a; \ - cell->connections_["\\B"] = sig_b; \ - cell->connections_["\\S"] = sig_s; \ - cell->connections_["\\Y"] = sig_y; \ + cell->set("\\A", sig_a); \ + cell->set("\\B", sig_b); \ + cell->set("\\S", sig_s); \ + cell->set("\\Y", sig_y); \ add(cell); \ return cell; \ } \ @@ -1036,8 +1036,8 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections_["\\" #_P1] = sig1; \ - cell->connections_["\\" #_P2] = sig2; \ + cell->connections()["\\" #_P1] = sig1; \ + cell->connections()["\\" #_P2] = sig2; \ add(cell); \ return cell; \ } \ @@ -1051,9 +1051,9 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections_["\\" #_P1] = sig1; \ - cell->connections_["\\" #_P2] = sig2; \ - cell->connections_["\\" #_P3] = sig3; \ + cell->connections()["\\" #_P1] = sig1; \ + cell->connections()["\\" #_P2] = sig2; \ + cell->connections()["\\" #_P3] = sig3; \ add(cell); \ return cell; \ } \ @@ -1067,10 +1067,10 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections_["\\" #_P1] = sig1; \ - cell->connections_["\\" #_P2] = sig2; \ - cell->connections_["\\" #_P3] = sig3; \ - cell->connections_["\\" #_P4] = sig4; \ + cell->connections()["\\" #_P1] = sig1; \ + cell->connections()["\\" #_P2] = sig2; \ + cell->connections()["\\" #_P3] = sig3; \ + cell->connections()["\\" #_P4] = sig4; \ add(cell); \ return cell; \ } \ @@ -1098,9 +1098,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\B_WIDTH"] = sig_b.size(); cell->parameters["\\Y_WIDTH"] = sig_y.size(); - cell->connections_["\\A"] = sig_a; - cell->connections_["\\B"] = sig_b; - cell->connections_["\\Y"] = sig_y; + cell->set("\\A", sig_a); + cell->set("\\B", sig_b); + cell->set("\\Y", sig_y); add(cell); return cell; } @@ -1113,8 +1113,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig_y.size(); cell->parameters["\\OFFSET"] = offset; - cell->connections_["\\A"] = sig_a; - cell->connections_["\\Y"] = sig_y; + cell->set("\\A", sig_a); + cell->set("\\Y", sig_y); add(cell); return cell; } @@ -1126,9 +1126,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a cell->type = "$concat"; cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\B_WIDTH"] = sig_b.size(); - cell->connections_["\\A"] = sig_a; - cell->connections_["\\B"] = sig_b; - cell->connections_["\\Y"] = sig_y; + cell->set("\\A", sig_a); + cell->set("\\B", sig_b); + cell->set("\\Y", sig_y); add(cell); return cell; } @@ -1140,8 +1140,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R cell->type = "$lut"; cell->parameters["\\LUT"] = lut; cell->parameters["\\WIDTH"] = sig_i.size(); - cell->connections_["\\I"] = sig_i; - cell->connections_["\\O"] = sig_o; + cell->set("\\I", sig_i); + cell->set("\\O", sig_o); add(cell); return cell; } @@ -1151,8 +1151,8 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = "$assert"; - cell->connections_["\\A"] = sig_a; - cell->connections_["\\EN"] = sig_en; + cell->set("\\A", sig_a); + cell->set("\\EN", sig_en); add(cell); return cell; } @@ -1165,9 +1165,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections_["\\SET"] = sig_set; - cell->connections_["\\CLR"] = sig_clr; - cell->connections_["\\Q"] = sig_q; + cell->set("\\SET", sig_set); + cell->set("\\CLR", sig_clr); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1179,9 +1179,9 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, cell->type = "$dff"; cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections_["\\CLK"] = sig_clk; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\CLK", sig_clk); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1196,11 +1196,11 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections_["\\CLK"] = sig_clk; - cell->connections_["\\SET"] = sig_set; - cell->connections_["\\CLR"] = sig_clr; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\CLK", sig_clk); + cell->set("\\SET", sig_set); + cell->set("\\CLR", sig_clr); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1215,10 +1215,10 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk cell->parameters["\\ARST_POLARITY"] = arst_polarity; cell->parameters["\\ARST_VALUE"] = arst_value; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections_["\\CLK"] = sig_clk; - cell->connections_["\\ARST"] = sig_arst; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\CLK", sig_clk); + cell->set("\\ARST", sig_arst); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1230,9 +1230,9 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e cell->type = "$dlatch"; cell->parameters["\\EN_POLARITY"] = en_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections_["\\EN"] = sig_en; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\EN", sig_en); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1247,11 +1247,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->connections_["\\EN"] = sig_en; - cell->connections_["\\SET"] = sig_set; - cell->connections_["\\CLR"] = sig_clr; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\EN", sig_en); + cell->set("\\SET", sig_set); + cell->set("\\CLR", sig_clr); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1261,9 +1261,9 @@ RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_ RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'); - cell->connections_["\\C"] = sig_clk; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\C", sig_clk); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1274,11 +1274,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'); - cell->connections_["\\C"] = sig_clk; - cell->connections_["\\S"] = sig_set; - cell->connections_["\\R"] = sig_clr; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\C", sig_clk); + cell->set("\\S", sig_set); + cell->set("\\R", sig_clr); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1289,10 +1289,10 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'); - cell->connections_["\\C"] = sig_clk; - cell->connections_["\\R"] = sig_arst; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\C", sig_clk); + cell->set("\\R", sig_arst); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1302,9 +1302,9 @@ RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec s RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'); - cell->connections_["\\E"] = sig_en; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\E", sig_en); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } @@ -1315,11 +1315,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec RTLIL::Cell *cell = new RTLIL::Cell; cell->name = name; cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'); - cell->connections_["\\E"] = sig_en; - cell->connections_["\\S"] = sig_set; - cell->connections_["\\R"] = sig_clr; - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; + cell->set("\\E", sig_en); + cell->set("\\S", sig_set); + cell->set("\\R", sig_clr); + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); add(cell); return cell; } diff --git a/kernel/satgen.h b/kernel/satgen.h index ec4480c36..6a288a8da 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -182,9 +182,9 @@ struct SatGen if (model_undef && (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || is_arith_compare)) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); if (is_arith_compare) extendSignalWidth(undef_a, undef_b, cell, true); else @@ -195,7 +195,7 @@ struct SatGen int undef_y_bit = ez->OR(undef_any_a, undef_any_b); if (cell->type == "$div" || cell->type == "$mod") { - std::vector b = importSigSpec(cell->connections_.at("\\B"), timestep); + std::vector b = importSigSpec(cell->get("\\B"), timestep); undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b))); } @@ -215,9 +215,9 @@ struct SatGen cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$sub") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector b = importDefSigSpec(cell->get("\\B"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -237,9 +237,9 @@ struct SatGen if (model_undef && !arith_undef_handled) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell, false); if (cell->type == "$and" || cell->type == "$_AND_") { @@ -265,7 +265,7 @@ struct SatGen } else if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -273,16 +273,16 @@ struct SatGen if (cell->type == "$_INV_" || cell->type == "$not") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_not(a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, true); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -292,20 +292,20 @@ struct SatGen if (cell->type == "$_MUX_" || cell->type == "$mux") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector s = importDefSigSpec(cell->connections_.at("\\S"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector b = importDefSigSpec(cell->get("\\B"), timestep); + std::vector s = importDefSigSpec(cell->get("\\S"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector undef_s = importUndefSigSpec(cell->connections_.at("\\S"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_s = importUndefSigSpec(cell->get("\\S"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); std::vector unequal_ab = ez->vec_not(ez->vec_iff(a, b)); std::vector undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b)); @@ -318,10 +318,10 @@ struct SatGen if (cell->type == "$pmux" || cell->type == "$safe_pmux") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector s = importDefSigSpec(cell->connections_.at("\\S"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector b = importDefSigSpec(cell->get("\\B"), timestep); + std::vector s = importDefSigSpec(cell->get("\\S"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -336,10 +336,10 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector undef_s = importUndefSigSpec(cell->connections_.at("\\S"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_s = importUndefSigSpec(cell->get("\\S"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); int maybe_one_hot = ez->FALSE; int maybe_many_hot = ez->FALSE; @@ -387,8 +387,8 @@ struct SatGen if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -402,8 +402,8 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0"); if (cell->type == "$pos" || cell->type == "$bu0") { @@ -422,8 +422,8 @@ struct SatGen if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -442,8 +442,8 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); int aX = ez->expression(ezSAT::OpOr, undef_a); if (cell->type == "$reduce_and") { @@ -469,12 +469,12 @@ struct SatGen if (cell->type == "$logic_and" || cell->type == "$logic_or") { - std::vector vec_a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector vec_b = importDefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector vec_a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector vec_b = importDefSigSpec(cell->get("\\B"), timestep); int a = ez->expression(ez->OpOr, vec_a); int b = ez->expression(ez->OpOr, vec_b); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -487,9 +487,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a))); int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b))); @@ -516,16 +516,16 @@ struct SatGen if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") { bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool(); - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector b = importDefSigSpec(cell->get("\\B"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); extendSignalWidth(a, b, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); a = ez->vec_or(a, undef_a); b = ez->vec_or(b, undef_b); @@ -548,9 +548,9 @@ struct SatGen if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); if (cell->type == "$eqx") @@ -565,9 +565,9 @@ struct SatGen } else if (model_undef && (cell->type == "$eq" || cell->type == "$ne")) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); @@ -589,7 +589,7 @@ struct SatGen else { if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); undefGating(y, yy, undef_y); } log_assert(!model_undef || arith_undef_handled); @@ -599,9 +599,9 @@ struct SatGen if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector b = importDefSigSpec(cell->get("\\B"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); char shift_left = cell->type == "$shl" || cell->type == "$sshl"; bool sign_extend = cell->type == "$sshr" && cell->parameters["\\A_SIGNED"].as_bool(); @@ -627,9 +627,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); while (undef_y.size() < undef_a.size()) undef_y.push_back(ez->literal()); @@ -657,9 +657,9 @@ struct SatGen if (cell->type == "$mul") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector b = importDefSigSpec(cell->get("\\B"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -676,7 +676,7 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -684,9 +684,9 @@ struct SatGen if (cell->type == "$div" || cell->type == "$mod") { - std::vector a = importDefSigSpec(cell->connections_.at("\\A"), timestep); - std::vector b = importDefSigSpec(cell->connections_.at("\\B"), timestep); - std::vector y = importDefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->get("\\A"), timestep); + std::vector b = importDefSigSpec(cell->get("\\B"), timestep); + std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -740,11 +740,11 @@ struct SatGen only_first_one.at(0) = ez->TRUE; div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones); } else { - div_zero_result.insert(div_zero_result.end(), cell->connections_.at("\\A").size(), ez->TRUE); + div_zero_result.insert(div_zero_result.end(), cell->get("\\A").size(), ez->TRUE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE); } } else { - int copy_a_bits = std::min(cell->connections_.at("\\A").size(), cell->connections_.at("\\B").size()); + int copy_a_bits = std::min(cell->get("\\A").size(), cell->get("\\B").size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); @@ -756,7 +756,7 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -764,17 +764,17 @@ struct SatGen if (cell->type == "$slice") { - RTLIL::SigSpec a = cell->connections_.at("\\A"); - RTLIL::SigSpec y = cell->connections_.at("\\Y"); + RTLIL::SigSpec a = cell->get("\\A"); + RTLIL::SigSpec y = cell->get("\\Y"); ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep)); return true; } if (cell->type == "$concat") { - RTLIL::SigSpec a = cell->connections_.at("\\A"); - RTLIL::SigSpec b = cell->connections_.at("\\B"); - RTLIL::SigSpec y = cell->connections_.at("\\Y"); + RTLIL::SigSpec a = cell->get("\\A"); + RTLIL::SigSpec b = cell->get("\\B"); + RTLIL::SigSpec y = cell->get("\\Y"); RTLIL::SigSpec ab = a; ab.append(b); @@ -787,20 +787,20 @@ struct SatGen { if (timestep == 1) { - initial_state.add((*sigmap)(cell->connections_.at("\\Q"))); + initial_state.add((*sigmap)(cell->get("\\Q"))); } else { - std::vector d = importDefSigSpec(cell->connections_.at("\\D"), timestep-1); - std::vector q = importDefSigSpec(cell->connections_.at("\\Q"), timestep); + std::vector d = importDefSigSpec(cell->get("\\D"), timestep-1); + std::vector q = importDefSigSpec(cell->get("\\Q"), timestep); std::vector qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector undef_d = importUndefSigSpec(cell->connections_.at("\\D"), timestep-1); - std::vector undef_q = importUndefSigSpec(cell->connections_.at("\\Q"), timestep); + std::vector undef_d = importUndefSigSpec(cell->get("\\D"), timestep-1); + std::vector undef_q = importUndefSigSpec(cell->get("\\Q"), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -812,8 +812,8 @@ struct SatGen if (cell->type == "$assert") { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - asserts_a[pf].append((*sigmap)(cell->connections_.at("\\A"))); - asserts_en[pf].append((*sigmap)(cell->connections_.at("\\EN"))); + asserts_a[pf].append((*sigmap)(cell->get("\\A"))); + asserts_en[pf].append((*sigmap)(cell->get("\\EN"))); return true; } diff --git a/kernel/sigtools.h b/kernel/sigtools.h index ea95e06ee..7035db73d 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -269,7 +269,7 @@ struct SigMap void set(RTLIL::Module *module) { clear(); - for (auto &it : module->connections_) + for (auto &it : module->connections()) add(it.first, it.second); } -- cgit v1.2.3 From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:57 +0200 Subject: Manual fixes for new cell connections API --- kernel/rtlil.cc | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9781fa32b..ceb2b0f52 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -773,7 +773,7 @@ void RTLIL::Module::optimize() void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const { new_mod->name = name; - new_mod->connections() = connections_; + new_mod->connections_ = connections_; new_mod->attributes = attributes; for (auto &it : wires) @@ -924,7 +924,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other) { RTLIL::Cell *cell = addCell(name, other->type); - cell->connections() = other->connections(); + cell->connections_ = other->connections_; cell->parameters = other->parameters; cell->attributes = other->attributes; return cell; @@ -1036,8 +1036,8 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections()["\\" #_P1] = sig1; \ - cell->connections()["\\" #_P2] = sig2; \ + cell->set("\\" #_P1, sig1); \ + cell->set("\\" #_P2, sig2); \ add(cell); \ return cell; \ } \ @@ -1051,9 +1051,9 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections()["\\" #_P1] = sig1; \ - cell->connections()["\\" #_P2] = sig2; \ - cell->connections()["\\" #_P3] = sig3; \ + cell->set("\\" #_P1, sig1); \ + cell->set("\\" #_P2, sig2); \ + cell->set("\\" #_P3, sig3); \ add(cell); \ return cell; \ } \ @@ -1067,10 +1067,10 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) RTLIL::Cell *cell = new RTLIL::Cell; \ cell->name = name; \ cell->type = _type; \ - cell->connections()["\\" #_P1] = sig1; \ - cell->connections()["\\" #_P2] = sig2; \ - cell->connections()["\\" #_P3] = sig3; \ - cell->connections()["\\" #_P4] = sig4; \ + cell->set("\\" #_P1, sig1); \ + cell->set("\\" #_P2, sig2); \ + cell->set("\\" #_P3, sig3); \ + cell->set("\\" #_P4, sig4); \ add(cell); \ return cell; \ } \ -- cgit v1.2.3 From 97a59851a6c411ccb06162d4b31725bf89262378 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 16:11:28 +0200 Subject: Added RTLIL::Cell::has(portname) --- kernel/consteval.h | 8 ++++---- kernel/rtlil.cc | 13 +++++++++---- kernel/rtlil.h | 1 + 3 files changed, 14 insertions(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 4050d2dcf..3a5c5347c 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -87,21 +87,21 @@ struct ConstEval { RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - assert(cell->connections().count("\\Y") > 0); + assert(cell->has("\\Y")); sig_y = values_map(assign_map(cell->get("\\Y"))); if (sig_y.is_fully_const()) return true; - if (cell->connections().count("\\S") > 0) { + if (cell->has("\\S")) { sig_s = cell->get("\\S"); if (!eval(sig_s, undef, cell)) return false; } - if (cell->connections().count("\\A") > 0) + if (cell->has("\\A")) sig_a = cell->get("\\A"); - if (cell->connections().count("\\B") > 0) + if (cell->has("\\B")) sig_b = cell->get("\\B"); if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_") diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ceb2b0f52..059357d21 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -348,9 +348,9 @@ namespace { void port(const char *name, int width) { - if (cell->connections().count(name) == 0) + if (!cell->has(name)) error(__LINE__); - if (cell->connections().at(name).size() != width) + if (cell->get(name).size() != width) error(__LINE__); expected_ports.insert(name); } @@ -379,9 +379,9 @@ namespace { for (const char *p = ports; *p; p++) { char portname[3] = { '\\', *p, 0 }; - if (cell->connections().count(portname) == 0) + if (!cell->has(portname)) error(__LINE__); - if (cell->connections().at(portname).size() != 1) + if (cell->get(portname).size() != 1) error(__LINE__); } @@ -1340,6 +1340,11 @@ RTLIL::Memory::Memory() size = 0; } +bool RTLIL::Cell::has(RTLIL::IdString portname) +{ + return connections_.count(portname) != 0; +} + void RTLIL::Cell::unset(RTLIL::IdString portname) { connections_.erase(portname); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 25d0a8309..73d3727ce 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -488,6 +488,7 @@ public: RTLIL_ATTRIBUTE_MEMBERS // access cell ports + bool has(RTLIL::IdString portname); void unset(RTLIL::IdString portname); void set(RTLIL::IdString portname, RTLIL::SigSpec signal); const RTLIL::SigSpec &get(RTLIL::IdString portname) const; -- cgit v1.2.3 From 267c61564047f8768c29040f898633d9444a5404 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 17:21:40 +0200 Subject: Added support for here documents --- kernel/driver.cc | 44 ++++++++++++++++++++++++++++---------------- kernel/register.cc | 31 ++++++++++++++++++++++++++++++- kernel/register.h | 6 +++++- 3 files changed, 63 insertions(+), 18 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 3c185e44b..97910aa98 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -28,6 +28,7 @@ #include #include +#include #include "kernel/rtlil.h" #include "kernel/register.h" @@ -116,26 +117,37 @@ static void run_frontend(std::string filename, std::string command, RTLIL::Desig if (f == NULL) log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); - std::string command; - while (fgetline(f, command)) { - while (!command.empty() && command[command.size()-1] == '\\') { - std::string next_line; - if (!fgetline(f, next_line)) - break; - command.resize(command.size()-1); - command += next_line; + FILE *backup_script_file = Frontend::current_script_file; + Frontend::current_script_file = f; + + try { + std::string command; + while (fgetline(f, command)) { + while (!command.empty() && command[command.size()-1] == '\\') { + std::string next_line; + if (!fgetline(f, next_line)) + break; + command.resize(command.size()-1); + command += next_line; + } + handle_label(command, from_to_active, run_from, run_to); + if (from_to_active) + Pass::call(design, command); } - handle_label(command, from_to_active, run_from, run_to); - if (from_to_active) - Pass::call(design, command); - } - if (!command.empty()) { - handle_label(command, from_to_active, run_from, run_to); - if (from_to_active) - Pass::call(design, command); + if (!command.empty()) { + handle_label(command, from_to_active, run_from, run_to); + if (from_to_active) + Pass::call(design, command); + } + } + catch (...) { + Frontend::current_script_file = backup_script_file; + std::rethrow_exception(std::current_exception()); } + Frontend::current_script_file = backup_script_file; + if (filename != "-") fclose(f); diff --git a/kernel/register.cc b/kernel/register.cc index e7ad7ef05..59667ac97 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -276,6 +276,9 @@ void Frontend::execute(std::vector args, RTLIL::Design *design) } while (!args.empty()); } +FILE *Frontend::current_script_file = NULL; +std::string Frontend::last_here_document; + void Frontend::extra_args(FILE *&f, std::string &filename, std::vector args, size_t argidx) { bool called_with_fp = f != NULL; @@ -291,7 +294,33 @@ void Frontend::extra_args(FILE *&f, std::string &filename, std::vector 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r')) + break; + } + int indent = buffer.find_first_not_of(" \t\r\n"); + if (buffer.substr(indent, eot_marker.size()) == eot_marker) + break; + last_here_document += buffer; + } + f = fmemopen((void*)last_here_document.c_str(), last_here_document.size(), "r"); + } else + f = fopen(filename.c_str(), "r"); if (f == NULL) log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); diff --git a/kernel/register.h b/kernel/register.h index fd073cbe7..73875e968 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -38,7 +38,7 @@ extern const char *yosys_version_str; extern RTLIL::Design *yosys_get_design(); extern std::string proc_self_dirname(); extern std::string proc_share_dirname(); -const char *create_prompt(RTLIL::Design *design, int recursion_counter); +extern const char *create_prompt(RTLIL::Design *design, int recursion_counter); // from passes/cmds/design.cc extern std::map saved_designs; @@ -76,6 +76,10 @@ struct Pass struct Frontend : Pass { + // for reading of here documents + static FILE *current_script_file; + static std::string last_here_document; + std::string frontend_name; Frontend(std::string name, std::string short_help = "** document me **"); virtual void run_register(); -- cgit v1.2.3 From 946ddff9cef3ea0b4dad8664319fb13074133775 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 20:12:50 +0200 Subject: Changed a lot of code to the new RTLIL::Wire constructors --- kernel/rtlil.cc | 40 ++++++++++++++++++++++++++++++++++++++++ kernel/rtlil.h | 3 +++ 2 files changed, 43 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 059357d21..930e8a719 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -827,6 +827,46 @@ void RTLIL::Module::add(RTLIL::Cell *cell) cells[cell->name] = cell; } +namespace { + struct DeleteWireWorker + { + RTLIL::Module *module; + const std::set *wires_p; + + void operator()(RTLIL::SigSpec &sig) { + std::vector chunks = sig; + for (auto &c : chunks) + if (c.wire != NULL && wires_p->count(c.wire)) { + c.wire = module->addWire(NEW_ID, c.width); + c.offset = 0; + } + sig = chunks; + } + }; +} + +#if 0 +void RTLIL::Module::remove(RTLIL::Wire *wire) +{ + std::set wires; + wires.insert(wire); + remove(wires); +} +#endif + +void RTLIL::Module::remove(const std::set &wires) +{ + DeleteWireWorker delete_wire_worker; + delete_wire_worker.module = this; + delete_wire_worker.wires_p = &wires; + rewrite_sigspecs(delete_wire_worker); + + for (auto &it : wires) { + this->wires.erase(it->name); + delete it; + } +} + void RTLIL::Module::remove(RTLIL::Cell *cell) { assert(cells.count(cell->name) != 0); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 73d3727ce..f43e7b670 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -299,6 +299,9 @@ struct RTLIL::Module void add(RTLIL::Wire *wire); void add(RTLIL::Cell *cell); + + // Removing wires is expensive. If you have to remove wires, remove them all at once. + void remove(const std::set &wires); void remove(RTLIL::Cell *cell); void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); -- cgit v1.2.3 From d68c993ed2ea384db4d6af5161b3b36096828499 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 21:16:05 +0200 Subject: Changed more code to the new RTLIL::Wire constructors --- kernel/rtlil.cc | 14 +++++++++++++- kernel/rtlil.h | 16 ++++++++++------ 2 files changed, 23 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 930e8a719..240bbc6be 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -777,7 +777,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const new_mod->attributes = attributes; for (auto &it : wires) - new_mod->wires[it.first] = new RTLIL::Wire(*it.second); + new_mod->addWire(it.first, it.second); for (auto &it : memories) new_mod->memories[it.first] = new RTLIL::Memory(*it.second); @@ -952,6 +952,18 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width) return wire; } +RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other) +{ + RTLIL::Wire *wire = addWire(name); + wire->width = other->width; + wire->start_offset = other->start_offset; + wire->port_id = other->port_id; + wire->port_input = other->port_input; + wire->port_output = other->port_output; + wire->attributes = other->attributes; + return wire; +} + RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) { RTLIL::Cell *cell = new RTLIL::Cell; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f43e7b670..cbb612473 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -273,6 +273,11 @@ struct RTLIL::Design { struct RTLIL::Module { +protected: + void add(RTLIL::Wire *wire); + void add(RTLIL::Cell *cell); + +public: RTLIL::IdString name; std::set avail_parameters; std::map wires; @@ -297,9 +302,6 @@ struct RTLIL::Module void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; - void add(RTLIL::Wire *wire); - void add(RTLIL::Cell *cell); - // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const std::set &wires); void remove(RTLIL::Cell *cell); @@ -309,6 +311,8 @@ struct RTLIL::Module void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); @@ -445,7 +449,7 @@ struct RTLIL::Module struct RTLIL::Wire { -//protected: +protected: // use module->addWire() and module->remove() to create or destroy wires friend struct RTLIL::Module; Wire(); @@ -453,8 +457,8 @@ struct RTLIL::Wire public: // do not simply copy wires - //Wire(RTLIL::Wire &other) = delete; - //void operator=(RTLIL::Wire &other) = delete; + Wire(RTLIL::Wire &other) = delete; + void operator=(RTLIL::Wire &other) = delete; RTLIL::IdString name; int width, start_offset, port_id; -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- kernel/celltypes.h | 8 ++++---- kernel/driver.cc | 2 +- kernel/modwalker.h | 2 +- kernel/rtlil.cc | 40 ++++++++++++++++++++-------------------- kernel/rtlil.h | 2 +- 5 files changed, 27 insertions(+), 27 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 769145838..d3c848f46 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -181,8 +181,8 @@ struct CellTypes if (cell_types.count(type) == 0) { for (auto design : designs) if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires.count(port)) - return design->modules.at(type)->wires.at(port)->port_output; + if (design->modules.at(type)->wires_.count(port)) + return design->modules.at(type)->wires_.at(port)->port_output; return false; } return false; @@ -204,8 +204,8 @@ struct CellTypes if (cell_types.count(type) == 0) { for (auto design : designs) if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires.count(port)) - return design->modules.at(type)->wires.at(port)->port_input; + if (design->modules.at(type)->wires_.count(port)) + return design->modules.at(type)->wires_.at(port)->port_input; return false; } return false; diff --git a/kernel/driver.cc b/kernel/driver.cc index 97910aa98..3fbb96580 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -243,7 +243,7 @@ static char *readline_obj_generator(const char *text, int state) { RTLIL::Module *module = design->modules.at(design->selected_active_module); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); diff --git a/kernel/modwalker.h b/kernel/modwalker.h index a3983a2c1..a90d739eb 100644 --- a/kernel/modwalker.h +++ b/kernel/modwalker.h @@ -121,7 +121,7 @@ struct ModWalker signal_inputs.clear(); signal_outputs.clear(); - for (auto &it : module->wires) + for (auto &it : module->wires_) add_wire(it.second); for (auto &it : module->cells) if (filter_ct == NULL || filter_ct->cell_known(it.second->type)) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 240bbc6be..0cfcf018c 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -203,7 +203,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) for (auto &it : selected_members) if (it.second.size() == 0) del_list.push_back(it.first); - else if (it.second.size() == design->modules[it.first]->wires.size() + design->modules[it.first]->memories.size() + + else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() + design->modules[it.first]->cells.size() + design->modules[it.first]->processes.size()) add_list.push_back(it.first); for (auto mod_name : del_list) @@ -276,7 +276,7 @@ bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString me RTLIL::Module::~Module() { - for (auto it = wires.begin(); it != wires.end(); it++) + for (auto it = wires_.begin(); it != wires_.end(); it++) delete it->second; for (auto it = memories.begin(); it != memories.end(); it++) delete it->second; @@ -293,7 +293,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::mapname); assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); assert(it.second->width >= 0); @@ -776,7 +776,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const new_mod->connections_ = connections_; new_mod->attributes = attributes; - for (auto &it : wires) + for (auto &it : wires_) new_mod->addWire(it.first, it.second); for (auto &it : memories) @@ -796,7 +796,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const std::vector chunks = sig.chunks(); for (auto &c : chunks) if (c.wire != NULL) - c.wire = mod->wires.at(c.wire->name); + c.wire = mod->wires_.at(c.wire->name); sig = chunks; } }; @@ -817,7 +817,7 @@ void RTLIL::Module::add(RTLIL::Wire *wire) { assert(!wire->name.empty()); assert(count_id(wire->name) == 0); - wires[wire->name] = wire; + wires_[wire->name] = wire; } void RTLIL::Module::add(RTLIL::Cell *cell) @@ -848,9 +848,9 @@ namespace { #if 0 void RTLIL::Module::remove(RTLIL::Wire *wire) { - std::set wires; - wires.insert(wire); - remove(wires); + std::set wires_; + wires_.insert(wire); + remove(wires_); } #endif @@ -862,7 +862,7 @@ void RTLIL::Module::remove(const std::set &wires) rewrite_sigspecs(delete_wire_worker); for (auto &it : wires) { - this->wires.erase(it->name); + this->wires_.erase(it->name); delete it; } } @@ -876,8 +876,8 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) { - assert(wires[wire->name] == wire); - wires.erase(wire->name); + assert(wires_[wire->name] == wire); + wires_.erase(wire->name); wire->name = new_name; add(wire); } @@ -893,8 +893,8 @@ void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name) void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name) { assert(count_id(old_name) != 0); - if (wires.count(old_name)) - rename(wires.at(old_name), new_name); + if (wires_.count(old_name)) + rename(wires_.at(old_name), new_name); else if (cells.count(old_name)) rename(cells.at(old_name), new_name); else @@ -932,7 +932,7 @@ void RTLIL::Module::fixup_ports() { std::vector all_ports; - for (auto &w : wires) + for (auto &w : wires_) if (w.second->port_input || w.second->port_output) all_ports.push_back(w.second); else @@ -2457,7 +2457,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri if (netname[0] != '$' && netname[0] != '\\') netname = "\\" + netname; - if (module->wires.count(netname) == 0) { + if (module->wires_.count(netname) == 0) { size_t indices_pos = netname.size()-1; if (indices_pos > 2 && netname[indices_pos] == ']') { @@ -2474,10 +2474,10 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri } } - if (module->wires.count(netname) == 0) + if (module->wires_.count(netname) == 0) return false; - RTLIL::Wire *wire = module->wires.at(netname); + RTLIL::Wire *wire = module->wires_.at(netname); if (!indices.empty()) { std::vector index_tokens; sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); @@ -2514,7 +2514,7 @@ bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL sig = RTLIL::SigSpec(); RTLIL::Selection &sel = design->selection_vars.at(str); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (sel.selected_member(module->name, it.first)) sig.append(it.second); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index cbb612473..1d040975b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -280,7 +280,7 @@ protected: public: RTLIL::IdString name; std::set avail_parameters; - std::map wires; + std::map wires_; std::map memories; std::map cells; std::map processes; -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- kernel/consteval.h | 2 +- kernel/driver.cc | 2 +- kernel/modwalker.h | 2 +- kernel/rtlil.cc | 24 ++++++++++++------------ kernel/rtlil.h | 4 ++-- 5 files changed, 17 insertions(+), 17 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 3a5c5347c..1727d91cf 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -40,7 +40,7 @@ struct ConstEval ct.setup_internals(); ct.setup_stdcells(); - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (!ct.cell_known(it.second->type)) continue; for (auto &it2 : it.second->connections()) diff --git a/kernel/driver.cc b/kernel/driver.cc index 3fbb96580..edf23cd20 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -251,7 +251,7 @@ static char *readline_obj_generator(const char *text, int state) if (RTLIL::unescape_id(it.first).substr(0, len) == text) obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); - for (auto &it : module->cells) + for (auto &it : module->cells_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); diff --git a/kernel/modwalker.h b/kernel/modwalker.h index a90d739eb..09f815b83 100644 --- a/kernel/modwalker.h +++ b/kernel/modwalker.h @@ -123,7 +123,7 @@ struct ModWalker for (auto &it : module->wires_) add_wire(it.second); - for (auto &it : module->cells) + for (auto &it : module->cells_) if (filter_ct == NULL || filter_ct->cell_known(it.second->type)) add_cell(it.second); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0cfcf018c..f307be43e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -204,7 +204,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) if (it.second.size() == 0) del_list.push_back(it.first); else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() + - design->modules[it.first]->cells.size() + design->modules[it.first]->processes.size()) + design->modules[it.first]->cells_.size() + design->modules[it.first]->processes.size()) add_list.push_back(it.first); for (auto mod_name : del_list) selected_members.erase(mod_name); @@ -280,7 +280,7 @@ RTLIL::Module::~Module() delete it->second; for (auto it = memories.begin(); it != memories.end(); it++) delete it->second; - for (auto it = cells.begin(); it != cells.end(); it++) + for (auto it = cells_.begin(); it != cells_.end(); it++) delete it->second; for (auto it = processes.begin(); it != processes.end(); it++) delete it->second; @@ -293,7 +293,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::mapname); assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$')); @@ -782,7 +782,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const for (auto &it : memories) new_mod->memories[it.first] = new RTLIL::Memory(*it.second); - for (auto &it : cells) + for (auto &it : cells_) new_mod->addCell(it.first, it.second); for (auto &it : processes) @@ -824,7 +824,7 @@ void RTLIL::Module::add(RTLIL::Cell *cell) { assert(!cell->name.empty()); assert(count_id(cell->name) == 0); - cells[cell->name] = cell; + cells_[cell->name] = cell; } namespace { @@ -869,8 +869,8 @@ void RTLIL::Module::remove(const std::set &wires) void RTLIL::Module::remove(RTLIL::Cell *cell) { - assert(cells.count(cell->name) != 0); - cells.erase(cell->name); + assert(cells_.count(cell->name) != 0); + cells_.erase(cell->name); delete cell; } @@ -884,8 +884,8 @@ void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name) { - assert(cells[cell->name] == cell); - cells.erase(cell->name); + assert(cells_[cell->name] == cell); + cells_.erase(cell->name); cell->name = new_name; add(cell); } @@ -895,8 +895,8 @@ void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name) assert(count_id(old_name) != 0); if (wires_.count(old_name)) rename(wires_.at(old_name), new_name); - else if (cells.count(old_name)) - rename(cells.at(old_name), new_name); + else if (cells_.count(old_name)) + rename(cells_.at(old_name), new_name); else log_abort(); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1d040975b..f8d2892f8 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -282,7 +282,7 @@ public: std::set avail_parameters; std::map wires_; std::map memories; - std::map cells; + std::map cells_; std::map processes; std::vector connections_; RTLIL_ATTRIBUTE_MEMBERS @@ -719,7 +719,7 @@ struct RTLIL::Process { template void RTLIL::Module::rewrite_sigspecs(T functor) { - for (auto &it : cells) + for (auto &it : cells_) it.second->rewrite_sigspecs(functor); for (auto &it : processes) it.second->rewrite_sigspecs(functor); -- cgit v1.2.3 From c91570bde32d59679ea8b72ed041ef8f6bb0d51a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 02:00:04 +0200 Subject: Mostly cosmetic changes to rtlil.h --- kernel/rtlil.h | 74 ++++++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 17 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f8d2892f8..f235b1de5 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -32,7 +32,7 @@ std::string stringf(const char *fmt, ...); namespace RTLIL { - enum State { + enum State : unsigned char { S0 = 0, S1 = 1, Sx = 2, // undefined value or conflict @@ -41,7 +41,7 @@ namespace RTLIL Sm = 5 // marker (used internally by some passes) }; - enum SyncType { + enum SyncType : unsigned char { ST0 = 0, // level sensitive: 0 ST1 = 1, // level sensitive: 1 STp = 2, // edge sensitive: posedge @@ -51,7 +51,7 @@ namespace RTLIL STi = 6 // init }; - enum ConstFlags { + enum ConstFlags : unsigned char { CONST_FLAG_NONE = 0, CONST_FLAG_STRING = 1, CONST_FLAG_SIGNED = 2, // only used for parameters @@ -191,67 +191,87 @@ namespace RTLIL RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); }; -struct RTLIL::Const { +struct RTLIL::Const +{ int flags; std::vector bits; + Const(); Const(std::string str); Const(int val, int width = 32); Const(RTLIL::State bit, int width = 1); Const(std::vector bits) : bits(bits) { flags = CONST_FLAG_NONE; }; + bool operator <(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const; bool operator !=(const RTLIL::Const &other) const; + bool as_bool() const; int as_int() const; std::string as_string() const; + std::string decode_string() const; }; -struct RTLIL::Selection { +struct RTLIL::Selection +{ bool full_selection; std::set selected_modules; std::map> selected_members; + Selection(bool full = true) : full_selection(full) { } + bool selected_module(RTLIL::IdString mod_name) const; bool selected_whole_module(RTLIL::IdString mod_name) const; bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; void optimize(RTLIL::Design *design); + template void select(T1 *module) { if (!full_selection && selected_modules.count(module->name) == 0) { selected_modules.insert(module->name); selected_members.erase(module->name); } } + template void select(T1 *module, T2 *member) { if (!full_selection && selected_modules.count(module->name) == 0) selected_members[module->name].insert(member->name); } + bool empty() const { return !full_selection && selected_modules.empty() && selected_members.empty(); } }; -struct RTLIL::Design { +struct RTLIL::Design +{ std::map modules; + std::vector selection_stack; std::map selection_vars; std::string selected_active_module; + ~Design(); + void check(); void optimize(); + bool selected_module(RTLIL::IdString mod_name) const; bool selected_whole_module(RTLIL::IdString mod_name) const; bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + bool full_selection() const { return selection_stack.back().full_selection; } + template bool selected(T1 *module) const { return selected_module(module->name); } + template bool selected(T1 *module, T2 *member) const { return selected_member(module->name, member->name); } + template void select(T1 *module, T2 *member) { if (selection_stack.size() > 0) { RTLIL::Selection &sel = selection_stack.back(); @@ -278,13 +298,14 @@ protected: void add(RTLIL::Cell *cell); public: + std::map wires_; + std::map cells_; + std::vector connections_; + RTLIL::IdString name; std::set avail_parameters; - std::map wires_; std::map memories; - std::map cells_; std::map processes; - std::vector connections_; RTLIL_ATTRIBUTE_MEMBERS virtual ~Module(); @@ -507,10 +528,12 @@ public: template void rewrite_sigspecs(T functor); }; -struct RTLIL::SigChunk { +struct RTLIL::SigChunk +{ RTLIL::Wire *wire; RTLIL::Const data; // only used if wire == NULL, LSB at index 0 int width, offset; + SigChunk(); SigChunk(const RTLIL::Const &value); SigChunk(RTLIL::Wire *wire); @@ -519,16 +542,20 @@ struct RTLIL::SigChunk { SigChunk(int val, int width = 32); SigChunk(RTLIL::State bit, int width = 1); SigChunk(RTLIL::SigBit bit); + RTLIL::SigChunk extract(int offset, int length) const; + bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; bool operator !=(const RTLIL::SigChunk &other) const; }; -struct RTLIL::SigBit { +struct RTLIL::SigBit +{ RTLIL::Wire *wire; RTLIL::State data; int offset; + SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { } SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(!wire || wire->width == 1); } @@ -536,26 +563,32 @@ struct RTLIL::SigBit { SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { assert(chunk.width == 1); } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { } SigBit(const RTLIL::SigSpec &sig); + bool operator <(const RTLIL::SigBit &other) const { return (wire != other.wire) ? (wire < other.wire) : wire ? (offset < other.offset) : (data < other.data); } + bool operator ==(const RTLIL::SigBit &other) const { return (wire == other.wire) && (wire ? (offset == other.offset) : (data == other.data)); } + bool operator !=(const RTLIL::SigBit &other) const { return (wire != other.wire) || (wire ? (offset != other.offset) : (data != other.data)); } }; -struct RTLIL::SigSpecIterator { +struct RTLIL::SigSpecIterator +{ RTLIL::SigSpec *sig_p; int index; + inline RTLIL::SigBit &operator*() const; inline bool operator!=(const RTLIL::SigSpecIterator &other) { return index != other.index; } inline void operator++() { index++; } }; -struct RTLIL::SigSpec { +struct RTLIL::SigSpec +{ private: int width_; unsigned long hash_; @@ -675,10 +708,12 @@ inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { *this = SigBit(sig.chunks().front()); } -struct RTLIL::CaseRule { +struct RTLIL::CaseRule +{ std::vector compare; std::vector actions; std::vector switches; + ~CaseRule(); void optimize(); @@ -686,17 +721,20 @@ struct RTLIL::CaseRule { RTLIL::CaseRule *clone() const; }; -struct RTLIL::SwitchRule { +struct RTLIL::SwitchRule +{ RTLIL::SigSpec signal; RTLIL_ATTRIBUTE_MEMBERS std::vector cases; + ~SwitchRule(); template void rewrite_sigspecs(T functor); RTLIL::SwitchRule *clone() const; }; -struct RTLIL::SyncRule { +struct RTLIL::SyncRule +{ RTLIL::SyncType type; RTLIL::SigSpec signal; std::vector actions; @@ -705,11 +743,13 @@ struct RTLIL::SyncRule { RTLIL::SyncRule *clone() const; }; -struct RTLIL::Process { +struct RTLIL::Process +{ RTLIL::IdString name; RTLIL_ATTRIBUTE_MEMBERS RTLIL::CaseRule root_case; std::vector syncs; + ~Process(); template void rewrite_sigspecs(T functor); -- cgit v1.2.3 From 7f3dc86ecd00a9ed5f5b7f09e02a6fe584259f79 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 02:11:57 +0200 Subject: Added RTLIL::SigSpec move constructor and move assignment operator --- kernel/rtlil.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f235b1de5..97d01617a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -625,6 +625,21 @@ public: SigSpec(std::vector bits); SigSpec(std::set bits); + SigSpec(RTLIL::SigSpec &&other) { + width_ = other.width_; + hash_ = other.hash_; + chunks_.swap(other.chunks_); + bits_.swap(other.bits_); + } + + const RTLIL::SigSpec &operator=(RTLIL::SigSpec &&other) { + width_ = other.width_; + hash_ = other.hash_; + chunks_.swap(other.chunks_); + bits_.swap(other.bits_); + return *this; + } + inline const std::vector &chunks() const { pack(); return chunks_; } inline const std::vector &bits() const { inline_unpack(); return bits_; } -- cgit v1.2.3 From ddc5b4184836e795e143fc00786b4b87a6e69bc4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 09:20:59 +0200 Subject: Using std::move() in SigSpec move constructor --- kernel/rtlil.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 97d01617a..91c9a1baa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -628,15 +628,15 @@ public: SigSpec(RTLIL::SigSpec &&other) { width_ = other.width_; hash_ = other.hash_; - chunks_.swap(other.chunks_); - bits_.swap(other.bits_); + chunks_ = std::move(other.chunks_); + bits_ = std::move(other.bits_); } const RTLIL::SigSpec &operator=(RTLIL::SigSpec &&other) { width_ = other.width_; hash_ = other.hash_; - chunks_.swap(other.chunks_); - bits_.swap(other.bits_); + chunks_ = std::move(other.chunks_); + bits_ = std::move(other.bits_); return *this; } -- cgit v1.2.3 From 1c8fdaeef86d6e33668e325556380bfa67ec0a6f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:13:22 +0200 Subject: Added RTLIL::ObjIterator and RTLIL::ObjRange --- kernel/rtlil.cc | 29 +++++++++++++++---- kernel/rtlil.h | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 111 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f307be43e..5fdcb025a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -274,6 +274,12 @@ bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString me return selection_stack.back().selected_member(mod_name, memb_name); } +RTLIL::Module::Module() +{ + refcount_wires_ = 0; + refcount_cells_ = 0; +} + RTLIL::Module::~Module() { for (auto it = wires_.begin(); it != wires_.end(); it++) @@ -772,6 +778,9 @@ void RTLIL::Module::optimize() void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const { + log_assert(new_mod->refcount_wires_ == 0); + log_assert(new_mod->refcount_cells_ == 0); + new_mod->name = name; new_mod->connections_ = connections_; new_mod->attributes = attributes; @@ -815,15 +824,17 @@ RTLIL::Module *RTLIL::Module::clone() const void RTLIL::Module::add(RTLIL::Wire *wire) { - assert(!wire->name.empty()); - assert(count_id(wire->name) == 0); + log_assert(!wire->name.empty()); + log_assert(count_id(wire->name) == 0); + log_assert(refcount_wires_ == 0); wires_[wire->name] = wire; } void RTLIL::Module::add(RTLIL::Cell *cell) { - assert(!cell->name.empty()); - assert(count_id(cell->name) == 0); + log_assert(!cell->name.empty()); + log_assert(count_id(cell->name) == 0); + log_assert(refcount_cells_ == 0); cells_[cell->name] = cell; } @@ -856,20 +867,24 @@ void RTLIL::Module::remove(RTLIL::Wire *wire) void RTLIL::Module::remove(const std::set &wires) { + log_assert(refcount_wires_ == 0); + DeleteWireWorker delete_wire_worker; delete_wire_worker.module = this; delete_wire_worker.wires_p = &wires; rewrite_sigspecs(delete_wire_worker); for (auto &it : wires) { - this->wires_.erase(it->name); + log_assert(wires_.count(it->name) != 0); + wires_.erase(it->name); delete it; } } void RTLIL::Module::remove(RTLIL::Cell *cell) { - assert(cells_.count(cell->name) != 0); + log_assert(cells_.count(cell->name) != 0); + log_assert(refcount_cells_ == 0); cells_.erase(cell->name); delete cell; } @@ -877,6 +892,7 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) { assert(wires_[wire->name] == wire); + log_assert(refcount_wires_ == 0); wires_.erase(wire->name); wire->name = new_name; add(wire); @@ -885,6 +901,7 @@ void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name) { assert(cells_[cell->name] == cell); + log_assert(refcount_wires_ == 0); cells_.erase(cell->name); cell->name = new_name; add(cell); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 91c9a1baa..be2822706 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -189,6 +189,86 @@ namespace RTLIL RTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_bu0 (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + + + // This iterator-range-pair is used for Design::modules(), Module::wires() and Module::cells(). + // It maintains a reference counter that is used to make sure that the container is not modified while being iterated over. + + template + struct ObjIterator + { + typename std::map::iterator it; + std::map *list_p; + int *refcount_p; + + ObjIterator() : list_p(nullptr), refcount_p(nullptr) { + } + + ObjIterator(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { + if (list_p->empty()) { + this->list_p = nullptr; + this->refcount_p = nullptr; + } else { + it = list_p->begin(); + (*refcount_p)++; + } + } + + ObjIterator(const RTLIL::ObjIterator &other) { + it = other.it; + list_p = other.list_p; + refcount_p = other.refcount_p; + if (refcount_p) + (*refcount_p)++; + } + + ObjIterator &operator=(const RTLIL::ObjIterator &other) { + if (refcount_p) + (*refcount_p)--; + it = other.it; + list_p = other.list_p; + refcount_p = other.refcount_p; + if (refcount_p) + (*refcount_p)++; + return *this; + } + + ~ObjIterator() { + if (refcount_p) + (*refcount_p)--; + } + + inline T operator*() const { + assert(list_p != nullptr); + return it->second; + } + + inline bool operator!=(const RTLIL::ObjIterator &other) const { + if (list_p == nullptr || other.list_p == nullptr) + return list_p != other.list_p; + return it != other.it; + } + + inline void operator++() { + assert(list_p != nullptr); + if (++it == list_p->end()) { + (*refcount_p)--; + list_p = nullptr; + refcount_p = nullptr; + } + } + }; + + template + struct ObjRange + { + std::map *list_p; + int *refcount_p; + + ObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { } + RTLIL::ObjIterator begin() { return RTLIL::ObjIterator(list_p, refcount_p); } + RTLIL::ObjIterator end() { return RTLIL::ObjIterator(); } + }; }; struct RTLIL::Const @@ -298,6 +378,9 @@ protected: void add(RTLIL::Cell *cell); public: + int refcount_wires_; + int refcount_cells_; + std::map wires_; std::map cells_; std::vector connections_; @@ -308,6 +391,7 @@ public: std::map processes; RTLIL_ATTRIBUTE_MEMBERS + Module(); virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters); virtual size_t count_id(RTLIL::IdString id); @@ -323,6 +407,9 @@ public: void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; + RTLIL::ObjRange wires() { return RTLIL::ObjRange(&wires_, &refcount_wires_); } + RTLIL::ObjRange cells() { return RTLIL::ObjRange(&cells_, &refcount_cells_); } + // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const std::set &wires); void remove(RTLIL::Cell *cell); @@ -583,7 +670,7 @@ struct RTLIL::SigSpecIterator int index; inline RTLIL::SigBit &operator*() const; - inline bool operator!=(const RTLIL::SigSpecIterator &other) { return index != other.index; } + inline bool operator!=(const RTLIL::SigSpecIterator &other) const { return index != other.index; } inline void operator++() { index++; } }; -- cgit v1.2.3 From d088854b47f5f77c6a62be2ba4b895164938d7a2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:41:06 +0200 Subject: Added conversion from ObjRange to std::vector and std::set --- kernel/rtlil.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index be2822706..2fbfe8049 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -268,6 +268,21 @@ namespace RTLIL ObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { } RTLIL::ObjIterator begin() { return RTLIL::ObjIterator(list_p, refcount_p); } RTLIL::ObjIterator end() { return RTLIL::ObjIterator(); } + + operator std::set() const { + std::set result; + for (auto &it : *list_p) + result.insert(it.second); + return result; + } + + operator std::vector() const { + std::vector result; + result.reserve(list_p->size()); + for (auto &it : *list_p) + result.push_back(it.second); + return result; + } }; }; -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- kernel/celltypes.h | 14 +++++++------- kernel/driver.cc | 6 +++--- kernel/rtlil.cc | 18 +++++++++--------- kernel/rtlil.h | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index d3c848f46..20d68d559 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -171,7 +171,7 @@ struct CellTypes if (cell_types.count(type) > 0) return true; for (auto design : designs) - if (design->modules.count(type) > 0) + if (design->modules_.count(type) > 0) return true; return false; } @@ -180,9 +180,9 @@ struct CellTypes { if (cell_types.count(type) == 0) { for (auto design : designs) - if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires_.count(port)) - return design->modules.at(type)->wires_.at(port)->port_output; + if (design->modules_.count(type) > 0) { + if (design->modules_.at(type)->wires_.count(port)) + return design->modules_.at(type)->wires_.at(port)->port_output; return false; } return false; @@ -203,9 +203,9 @@ struct CellTypes { if (cell_types.count(type) == 0) { for (auto design : designs) - if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires_.count(port)) - return design->modules.at(type)->wires_.at(port)->port_input; + if (design->modules_.count(type) > 0) { + if (design->modules_.at(type)->wires_.count(port)) + return design->modules_.at(type)->wires_.at(port)->port_input; return false; } return false; diff --git a/kernel/driver.cc b/kernel/driver.cc index edf23cd20..7a1c7ed16 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -234,14 +234,14 @@ static char *readline_obj_generator(const char *text, int state) if (design->selected_active_module.empty()) { - for (auto &it : design->modules) + for (auto &it : design->modules_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); } else - if (design->modules.count(design->selected_active_module) > 0) + if (design->modules_.count(design->selected_active_module) > 0) { - RTLIL::Module *module = design->modules.at(design->selected_active_module); + RTLIL::Module *module = design->modules_.at(design->selected_active_module); for (auto &it : module->wires_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5fdcb025a..5709875ec 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -175,7 +175,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) del_list.clear(); for (auto mod_name : selected_modules) { - if (design->modules.count(mod_name) == 0) + if (design->modules_.count(mod_name) == 0) del_list.push_back(mod_name); selected_members.erase(mod_name); } @@ -184,7 +184,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) del_list.clear(); for (auto &it : selected_members) - if (design->modules.count(it.first) == 0) + if (design->modules_.count(it.first) == 0) del_list.push_back(it.first); for (auto mod_name : del_list) selected_members.erase(mod_name); @@ -192,7 +192,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) for (auto &it : selected_members) { del_list.clear(); for (auto memb_name : it.second) - if (design->modules[it.first]->count_id(memb_name) == 0) + if (design->modules_[it.first]->count_id(memb_name) == 0) del_list.push_back(memb_name); for (auto memb_name : del_list) it.second.erase(memb_name); @@ -203,8 +203,8 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) for (auto &it : selected_members) if (it.second.size() == 0) del_list.push_back(it.first); - else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() + - design->modules[it.first]->cells_.size() + design->modules[it.first]->processes.size()) + else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() + + design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size()) add_list.push_back(it.first); for (auto mod_name : del_list) selected_members.erase(mod_name); @@ -213,7 +213,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) selected_modules.insert(mod_name); } - if (selected_modules.size() == design->modules.size()) { + if (selected_modules.size() == design->modules_.size()) { full_selection = true; selected_modules.clear(); selected_members.clear(); @@ -222,14 +222,14 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) RTLIL::Design::~Design() { - for (auto it = modules.begin(); it != modules.end(); it++) + for (auto it = modules_.begin(); it != modules_.end(); it++) delete it->second; } void RTLIL::Design::check() { #ifndef NDEBUG - for (auto &it : modules) { + for (auto &it : modules_) { assert(it.first == it.second->name); assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); it.second->check(); @@ -239,7 +239,7 @@ void RTLIL::Design::check() void RTLIL::Design::optimize() { - for (auto &it : modules) + for (auto &it : modules_) it.second->optimize(); for (auto &it : selection_stack) it.optimize(this); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 2fbfe8049..7249f0cad 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -340,7 +340,7 @@ struct RTLIL::Selection struct RTLIL::Design { - std::map modules; + std::map modules_; std::vector selection_stack; std::map selection_vars; -- cgit v1.2.3 From 0bd8fafbd2f36f59327289e52abf962c166dab8b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:40:31 +0200 Subject: Added RTLIL::Design::modules() --- kernel/rtlil.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7249f0cad..6eb52cf2d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -340,6 +340,7 @@ struct RTLIL::Selection struct RTLIL::Design { + int refcount_modules_; std::map modules_; std::vector selection_stack; @@ -348,6 +349,8 @@ struct RTLIL::Design ~Design(); + RTLIL::ObjRange modules() { return RTLIL::ObjRange(&modules_, &refcount_modules_); } + void check(); void optimize(); -- cgit v1.2.3 From 675cb93da9e67f5c2fe8a3760de5893176ea906d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 11:03:56 +0200 Subject: Added RTLIL::Module::wire(id) and cell(id) lookup functions --- kernel/rtlil.cc | 12 ++++++++++++ kernel/rtlil.h | 10 ++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5709875ec..db85f9e3d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -274,6 +274,16 @@ bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString me return selection_stack.back().selected_member(mod_name, memb_name); } +bool RTLIL::Design::selected_module(RTLIL::Module *mod) const +{ + return selected_module(mod->name); +} + +bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const +{ + return selected_whole_module(mod->name); +} + RTLIL::Module::Module() { refcount_wires_ = 0; @@ -1502,6 +1512,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value) RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire) { + log_assert(wire != nullptr); this->wire = wire; this->width = wire->width; this->offset = 0; @@ -1509,6 +1520,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire) RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width) { + log_assert(wire != nullptr); this->wire = wire; this->width = width; this->offset = offset; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6eb52cf2d..7c69ff64c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -358,6 +358,9 @@ struct RTLIL::Design bool selected_whole_module(RTLIL::IdString mod_name) const; bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + bool selected_module(RTLIL::Module *mod) const; + bool selected_whole_module(RTLIL::Module *mod) const; + bool full_selection() const { return selection_stack.back().full_selection; } @@ -425,6 +428,9 @@ public: void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; + RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } + RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } + RTLIL::ObjRange wires() { return RTLIL::ObjRange(&wires_, &refcount_wires_); } RTLIL::ObjRange cells() { return RTLIL::ObjRange(&cells_, &refcount_cells_); } @@ -663,8 +669,8 @@ struct RTLIL::SigBit SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { } - SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(!wire || wire->width == 1); } - SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { } + SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(wire && wire->width == 1); } + SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { assert(wire); } SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { assert(chunk.width == 1); } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { } SigBit(const RTLIL::SigSpec &sig); -- cgit v1.2.3 From d878fcbdc76f4b612ba8578213f73f27585fc792 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 12:04:12 +0200 Subject: Added log_cmd_error_expection --- kernel/driver.cc | 6 +++--- kernel/log.cc | 2 +- kernel/log.h | 2 ++ 3 files changed, 6 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 7a1c7ed16..380315e7c 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -141,9 +141,9 @@ static void run_frontend(std::string filename, std::string command, RTLIL::Desig Pass::call(design, command); } } - catch (...) { + catch (log_cmd_error_expection) { Frontend::current_script_file = backup_script_file; - std::rethrow_exception(std::current_exception()); + throw log_cmd_error_expection(); } Frontend::current_script_file = backup_script_file; @@ -329,7 +329,7 @@ static void shell(RTLIL::Design *design) try { assert(design->selection_stack.size() == 1); Pass::call(design, command); - } catch (int) { + } catch (log_cmd_error_expection) { while (design->selection_stack.size() > 1) design->selection_stack.pop_back(); log_reset_stack(); diff --git a/kernel/log.cc b/kernel/log.cc index 63a0a84dd..b8a47e1cf 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -160,7 +160,7 @@ void log_cmd_error(const char *format, ...) log("ERROR: "); logv(format, ap); log_flush(); - throw 0; + throw log_cmd_error_expection(); } logv_error(format, ap); diff --git a/kernel/log.h b/kernel/log.h index 1658800dd..abfb810f7 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -34,6 +34,8 @@ #define S__LINE__sub1(x) S__LINE__sub2(x) #define S__LINE__ S__LINE__sub1(__LINE__) +struct log_cmd_error_expection { }; + extern std::vector log_files; extern FILE *log_errfile; extern bool log_time; -- cgit v1.2.3 From cbc3a46a9717f0f6e90b20b29c9003c3720a5aa0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 14:47:23 +0200 Subject: Added RTLIL::SigSpecConstIterator --- kernel/rtlil.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7c69ff64c..4341e0676 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -70,6 +70,7 @@ namespace RTLIL struct SigChunk; struct SigBit; struct SigSpecIterator; + struct SigSpecConstIterator; struct SigSpec; struct CaseRule; struct SwitchRule; @@ -698,6 +699,16 @@ struct RTLIL::SigSpecIterator inline void operator++() { index++; } }; +struct RTLIL::SigSpecConstIterator +{ + const RTLIL::SigSpec *sig_p; + int index; + + inline const RTLIL::SigBit &operator*() const; + inline bool operator!=(const RTLIL::SigSpecConstIterator &other) const { return index != other.index; } + inline void operator++() { index++; } +}; + struct RTLIL::SigSpec { private: @@ -762,6 +773,9 @@ public: inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } + inline RTLIL::SigSpecConstIterator begin() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = 0; return it; } + inline RTLIL::SigSpecConstIterator end() const { RTLIL::SigSpecConstIterator it; it.sig_p = this; it.index = width_; return it; } + void sort(); void sort_and_unify(); @@ -829,6 +843,10 @@ inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const { return (*sig_p)[index]; } +inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const { + return (*sig_p)[index]; +} + inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { assert(sig.size() == 1 && sig.chunks().size() == 1); *this = SigBit(sig.chunks().front()); -- cgit v1.2.3 From 4be645860bf83de75cdd00fbe615f3fe05221d54 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 14:47:48 +0200 Subject: Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs --- kernel/rtlil.cc | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index db85f9e3d..9f9bd7e03 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1978,19 +1978,36 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) void RTLIL::SigSpec::remove_const() { - cover("kernel.rtlil.sigspec.remove_const"); + if (packed()) + { + cover("kernel.rtlil.sigspec.remove_const.packed"); - unpack(); + std::vector new_chunks; + new_chunks.reserve(SIZE(chunks_)); + + width_ = 0; + for (auto &chunk : chunks_) + if (chunk.wire != NULL) { + new_chunks.push_back(chunk); + width_ += chunk.width; + } + + chunks_.swap(new_chunks); + } + else + { + cover("kernel.rtlil.sigspec.remove_const.unpacked"); - std::vector new_bits; - new_bits.reserve(width_); + std::vector new_bits; + new_bits.reserve(width_); - for (auto &bit : bits_) - if (bit.wire != NULL) - new_bits.push_back(bit); + for (auto &bit : bits_) + if (bit.wire != NULL) + new_bits.push_back(bit); - bits_.swap(new_bits); - width_ = bits_.size(); + bits_.swap(new_bits); + width_ = bits_.size(); + } check(); } -- cgit v1.2.3 From d07a871d35401b6b8628dd3f1df3b91149e827d5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 14:50:25 +0200 Subject: Improved performance of opt_const on large modules --- kernel/toposort.h | 103 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 kernel/toposort.h (limited to 'kernel') diff --git a/kernel/toposort.h b/kernel/toposort.h new file mode 100644 index 000000000..7e978c1e2 --- /dev/null +++ b/kernel/toposort.h @@ -0,0 +1,103 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef TOPOSORT_H +#define TOPOSORT_H + +template +struct TopoSort +{ + bool analyze_loops, found_loops; + std::map> database; + std::set> loops; + std::vector sorted; + + TopoSort() + { + analyze_loops = true; + found_loops = false; + } + + void node(T n) + { + if (database.count(n) == 0) + database[n] = std::set(); + } + + void edge(T left, T right) + { + node(left); + database[right].insert(left); + } + + void sort_worker(T n, std::set &marked_cells, std::set &active_cells, std::vector active_stack) + { + if (active_cells.count(n)) { + found_loops = false; + if (analyze_loops) { + std::set loop; + for (int i = SIZE(active_stack)-1; i >= 0; i--) { + loop.insert(active_stack[i]); + if (active_stack[i] == n) + break; + } + loops.insert(loop); + } + return; + } + + if (marked_cells.count(n)) + return; + + if (!database.at(n).empty()) + { + if (analyze_loops) + active_stack.push_back(n); + active_cells.insert(n); + + for (auto &left_n : database.at(n)) + sort_worker(left_n, marked_cells, active_cells, active_stack); + + if (analyze_loops) + active_stack.pop_back(); + active_cells.erase(n); + } + + marked_cells.insert(n); + sorted.push_back(n); + } + + bool sort() + { + loops.clear(); + sorted.clear(); + found_loops = false; + + std::set marked_cells; + std::set active_cells; + std::vector active_stack; + + for (auto &it : database) + sort_worker(it.first, marked_cells, active_cells, active_stack); + + return !found_loops; + } +}; + +#endif -- cgit v1.2.3 From ddd31a0b66259a458f7bfb3475f53c30aa859bc8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 15:14:02 +0200 Subject: Small improvements in PerformanceTimer API --- kernel/log.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index abfb810f7..ca1e7c67c 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -199,12 +199,12 @@ struct PerformanceTimer total_ns = 0; } - void add() { - total_ns += query(); + void begin() { + total_ns -= query(); } - void sub() { - total_ns -= query(); + void end() { + total_ns += query(); } float sec() const { @@ -212,8 +212,8 @@ struct PerformanceTimer } #else void reset() { } - void add() { } - void sub() { } + void begin() { } + void end() { } float sec() const { return 0; } #endif }; @@ -235,6 +235,7 @@ static inline void log_dump_val_worker(double v) { log("%f", v); } static inline void log_dump_val_worker(const char *v) { log("%s", v); } static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); } static inline void log_dump_val_worker(RTLIL::SigSpec v) { log("%s", log_signal(v)); } +static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); } static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); } template -- cgit v1.2.3 From 0c86d6106c3ff4cd7628b1206281eb6080f8bf51 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 15:38:02 +0200 Subject: Added SigPool::check(bit) --- kernel/sigtools.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'kernel') diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 7035db73d..52e4aa0fb 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -93,6 +93,11 @@ struct SigPool return result; } + bool check(RTLIL::SigBit bit) + { + return bit.wire != NULL && bits.count(bit); + } + bool check_any(RTLIL::SigSpec sig) { for (auto &bit : sig) -- cgit v1.2.3 From 5da343b7de8c4fd45695af68aaba3d5091d8e670 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 16:19:24 +0200 Subject: Added topological sorting to techmap --- kernel/toposort.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/toposort.h b/kernel/toposort.h index 7e978c1e2..4226e270e 100644 --- a/kernel/toposort.h +++ b/kernel/toposort.h @@ -46,7 +46,7 @@ struct TopoSort database[right].insert(left); } - void sort_worker(T n, std::set &marked_cells, std::set &active_cells, std::vector active_stack) + void sort_worker(const T &n, std::set &marked_cells, std::set &active_cells, std::vector &active_stack) { if (active_cells.count(n)) { found_loops = false; @@ -96,6 +96,7 @@ struct TopoSort for (auto &it : database) sort_worker(it.first, marked_cells, active_cells, active_stack); + log_assert(SIZE(sorted) == SIZE(database)); return !found_loops; } }; -- cgit v1.2.3 From c4bdba78cb88df6628d975aad7a92c8cebc5d95f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 21:12:09 +0200 Subject: Added proper Design->addModule interface --- kernel/rtlil.cc | 39 ++++++++++++++++++++++++++++++++++++--- kernel/rtlil.h | 7 ++++++- 2 files changed, 42 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9f9bd7e03..aec0a045f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -226,6 +226,39 @@ RTLIL::Design::~Design() delete it->second; } +RTLIL::ObjRange RTLIL::Design::modules() +{ + return RTLIL::ObjRange(&modules_, &refcount_modules_); +} + +RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) +{ + return modules_.count(name) ? modules_.at(name) : NULL; +} + +void RTLIL::Design::add(RTLIL::Module *module) +{ + assert(modules_.count(module->name) == 0); + assert(refcount_modules_ == 0); + modules_[module->name] = module; +} + +RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) +{ + assert(modules_.count(name) == 0); + assert(refcount_modules_ == 0); + modules_[name] = new RTLIL::Module; + modules_[name]->name = name; + return modules_[name]; +} + +void RTLIL::Design::remove(RTLIL::Module *module) +{ + assert(modules_.at(module->name) == module); + modules_.erase(module->name); + delete module; +} + void RTLIL::Design::check() { #ifndef NDEBUG @@ -412,7 +445,7 @@ namespace { void check() { if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || - cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:") + cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") return; if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") { @@ -791,7 +824,6 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const log_assert(new_mod->refcount_wires_ == 0); log_assert(new_mod->refcount_cells_ == 0); - new_mod->name = name; new_mod->connections_ = connections_; new_mod->attributes = attributes; @@ -828,6 +860,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const RTLIL::Module *RTLIL::Module::clone() const { RTLIL::Module *new_mod = new RTLIL::Module; + new_mod->name = name; cloneInto(new_mod); return new_mod; } @@ -1455,7 +1488,7 @@ void RTLIL::Cell::check() void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || - type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:") + type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") return; if (type == "$mux" || type == "$pmux" || type == "$safe_pmux") diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4341e0676..cd00b43d8 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -350,7 +350,12 @@ struct RTLIL::Design ~Design(); - RTLIL::ObjRange modules() { return RTLIL::ObjRange(&modules_, &refcount_modules_); } + RTLIL::ObjRange modules(); + RTLIL::Module *module(RTLIL::IdString name); + + void add(RTLIL::Module *module); + RTLIL::Module *addModule(RTLIL::IdString name); + void remove(RTLIL::Module *module); void check(); void optimize(); -- cgit v1.2.3 From f99495a895eda0b1de6c1d7e8e1d5b1074316b34 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 10:52:30 +0200 Subject: Added cover() to all SigSpec constructors --- kernel/rtlil.cc | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index aec0a045f..610ab6a83 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1691,6 +1691,8 @@ const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other) RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) { + cover("kernel.rtlil.sigspec.init.const"); + chunks_.push_back(RTLIL::SigChunk(value)); width_ = chunks_.back().width; hash_ = 0; @@ -1699,6 +1701,8 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) { + cover("kernel.rtlil.sigspec.init.chunk"); + chunks_.push_back(chunk); width_ = chunks_.back().width; hash_ = 0; @@ -1707,6 +1711,8 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) { + cover("kernel.rtlil.sigspec.init.wire"); + chunks_.push_back(RTLIL::SigChunk(wire)); width_ = chunks_.back().width; hash_ = 0; @@ -1715,6 +1721,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width) { + cover("kernel.rtlil.sigspec.init.wire_part"); + chunks_.push_back(RTLIL::SigChunk(wire, offset, width)); width_ = chunks_.back().width; hash_ = 0; @@ -1723,6 +1731,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width) RTLIL::SigSpec::SigSpec(const std::string &str) { + cover("kernel.rtlil.sigspec.init.str"); + chunks_.push_back(RTLIL::SigChunk(str)); width_ = chunks_.back().width; hash_ = 0; @@ -1731,6 +1741,8 @@ RTLIL::SigSpec::SigSpec(const std::string &str) RTLIL::SigSpec::SigSpec(int val, int width) { + cover("kernel.rtlil.sigspec.init.int"); + chunks_.push_back(RTLIL::SigChunk(val, width)); width_ = width; hash_ = 0; @@ -1739,6 +1751,8 @@ RTLIL::SigSpec::SigSpec(int val, int width) RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) { + cover("kernel.rtlil.sigspec.init.state"); + chunks_.push_back(RTLIL::SigChunk(bit, width)); width_ = width; hash_ = 0; @@ -1747,6 +1761,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) { + cover("kernel.rtlil.sigspec.init.bit"); + if (bit.wire == NULL) chunks_.push_back(RTLIL::SigChunk(bit.data, width)); else @@ -1759,6 +1775,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width) RTLIL::SigSpec::SigSpec(std::vector chunks) { + cover("kernel.rtlil.sigspec.init.stdvec_chunks"); + width_ = 0; hash_ = 0; for (auto &c : chunks) @@ -1768,6 +1786,8 @@ RTLIL::SigSpec::SigSpec(std::vector chunks) RTLIL::SigSpec::SigSpec(std::vector bits) { + cover("kernel.rtlil.sigspec.init.stdvec_bits"); + width_ = 0; hash_ = 0; for (auto &bit : bits) @@ -1777,6 +1797,8 @@ RTLIL::SigSpec::SigSpec(std::vector bits) RTLIL::SigSpec::SigSpec(std::set bits) { + cover("kernel.rtlil.sigspec.init.stdset_bits"); + width_ = 0; hash_ = 0; for (auto &bit : bits) -- cgit v1.2.3 From d86a25f145012ccb6b2048af3aae22f13b97b505 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 10:52:58 +0200 Subject: Added std::initializer_list<> constructor to SigSpec --- kernel/rtlil.cc | 12 ++++++++++++ kernel/rtlil.h | 3 +++ 2 files changed, 15 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 610ab6a83..753c40090 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1652,6 +1652,18 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other) *this = other; } +RTLIL::SigSpec::SigSpec(std::initializer_list parts) +{ + cover("kernel.rtlil.sigspec.init.list"); + + width_ = 0; + hash_ = 0; + + std::vector parts_vec(parts.begin(), parts.end()); + for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++) + append(*it); +} + const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other) { cover("kernel.rtlil.sigspec.assign"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index cd00b43d8..331ea3770 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -26,6 +26,8 @@ #include #include +#include + // various helpers (unrelated to RTLIL) std::string stringf(const char *fmt, ...); #define SIZE(__obj) int(__obj.size()) @@ -738,6 +740,7 @@ private: public: SigSpec(); SigSpec(const RTLIL::SigSpec &other); + SigSpec(std::initializer_list parts); const RTLIL::SigSpec &operator=(const RTLIL::SigSpec &other); SigSpec(const RTLIL::Const &value); -- cgit v1.2.3 From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- kernel/bitpattern.h | 4 +- kernel/calc.cc | 1 - kernel/celltypes.h | 2 +- kernel/consteval.h | 8 ++-- kernel/driver.cc | 2 +- kernel/log.cc | 57 +++++++++++++++++++++++-- kernel/log.h | 56 +++++-------------------- kernel/register.cc | 15 ++++--- kernel/rtlil.cc | 119 ++++++++++++++++++++++++++-------------------------- kernel/rtlil.h | 16 +++---- kernel/satgen.h | 8 ++-- kernel/sigtools.h | 13 +++--- 12 files changed, 157 insertions(+), 144 deletions(-) (limited to 'kernel') diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 05b2bbc24..91f54593f 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -66,8 +66,8 @@ struct BitPatternPool bool match(bits_t a, bits_t b) { - assert(int(a.size()) == width); - assert(int(b.size()) == width); + log_assert(int(a.size()) == width); + log_assert(int(b.size()) == width); for (int i = 0; i < width; i++) if (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i]) return false; diff --git a/kernel/calc.cc b/kernel/calc.cc index 749589f20..b413760d1 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -24,7 +24,6 @@ #include "kernel/log.h" #include "kernel/rtlil.h" #include "libs/bigint/BigIntegerLibrary.hh" -#include static void extend(RTLIL::Const &arg, int width, bool is_signed) { diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 20d68d559..43c23add3 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -313,7 +313,7 @@ struct CellTypes return ret; } - assert(sel.bits.size() == 0); + log_assert(sel.bits.size() == 0); return eval(cell, arg1, arg2); } }; diff --git a/kernel/consteval.h b/kernel/consteval.h index 1727d91cf..e5cae1022 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -72,7 +72,7 @@ struct ConstEval #ifndef NDEBUG RTLIL::SigSpec current_val = values_map(sig); for (int i = 0; i < SIZE(current_val); i++) - assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]); + log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]); #endif values_map.add(sig, RTLIL::SigSpec(value)); } @@ -87,7 +87,7 @@ struct ConstEval { RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - assert(cell->has("\\Y")); + log_assert(cell->has("\\Y")); sig_y = values_map(assign_map(cell->get("\\Y"))); if (sig_y.is_fully_const()) return true; @@ -133,7 +133,7 @@ struct ConstEval std::vector y_values; - assert(y_candidates.size() > 0); + log_assert(y_candidates.size() > 0); for (auto &yc : y_candidates) { if (!eval(yc, undef, cell)) return false; @@ -146,7 +146,7 @@ struct ConstEval for (size_t i = 1; i < y_values.size(); i++) { std::vector &slave_bits = y_values.at(i).bits; - assert(master_bits.size() == slave_bits.size()); + log_assert(master_bits.size() == slave_bits.size()); for (size_t j = 0; j < master_bits.size(); j++) if (master_bits[j] != slave_bits[j]) master_bits[j] = RTLIL::State::Sx; diff --git a/kernel/driver.cc b/kernel/driver.cc index 380315e7c..a55fbbed5 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -327,7 +327,7 @@ static void shell(RTLIL::Design *design) } try { - assert(design->selection_stack.size() == 1); + log_assert(design->selection_stack.size() == 1); Pass::call(design, command); } catch (log_cmd_error_expection) { while (design->selection_stack.size() > 1) diff --git a/kernel/log.cc b/kernel/log.cc index b8a47e1cf..8036b2360 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -18,6 +18,8 @@ */ #include "kernel/log.h" +#include "kernel/rtlil.h" +#include "kernel/register.h" #include "kernel/compatibility.h" #include "backends/ilang/ilang_backend.h" @@ -29,9 +31,6 @@ #include #include -// declared extern in log.h -std::map> extra_coverage_data; - std::vector log_files; FILE *log_errfile = NULL; bool log_time = false; @@ -192,6 +191,10 @@ void log_flush() fflush(f); } +void log_dump_val_worker(RTLIL::SigSpec v) { + log("%s", log_signal(v)); +} + const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) { char *ptr; @@ -231,3 +234,51 @@ void log_cell(RTLIL::Cell *cell, std::string indent) free(ptr); } +// --------------------------------------------------- +// This is the magic behind the code coverage counters +// --------------------------------------------------- + +std::map> extra_coverage_data; + +void cover_extra(std::string parent, std::string id, bool increment) { + if (extra_coverage_data.count(id) == 0) { + for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) + if (p->id == parent) + extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func); + log_assert(extra_coverage_data.count(id)); + } + if (increment) + extra_coverage_data[id].second++; +} + +std::map> get_coverage_data() +{ + std::map> coverage_data; + + for (auto &it : REGISTER_INTERN::pass_register) { + std::string key = stringf("passes.%s", it.first.c_str()); + coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__); + coverage_data[key].second += it.second->call_counter; + } + + for (auto &it : extra_coverage_data) { + if (coverage_data.count(it.first)) + log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str()); + coverage_data[it.first].first = it.second.first; + coverage_data[it.first].second += it.second.second; + } + + for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) { + if (coverage_data.count(p->id)) + log("WARNING: found duplicate coverage id \"%s\".\n", p->id); + coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func); + coverage_data[p->id].second += p->counter; + } + + for (auto &it : coverage_data) + if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/")) + it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/")); + + return coverage_data; +} + diff --git a/kernel/log.h b/kernel/log.h index ca1e7c67c..3152fc5af 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -20,15 +20,15 @@ #ifndef LOG_H #define LOG_H -#include "kernel/rtlil.h" -#include "kernel/register.h" - #include #include #include #include #include + +#include #include +#include #define S__LINE__sub2(x) #x #define S__LINE__sub1(x) S__LINE__sub2(x) @@ -59,6 +59,11 @@ void log_pop(); void log_reset_stack(); void log_flush(); +namespace RTLIL { + struct SigSpec; + struct Cell; +} + const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); const char *log_id(std::string id); @@ -96,47 +101,8 @@ extern "C" struct CoverData __stop_yosys_cover_list[]; extern std::map> extra_coverage_data; -static inline void cover_extra(std::string parent, std::string id, bool increment = true) { - if (extra_coverage_data.count(id) == 0) { - for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) - if (p->id == parent) - extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func); - log_assert(extra_coverage_data.count(id)); - } - if (increment) - extra_coverage_data[id].second++; -} - -static inline std::map> get_coverage_data() -{ - std::map> coverage_data; - - for (auto &it : REGISTER_INTERN::pass_register) { - std::string key = stringf("passes.%s", it.first.c_str()); - coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__); - coverage_data[key].second += it.second->call_counter; - } - - for (auto &it : extra_coverage_data) { - if (coverage_data.count(it.first)) - log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str()); - coverage_data[it.first].first = it.second.first; - coverage_data[it.first].second += it.second.second; - } - - for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) { - if (coverage_data.count(p->id)) - log("WARNING: found duplicate coverage id \"%s\".\n", p->id); - coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func); - coverage_data[p->id].second += p->counter; - } - - for (auto &it : coverage_data) - if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/")) - it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/")); - - return coverage_data; -} +void cover_extra(std::string parent, std::string id, bool increment = true); +std::map> get_coverage_data(); #define cover_list(_id, ...) do { cover(_id); \ std::string r = cover_list_worker(_id, __VA_ARGS__); \ @@ -234,9 +200,9 @@ static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false") static inline void log_dump_val_worker(double v) { log("%f", v); } static inline void log_dump_val_worker(const char *v) { log("%s", v); } static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); } -static inline void log_dump_val_worker(RTLIL::SigSpec v) { log("%s", log_signal(v)); } static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); } static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); } +void log_dump_val_worker(RTLIL::SigSpec v); template static inline void log_dump_val_worker(T *ptr) { log("%p", ptr); } diff --git a/kernel/register.cc b/kernel/register.cc index 59667ac97..da3569831 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -20,7 +20,6 @@ #include "kernel/compatibility.h" #include "kernel/register.h" #include "kernel/log.h" -#include #include #include #include @@ -50,7 +49,7 @@ Pass::Pass(std::string name, std::string short_help) : pass_name(name), short_he void Pass::run_register() { - assert(pass_register.count(pass_name) == 0); + log_assert(pass_register.count(pass_name) == 0); pass_register[pass_name] = this; } @@ -67,7 +66,7 @@ void Pass::done_register() frontend_register.clear(); pass_register.clear(); backend_register.clear(); - assert(first_queued_pass == NULL); + log_assert(first_queued_pass == NULL); } Pass::~Pass() @@ -252,10 +251,10 @@ Frontend::Frontend(std::string name, std::string short_help) : Pass("read_"+name void Frontend::run_register() { - assert(pass_register.count(pass_name) == 0); + log_assert(pass_register.count(pass_name) == 0); pass_register[pass_name] = this; - assert(frontend_register.count(frontend_name) == 0); + log_assert(frontend_register.count(frontend_name) == 0); frontend_register[frontend_name] = this; } @@ -265,7 +264,7 @@ Frontend::~Frontend() void Frontend::execute(std::vector args, RTLIL::Design *design) { - assert(next_args.empty()); + log_assert(next_args.empty()); do { FILE *f = NULL; next_args.clear(); @@ -383,10 +382,10 @@ Backend::Backend(std::string name, std::string short_help) : Pass("write_"+name, void Backend::run_register() { - assert(pass_register.count(pass_name) == 0); + log_assert(pass_register.count(pass_name) == 0); pass_register[pass_name] = this; - assert(backend_register.count(backend_name) == 0); + log_assert(backend_register.count(backend_name) == 0); backend_register[backend_name] = this; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 753c40090..783286182 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -23,7 +23,6 @@ #include "frontends/verilog/verilog_frontend.h" #include "backends/ilang/ilang_backend.h" -#include #include #include @@ -238,15 +237,15 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) void RTLIL::Design::add(RTLIL::Module *module) { - assert(modules_.count(module->name) == 0); - assert(refcount_modules_ == 0); + log_assert(modules_.count(module->name) == 0); + log_assert(refcount_modules_ == 0); modules_[module->name] = module; } RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) { - assert(modules_.count(name) == 0); - assert(refcount_modules_ == 0); + log_assert(modules_.count(name) == 0); + log_assert(refcount_modules_ == 0); modules_[name] = new RTLIL::Module; modules_[name]->name = name; return modules_[name]; @@ -254,7 +253,7 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) void RTLIL::Design::remove(RTLIL::Module *module) { - assert(modules_.at(module->name) == module); + log_assert(modules_.at(module->name) == module); modules_.erase(module->name); delete module; } @@ -263,8 +262,8 @@ void RTLIL::Design::check() { #ifndef NDEBUG for (auto &it : modules_) { - assert(it.first == it.second->name); - assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(it.first == it.second->name); + log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); it.second->check(); } #endif @@ -760,57 +759,57 @@ void RTLIL::Module::check() { #ifndef NDEBUG for (auto &it : wires_) { - assert(it.first == it.second->name); - assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); - assert(it.second->width >= 0); - assert(it.second->port_id >= 0); + log_assert(it.first == it.second->name); + log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(it.second->width >= 0); + log_assert(it.second->port_id >= 0); for (auto &it2 : it.second->attributes) { - assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); } } for (auto &it : memories) { - assert(it.first == it.second->name); - assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); - assert(it.second->width >= 0); - assert(it.second->size >= 0); + log_assert(it.first == it.second->name); + log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(it.second->width >= 0); + log_assert(it.second->size >= 0); for (auto &it2 : it.second->attributes) { - assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); } } for (auto &it : cells_) { - assert(it.first == it.second->name); - assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); - assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$')); + log_assert(it.first == it.second->name); + log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$')); for (auto &it2 : it.second->connections()) { - assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); it2.second.check(); } for (auto &it2 : it.second->attributes) { - assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); } for (auto &it2 : it.second->parameters) { - assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); } InternalCellChecker checker(this, it.second); checker.check(); } for (auto &it : processes) { - assert(it.first == it.second->name); - assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(it.first == it.second->name); + log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); // FIXME: More checks here.. } for (auto &it : connections_) { - assert(it.first.size() == it.second.size()); + log_assert(it.first.size() == it.second.size()); it.first.check(); it.second.check(); } for (auto &it : attributes) { - assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); } #endif } @@ -934,7 +933,7 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) { - assert(wires_[wire->name] == wire); + log_assert(wires_[wire->name] == wire); log_assert(refcount_wires_ == 0); wires_.erase(wire->name); wire->name = new_name; @@ -943,7 +942,7 @@ void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name) { - assert(cells_[cell->name] == cell); + log_assert(cells_[cell->name] == cell); log_assert(refcount_wires_ == 0); cells_.erase(cell->name); cell->name = new_name; @@ -952,7 +951,7 @@ void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name) void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name) { - assert(count_id(old_name) != 0); + log_assert(count_id(old_name) != 0); if (wires_.count(old_name)) rename(wires_.at(old_name), new_name); else if (cells_.count(old_name)) @@ -1927,11 +1926,11 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec pattern.unpack(); with.unpack(); - assert(other != NULL); - assert(width_ == other->width_); + log_assert(other != NULL); + log_assert(width_ == other->width_); other->unpack(); - assert(pattern.width_ == with.width_); + log_assert(pattern.width_ == with.width_); std::map pattern_map; for (int i = 0; i < SIZE(pattern.bits_); i++) @@ -1966,7 +1965,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe unpack(); if (other != NULL) { - assert(width_ == other->width_); + log_assert(width_ == other->width_); other->unpack(); } @@ -2005,7 +2004,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigS if (other != NULL) other->pack(); - assert(other == NULL || width_ == other->width_); + log_assert(other == NULL || width_ == other->width_); std::set pat = pattern.to_sigbit_set(); std::vector bits_match = to_sigbit_vector(); @@ -2033,9 +2032,9 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with) unpack(); with.unpack(); - assert(offset >= 0); - assert(with.width_ >= 0); - assert(offset+with.width_ <= width_); + log_assert(offset >= 0); + log_assert(with.width_ >= 0); + log_assert(offset+with.width_ <= width_); for (int i = 0; i < with.width_; i++) bits_.at(offset + i) = with.bits_.at(i); @@ -2085,9 +2084,9 @@ void RTLIL::SigSpec::remove(int offset, int length) unpack(); - assert(offset >= 0); - assert(length >= 0); - assert(offset + length <= width_); + log_assert(offset >= 0); + log_assert(length >= 0); + log_assert(offset + length <= width_); bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length); width_ = bits_.size(); @@ -2236,28 +2235,28 @@ void RTLIL::SigSpec::check() const const RTLIL::SigChunk chunk = chunks_[i]; if (chunk.wire == NULL) { if (i > 0) - assert(chunks_[i-1].wire != NULL); - assert(chunk.offset == 0); - assert(chunk.data.bits.size() == (size_t)chunk.width); + log_assert(chunks_[i-1].wire != NULL); + log_assert(chunk.offset == 0); + log_assert(chunk.data.bits.size() == (size_t)chunk.width); } else { if (i > 0 && chunks_[i-1].wire == chunk.wire) - assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width); - assert(chunk.offset >= 0); - assert(chunk.width >= 0); - assert(chunk.offset + chunk.width <= chunk.wire->width); - assert(chunk.data.bits.size() == 0); + log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width); + log_assert(chunk.offset >= 0); + log_assert(chunk.width >= 0); + log_assert(chunk.offset + chunk.width <= chunk.wire->width); + log_assert(chunk.data.bits.size() == 0); } w += chunk.width; } - assert(w == width_); - assert(bits_.empty()); + log_assert(w == width_); + log_assert(bits_.empty()); } else { cover("kernel.rtlil.sigspec.check.unpacked"); - assert(width_ == SIZE(bits_)); - assert(chunks_.empty()); + log_assert(width_ == SIZE(bits_)); + log_assert(chunks_.empty()); } } #endif @@ -2402,7 +2401,7 @@ bool RTLIL::SigSpec::as_bool() const cover("kernel.rtlil.sigspec.as_bool"); pack(); - assert(is_fully_const() && SIZE(chunks_) <= 1); + log_assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) return chunks_[0].data.as_bool(); return false; @@ -2413,7 +2412,7 @@ int RTLIL::SigSpec::as_int() const cover("kernel.rtlil.sigspec.as_int"); pack(); - assert(is_fully_const() && SIZE(chunks_) <= 1); + log_assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) return chunks_[0].data.as_int(); return 0; @@ -2441,7 +2440,7 @@ RTLIL::Const RTLIL::SigSpec::as_const() const cover("kernel.rtlil.sigspec.as_const"); pack(); - assert(is_fully_const() && SIZE(chunks_) <= 1); + log_assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) return chunks_[0].data; return RTLIL::Const(); @@ -2452,7 +2451,7 @@ RTLIL::Wire *RTLIL::SigSpec::as_wire() const cover("kernel.rtlil.sigspec.as_wire"); pack(); - assert(is_wire()); + log_assert(is_wire()); return chunks_[0].wire; } @@ -2461,7 +2460,7 @@ RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const cover("kernel.rtlil.sigspec.as_chunk"); pack(); - assert(is_chunk()); + log_assert(is_chunk()); return chunks_[0]; } @@ -2471,7 +2470,7 @@ bool RTLIL::SigSpec::match(std::string pattern) const pack(); std::string str = as_string(); - assert(pattern.size() == str.size()); + log_assert(pattern.size() == str.size()); for (size_t i = 0; i < pattern.size(); i++) { if (pattern[i] == ' ') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 331ea3770..d78a6df22 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -24,8 +24,8 @@ #include #include #include -#include +#include "kernel/log.h" #include // various helpers (unrelated to RTLIL) @@ -107,7 +107,7 @@ namespace RTLIL return std::string(*this) < std::string(rhs); } void check() const { - assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\'))); + log_assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\'))); } }; #endif @@ -242,7 +242,7 @@ namespace RTLIL } inline T operator*() const { - assert(list_p != nullptr); + log_assert(list_p != nullptr); return it->second; } @@ -253,7 +253,7 @@ namespace RTLIL } inline void operator++() { - assert(list_p != nullptr); + log_assert(list_p != nullptr); if (++it == list_p->end()) { (*refcount_p)--; list_p = nullptr; @@ -677,9 +677,9 @@ struct RTLIL::SigBit SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { } - SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(wire && wire->width == 1); } - SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { assert(wire); } - SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { assert(chunk.width == 1); } + SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { log_assert(wire && wire->width == 1); } + SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { log_assert(wire); } + SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { log_assert(chunk.width == 1); } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { } SigBit(const RTLIL::SigSpec &sig); @@ -856,7 +856,7 @@ inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const { } inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { - assert(sig.size() == 1 && sig.chunks().size() == 1); + log_assert(sig.size() == 1 && sig.chunks().size() == 1); *this = SigBit(sig.chunks().front()); } diff --git a/kernel/satgen.h b/kernel/satgen.h index 6a288a8da..27a29cb57 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -116,7 +116,7 @@ struct SatGen if (timestep_rhs < 0) timestep_rhs = timestep_lhs; - assert(lhs.size() == rhs.size()); + log_assert(lhs.size() == rhs.size()); std::vector vec_lhs = importSigSpec(lhs, timestep_lhs); std::vector vec_rhs = importSigSpec(rhs, timestep_rhs); @@ -163,14 +163,14 @@ struct SatGen void undefGating(std::vector &vec_y, std::vector &vec_yy, std::vector &vec_undef) { - assert(model_undef); - assert(vec_y.size() == vec_yy.size()); + log_assert(model_undef); + log_assert(vec_y.size() == vec_yy.size()); if (vec_y.size() > vec_undef.size()) { std::vector trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size()); std::vector trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size()); ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy)))); } else { - assert(vec_y.size() == vec_undef.size()); + log_assert(vec_y.size() == vec_undef.size()); ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy)))); } } diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 52e4aa0fb..79a9fb238 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -22,7 +22,6 @@ #include "kernel/rtlil.h" #include "kernel/log.h" -#include #include struct SigPool @@ -67,7 +66,7 @@ struct SigPool void expand(RTLIL::SigSpec from, RTLIL::SigSpec to) { - assert(SIZE(from) == SIZE(to)); + log_assert(SIZE(from) == SIZE(to)); for (int i = 0; i < SIZE(from); i++) { bitDef_t bit_from(from[i]), bit_to(to[i]); if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0) @@ -304,11 +303,11 @@ struct SigMap // internal helper function void merge_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2) { - assert(bit1.wire != NULL && bit2.wire != NULL); + log_assert(bit1.wire != NULL && bit2.wire != NULL); shared_bit_data_t *bd1 = bits[bit1]; shared_bit_data_t *bd2 = bits[bit2]; - assert(bd1 != NULL && bd2 != NULL); + log_assert(bd1 != NULL && bd2 != NULL); if (bd1 == bd2) return; @@ -333,8 +332,8 @@ struct SigMap // internal helper function void set_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2) { - assert(bit1.wire != NULL); - assert(bits.count(bit1) > 0); + log_assert(bit1.wire != NULL); + log_assert(bits.count(bit1) > 0); bits[bit1]->map_to = bit2; } @@ -347,7 +346,7 @@ struct SigMap void add(RTLIL::SigSpec from, RTLIL::SigSpec to) { - assert(SIZE(from) == SIZE(to)); + log_assert(SIZE(from) == SIZE(to)); for (int i = 0; i < SIZE(from); i++) { -- cgit v1.2.3 From 3c45277ee0f5822181c6058f679de632f834e7d2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 12:12:13 +0200 Subject: Added wire->upto flag for signals such as "wire [0:7] x;" --- kernel/rtlil.cc | 2 ++ kernel/rtlil.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 783286182..b562e2afb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1019,6 +1019,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth wire->port_id = other->port_id; wire->port_input = other->port_input; wire->port_output = other->port_output; + wire->upto = other->upto; wire->attributes = other->attributes; return wire; } @@ -1443,6 +1444,7 @@ RTLIL::Wire::Wire() port_id = 0; port_input = false; port_output = false; + upto = false; } RTLIL::Memory::Memory() diff --git a/kernel/rtlil.h b/kernel/rtlil.h index d78a6df22..097af9d28 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -602,7 +602,7 @@ public: RTLIL::IdString name; int width, start_offset, port_id; - bool port_input, port_output; + bool port_input, port_output, upto; RTLIL_ATTRIBUTE_MEMBERS }; -- cgit v1.2.3 From 397b00252dc0c4af725614bd12fc299147ba8efa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 14:42:33 +0200 Subject: Added $shift and $shiftx cell types (needed for correct part select behavior) --- kernel/calc.cc | 43 ++++++++++++++++++++++++++++++++++++++----- kernel/celltypes.h | 6 +++++- kernel/rtlil.cc | 5 ++++- kernel/rtlil.h | 22 ++++++++++++++-------- kernel/satgen.h | 18 ++++++++++++++---- 5 files changed, 75 insertions(+), 19 deletions(-) (limited to 'kernel') diff --git a/kernel/calc.cc b/kernel/calc.cc index b413760d1..b3ff3cf2a 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -276,7 +276,7 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const return result; } -static RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool sign_ext, int direction, int result_len) +static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool sign_ext, int direction, int result_len) { int undef_bit_pos = -1; BigInteger offset = const2big(arg2, false, undef_bit_pos) * direction; @@ -305,28 +305,61 @@ RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2 { RTLIL::Const arg1_ext = arg1; extend_u0(arg1_ext, result_len, signed1); - return const_shift(arg1_ext, arg2, false, -1, result_len); + return const_shift_worker(arg1_ext, arg2, false, -1, result_len); } RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; extend_u0(arg1_ext, result_len, signed1); - return const_shift(arg1_ext, arg2, false, +1, result_len); + return const_shift_worker(arg1_ext, arg2, false, +1, result_len); } RTLIL::Const RTLIL::const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { if (!signed1) return const_shl(arg1, arg2, signed1, signed2, result_len); - return const_shift(arg1, arg2, true, -1, result_len); + return const_shift_worker(arg1, arg2, true, -1, result_len); } RTLIL::Const RTLIL::const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { if (!signed1) return const_shr(arg1, arg2, signed1, signed2, result_len); - return const_shift(arg1, arg2, true, +1, result_len); + return const_shift_worker(arg1, arg2, true, +1, result_len); +} + +static RTLIL::Const const_shift_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool, bool signed2, int result_len, RTLIL::State other_bits) +{ + int undef_bit_pos = -1; + BigInteger offset = const2big(arg2, signed2, undef_bit_pos); + + if (result_len < 0) + result_len = arg1.bits.size(); + + RTLIL::Const result(RTLIL::State::Sx, result_len); + if (undef_bit_pos >= 0) + return result; + + for (int i = 0; i < result_len; i++) { + BigInteger pos = BigInteger(i) + offset; + if (pos < 0 || pos >= arg1.bits.size()) + result.bits[i] = other_bits; + else + result.bits[i] = arg1.bits[pos.toInt()]; + } + + return result; +} + +RTLIL::Const RTLIL::const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) +{ + return const_shift_shiftx(arg1, arg2, signed1, signed2, result_len, RTLIL::State::S0); +} + +RTLIL::Const RTLIL::const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) +{ + return const_shift_shiftx(arg1, arg2, signed1, signed2, result_len, RTLIL::State::Sx); } RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 43c23add3..e1a1110d3 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -75,6 +75,8 @@ struct CellTypes cell_types.insert("$shr"); cell_types.insert("$sshl"); cell_types.insert("$sshr"); + cell_types.insert("$shift"); + cell_types.insert("$shiftx"); cell_types.insert("$lt"); cell_types.insert("$le"); cell_types.insert("$eq"); @@ -224,7 +226,7 @@ struct CellTypes if (type == "$sshl" && !signed1) type = "$shl"; - if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && + if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && type != "$shift" && type != "$shiftx" && type != "$pos" && type != "$neg" && type != "$not" && type != "$bu0") { if (!signed1 || !signed2) signed1 = false, signed2 = false; @@ -248,6 +250,8 @@ struct CellTypes HANDLE_CELL_TYPE(shr) HANDLE_CELL_TYPE(sshl) HANDLE_CELL_TYPE(sshr) + HANDLE_CELL_TYPE(shift) + HANDLE_CELL_TYPE(shiftx) HANDLE_CELL_TYPE(lt) HANDLE_CELL_TYPE(le) HANDLE_CELL_TYPE(eq) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b562e2afb..83bbd7b17 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -474,7 +474,8 @@ namespace { return; } - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { + if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || + cell->type == "$shift" || cell->type == "$shiftx") { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); port("\\A", param("\\A_WIDTH")); @@ -1101,6 +1102,8 @@ DEF_METHOD(Shl, sig_a.size(), "$shl") DEF_METHOD(Shr, sig_a.size(), "$shr") DEF_METHOD(Sshl, sig_a.size(), "$sshl") DEF_METHOD(Sshr, sig_a.size(), "$sshr") +DEF_METHOD(Shift, sig_a.size(), "$shift") +DEF_METHOD(Shiftx, sig_a.size(), "$shiftx") DEF_METHOD(Lt, 1, "$lt") DEF_METHOD(Le, 1, "$le") DEF_METHOD(Eq, 1, "$eq") diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 097af9d28..e8d05e7e4 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -172,6 +172,8 @@ namespace RTLIL RTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + RTLIL::Const const_shift (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + RTLIL::Const const_shiftx (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); @@ -474,10 +476,12 @@ public: RTLIL::Cell* addReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); - RTLIL::Cell* addShl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); - RTLIL::Cell* addShr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); - RTLIL::Cell* addSshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); - RTLIL::Cell* addSshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addShl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addShr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addSshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addSshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addShift (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); + RTLIL::Cell* addShiftx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addLt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addLe (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); @@ -551,10 +555,12 @@ public: RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); RTLIL::SigSpec ReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false); - RTLIL::SigSpec Shl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); - RTLIL::SigSpec Shr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); - RTLIL::SigSpec Sshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); - RTLIL::SigSpec Sshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Shl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Shr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Sshl (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Sshr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Shift (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); + RTLIL::SigSpec Shiftx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); RTLIL::SigSpec Lt (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); RTLIL::SigSpec Le (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false); diff --git a/kernel/satgen.h b/kernel/satgen.h index 27a29cb57..a079b42f0 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -597,7 +597,7 @@ struct SatGen return true; } - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") + if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") { std::vector a = importDefSigSpec(cell->get("\\A"), timestep); std::vector b = importDefSigSpec(cell->get("\\B"), timestep); @@ -605,6 +605,7 @@ struct SatGen char shift_left = cell->type == "$shl" || cell->type == "$sshl"; bool sign_extend = cell->type == "$sshr" && cell->parameters["\\A_SIGNED"].as_bool(); + bool shift_shiftx = cell->type == "$shift" || cell->type == "$shiftx"; while (y.size() < a.size()) y.push_back(ez->literal()); @@ -616,9 +617,13 @@ struct SatGen std::vector tmp = a; for (size_t i = 0; i < b.size(); i++) { + bool shift_left_this = shift_left; + if (shift_shiftx && i == b.size()-1 && cell->parameters["\\B_SIGNED"].as_bool()) + shift_left_this = true; + std::vector tmp_shifted(tmp.size()); for (size_t j = 0; j < tmp.size(); j++) { - int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left ? -1 : +1); + int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left_this ? -1 : +1); tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE; } tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp); @@ -639,10 +644,15 @@ struct SatGen tmp = undef_a; for (size_t i = 0; i < b.size(); i++) { + bool shift_left_this = shift_left; + if (shift_shiftx && i == b.size()-1 && cell->parameters["\\B_SIGNED"].as_bool()) + shift_left_this = true; + std::vector tmp_shifted(tmp.size()); for (size_t j = 0; j < tmp.size(); j++) { - int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left ? -1 : +1); - tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE; + int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left_this ? -1 : +1); + tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : + sign_extend ? tmp.back() : cell->type == "$shiftx" ? ez->TRUE : ez->FALSE; } tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp); } -- cgit v1.2.3 From 03c96f9ce7120adf1c9bab93485a3b4bf6493ae9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 16:06:27 +0200 Subject: Added "techmap -map %{design-name}" --- kernel/rtlil.cc | 5 +++++ kernel/rtlil.h | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 83bbd7b17..f864d88c0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -219,6 +219,11 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) } } +RTLIL::Design::Design() +{ + refcount_modules_ = 0; +} + RTLIL::Design::~Design() { for (auto it = modules_.begin(); it != modules_.end(); it++) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e8d05e7e4..1f25542f3 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -352,11 +352,16 @@ struct RTLIL::Design std::map selection_vars; std::string selected_active_module; + Design(); ~Design(); RTLIL::ObjRange modules(); RTLIL::Module *module(RTLIL::IdString name); + bool has(RTLIL::IdString id) const { + return modules_.count(id) != 0; + } + void add(RTLIL::Module *module); RTLIL::Module *addModule(RTLIL::IdString name); void remove(RTLIL::Module *module); -- cgit v1.2.3 From e6df25bf740b259027541db3543a769ecfc92d4f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 21:12:50 +0200 Subject: Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ --- kernel/register.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index da3569831..4569481fa 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -376,7 +376,9 @@ void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filenam design->check(); } -Backend::Backend(std::string name, std::string short_help) : Pass("write_"+name, short_help), backend_name(name) +Backend::Backend(std::string name, std::string short_help) : + Pass(name.substr(0, 1) == "=" ? name.substr(1) : "write_"+name, short_help), + backend_name(name.substr(0, 1) == "=" ? name.substr(1) : name) { } -- cgit v1.2.3 From 273383692a50490f02a51d0c44ba63b9f557da4e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 22:05:00 +0200 Subject: Added "test_cell" command --- kernel/driver.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index a55fbbed5..2e56f9a33 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -289,7 +289,7 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter) str += "yosys"; if (!design->selected_active_module.empty()) str += stringf(" [%s]", RTLIL::id2cstr(design->selected_active_module)); - if (!design->selection_stack.back().full_selection) { + if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) { if (design->selected_active_module.empty()) str += "*"; else if (design->selection_stack.back().selected_modules.size() != 1 || design->selection_stack.back().selected_members.size() != 0 || -- cgit v1.2.3 From a7c6b37abf3e4628dd921bb12f77987d1f94c45f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 Jul 2014 14:10:15 +0200 Subject: Added "kernel/yosys.h" and "kernel/yosys.cc" --- kernel/driver.cc | 4 +-- kernel/log.cc | 24 +--------------- kernel/log.h | 6 ++-- kernel/register.h | 18 ------------ kernel/rtlil.h | 14 ++------- kernel/yosys.cc | 40 ++++++++++++++++++++++++++ kernel/yosys.h | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 132 insertions(+), 60 deletions(-) create mode 100644 kernel/yosys.cc create mode 100644 kernel/yosys.h (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 2e56f9a33..c20be1dc1 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -30,9 +30,7 @@ #include #include -#include "kernel/rtlil.h" -#include "kernel/register.h" -#include "kernel/log.h" +#include "kernel/yosys.h" bool fgetline(FILE *f, std::string &buffer) { diff --git a/kernel/log.cc b/kernel/log.cc index 8036b2360..5fe0d0863 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -17,10 +17,7 @@ * */ -#include "kernel/log.h" -#include "kernel/rtlil.h" -#include "kernel/register.h" -#include "kernel/compatibility.h" +#include "kernel/yosys.h" #include "backends/ilang/ilang_backend.h" #include @@ -43,25 +40,6 @@ std::list string_buf; static struct timeval initial_tv = { 0, 0 }; static bool next_print_log = false; -std::string stringf(const char *fmt, ...) -{ - std::string string; - char *str = NULL; - va_list ap; - - va_start(ap, fmt); - if (vasprintf(&str, fmt, ap) < 0) - str = NULL; - va_end(ap); - - if (str != NULL) { - string = str; - free(str); - } - - return string; -} - void logv(const char *format, va_list ap) { if (log_time) { diff --git a/kernel/log.h b/kernel/log.h index 3152fc5af..803365b39 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -17,6 +17,8 @@ * */ +#include "kernel/yosys.h" + #ifndef LOG_H #define LOG_H @@ -26,10 +28,6 @@ #include #include -#include -#include -#include - #define S__LINE__sub2(x) #x #define S__LINE__sub1(x) S__LINE__sub2(x) #define S__LINE__ S__LINE__sub1(__LINE__) diff --git a/kernel/register.h b/kernel/register.h index 73875e968..68f09c822 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -26,24 +26,6 @@ #include #include -#ifdef YOSYS_ENABLE_TCL -#include -extern Tcl_Interp *yosys_get_tcl_interp(); -#endif - -// from kernel/version_*.o (cc source generated from Makefile) -extern const char *yosys_version_str; - -// implemented in driver.cc -extern RTLIL::Design *yosys_get_design(); -extern std::string proc_self_dirname(); -extern std::string proc_share_dirname(); -extern const char *create_prompt(RTLIL::Design *design, int recursion_counter); - -// from passes/cmds/design.cc -extern std::map saved_designs; -extern std::vector pushed_designs; - struct Pass { std::string pass_name, short_help; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1f25542f3..d6acb5bcc 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -17,21 +17,11 @@ * */ +#include "kernel/yosys.h" + #ifndef RTLIL_H #define RTLIL_H -#include -#include -#include -#include - -#include "kernel/log.h" -#include - -// various helpers (unrelated to RTLIL) -std::string stringf(const char *fmt, ...); -#define SIZE(__obj) int(__obj.size()) - namespace RTLIL { enum State : unsigned char { diff --git a/kernel/yosys.cc b/kernel/yosys.cc new file mode 100644 index 000000000..d25443826 --- /dev/null +++ b/kernel/yosys.cc @@ -0,0 +1,40 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" + +std::string stringf(const char *fmt, ...) +{ + std::string string; + char *str = NULL; + va_list ap; + + va_start(ap, fmt); + if (vasprintf(&str, fmt, ap) < 0) + str = NULL; + va_end(ap); + + if (str != NULL) { + string = str; + free(str); + } + + return string; +} + diff --git a/kernel/yosys.h b/kernel/yosys.h new file mode 100644 index 000000000..67629d9b1 --- /dev/null +++ b/kernel/yosys.h @@ -0,0 +1,86 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + + +// *** NOTE TO THE READER *** +// +// Maybe you have just opened this file in the hope to learn more about the +// Yosys API. Let me congratulate you on this great decision! ;) +// +// If you want to know how the design is represented by Yosys in the memory, +// you should read "kernel/rtlil.h". +// +// If you want to know how to register a command with Yosys, you could read +// "kernel/register.h", but it would be easier to just look at a simple +// example instead. A simple one would be "passes/cmds/log.cc". + + +#ifndef YOSYS_H +#define YOSYS_H + +#include +#include +#include +#include +#include + +#if 0 +# define YOSYS_NAMESPACE_BEGIN namespace Yosys { +# define YOSYS_NAMESPACE_END } +#else +# define YOSYS_NAMESPACE_BEGIN +# define YOSYS_NAMESPACE_END +#endif + +YOSYS_NAMESPACE_BEGIN + +std::string stringf(const char *fmt, ...); + +#define SIZE(__obj) int(__obj.size()) + +YOSYS_NAMESPACE_END + +#include "kernel/log.h" +#include "kernel/rtlil.h" +#include "kernel/register.h" +#include "kernel/compatibility.h" + +YOSYS_NAMESPACE_BEGIN + +#ifdef YOSYS_ENABLE_TCL +#include +extern Tcl_Interp *yosys_get_tcl_interp(); +#endif + +// from kernel/version_*.o (cc source generated from Makefile) +extern const char *yosys_version_str; + +// implemented in driver.cc +extern RTLIL::Design *yosys_get_design(); +extern std::string proc_self_dirname(); +extern std::string proc_share_dirname(); +extern const char *create_prompt(RTLIL::Design *design, int recursion_counter); + +// from passes/cmds/design.cc +extern std::map saved_designs; +extern std::vector pushed_designs; + +YOSYS_NAMESPACE_END + +#endif -- cgit v1.2.3 From 45fd26b76e1ca72927ab0a8ce207aab0d024eba3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 Jul 2014 15:58:21 +0200 Subject: Added "log_dump_val_worker(char *v)" --- kernel/log.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index 803365b39..a491d067d 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -196,6 +196,7 @@ static inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? "'%c'" static inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? "'%c'" : "'\\x%02x'", c); } static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false"); } static inline void log_dump_val_worker(double v) { log("%f", v); } +static inline void log_dump_val_worker(char *v) { log("%s", v); } static inline void log_dump_val_worker(const char *v) { log("%s", v); } static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); } static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); } -- cgit v1.2.3 From 3f0a5746ef0940accb5fd14d97804c75c0531c0b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 Jul 2014 17:18:31 +0200 Subject: Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models --- kernel/satgen.h | 75 ++++++++++++++++++++++++++++++--------------------------- 1 file changed, 39 insertions(+), 36 deletions(-) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index a079b42f0..ce2c90280 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -603,63 +603,66 @@ struct SatGen std::vector b = importDefSigSpec(cell->get("\\B"), timestep); std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); - char shift_left = cell->type == "$shl" || cell->type == "$sshl"; - bool sign_extend = cell->type == "$sshr" && cell->parameters["\\A_SIGNED"].as_bool(); - bool shift_shiftx = cell->type == "$shift" || cell->type == "$shiftx"; + int extend_bit = ez->FALSE; + + if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool()) + extend_bit = a.back(); while (y.size() < a.size()) y.push_back(ez->literal()); while (y.size() > a.size()) - a.push_back(cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->FALSE); + a.push_back(extend_bit); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; + std::vector shifted_a; - std::vector tmp = a; - for (size_t i = 0; i < b.size(); i++) - { - bool shift_left_this = shift_left; - if (shift_shiftx && i == b.size()-1 && cell->parameters["\\B_SIGNED"].as_bool()) - shift_left_this = true; - - std::vector tmp_shifted(tmp.size()); - for (size_t j = 0; j < tmp.size(); j++) { - int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left_this ? -1 : +1); - tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE; - } - tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp); - } - ez->assume(ez->vec_eq(tmp, yy)); + if (cell->type == "$shl" || cell->type == "$sshl") + shifted_a = ez->vec_shift_left(a, b, false, ez->FALSE, ez->FALSE); + + if (cell->type == "$shr") + shifted_a = ez->vec_shift_right(a, b, false, ez->FALSE, ez->FALSE); + + if (cell->type == "$sshr") + shifted_a = ez->vec_shift_right(a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->FALSE, ez->FALSE); + + if (cell->type == "$shift" || cell->type == "$shiftx") + shifted_a = ez->vec_shift_right(a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE); + + ez->assume(ez->vec_eq(shifted_a, yy)); if (model_undef) { std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a_shifted; + + if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool()) + extend_bit = undef_a.back(); while (undef_y.size() < undef_a.size()) undef_y.push_back(ez->literal()); while (undef_y.size() > undef_a.size()) - undef_a.push_back(cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE); + undef_a.push_back(extend_bit); - tmp = undef_a; - for (size_t i = 0; i < b.size(); i++) - { - bool shift_left_this = shift_left; - if (shift_shiftx && i == b.size()-1 && cell->parameters["\\B_SIGNED"].as_bool()) - shift_left_this = true; - - std::vector tmp_shifted(tmp.size()); - for (size_t j = 0; j < tmp.size(); j++) { - int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left_this ? -1 : +1); - tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : - sign_extend ? tmp.back() : cell->type == "$shiftx" ? ez->TRUE : ez->FALSE; - } - tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp); - } + if (cell->type == "$shl" || cell->type == "$sshl") + undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->FALSE, ez->FALSE); + + if (cell->type == "$shr") + undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->FALSE, ez->FALSE); + + if (cell->type == "$sshr") + undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE, ez->FALSE); + + if (cell->type == "$shift") + undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE); + + if (cell->type == "$shiftx") + undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->TRUE, ez->TRUE); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); std::vector undef_all_y_bits(undef_y.size(), undef_any_b); - ez->assume(ez->vec_eq(ez->vec_or(tmp, undef_all_y_bits), undef_y)); + ez->assume(ez->vec_eq(ez->vec_or(undef_a_shifted, undef_all_y_bits), undef_y)); undefGating(y, yy, undef_y); } return true; -- cgit v1.2.3 From 6400ae36489a7ada5419d7bc502934f6d05e69bb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 Jul 2014 19:59:29 +0200 Subject: Added write_file command --- kernel/register.cc | 8 +++++--- kernel/register.h | 4 ++-- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 4569481fa..c7bd2cce7 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -245,7 +245,9 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vec design->selected_active_module = backup_selected_active_module; } -Frontend::Frontend(std::string name, std::string short_help) : Pass("read_"+name, short_help), frontend_name(name) +Frontend::Frontend(std::string name, std::string short_help) : + Pass(name.rfind("=", 0) == 0 ? name.substr(1) : "read_" + name, short_help), + frontend_name(name.rfind("=", 0) == 0 ? name.substr(1) : name) { } @@ -377,8 +379,8 @@ void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filenam } Backend::Backend(std::string name, std::string short_help) : - Pass(name.substr(0, 1) == "=" ? name.substr(1) : "write_"+name, short_help), - backend_name(name.substr(0, 1) == "=" ? name.substr(1) : name) + Pass(name.rfind("=", 0) == 0 ? name.substr(1) : "write_" + name, short_help), + backend_name(name.rfind("=", 0) == 0 ? name.substr(1) : name) { } diff --git a/kernel/register.h b/kernel/register.h index 68f09c822..41780bfb9 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -66,7 +66,7 @@ struct Frontend : Pass Frontend(std::string name, std::string short_help = "** document me **"); virtual void run_register(); virtual ~Frontend(); - virtual void execute(std::vector args, RTLIL::Design *design); + virtual void execute(std::vector args, RTLIL::Design *design) override final; virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; static std::vector next_args; @@ -82,7 +82,7 @@ struct Backend : Pass Backend(std::string name, std::string short_help = "** document me **"); virtual void run_register(); virtual ~Backend(); - virtual void execute(std::vector args, RTLIL::Design *design); + virtual void execute(std::vector args, RTLIL::Design *design) override final; virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; void extra_args(FILE *&f, std::string &filename, std::vector args, size_t argidx); -- cgit v1.2.3 From 254148910556d057ec296e4f8c44e92bdb8c09a3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 Jul 2014 22:04:30 +0200 Subject: Added techmap CONSTMAP feature --- kernel/rtlil.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index d6acb5bcc..7bd75bd1d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -278,6 +278,9 @@ namespace RTLIL result.push_back(it.second); return result; } + + std::set to_set() const { return *this; } + std::vector to_vector() const { return *this; } }; }; -- cgit v1.2.3 From e5c245df9d086595063978298139a9aaed68979d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 00:53:21 +0200 Subject: Added "yosys -Q" --- kernel/driver.cc | 61 ++++++++++++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 26 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index c20be1dc1..ab8ecba9d 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -555,6 +555,7 @@ int main(int argc, char **argv) std::string scriptfile = ""; bool scriptfile_tcl = false; bool got_output_filename = false; + bool print_banner = true; int history_offset = 0; std::string history_file; @@ -565,10 +566,13 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "VSm:f:Hh:b:o:p:l:qv:ts:c:")) != -1) + while ((opt = getopt(argc, argv, "QVSm:f:Hh:b:o:p:l:qv:ts:c:")) != -1) { switch (opt) { + case 'Q': + print_banner = false; + break; case 'V': printf("%s\n", yosys_version_str); exit(0); @@ -634,9 +638,12 @@ int main(int argc, char **argv) break; default: fprintf(stderr, "\n"); - fprintf(stderr, "Usage: %s [-V] [-S] [-q] [-v [-t] [-l ] [-o ] [-f ] [-h cmd] \\\n", argv[0]); + fprintf(stderr, "Usage: %s [-V -S -Q -q] [-v [-t] [-l ] [-o ] [-f ] [-h cmd] \\\n", argv[0]); fprintf(stderr, " %*s[{-s|-c} ] [-p [-p ..]] [-b ] [-m ] [ [..]]\n", int(strlen(argv[0])+1), ""); fprintf(stderr, "\n"); + fprintf(stderr, " -Q\n"); + fprintf(stderr, " suppress printing of banner (copyright, disclaimer, version)\n"); + fprintf(stderr, "\n"); fprintf(stderr, " -q\n"); fprintf(stderr, " quiet operation. only write error messages to console\n"); fprintf(stderr, "\n"); @@ -699,29 +706,31 @@ int main(int argc, char **argv) if (log_errfile == NULL) log_files.push_back(stderr); - log("\n"); - log(" /-----------------------------------------------------------------------------\\\n"); - log(" | |\n"); - log(" | yosys -- Yosys Open SYnthesis Suite |\n"); - log(" | |\n"); - log(" | Copyright (C) 2012 Clifford Wolf |\n"); - log(" | |\n"); - log(" | Permission to use, copy, modify, and/or distribute this software for any |\n"); - log(" | purpose with or without fee is hereby granted, provided that the above |\n"); - log(" | copyright notice and this permission notice appear in all copies. |\n"); - log(" | |\n"); - log(" | THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |\n"); - log(" | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |\n"); - log(" | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |\n"); - log(" | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |\n"); - log(" | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |\n"); - log(" | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |\n"); - log(" | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |\n"); - log(" | |\n"); - log(" \\-----------------------------------------------------------------------------/\n"); - log("\n"); - log(" %s\n", yosys_version_str); - log("\n"); + if (print_banner) { + log("\n"); + log(" /-----------------------------------------------------------------------------\\\n"); + log(" | |\n"); + log(" | yosys -- Yosys Open SYnthesis Suite |\n"); + log(" | |\n"); + log(" | Copyright (C) 2012 Clifford Wolf |\n"); + log(" | |\n"); + log(" | Permission to use, copy, modify, and/or distribute this software for any |\n"); + log(" | purpose with or without fee is hereby granted, provided that the above |\n"); + log(" | copyright notice and this permission notice appear in all copies. |\n"); + log(" | |\n"); + log(" | THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |\n"); + log(" | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |\n"); + log(" | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |\n"); + log(" | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |\n"); + log(" | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |\n"); + log(" | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |\n"); + log(" | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |\n"); + log(" | |\n"); + log(" \\-----------------------------------------------------------------------------/\n"); + log("\n"); + log(" %s\n", yosys_version_str); + log("\n"); + } Pass::init_register(); @@ -785,7 +794,7 @@ int main(int argc, char **argv) } #endif - log("\nREADY.\n"); + log("\nEnd of script.\n"); log_pop(); if (!history_file.empty()) { -- cgit v1.2.3 From 6166c768313f6a2dee774f0ba0a531816b24502d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 01:05:27 +0200 Subject: Added "yosys -A" --- kernel/driver.cc | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index ab8ecba9d..d9ef22238 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -556,6 +556,7 @@ int main(int argc, char **argv) bool scriptfile_tcl = false; bool got_output_filename = false; bool print_banner = true; + bool call_abort = false; int history_offset = 0; std::string history_file; @@ -566,10 +567,13 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "QVSm:f:Hh:b:o:p:l:qv:ts:c:")) != -1) + while ((opt = getopt(argc, argv, "AQVSm:f:Hh:b:o:p:l:qv:ts:c:")) != -1) { switch (opt) { + case 'A': + call_abort = true; + break; case 'Q': print_banner = false; break; @@ -683,6 +687,9 @@ int main(int argc, char **argv) fprintf(stderr, " -m module_file\n"); fprintf(stderr, " load the specified module (aka plugin)\n"); fprintf(stderr, "\n"); + fprintf(stderr, " -A\n"); + fprintf(stderr, " will call abort() at the end of the script. useful for debugging\n"); + fprintf(stderr, "\n"); fprintf(stderr, " -V\n"); fprintf(stderr, " print version information and exit\n"); fprintf(stderr, "\n"); @@ -795,6 +802,8 @@ int main(int argc, char **argv) #endif log("\nEnd of script.\n"); + if (call_abort) + abort(); log_pop(); if (!history_file.empty()) { -- cgit v1.2.3 From 1cb25c05b37b0172dbc50e140fe20f25d973dd8a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 13:19:47 +0200 Subject: Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace --- kernel/calc.cc | 7 +- kernel/driver.cc | 546 +-------------------------------------------------- kernel/log.cc | 6 +- kernel/log.h | 6 +- kernel/register.cc | 34 ++-- kernel/register.h | 14 +- kernel/rtlil.cc | 8 +- kernel/rtlil.h | 18 +- kernel/sigtools.h | 8 +- kernel/yosys.cc | 565 +++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/yosys.h | 38 +++- 11 files changed, 653 insertions(+), 597 deletions(-) (limited to 'kernel') diff --git a/kernel/calc.cc b/kernel/calc.cc index b3ff3cf2a..29717aad5 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -21,10 +21,11 @@ // Schneier, Bruce (1996). Applied Cryptography: Protocols, Algorithms, and Source Code in C, // Second Edition (2nd ed.). Wiley. ISBN 978-0-471-11709-4, page 244 -#include "kernel/log.h" -#include "kernel/rtlil.h" +#include "kernel/yosys.h" #include "libs/bigint/BigIntegerLibrary.hh" +YOSYS_NAMESPACE_BEGIN + static void extend(RTLIL::Const &arg, int width, bool is_signed) { RTLIL::State padding = RTLIL::State::S0; @@ -592,3 +593,5 @@ RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, boo return RTLIL::const_sub(zero, arg1_ext, false, signed1, result_len); } +YOSYS_NAMESPACE_END + diff --git a/kernel/driver.cc b/kernel/driver.cc index d9ef22238..01ade7d46 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -17,9 +17,12 @@ * */ -#include +#include "kernel/yosys.h" + #include #include + +#include #include #include #include @@ -27,523 +30,7 @@ #include #include -#include -#include - -#include "kernel/yosys.h" - -bool fgetline(FILE *f, std::string &buffer) -{ - buffer = ""; - char block[4096]; - while (1) { - if (fgets(block, 4096, f) == NULL) - return false; - buffer += block; - if (buffer.size() > 0 && (buffer[buffer.size()-1] == '\n' || buffer[buffer.size()-1] == '\r')) { - while (buffer.size() > 0 && (buffer[buffer.size()-1] == '\n' || buffer[buffer.size()-1] == '\r')) - buffer.resize(buffer.size()-1); - return true; - } - } -} - -static void handle_label(std::string &command, bool &from_to_active, const std::string &run_from, const std::string &run_to) -{ - int pos = 0; - std::string label; - - while (pos < SIZE(command) && (command[pos] == ' ' || command[pos] == '\t')) - pos++; - - while (pos < SIZE(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n') - label += command[pos++]; - - if (label.back() == ':' && SIZE(label) > 1) - { - label = label.substr(0, SIZE(label)-1); - command = command.substr(pos); - - if (label == run_from) - from_to_active = true; - else if (label == run_to || (run_from == run_to && !run_from.empty())) - from_to_active = false; - } -} - -static void run_frontend(std::string filename, std::string command, RTLIL::Design *design, std::string *backend_command, std::string *from_to_label) -{ - if (command == "auto") { - if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") - command = "verilog"; - else if (filename.size() > 2 && filename.substr(filename.size()-3) == ".sv") - command = "verilog -sv"; - else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") - command = "ilang"; - else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".ys") - command = "script"; - else if (filename == "-") - command = "script"; - else - log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str()); - } - - if (command == "script") - { - std::string run_from, run_to; - bool from_to_active = true; - - if (from_to_label != NULL) { - size_t pos = from_to_label->find(':'); - if (pos == std::string::npos) { - run_from = *from_to_label; - run_to = *from_to_label; - } else { - run_from = from_to_label->substr(0, pos); - run_to = from_to_label->substr(pos+1); - } - from_to_active = run_from.empty(); - } - - log("\n-- Executing script file `%s' --\n", filename.c_str()); - - FILE *f = stdin; - - if (filename != "-") - f = fopen(filename.c_str(), "r"); - - if (f == NULL) - log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); - - FILE *backup_script_file = Frontend::current_script_file; - Frontend::current_script_file = f; - - try { - std::string command; - while (fgetline(f, command)) { - while (!command.empty() && command[command.size()-1] == '\\') { - std::string next_line; - if (!fgetline(f, next_line)) - break; - command.resize(command.size()-1); - command += next_line; - } - handle_label(command, from_to_active, run_from, run_to); - if (from_to_active) - Pass::call(design, command); - } - - if (!command.empty()) { - handle_label(command, from_to_active, run_from, run_to); - if (from_to_active) - Pass::call(design, command); - } - } - catch (log_cmd_error_expection) { - Frontend::current_script_file = backup_script_file; - throw log_cmd_error_expection(); - } - - Frontend::current_script_file = backup_script_file; - - if (filename != "-") - fclose(f); - - if (backend_command != NULL && *backend_command == "auto") - *backend_command = ""; - - return; - } - - if (filename == "-") { - log("\n-- Parsing stdin using frontend `%s' --\n", command.c_str()); - } else { - log("\n-- Parsing `%s' using frontend `%s' --\n", filename.c_str(), command.c_str()); - } - - Frontend::frontend_call(design, NULL, filename, command); -} - -static void run_pass(std::string command, RTLIL::Design *design) -{ - log("\n-- Running pass `%s' --\n", command.c_str()); - - Pass::call(design, command); -} - -static void run_backend(std::string filename, std::string command, RTLIL::Design *design) -{ - if (command == "auto") { - if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") - command = "verilog"; - else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") - command = "ilang"; - else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif") - command = "blif"; - else if (filename == "-") - command = "ilang"; - else if (filename.empty()) - return; - else - log_error("Can't guess backend for output file `%s' (missing -b option)!\n", filename.c_str()); - } - - if (filename.empty()) - filename = "-"; - - if (filename == "-") { - log("\n-- Writing to stdout using backend `%s' --\n", command.c_str()); - } else { - log("\n-- Writing to `%s' using backend `%s' --\n", filename.c_str(), command.c_str()); - } - - Backend::backend_call(design, NULL, filename, command); -} - -static char *readline_cmd_generator(const char *text, int state) -{ - static std::map::iterator it; - static int len; - - if (!state) { - it = REGISTER_INTERN::pass_register.begin(); - len = strlen(text); - } - - for (; it != REGISTER_INTERN::pass_register.end(); it++) { - if (it->first.substr(0, len) == text) - return strdup((it++)->first.c_str()); - } - return NULL; -} - -static char *readline_obj_generator(const char *text, int state) -{ - static std::vector obj_names; - static size_t idx; - - if (!state) - { - idx = 0; - obj_names.clear(); - - RTLIL::Design *design = yosys_get_design(); - int len = strlen(text); - - if (design->selected_active_module.empty()) - { - for (auto &it : design->modules_) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); - } - else - if (design->modules_.count(design->selected_active_module) > 0) - { - RTLIL::Module *module = design->modules_.at(design->selected_active_module); - - for (auto &it : module->wires_) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); - - for (auto &it : module->memories) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); - - for (auto &it : module->cells_) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); - - for (auto &it : module->processes) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); - } - - std::sort(obj_names.begin(), obj_names.end()); - } - - if (idx < obj_names.size()) - return strdup(obj_names[idx++]); - - idx = 0; - obj_names.clear(); - return NULL; -} - -static char **readline_completion(const char *text, int start, int) -{ - if (start == 0) - return rl_completion_matches(text, readline_cmd_generator); - if (strncmp(rl_line_buffer, "read_", 5) && strncmp(rl_line_buffer, "write_", 6)) - return rl_completion_matches(text, readline_obj_generator); - return NULL; -} - -const char *create_prompt(RTLIL::Design *design, int recursion_counter) -{ - static char buffer[100]; - std::string str = "\n"; - if (recursion_counter > 1) - str += stringf("(%d) ", recursion_counter); - str += "yosys"; - if (!design->selected_active_module.empty()) - str += stringf(" [%s]", RTLIL::id2cstr(design->selected_active_module)); - if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) { - if (design->selected_active_module.empty()) - str += "*"; - else if (design->selection_stack.back().selected_modules.size() != 1 || design->selection_stack.back().selected_members.size() != 0 || - design->selection_stack.back().selected_modules.count(design->selected_active_module) == 0) - str += "*"; - } - snprintf(buffer, 100, "%s> ", str.c_str()); - return buffer; -} - -static void shell(RTLIL::Design *design) -{ - static int recursion_counter = 0; - - recursion_counter++; - log_cmd_error_throw = true; - - rl_readline_name = "yosys"; - rl_attempted_completion_function = readline_completion; - rl_basic_word_break_characters = " \t\n"; - - char *command = NULL; - while ((command = readline(create_prompt(design, recursion_counter))) != NULL) - { - if (command[strspn(command, " \t\r\n")] == 0) - continue; - add_history(command); - - char *p = command + strspn(command, " \t\r\n"); - if (!strncmp(p, "exit", 4)) { - p += 4; - p += strspn(p, " \t\r\n"); - if (*p == 0) - break; - } - - try { - log_assert(design->selection_stack.size() == 1); - Pass::call(design, command); - } catch (log_cmd_error_expection) { - while (design->selection_stack.size() > 1) - design->selection_stack.pop_back(); - log_reset_stack(); - } - } - if (command == NULL) - printf("exit\n"); - - recursion_counter--; - log_cmd_error_throw = false; -} - -struct ShellPass : public Pass { - ShellPass() : Pass("shell", "enter interactive command mode") { } - virtual void help() { - log("\n"); - log(" shell\n"); - log("\n"); - log("This command enters the interactive command mode. This can be useful\n"); - log("in a script to interrupt the script at a certain point and allow for\n"); - log("interactive inspection or manual synthesis of the design at this point.\n"); - log("\n"); - log("The command prompt of the interactive shell indicates the current\n"); - log("selection (see 'help select'):\n"); - log("\n"); - log(" yosys>\n"); - log(" the entire design is selected\n"); - log("\n"); - log(" yosys*>\n"); - log(" only part of the design is selected\n"); - log("\n"); - log(" yosys [modname]>\n"); - log(" the entire module 'modname' is selected using 'select -module modname'\n"); - log("\n"); - log(" yosys [modname]*>\n"); - log(" only part of current module 'modname' is selected\n"); - log("\n"); - log("When in interactive shell, some errors (e.g. invalid command arguments)\n"); - log("do not terminate yosys but return to the command prompt.\n"); - log("\n"); - log("This command is the default action if nothing else has been specified\n"); - log("on the command line.\n"); - log("\n"); - log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n"); - log("\n"); - } - virtual void execute(std::vector args, RTLIL::Design *design) { - extra_args(args, 1, design, false); - shell(design); - } -} ShellPass; - -struct HistoryPass : public Pass { - HistoryPass() : Pass("history", "show last interactive commands") { } - virtual void help() { - log("\n"); - log(" history\n"); - log("\n"); - log("This command prints all commands in the shell history buffer. This are\n"); - log("all commands executed in an interactive session, but not the commands\n"); - log("from executed scripts.\n"); - log("\n"); - } - virtual void execute(std::vector args, RTLIL::Design *design) { - extra_args(args, 1, design, false); - for(HIST_ENTRY **list = history_list(); *list != NULL; list++) - log("%s\n", (*list)->line); - } -} HistoryPass; - -struct ScriptPass : public Pass { - ScriptPass() : Pass("script", "execute commands from script file") { } - virtual void help() { - log("\n"); - log(" script [:]\n"); - log("\n"); - log("This command executes the yosys commands in the specified file.\n"); - log("\n"); - log("The 2nd argument can be used to only execute the section of the\n"); - log("file between the specified labels. An empty from label is synonymous\n"); - log("for the beginning of the file and an empty to label is synonymous\n"); - log("for the end of the file.\n"); - log("\n"); - log("If only one label is specified (without ':') then only the block\n"); - log("marked with that label (until the next label) is executed.\n"); - log("\n"); - } - virtual void execute(std::vector args, RTLIL::Design *design) { - if (args.size() < 2) - log_cmd_error("Missing script file.\n"); - else if (args.size() == 2) - run_frontend(args[1], "script", design, NULL, NULL); - else if (args.size() == 3) - run_frontend(args[1], "script", design, NULL, &args[2]); - else - extra_args(args, 2, design, false); - } -} ScriptPass; - -#ifdef YOSYS_ENABLE_TCL -static Tcl_Interp *yosys_tcl_interp = NULL; - -static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *argv[]) -{ - std::vector args; - for (int i = 1; i < argc; i++) - args.push_back(argv[i]); - - if (args.size() >= 1 && args[0] == "-import") { - for (auto &it : REGISTER_INTERN::pass_register) { - std::string tcl_command_name = it.first; - if (tcl_command_name == "proc") - tcl_command_name = "procs"; - Tcl_CmdInfo info; - if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) { - log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str()); - } else { - std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name.c_str(), it.first.c_str()); - Tcl_Eval(interp, tcl_script.c_str()); - } - } - return TCL_OK; - } - - if (args.size() == 1) { - Pass::call(yosys_get_design(), args[0]); - return TCL_OK; - } - - Pass::call(yosys_get_design(), args); - return TCL_OK; -} - -extern Tcl_Interp *yosys_get_tcl_interp() -{ - if (yosys_tcl_interp == NULL) { - yosys_tcl_interp = Tcl_CreateInterp(); - Tcl_CreateCommand(yosys_tcl_interp, "yosys", tcl_yosys_cmd, NULL, NULL); - } - return yosys_tcl_interp; -} - -struct TclPass : public Pass { - TclPass() : Pass("tcl", "execute a TCL script file") { } - virtual void help() { - log("\n"); - log(" tcl \n"); - log("\n"); - log("This command executes the tcl commands in the specified file.\n"); - log("Use 'yosys cmd' to run the yosys command 'cmd' from tcl.\n"); - log("\n"); - log("The tcl command 'yosys -import' can be used to import all yosys\n"); - log("commands directly as tcl commands to the tcl shell. The yosys\n"); - log("command 'proc' is wrapped using the tcl command 'procs' in order\n"); - log("to avoid a name collision with the tcl builting command 'proc'.\n"); - log("\n"); - } - virtual void execute(std::vector args, RTLIL::Design *design) { - if (args.size() < 2) - log_cmd_error("Missing script file.\n"); - if (args.size() > 2) - extra_args(args, 1, design, false); - if (Tcl_EvalFile(yosys_get_tcl_interp(), args[1].c_str()) != TCL_OK) - log_cmd_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp())); - } -} TclPass; -#endif - -static RTLIL::Design *yosys_design = NULL; - -extern RTLIL::Design *yosys_get_design() -{ - return yosys_design; -} - -#if defined(__linux__) -std::string proc_self_dirname () -{ - char path [PATH_MAX]; - ssize_t buflen = readlink("/proc/self/exe", path, sizeof(path)); - if (buflen < 0) { - log_cmd_error("readlink(\"/proc/self/exe\") failed: %s", strerror(errno)); - log_abort(); - } - while (buflen > 0 && path[buflen-1] != '/') - buflen--; - return std::string(path, buflen); -} -#elif defined(__APPLE__) -#include -std::string proc_self_dirname () -{ - char * path = NULL; - uint32_t buflen = 0; - while (_NSGetExecutablePath(path, &buflen) != 0) - path = (char *) realloc((void *) path, buflen); - while (buflen > 0 && path[buflen-1] != '/') - buflen--; - return std::string(path, buflen); -} -#else - #error Dont know how to determine process executable base path! -#endif - -std::string proc_share_dirname () -{ - std::string proc_self_path = proc_self_dirname(); - std::string proc_share_path = proc_self_path + "share/"; - if (access(proc_share_path.c_str(), X_OK) == 0) - return proc_share_path; - proc_share_path = proc_self_path + "../share/yosys/"; - if (access(proc_share_path.c_str(), X_OK) == 0) - return proc_share_path; - log_cmd_error("proc_share_dirname: unable to determine share/ directory!"); - log_abort(); -} +USING_YOSYS_NAMESPACE int main(int argc, char **argv) { @@ -739,11 +226,7 @@ int main(int argc, char **argv) log("\n"); } - Pass::init_register(); - - yosys_design = new RTLIL::Design; - yosys_design->selection_stack.push_back(RTLIL::Selection()); - log_push(); + yosys_setup(); if (optind == argc && passes_commands.size() == 0 && scriptfile.empty()) { if (!got_output_filename) @@ -804,7 +287,6 @@ int main(int argc, char **argv) log("\nEnd of script.\n"); if (call_abort) abort(); - log_pop(); if (!history_file.empty()) { if (history_offset > 0) { @@ -819,25 +301,11 @@ int main(int argc, char **argv) if (hist_list != NULL) free(hist_list); - for (auto f : log_files) - if (f != stderr) - fclose(f); - log_errfile = NULL; - log_files.clear(); - - Pass::done_register(); + yosys_shutdown(); for (auto mod : loaded_modules) dlclose(mod); -#ifdef YOSYS_ENABLE_TCL - if (yosys_tcl_interp != NULL) { - Tcl_DeleteInterp(yosys_tcl_interp); - Tcl_Finalize(); - yosys_tcl_interp = NULL; - } -#endif - return 0; } diff --git a/kernel/log.cc b/kernel/log.cc index 5fe0d0863..64dd7a92a 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -28,6 +28,8 @@ #include #include +YOSYS_NAMESPACE_BEGIN + std::vector log_files; FILE *log_errfile = NULL; bool log_time = false; @@ -233,7 +235,7 @@ std::map> get_coverage_data() { std::map> coverage_data; - for (auto &it : REGISTER_INTERN::pass_register) { + for (auto &it : pass_register) { std::string key = stringf("passes.%s", it.first.c_str()); coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__); coverage_data[key].second += it.second->call_counter; @@ -260,3 +262,5 @@ std::map> get_coverage_data() return coverage_data; } +YOSYS_NAMESPACE_END + diff --git a/kernel/log.h b/kernel/log.h index a491d067d..0109faf62 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -28,6 +28,8 @@ #include #include +YOSYS_NAMESPACE_BEGIN + #define S__LINE__sub2(x) #x #define S__LINE__sub1(x) S__LINE__sub2(x) #define S__LINE__ S__LINE__sub1(__LINE__) @@ -40,8 +42,6 @@ extern bool log_time; extern bool log_cmd_error_throw; extern int log_verbose_level; -std::string stringf(const char *fmt, ...); - void logv(const char *format, va_list ap); void logv_header(const char *format, va_list ap); void logv_error(const char *format, va_list ap) __attribute__ ((noreturn)); @@ -246,4 +246,6 @@ void log_dump_args_worker(const char *p, T first, Args ... args) log("\n"); \ } while (0) +YOSYS_NAMESPACE_END + #endif diff --git a/kernel/register.cc b/kernel/register.cc index c7bd2cce7..7469b3e81 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -17,26 +17,22 @@ * */ -#include "kernel/compatibility.h" -#include "kernel/register.h" -#include "kernel/log.h" +#include "kernel/yosys.h" #include #include #include #include -using namespace REGISTER_INTERN; +YOSYS_NAMESPACE_BEGIN + #define MAX_REG_COUNT 1000 -namespace REGISTER_INTERN -{ - bool echo_mode = false; - Pass *first_queued_pass; +bool echo_mode = false; +Pass *first_queued_pass; - std::map frontend_register; - std::map pass_register; - std::map backend_register; -} +std::map frontend_register; +std::map pass_register; +std::map backend_register; std::vector Frontend::next_args; @@ -552,7 +548,7 @@ struct HelpPass : public Pass { { if (args.size() == 1) { log("\n"); - for (auto &it : REGISTER_INTERN::pass_register) + for (auto &it : pass_register) log(" %-20s %s\n", it.first.c_str(), it.second->short_help.c_str()); log("\n"); log("Type 'help ' for more information on a command.\n"); @@ -562,7 +558,7 @@ struct HelpPass : public Pass { if (args.size() == 2) { if (args[1] == "-all") { - for (auto &it : REGISTER_INTERN::pass_register) { + for (auto &it : pass_register) { log("\n\n"); log("%s -- %s\n", it.first.c_str(), it.second->short_help.c_str()); for (size_t i = 0; i < it.first.size() + it.second->short_help.size() + 6; i++) @@ -575,7 +571,7 @@ struct HelpPass : public Pass { else if (args[1] == "-write-tex-command-reference-manual") { FILE *f = fopen("command-reference-manual.tex", "wt"); fprintf(f, "%% Generated using the yosys 'help -write-tex-command-reference-manual' command.\n\n"); - for (auto &it : REGISTER_INTERN::pass_register) { + for (auto &it : pass_register) { size_t memsize; char *memptr; FILE *memf = open_memstream(&memptr, &memsize); @@ -591,7 +587,7 @@ struct HelpPass : public Pass { // this option is undocumented as it is for internal use only else if (args[1] == "-write-web-command-reference-manual") { FILE *f = fopen("templates/cmd_index.in", "wt"); - for (auto &it : REGISTER_INTERN::pass_register) { + for (auto &it : pass_register) { size_t memsize; char *memptr; FILE *memf = open_memstream(&memptr, &memsize); @@ -604,10 +600,10 @@ struct HelpPass : public Pass { } fclose(f); } - else if (REGISTER_INTERN::pass_register.count(args[1]) == 0) + else if (pass_register.count(args[1]) == 0) log("No such command: %s\n", args[1].c_str()); else - REGISTER_INTERN::pass_register.at(args[1])->help(); + pass_register.at(args[1])->help(); return; } @@ -648,3 +644,5 @@ struct EchoPass : public Pass { } } EchoPass; +YOSYS_NAMESPACE_END + diff --git a/kernel/register.h b/kernel/register.h index 41780bfb9..17942ca96 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -20,12 +20,14 @@ #ifndef REGISTER_H #define REGISTER_H -#include "kernel/rtlil.h" +#include "kernel/yosys.h" #include #include #include #include +YOSYS_NAMESPACE_BEGIN + struct Pass { std::string pass_name, short_help; @@ -94,10 +96,10 @@ struct Backend : Pass // implemented in passes/cmds/select.cc extern void handle_extra_select_args(Pass *pass, std::vector args, size_t argidx, size_t args_size, RTLIL::Design *design); -namespace REGISTER_INTERN { - extern std::map pass_register; - extern std::map frontend_register; - extern std::map backend_register; -} +extern std::map pass_register; +extern std::map frontend_register; +extern std::map backend_register; + +YOSYS_NAMESPACE_END #endif diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f864d88c0..82fa7aec2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -17,16 +17,14 @@ * */ -#include "kernel/compatibility.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" +#include "kernel/yosys.h" #include "frontends/verilog/verilog_frontend.h" #include "backends/ilang/ilang_backend.h" #include #include -int RTLIL::autoidx = 1; +YOSYS_NAMESPACE_BEGIN RTLIL::Const::Const() { @@ -2736,3 +2734,5 @@ RTLIL::Process *RTLIL::Process::clone() const return new_proc; } +YOSYS_NAMESPACE_END + diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7bd75bd1d..4d8581c72 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -22,6 +22,8 @@ #ifndef RTLIL_H #define RTLIL_H +YOSYS_NAMESPACE_BEGIN + namespace RTLIL { enum State : unsigned char { @@ -50,8 +52,6 @@ namespace RTLIL CONST_FLAG_REAL = 4 // unused -- to be used for parameters }; - extern int autoidx; - struct Const; struct Selection; struct Design; @@ -123,18 +123,6 @@ namespace RTLIL return str.c_str(); } - static IdString new_id(std::string file, int line, std::string func) __attribute__((unused)); - static IdString new_id(std::string file, int line, std::string func) { - std::string str = "$auto$"; - size_t pos = file.find_last_of('/'); - str += pos != std::string::npos ? file.substr(pos+1) : file; - str += stringf(":%d:%s$%d", line, func.c_str(), autoidx++); - return str; - } - -#define NEW_ID \ - RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) - template struct sort_by_name { bool operator()(T *a, T *b) const { return a->name < b->name; @@ -969,4 +957,6 @@ void RTLIL::Process::rewrite_sigspecs(T functor) it->rewrite_sigspecs(functor); } +YOSYS_NAMESPACE_END + #endif diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 79a9fb238..b691749a8 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -20,9 +20,9 @@ #ifndef SIGTOOLS_H #define SIGTOOLS_H -#include "kernel/rtlil.h" -#include "kernel/log.h" -#include +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN struct SigPool { @@ -398,4 +398,6 @@ struct SigMap } }; +YOSYS_NAMESPACE_END + #endif /* SIGTOOLS_H */ diff --git a/kernel/yosys.cc b/kernel/yosys.cc index d25443826..34800ce8e 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -19,6 +19,21 @@ #include "kernel/yosys.h" +#include +#include + +#include +#include + +YOSYS_NAMESPACE_BEGIN + +int autoidx = 1; +RTLIL::Design *yosys_design = NULL; + +#ifdef YOSYS_ENABLE_TCL +Tcl_Interp *yosys_tcl_interp = NULL; +#endif + std::string stringf(const char *fmt, ...) { std::string string; @@ -38,3 +53,553 @@ std::string stringf(const char *fmt, ...) return string; } +void yosys_setup() +{ + Pass::init_register(); + + yosys_design = new RTLIL::Design; + yosys_design->selection_stack.push_back(RTLIL::Selection()); + log_push(); +} + +void yosys_shutdown() +{ + log_pop(); + + for (auto f : log_files) + if (f != stderr) + fclose(f); + log_errfile = NULL; + log_files.clear(); + + Pass::done_register(); + +#ifdef YOSYS_ENABLE_TCL + if (yosys_tcl_interp != NULL) { + Tcl_DeleteInterp(yosys_tcl_interp); + Tcl_Finalize(); + yosys_tcl_interp = NULL; + } +#endif +} + +RTLIL::IdString new_id(std::string file, int line, std::string func) +{ + std::string str = "$auto$"; + size_t pos = file.find_last_of('/'); + str += pos != std::string::npos ? file.substr(pos+1) : file; + str += stringf(":%d:%s$%d", line, func.c_str(), autoidx++); + return str; +} + +RTLIL::Design *yosys_get_design() +{ + return yosys_design; +} + +const char *create_prompt(RTLIL::Design *design, int recursion_counter) +{ + static char buffer[100]; + std::string str = "\n"; + if (recursion_counter > 1) + str += stringf("(%d) ", recursion_counter); + str += "yosys"; + if (!design->selected_active_module.empty()) + str += stringf(" [%s]", RTLIL::id2cstr(design->selected_active_module)); + if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) { + if (design->selected_active_module.empty()) + str += "*"; + else if (design->selection_stack.back().selected_modules.size() != 1 || design->selection_stack.back().selected_members.size() != 0 || + design->selection_stack.back().selected_modules.count(design->selected_active_module) == 0) + str += "*"; + } + snprintf(buffer, 100, "%s> ", str.c_str()); + return buffer; +} + +#ifdef YOSYS_ENABLE_TCL +static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *argv[]) +{ + std::vector args; + for (int i = 1; i < argc; i++) + args.push_back(argv[i]); + + if (args.size() >= 1 && args[0] == "-import") { + for (auto &it : pass_register) { + std::string tcl_command_name = it.first; + if (tcl_command_name == "proc") + tcl_command_name = "procs"; + Tcl_CmdInfo info; + if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) { + log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str()); + } else { + std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name.c_str(), it.first.c_str()); + Tcl_Eval(interp, tcl_script.c_str()); + } + } + return TCL_OK; + } + + if (args.size() == 1) { + Pass::call(yosys_get_design(), args[0]); + return TCL_OK; + } + + Pass::call(yosys_get_design(), args); + return TCL_OK; +} + +extern Tcl_Interp *yosys_get_tcl_interp() +{ + if (yosys_tcl_interp == NULL) { + yosys_tcl_interp = Tcl_CreateInterp(); + Tcl_CreateCommand(yosys_tcl_interp, "yosys", tcl_yosys_cmd, NULL, NULL); + } + return yosys_tcl_interp; +} + +struct TclPass : public Pass { + TclPass() : Pass("tcl", "execute a TCL script file") { } + virtual void help() { + log("\n"); + log(" tcl \n"); + log("\n"); + log("This command executes the tcl commands in the specified file.\n"); + log("Use 'yosys cmd' to run the yosys command 'cmd' from tcl.\n"); + log("\n"); + log("The tcl command 'yosys -import' can be used to import all yosys\n"); + log("commands directly as tcl commands to the tcl shell. The yosys\n"); + log("command 'proc' is wrapped using the tcl command 'procs' in order\n"); + log("to avoid a name collision with the tcl builting command 'proc'.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) { + if (args.size() < 2) + log_cmd_error("Missing script file.\n"); + if (args.size() > 2) + extra_args(args, 1, design, false); + if (Tcl_EvalFile(yosys_get_tcl_interp(), args[1].c_str()) != TCL_OK) + log_cmd_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp())); + } +} TclPass; +#endif + +#if defined(__linux__) +std::string proc_self_dirname () +{ + char path [PATH_MAX]; + ssize_t buflen = readlink("/proc/self/exe", path, sizeof(path)); + if (buflen < 0) { + log_cmd_error("readlink(\"/proc/self/exe\") failed: %s", strerror(errno)); + log_abort(); + } + while (buflen > 0 && path[buflen-1] != '/') + buflen--; + return std::string(path, buflen); +} +#elif defined(__APPLE__) +#include +std::string proc_self_dirname () +{ + char * path = NULL; + uint32_t buflen = 0; + while (_NSGetExecutablePath(path, &buflen) != 0) + path = (char *) realloc((void *) path, buflen); + while (buflen > 0 && path[buflen-1] != '/') + buflen--; + return std::string(path, buflen); +} +#else + #error Dont know how to determine process executable base path! +#endif + +std::string proc_share_dirname () +{ + std::string proc_self_path = proc_self_dirname(); + std::string proc_share_path = proc_self_path + "share/"; + if (access(proc_share_path.c_str(), X_OK) == 0) + return proc_share_path; + proc_share_path = proc_self_path + "../share/yosys/"; + if (access(proc_share_path.c_str(), X_OK) == 0) + return proc_share_path; + log_cmd_error("proc_share_dirname: unable to determine share/ directory!"); + log_abort(); +} + +bool fgetline(FILE *f, std::string &buffer) +{ + buffer = ""; + char block[4096]; + while (1) { + if (fgets(block, 4096, f) == NULL) + return false; + buffer += block; + if (buffer.size() > 0 && (buffer[buffer.size()-1] == '\n' || buffer[buffer.size()-1] == '\r')) { + while (buffer.size() > 0 && (buffer[buffer.size()-1] == '\n' || buffer[buffer.size()-1] == '\r')) + buffer.resize(buffer.size()-1); + return true; + } + } +} + +static void handle_label(std::string &command, bool &from_to_active, const std::string &run_from, const std::string &run_to) +{ + int pos = 0; + std::string label; + + while (pos < SIZE(command) && (command[pos] == ' ' || command[pos] == '\t')) + pos++; + + while (pos < SIZE(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n') + label += command[pos++]; + + if (label.back() == ':' && SIZE(label) > 1) + { + label = label.substr(0, SIZE(label)-1); + command = command.substr(pos); + + if (label == run_from) + from_to_active = true; + else if (label == run_to || (run_from == run_to && !run_from.empty())) + from_to_active = false; + } +} + +void run_frontend(std::string filename, std::string command, RTLIL::Design *design, std::string *backend_command, std::string *from_to_label) +{ + if (command == "auto") { + if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") + command = "verilog"; + else if (filename.size() > 2 && filename.substr(filename.size()-3) == ".sv") + command = "verilog -sv"; + else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") + command = "ilang"; + else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".ys") + command = "script"; + else if (filename == "-") + command = "script"; + else + log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str()); + } + + if (command == "script") + { + std::string run_from, run_to; + bool from_to_active = true; + + if (from_to_label != NULL) { + size_t pos = from_to_label->find(':'); + if (pos == std::string::npos) { + run_from = *from_to_label; + run_to = *from_to_label; + } else { + run_from = from_to_label->substr(0, pos); + run_to = from_to_label->substr(pos+1); + } + from_to_active = run_from.empty(); + } + + log("\n-- Executing script file `%s' --\n", filename.c_str()); + + FILE *f = stdin; + + if (filename != "-") + f = fopen(filename.c_str(), "r"); + + if (f == NULL) + log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); + + FILE *backup_script_file = Frontend::current_script_file; + Frontend::current_script_file = f; + + try { + std::string command; + while (fgetline(f, command)) { + while (!command.empty() && command[command.size()-1] == '\\') { + std::string next_line; + if (!fgetline(f, next_line)) + break; + command.resize(command.size()-1); + command += next_line; + } + handle_label(command, from_to_active, run_from, run_to); + if (from_to_active) + Pass::call(design, command); + } + + if (!command.empty()) { + handle_label(command, from_to_active, run_from, run_to); + if (from_to_active) + Pass::call(design, command); + } + } + catch (log_cmd_error_expection) { + Frontend::current_script_file = backup_script_file; + throw log_cmd_error_expection(); + } + + Frontend::current_script_file = backup_script_file; + + if (filename != "-") + fclose(f); + + if (backend_command != NULL && *backend_command == "auto") + *backend_command = ""; + + return; + } + + if (filename == "-") { + log("\n-- Parsing stdin using frontend `%s' --\n", command.c_str()); + } else { + log("\n-- Parsing `%s' using frontend `%s' --\n", filename.c_str(), command.c_str()); + } + + Frontend::frontend_call(design, NULL, filename, command); +} + +void run_pass(std::string command, RTLIL::Design *design) +{ + log("\n-- Running pass `%s' --\n", command.c_str()); + + Pass::call(design, command); +} + +void run_backend(std::string filename, std::string command, RTLIL::Design *design) +{ + if (command == "auto") { + if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") + command = "verilog"; + else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") + command = "ilang"; + else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif") + command = "blif"; + else if (filename == "-") + command = "ilang"; + else if (filename.empty()) + return; + else + log_error("Can't guess backend for output file `%s' (missing -b option)!\n", filename.c_str()); + } + + if (filename.empty()) + filename = "-"; + + if (filename == "-") { + log("\n-- Writing to stdout using backend `%s' --\n", command.c_str()); + } else { + log("\n-- Writing to `%s' using backend `%s' --\n", filename.c_str(), command.c_str()); + } + + Backend::backend_call(design, NULL, filename, command); +} + +static char *readline_cmd_generator(const char *text, int state) +{ + static std::map::iterator it; + static int len; + + if (!state) { + it = pass_register.begin(); + len = strlen(text); + } + + for (; it != pass_register.end(); it++) { + if (it->first.substr(0, len) == text) + return strdup((it++)->first.c_str()); + } + return NULL; +} + +static char *readline_obj_generator(const char *text, int state) +{ + static std::vector obj_names; + static size_t idx; + + if (!state) + { + idx = 0; + obj_names.clear(); + + RTLIL::Design *design = yosys_get_design(); + int len = strlen(text); + + if (design->selected_active_module.empty()) + { + for (auto &it : design->modules_) + if (RTLIL::unescape_id(it.first).substr(0, len) == text) + obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + } + else + if (design->modules_.count(design->selected_active_module) > 0) + { + RTLIL::Module *module = design->modules_.at(design->selected_active_module); + + for (auto &it : module->wires_) + if (RTLIL::unescape_id(it.first).substr(0, len) == text) + obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + + for (auto &it : module->memories) + if (RTLIL::unescape_id(it.first).substr(0, len) == text) + obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + + for (auto &it : module->cells_) + if (RTLIL::unescape_id(it.first).substr(0, len) == text) + obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + + for (auto &it : module->processes) + if (RTLIL::unescape_id(it.first).substr(0, len) == text) + obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + } + + std::sort(obj_names.begin(), obj_names.end()); + } + + if (idx < obj_names.size()) + return strdup(obj_names[idx++]); + + idx = 0; + obj_names.clear(); + return NULL; +} + +static char **readline_completion(const char *text, int start, int) +{ + if (start == 0) + return rl_completion_matches(text, readline_cmd_generator); + if (strncmp(rl_line_buffer, "read_", 5) && strncmp(rl_line_buffer, "write_", 6)) + return rl_completion_matches(text, readline_obj_generator); + return NULL; +} + +void shell(RTLIL::Design *design) +{ + static int recursion_counter = 0; + + recursion_counter++; + log_cmd_error_throw = true; + + rl_readline_name = "yosys"; + rl_attempted_completion_function = readline_completion; + rl_basic_word_break_characters = " \t\n"; + + char *command = NULL; + while ((command = readline(create_prompt(design, recursion_counter))) != NULL) + { + if (command[strspn(command, " \t\r\n")] == 0) + continue; + add_history(command); + + char *p = command + strspn(command, " \t\r\n"); + if (!strncmp(p, "exit", 4)) { + p += 4; + p += strspn(p, " \t\r\n"); + if (*p == 0) + break; + } + + try { + log_assert(design->selection_stack.size() == 1); + Pass::call(design, command); + } catch (log_cmd_error_expection) { + while (design->selection_stack.size() > 1) + design->selection_stack.pop_back(); + log_reset_stack(); + } + } + if (command == NULL) + printf("exit\n"); + + recursion_counter--; + log_cmd_error_throw = false; +} + +struct ShellPass : public Pass { + ShellPass() : Pass("shell", "enter interactive command mode") { } + virtual void help() { + log("\n"); + log(" shell\n"); + log("\n"); + log("This command enters the interactive command mode. This can be useful\n"); + log("in a script to interrupt the script at a certain point and allow for\n"); + log("interactive inspection or manual synthesis of the design at this point.\n"); + log("\n"); + log("The command prompt of the interactive shell indicates the current\n"); + log("selection (see 'help select'):\n"); + log("\n"); + log(" yosys>\n"); + log(" the entire design is selected\n"); + log("\n"); + log(" yosys*>\n"); + log(" only part of the design is selected\n"); + log("\n"); + log(" yosys [modname]>\n"); + log(" the entire module 'modname' is selected using 'select -module modname'\n"); + log("\n"); + log(" yosys [modname]*>\n"); + log(" only part of current module 'modname' is selected\n"); + log("\n"); + log("When in interactive shell, some errors (e.g. invalid command arguments)\n"); + log("do not terminate yosys but return to the command prompt.\n"); + log("\n"); + log("This command is the default action if nothing else has been specified\n"); + log("on the command line.\n"); + log("\n"); + log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) { + extra_args(args, 1, design, false); + shell(design); + } +} ShellPass; + +struct HistoryPass : public Pass { + HistoryPass() : Pass("history", "show last interactive commands") { } + virtual void help() { + log("\n"); + log(" history\n"); + log("\n"); + log("This command prints all commands in the shell history buffer. This are\n"); + log("all commands executed in an interactive session, but not the commands\n"); + log("from executed scripts.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) { + extra_args(args, 1, design, false); + for(HIST_ENTRY **list = history_list(); *list != NULL; list++) + log("%s\n", (*list)->line); + } +} HistoryPass; + +struct ScriptPass : public Pass { + ScriptPass() : Pass("script", "execute commands from script file") { } + virtual void help() { + log("\n"); + log(" script [:]\n"); + log("\n"); + log("This command executes the yosys commands in the specified file.\n"); + log("\n"); + log("The 2nd argument can be used to only execute the section of the\n"); + log("file between the specified labels. An empty from label is synonymous\n"); + log("for the beginning of the file and an empty to label is synonymous\n"); + log("for the end of the file.\n"); + log("\n"); + log("If only one label is specified (without ':') then only the block\n"); + log("marked with that label (until the next label) is executed.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) { + if (args.size() < 2) + log_cmd_error("Missing script file.\n"); + else if (args.size() == 2) + run_frontend(args[1], "script", design, NULL, NULL); + else if (args.size() == 3) + run_frontend(args[1], "script", design, NULL, &args[2]); + else + extra_args(args, 2, design, false); + } +} ScriptPass; + +YOSYS_NAMESPACE_END + diff --git a/kernel/yosys.h b/kernel/yosys.h index 67629d9b1..9b36ebcc9 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -29,6 +29,9 @@ // If you want to know how to register a command with Yosys, you could read // "kernel/register.h", but it would be easier to just look at a simple // example instead. A simple one would be "passes/cmds/log.cc". +// +// This header is very boring. It just defines some general things that +// belong nowhere else and includes the interesting headers. #ifndef YOSYS_H @@ -38,20 +41,24 @@ #include #include #include +#include #include #if 0 # define YOSYS_NAMESPACE_BEGIN namespace Yosys { # define YOSYS_NAMESPACE_END } +# define YOSYS_NAMESPACE_PREFIX Yosys:: +# define USING_YOSYS_NAMESPACE using namespace Yosys; #else # define YOSYS_NAMESPACE_BEGIN # define YOSYS_NAMESPACE_END +# define YOSYS_NAMESPACE_PREFIX +# define USING_YOSYS_NAMESPACE #endif YOSYS_NAMESPACE_BEGIN std::string stringf(const char *fmt, ...); - #define SIZE(__obj) int(__obj.size()) YOSYS_NAMESPACE_END @@ -63,20 +70,35 @@ YOSYS_NAMESPACE_END YOSYS_NAMESPACE_BEGIN +void yosys_setup(); +void yosys_shutdown(); + #ifdef YOSYS_ENABLE_TCL #include -extern Tcl_Interp *yosys_get_tcl_interp(); +Tcl_Interp *yosys_get_tcl_interp(); #endif +extern int autoidx; +extern RTLIL::Design *yosys_design; + +RTLIL::IdString new_id(std::string file, int line, std::string func); + +#define NEW_ID \ + YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__) + +RTLIL::Design *yosys_get_design(); +std::string proc_self_dirname(); +std::string proc_share_dirname(); +const char *create_prompt(RTLIL::Design *design, int recursion_counter); + +void run_frontend(std::string filename, std::string command, RTLIL::Design *design, std::string *backend_command, std::string *from_to_label); +void run_pass(std::string command, RTLIL::Design *design); +void run_backend(std::string filename, std::string command, RTLIL::Design *design); +void shell(RTLIL::Design *design); + // from kernel/version_*.o (cc source generated from Makefile) extern const char *yosys_version_str; -// implemented in driver.cc -extern RTLIL::Design *yosys_get_design(); -extern std::string proc_self_dirname(); -extern std::string proc_share_dirname(); -extern const char *create_prompt(RTLIL::Design *design, int recursion_counter); - // from passes/cmds/design.cc extern std::map saved_designs; extern std::vector pushed_designs; -- cgit v1.2.3 From e6d33513a5b809facc6e3e5e75d2248bfa94f82b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 14:11:39 +0200 Subject: Added module->design and cell->module, wire->module pointers --- kernel/rtlil.cc | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/rtlil.h | 20 ++++++++++++++ 2 files changed, 103 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 82fa7aec2..9f10b5d82 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -243,6 +243,7 @@ void RTLIL::Design::add(RTLIL::Module *module) log_assert(modules_.count(module->name) == 0); log_assert(refcount_modules_ == 0); modules_[module->name] = module; + module->design = this; } RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) @@ -250,6 +251,7 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) log_assert(modules_.count(name) == 0); log_assert(refcount_modules_ == 0); modules_[name] = new RTLIL::Module; + modules_[name]->design = this; modules_[name]->name = name; return modules_[name]; } @@ -265,6 +267,7 @@ void RTLIL::Design::check() { #ifndef NDEBUG for (auto &it : modules_) { + log_assert(this == it.second->design); log_assert(it.first == it.second->name); log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); it.second->check(); @@ -319,6 +322,38 @@ bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const return selected_whole_module(mod->name); } +std::vector RTLIL::Design::selected_modules() const +{ + std::vector result; + result.reserve(modules_.size()); + for (auto &it : modules_) + if (selected_module(it.first)) + result.push_back(it.second); + return result; +} + +std::vector RTLIL::Design::selected_whole_modules() const +{ + std::vector result; + result.reserve(modules_.size()); + for (auto &it : modules_) + if (selected_whole_module(it.first)) + result.push_back(it.second); + return result; +} + +std::vector RTLIL::Design::selected_whole_modules_warn() const +{ + std::vector result; + result.reserve(modules_.size()); + for (auto &it : modules_) + if (selected_whole_module(it.first)) + result.push_back(it.second); + else if (selected_module(it.first)) + log("Warning: Ignoring partially selected module %s.\n", log_id(it.first)); + return result; +} + RTLIL::Module::Module() { refcount_wires_ = 0; @@ -763,6 +798,7 @@ void RTLIL::Module::check() { #ifndef NDEBUG for (auto &it : wires_) { + log_assert(this == it.second->module); log_assert(it.first == it.second->name); log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); log_assert(it.second->width >= 0); @@ -783,6 +819,7 @@ void RTLIL::Module::check() } for (auto &it : cells_) { + log_assert(this == it.second->module); log_assert(it.first == it.second->name); log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$')); @@ -868,12 +905,57 @@ RTLIL::Module *RTLIL::Module::clone() const return new_mod; } +bool RTLIL::Module::has_memories() const +{ + return !memories.empty(); +} + +bool RTLIL::Module::has_processes() const +{ + return !processes.empty(); +} + +bool RTLIL::Module::has_memories_warn() const +{ + if (!memories.empty()) + log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this)); + return !memories.empty(); +} + +bool RTLIL::Module::has_processes_warn() const +{ + if (!processes.empty()) + log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this)); + return !processes.empty(); +} + +std::vector RTLIL::Module::selected_wires() const +{ + std::vector result; + result.reserve(wires_.size()); + for (auto &it : wires_) + if (design->selected(this, it.second)) + result.push_back(it.second); + return result; +} + +std::vector RTLIL::Module::selected_cells() const +{ + std::vector result; + result.reserve(wires_.size()); + for (auto &it : cells_) + if (design->selected(this, it.second)) + result.push_back(it.second); + return result; +} + void RTLIL::Module::add(RTLIL::Wire *wire) { log_assert(!wire->name.empty()); log_assert(count_id(wire->name) == 0); log_assert(refcount_wires_ == 0); wires_[wire->name] = wire; + wire->module = this; } void RTLIL::Module::add(RTLIL::Cell *cell) @@ -882,6 +964,7 @@ void RTLIL::Module::add(RTLIL::Cell *cell) log_assert(count_id(cell->name) == 0); log_assert(refcount_cells_ == 0); cells_[cell->name] = cell; + cell->module = this; } namespace { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4d8581c72..1163dccef 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -252,6 +252,10 @@ namespace RTLIL RTLIL::ObjIterator begin() { return RTLIL::ObjIterator(list_p, refcount_p); } RTLIL::ObjIterator end() { return RTLIL::ObjIterator(); } + size_t size() const { + return list_p->size(); + } + operator std::set() const { std::set result; for (auto &it : *list_p) @@ -375,6 +379,10 @@ struct RTLIL::Design sel.select(module, member); } } + + std::vector selected_modules() const; + std::vector selected_whole_modules() const; + std::vector selected_whole_modules_warn() const; }; #define RTLIL_ATTRIBUTE_MEMBERS \ @@ -395,6 +403,7 @@ protected: void add(RTLIL::Cell *cell); public: + RTLIL::Design *design; int refcount_wires_; int refcount_cells_; @@ -424,6 +433,15 @@ public: void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; + bool has_memories() const; + bool has_processes() const; + + bool has_memories_warn() const; + bool has_processes_warn() const; + + std::vector selected_wires() const; + std::vector selected_cells() const; + RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } @@ -592,6 +610,7 @@ public: Wire(RTLIL::Wire &other) = delete; void operator=(RTLIL::Wire &other) = delete; + RTLIL::Module *module; RTLIL::IdString name; int width, start_offset, port_id; bool port_input, port_output, upto; @@ -620,6 +639,7 @@ public: Cell(RTLIL::Cell &other) = delete; void operator=(RTLIL::Cell &other) = delete; + RTLIL::Module *module; RTLIL::IdString name; RTLIL::IdString type; std::map connections_; -- cgit v1.2.3 From cd9407404a7bf3a5b8735af00c8f13ff97ac1495 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 14:34:12 +0200 Subject: Added RTLIL::Monitor --- kernel/rtlil.cc | 173 ++++++++++++++++++++++++++------------------------------ kernel/rtlil.h | 20 ++++++- 2 files changed, 97 insertions(+), 96 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9f10b5d82..28de216cd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -244,20 +244,32 @@ void RTLIL::Design::add(RTLIL::Module *module) log_assert(refcount_modules_ == 0); modules_[module->name] = module; module->design = this; + + for (auto mon : monitors) + mon->notify_module_add(module); } RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) { log_assert(modules_.count(name) == 0); log_assert(refcount_modules_ == 0); - modules_[name] = new RTLIL::Module; - modules_[name]->design = this; - modules_[name]->name = name; - return modules_[name]; + + RTLIL::Module *module = new RTLIL::Module; + modules_[name] = module; + module->design = this; + module->name = name; + + for (auto mon : monitors) + mon->notify_module_add(module); + + return module; } void RTLIL::Design::remove(RTLIL::Module *module) { + for (auto mon : monitors) + mon->notify_module_del(module); + log_assert(modules_.at(module->name) == module); modules_.erase(module->name); delete module; @@ -356,6 +368,7 @@ std::vector RTLIL::Design::selected_whole_modules_warn() const RTLIL::Module::Module() { + design = nullptr; refcount_wires_ = 0; refcount_cells_ = 0; } @@ -1061,12 +1074,31 @@ static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) void RTLIL::Module::connect(const RTLIL::SigSig &conn) { + for (auto mon : monitors) + mon->notify_connect(this, conn); + + if (design) + for (auto mon : design->monitors) + mon->notify_connect(this, conn); + connections_.push_back(conn); } void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs) { - connections_.push_back(RTLIL::SigSig(lhs, rhs)); + connect(RTLIL::SigSig(lhs, rhs)); +} + +void RTLIL::Module::new_connections(const std::vector &new_conn) +{ + for (auto mon : monitors) + mon->notify_new_connections(this, new_conn); + + if (design) + for (auto mon : design->monitors) + mon->notify_new_connections(this, new_conn); + + connections_ = new_conn; } const std::vector &RTLIL::Module::connections() const @@ -1131,15 +1163,12 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ + RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ cell->set("\\A", sig_a); \ cell->set("\\Y", sig_y); \ - add(cell); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \ @@ -1161,9 +1190,7 @@ DEF_METHOD(LogicNot, 1, "$logic_not") #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ + RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\B_SIGNED"] = is_signed; \ cell->parameters["\\A_WIDTH"] = sig_a.size(); \ @@ -1172,7 +1199,6 @@ DEF_METHOD(LogicNot, 1, "$logic_not") cell->set("\\A", sig_a); \ cell->set("\\B", sig_b); \ cell->set("\\Y", sig_y); \ - add(cell); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \ @@ -1209,9 +1235,7 @@ DEF_METHOD(LogicOr, 1, "$logic_or") #define DEF_METHOD(_func, _type, _pmux) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ + RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\WIDTH"] = sig_a.size(); \ cell->parameters["\\WIDTH"] = sig_b.size(); \ if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ @@ -1219,7 +1243,6 @@ DEF_METHOD(LogicOr, 1, "$logic_or") cell->set("\\B", sig_b); \ cell->set("\\S", sig_s); \ cell->set("\\Y", sig_y); \ - add(cell); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \ @@ -1234,12 +1257,9 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) #define DEF_METHOD_2(_func, _type, _P1, _P2) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ + RTLIL::Cell *cell = addCell(name, _type); \ cell->set("\\" #_P1, sig1); \ cell->set("\\" #_P2, sig2); \ - add(cell); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \ @@ -1249,13 +1269,10 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) } #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ + RTLIL::Cell *cell = addCell(name, _type); \ cell->set("\\" #_P1, sig1); \ cell->set("\\" #_P2, sig2); \ cell->set("\\" #_P3, sig3); \ - add(cell); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ @@ -1265,14 +1282,11 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) } #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \ - RTLIL::Cell *cell = new RTLIL::Cell; \ - cell->name = name; \ - cell->type = _type; \ + RTLIL::Cell *cell = addCell(name, _type); \ cell->set("\\" #_P1, sig1); \ cell->set("\\" #_P2, sig2); \ cell->set("\\" #_P3, sig3); \ cell->set("\\" #_P4, sig4); \ - add(cell); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ @@ -1291,9 +1305,7 @@ DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y) RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$pow"; + RTLIL::Cell *cell = addCell(name, "$pow"); cell->parameters["\\A_SIGNED"] = a_signed; cell->parameters["\\B_SIGNED"] = b_signed; cell->parameters["\\A_WIDTH"] = sig_a.size(); @@ -1302,97 +1314,76 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R cell->set("\\A", sig_a); cell->set("\\B", sig_b); cell->set("\\Y", sig_y); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$slice"; + RTLIL::Cell *cell = addCell(name, "$slice"); cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig_y.size(); cell->parameters["\\OFFSET"] = offset; cell->set("\\A", sig_a); cell->set("\\Y", sig_y); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$concat"; + RTLIL::Cell *cell = addCell(name, "$concat"); cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\B_WIDTH"] = sig_b.size(); cell->set("\\A", sig_a); cell->set("\\B", sig_b); cell->set("\\Y", sig_y); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$lut"; + RTLIL::Cell *cell = addCell(name, "$lut"); cell->parameters["\\LUT"] = lut; cell->parameters["\\WIDTH"] = sig_i.size(); cell->set("\\I", sig_i); cell->set("\\O", sig_o); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$assert"; + RTLIL::Cell *cell = addCell(name, "$assert"); cell->set("\\A", sig_a); cell->set("\\EN", sig_en); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$sr"; + RTLIL::Cell *cell = addCell(name, "$sr"); cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); cell->set("\\SET", sig_set); cell->set("\\CLR", sig_clr); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$dff"; + RTLIL::Cell *cell = addCell(name, "$dff"); cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); cell->set("\\CLK", sig_clk); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$dffsr"; + RTLIL::Cell *cell = addCell(name, "$dffsr"); cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; @@ -1402,16 +1393,13 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl cell->set("\\CLR", sig_clr); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$adff"; + RTLIL::Cell *cell = addCell(name, "$adff"); cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\ARST_POLARITY"] = arst_polarity; cell->parameters["\\ARST_VALUE"] = arst_value; @@ -1420,30 +1408,24 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk cell->set("\\ARST", sig_arst); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$dlatch"; + RTLIL::Cell *cell = addCell(name, "$dlatch"); cell->parameters["\\EN_POLARITY"] = en_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); cell->set("\\EN", sig_en); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = "$dlatchsr"; + RTLIL::Cell *cell = addCell(name, "$dlatchsr"); cell->parameters["\\EN_POLARITY"] = en_polarity; cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; @@ -1453,81 +1435,66 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig cell->set("\\CLR", sig_clr); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'); + RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')); cell->set("\\C", sig_clk); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'); + RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); cell->set("\\C", sig_clk); cell->set("\\S", sig_set); cell->set("\\R", sig_clr); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool arst_value, bool clk_polarity, bool arst_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'); + RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); cell->set("\\C", sig_clk); cell->set("\\R", sig_arst); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'); + RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')); cell->set("\\E", sig_en); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = name; - cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'); + RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); cell->set("\\E", sig_en); cell->set("\\S", sig_set); cell->set("\\R", sig_clr); cell->set("\\D", sig_d); cell->set("\\Q", sig_q); - add(cell); return cell; } RTLIL::Wire::Wire() { + module = nullptr; width = 1; start_offset = 0; port_id = 0; @@ -1542,18 +1509,36 @@ RTLIL::Memory::Memory() size = 0; } -bool RTLIL::Cell::has(RTLIL::IdString portname) +bool RTLIL::Cell::has(RTLIL::IdString portname) const { return connections_.count(portname) != 0; } void RTLIL::Cell::unset(RTLIL::IdString portname) { + std::pair new_conn(portname, RTLIL::SigSpec()); + + for (auto mon : module->monitors) + mon->notify_cell_connect(this, new_conn); + + if (module->design) + for (auto mon : module->design->monitors) + mon->notify_cell_connect(this, new_conn); + connections_.erase(portname); } void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal) { + std::pair new_conn(portname, signal); + + for (auto mon : module->monitors) + mon->notify_cell_connect(this, new_conn); + + if (module->design) + for (auto mon : module->design->monitors) + mon->notify_cell_connect(this, new_conn); + connections_[portname] = signal; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1163dccef..5107e5f2b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -54,6 +54,7 @@ namespace RTLIL struct Const; struct Selection; + struct Monitor; struct Design; struct Module; struct Wire; @@ -328,8 +329,20 @@ struct RTLIL::Selection } }; +struct RTLIL::Monitor +{ + virtual void notify_module_add(RTLIL::Module*) { } + virtual void notify_module_del(RTLIL::Module*) { } + virtual void notify_cell_connect(RTLIL::Cell*, const std::pair&) { } + virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } + virtual void notify_new_connections(RTLIL::Module*, const std::vector&) { } + virtual void notify_blackout(RTLIL::Module*) { } +}; + struct RTLIL::Design { + std::set monitors; + int refcount_modules_; std::map modules_; @@ -404,6 +417,8 @@ protected: public: RTLIL::Design *design; + std::set monitors; + int refcount_wires_; int refcount_cells_; @@ -426,6 +441,7 @@ public: void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + void new_connections(const std::vector &new_conn); const std::vector &connections() const; void fixup_ports(); @@ -631,7 +647,7 @@ struct RTLIL::Cell protected: // use module->addCell() and module->remove() to create or destroy cells friend struct RTLIL::Module; - Cell() { }; + Cell() : module(nullptr) { }; ~Cell() { }; public: @@ -647,7 +663,7 @@ public: RTLIL_ATTRIBUTE_MEMBERS // access cell ports - bool has(RTLIL::IdString portname); + bool has(RTLIL::IdString portname) const; void unset(RTLIL::IdString portname); void set(RTLIL::IdString portname, RTLIL::SigSpec signal); const RTLIL::SigSpec &get(RTLIL::IdString portname) const; -- cgit v1.2.3 From b5a9e51b966abdfedc9309defa79b5141928e84a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 15:02:16 +0200 Subject: Added "trace" command --- kernel/yosys.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index 9b36ebcc9..119e7e8a6 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -44,6 +44,9 @@ #include #include +#define PRIVATE_NAMESPACE_BEGIN namespace { +#define PRIVATE_NAMESPACE_END } + #if 0 # define YOSYS_NAMESPACE_BEGIN namespace Yosys { # define YOSYS_NAMESPACE_END } -- cgit v1.2.3 From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- kernel/consteval.h | 16 ++--- kernel/rtlil.cc | 184 +++++++++++++++++++++++++++++------------------------ kernel/rtlil.h | 15 +++-- kernel/satgen.h | 170 ++++++++++++++++++++++++------------------------- 4 files changed, 206 insertions(+), 179 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index e5cae1022..529d8962d 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -87,22 +87,22 @@ struct ConstEval { RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - log_assert(cell->has("\\Y")); - sig_y = values_map(assign_map(cell->get("\\Y"))); + log_assert(cell->hasPort("\\Y")); + sig_y = values_map(assign_map(cell->getPort("\\Y"))); if (sig_y.is_fully_const()) return true; - if (cell->has("\\S")) { - sig_s = cell->get("\\S"); + if (cell->hasPort("\\S")) { + sig_s = cell->getPort("\\S"); if (!eval(sig_s, undef, cell)) return false; } - if (cell->has("\\A")) - sig_a = cell->get("\\A"); + if (cell->hasPort("\\A")) + sig_a = cell->getPort("\\A"); - if (cell->has("\\B")) - sig_b = cell->get("\\B"); + if (cell->hasPort("\\B")) + sig_b = cell->getPort("\\B"); if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_") { diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 28de216cd..012253144 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -447,9 +447,9 @@ namespace { void port(const char *name, int width) { - if (!cell->has(name)) + if (!cell->hasPort(name)) error(__LINE__); - if (cell->get(name).size() != width) + if (cell->getPort(name).size() != width) error(__LINE__); expected_ports.insert(name); } @@ -478,9 +478,9 @@ namespace { for (const char *p = ports; *p; p++) { char portname[3] = { '\\', *p, 0 }; - if (!cell->has(portname)) + if (!cell->hasPort(portname)) error(__LINE__); - if (cell->get(portname).size() != 1) + if (cell->getPort(portname).size() != 1) error(__LINE__); } @@ -1001,7 +1001,7 @@ namespace { #if 0 void RTLIL::Module::remove(RTLIL::Wire *wire) { - std::set wires_; + std::setPort wires_; wires_.insert(wire); remove(wires_); } @@ -1167,8 +1167,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->set("\\A", sig_a); \ - cell->set("\\Y", sig_y); \ + cell->setPort("\\A", sig_a); \ + cell->setPort("\\Y", sig_y); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \ @@ -1196,9 +1196,9 @@ DEF_METHOD(LogicNot, 1, "$logic_not") cell->parameters["\\A_WIDTH"] = sig_a.size(); \ cell->parameters["\\B_WIDTH"] = sig_b.size(); \ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->set("\\A", sig_a); \ - cell->set("\\B", sig_b); \ - cell->set("\\Y", sig_y); \ + cell->setPort("\\A", sig_a); \ + cell->setPort("\\B", sig_b); \ + cell->setPort("\\Y", sig_y); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \ @@ -1239,10 +1239,10 @@ DEF_METHOD(LogicOr, 1, "$logic_or") cell->parameters["\\WIDTH"] = sig_a.size(); \ cell->parameters["\\WIDTH"] = sig_b.size(); \ if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ - cell->set("\\A", sig_a); \ - cell->set("\\B", sig_b); \ - cell->set("\\S", sig_s); \ - cell->set("\\Y", sig_y); \ + cell->setPort("\\A", sig_a); \ + cell->setPort("\\B", sig_b); \ + cell->setPort("\\S", sig_s); \ + cell->setPort("\\Y", sig_y); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \ @@ -1258,8 +1258,8 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) #define DEF_METHOD_2(_func, _type, _P1, _P2) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->set("\\" #_P1, sig1); \ - cell->set("\\" #_P2, sig2); \ + cell->setPort("\\" #_P1, sig1); \ + cell->setPort("\\" #_P2, sig2); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \ @@ -1270,9 +1270,9 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->set("\\" #_P1, sig1); \ - cell->set("\\" #_P2, sig2); \ - cell->set("\\" #_P3, sig3); \ + cell->setPort("\\" #_P1, sig1); \ + cell->setPort("\\" #_P2, sig2); \ + cell->setPort("\\" #_P3, sig3); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ @@ -1283,10 +1283,10 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1) #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->set("\\" #_P1, sig1); \ - cell->set("\\" #_P2, sig2); \ - cell->set("\\" #_P3, sig3); \ - cell->set("\\" #_P4, sig4); \ + cell->setPort("\\" #_P1, sig1); \ + cell->setPort("\\" #_P2, sig2); \ + cell->setPort("\\" #_P3, sig3); \ + cell->setPort("\\" #_P4, sig4); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ @@ -1311,9 +1311,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\B_WIDTH"] = sig_b.size(); cell->parameters["\\Y_WIDTH"] = sig_y.size(); - cell->set("\\A", sig_a); - cell->set("\\B", sig_b); - cell->set("\\Y", sig_y); + cell->setPort("\\A", sig_a); + cell->setPort("\\B", sig_b); + cell->setPort("\\Y", sig_y); return cell; } @@ -1323,8 +1323,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig_y.size(); cell->parameters["\\OFFSET"] = offset; - cell->set("\\A", sig_a); - cell->set("\\Y", sig_y); + cell->setPort("\\A", sig_a); + cell->setPort("\\Y", sig_y); return cell; } @@ -1333,9 +1333,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell *cell = addCell(name, "$concat"); cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\B_WIDTH"] = sig_b.size(); - cell->set("\\A", sig_a); - cell->set("\\B", sig_b); - cell->set("\\Y", sig_y); + cell->setPort("\\A", sig_a); + cell->setPort("\\B", sig_b); + cell->setPort("\\Y", sig_y); return cell; } @@ -1344,16 +1344,16 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R RTLIL::Cell *cell = addCell(name, "$lut"); cell->parameters["\\LUT"] = lut; cell->parameters["\\WIDTH"] = sig_i.size(); - cell->set("\\I", sig_i); - cell->set("\\O", sig_o); + cell->setPort("\\I", sig_i); + cell->setPort("\\O", sig_o); return cell; } RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) { RTLIL::Cell *cell = addCell(name, "$assert"); - cell->set("\\A", sig_a); - cell->set("\\EN", sig_en); + cell->setPort("\\A", sig_a); + cell->setPort("\\EN", sig_en); return cell; } @@ -1363,9 +1363,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->set("\\SET", sig_set); - cell->set("\\CLR", sig_clr); - cell->set("\\Q", sig_q); + cell->setPort("\\SET", sig_set); + cell->setPort("\\CLR", sig_clr); + cell->setPort("\\Q", sig_q); return cell; } @@ -1374,9 +1374,9 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::Cell *cell = addCell(name, "$dff"); cell->parameters["\\CLK_POLARITY"] = clk_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->set("\\CLK", sig_clk); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\CLK", sig_clk); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } @@ -1388,11 +1388,11 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->set("\\CLK", sig_clk); - cell->set("\\SET", sig_set); - cell->set("\\CLR", sig_clr); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\CLK", sig_clk); + cell->setPort("\\SET", sig_set); + cell->setPort("\\CLR", sig_clr); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } @@ -1404,10 +1404,10 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk cell->parameters["\\ARST_POLARITY"] = arst_polarity; cell->parameters["\\ARST_VALUE"] = arst_value; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->set("\\CLK", sig_clk); - cell->set("\\ARST", sig_arst); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\CLK", sig_clk); + cell->setPort("\\ARST", sig_arst); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } @@ -1416,9 +1416,9 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e RTLIL::Cell *cell = addCell(name, "$dlatch"); cell->parameters["\\EN_POLARITY"] = en_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->set("\\EN", sig_en); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\EN", sig_en); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } @@ -1430,20 +1430,20 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig cell->parameters["\\SET_POLARITY"] = set_polarity; cell->parameters["\\CLR_POLARITY"] = clr_polarity; cell->parameters["\\WIDTH"] = sig_q.size(); - cell->set("\\EN", sig_en); - cell->set("\\SET", sig_set); - cell->set("\\CLR", sig_clr); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\EN", sig_en); + cell->setPort("\\SET", sig_set); + cell->setPort("\\CLR", sig_clr); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')); - cell->set("\\C", sig_clk); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\C", sig_clk); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } @@ -1451,11 +1451,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity) { RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->set("\\C", sig_clk); - cell->set("\\S", sig_set); - cell->set("\\R", sig_clr); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\C", sig_clk); + cell->setPort("\\S", sig_set); + cell->setPort("\\R", sig_clr); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } @@ -1463,19 +1463,19 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig bool arst_value, bool clk_polarity, bool arst_polarity) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); - cell->set("\\C", sig_clk); - cell->set("\\R", sig_arst); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\C", sig_clk); + cell->setPort("\\R", sig_arst); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity) { RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')); - cell->set("\\E", sig_en); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\E", sig_en); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } @@ -1483,11 +1483,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity) { RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->set("\\E", sig_en); - cell->set("\\S", sig_set); - cell->set("\\R", sig_clr); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); + cell->setPort("\\E", sig_en); + cell->setPort("\\S", sig_set); + cell->setPort("\\R", sig_clr); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); return cell; } @@ -1509,12 +1509,12 @@ RTLIL::Memory::Memory() size = 0; } -bool RTLIL::Cell::has(RTLIL::IdString portname) const +bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const { return connections_.count(portname) != 0; } -void RTLIL::Cell::unset(RTLIL::IdString portname) +void RTLIL::Cell::unsetPort(RTLIL::IdString portname) { std::pair new_conn(portname, RTLIL::SigSpec()); @@ -1528,7 +1528,7 @@ void RTLIL::Cell::unset(RTLIL::IdString portname) connections_.erase(portname); } -void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal) +void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) { std::pair new_conn(portname, signal); @@ -1542,7 +1542,7 @@ void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal) connections_[portname] = signal; } -const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const +const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const { return connections_.at(portname); } @@ -1552,6 +1552,26 @@ const std::map &RTLIL::Cell::connections() cons return connections_; } +bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const +{ + return parameters.count(paramname); +} + +void RTLIL::Cell::unsetParam(RTLIL::IdString paramname) +{ + parameters.erase(paramname); +} + +void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value) +{ + parameters[paramname] = value; +} + +const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const +{ + return parameters.at(paramname); +} + void RTLIL::Cell::check() { #ifndef NDEBUG diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 5107e5f2b..796d45df1 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -331,6 +331,7 @@ struct RTLIL::Selection struct RTLIL::Monitor { + virtual ~Monitor() { } virtual void notify_module_add(RTLIL::Module*) { } virtual void notify_module_del(RTLIL::Module*) { } virtual void notify_cell_connect(RTLIL::Cell*, const std::pair&) { } @@ -663,12 +664,18 @@ public: RTLIL_ATTRIBUTE_MEMBERS // access cell ports - bool has(RTLIL::IdString portname) const; - void unset(RTLIL::IdString portname); - void set(RTLIL::IdString portname, RTLIL::SigSpec signal); - const RTLIL::SigSpec &get(RTLIL::IdString portname) const; + bool hasPort(RTLIL::IdString portname) const; + void unsetPort(RTLIL::IdString portname); + void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); + const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const; const std::map &connections() const; + // access cell parameters + bool hasParam(RTLIL::IdString portname) const; + void unsetParam(RTLIL::IdString portname); + void setParam(RTLIL::IdString portname, RTLIL::Const value); + const RTLIL::Const &getParam(RTLIL::IdString portname) const; + void check(); void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); diff --git a/kernel/satgen.h b/kernel/satgen.h index ce2c90280..1ada1e16a 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -182,9 +182,9 @@ struct SatGen if (model_undef && (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || is_arith_compare)) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); if (is_arith_compare) extendSignalWidth(undef_a, undef_b, cell, true); else @@ -195,7 +195,7 @@ struct SatGen int undef_y_bit = ez->OR(undef_any_a, undef_any_b); if (cell->type == "$div" || cell->type == "$mod") { - std::vector b = importSigSpec(cell->get("\\B"), timestep); + std::vector b = importSigSpec(cell->getPort("\\B"), timestep); undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b))); } @@ -215,9 +215,9 @@ struct SatGen cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$sub") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector b = importDefSigSpec(cell->get("\\B"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -237,9 +237,9 @@ struct SatGen if (model_undef && !arith_undef_handled) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell, false); if (cell->type == "$and" || cell->type == "$_AND_") { @@ -265,7 +265,7 @@ struct SatGen } else if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -273,16 +273,16 @@ struct SatGen if (cell->type == "$_INV_" || cell->type == "$not") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_not(a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, true); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -292,20 +292,20 @@ struct SatGen if (cell->type == "$_MUX_" || cell->type == "$mux") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector b = importDefSigSpec(cell->get("\\B"), timestep); - std::vector s = importDefSigSpec(cell->get("\\S"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector s = importDefSigSpec(cell->getPort("\\S"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); - std::vector undef_s = importUndefSigSpec(cell->get("\\S"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); std::vector unequal_ab = ez->vec_not(ez->vec_iff(a, b)); std::vector undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b)); @@ -318,10 +318,10 @@ struct SatGen if (cell->type == "$pmux" || cell->type == "$safe_pmux") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector b = importDefSigSpec(cell->get("\\B"), timestep); - std::vector s = importDefSigSpec(cell->get("\\S"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector s = importDefSigSpec(cell->getPort("\\S"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -336,10 +336,10 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); - std::vector undef_s = importUndefSigSpec(cell->get("\\S"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); int maybe_one_hot = ez->FALSE; int maybe_many_hot = ez->FALSE; @@ -387,8 +387,8 @@ struct SatGen if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -402,8 +402,8 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0"); if (cell->type == "$pos" || cell->type == "$bu0") { @@ -422,8 +422,8 @@ struct SatGen if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -442,8 +442,8 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); int aX = ez->expression(ezSAT::OpOr, undef_a); if (cell->type == "$reduce_and") { @@ -469,12 +469,12 @@ struct SatGen if (cell->type == "$logic_and" || cell->type == "$logic_or") { - std::vector vec_a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector vec_b = importDefSigSpec(cell->get("\\B"), timestep); + std::vector vec_a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector vec_b = importDefSigSpec(cell->getPort("\\B"), timestep); int a = ez->expression(ez->OpOr, vec_a); int b = ez->expression(ez->OpOr, vec_b); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -487,9 +487,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a))); int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b))); @@ -516,16 +516,16 @@ struct SatGen if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") { bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool(); - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector b = importDefSigSpec(cell->get("\\B"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidth(a, b, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); a = ez->vec_or(a, undef_a); b = ez->vec_or(b, undef_b); @@ -548,9 +548,9 @@ struct SatGen if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); if (cell->type == "$eqx") @@ -565,9 +565,9 @@ struct SatGen } else if (model_undef && (cell->type == "$eq" || cell->type == "$ne")) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, cell, true); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); @@ -589,7 +589,7 @@ struct SatGen else { if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); undefGating(y, yy, undef_y); } log_assert(!model_undef || arith_undef_handled); @@ -599,9 +599,9 @@ struct SatGen if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector b = importDefSigSpec(cell->get("\\B"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); int extend_bit = ez->FALSE; @@ -632,9 +632,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->get("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->get("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); std::vector undef_a_shifted; if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool()) @@ -670,9 +670,9 @@ struct SatGen if (cell->type == "$mul") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector b = importDefSigSpec(cell->get("\\B"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -689,7 +689,7 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -697,9 +697,9 @@ struct SatGen if (cell->type == "$div" || cell->type == "$mod") { - std::vector a = importDefSigSpec(cell->get("\\A"), timestep); - std::vector b = importDefSigSpec(cell->get("\\B"), timestep); - std::vector y = importDefSigSpec(cell->get("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -753,11 +753,11 @@ struct SatGen only_first_one.at(0) = ez->TRUE; div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones); } else { - div_zero_result.insert(div_zero_result.end(), cell->get("\\A").size(), ez->TRUE); + div_zero_result.insert(div_zero_result.end(), cell->getPort("\\A").size(), ez->TRUE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE); } } else { - int copy_a_bits = std::min(cell->get("\\A").size(), cell->get("\\B").size()); + int copy_a_bits = std::min(cell->getPort("\\A").size(), cell->getPort("\\B").size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); @@ -769,7 +769,7 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->get("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); undefGating(y, yy, undef_y); } return true; @@ -777,17 +777,17 @@ struct SatGen if (cell->type == "$slice") { - RTLIL::SigSpec a = cell->get("\\A"); - RTLIL::SigSpec y = cell->get("\\Y"); + RTLIL::SigSpec a = cell->getPort("\\A"); + RTLIL::SigSpec y = cell->getPort("\\Y"); ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep)); return true; } if (cell->type == "$concat") { - RTLIL::SigSpec a = cell->get("\\A"); - RTLIL::SigSpec b = cell->get("\\B"); - RTLIL::SigSpec y = cell->get("\\Y"); + RTLIL::SigSpec a = cell->getPort("\\A"); + RTLIL::SigSpec b = cell->getPort("\\B"); + RTLIL::SigSpec y = cell->getPort("\\Y"); RTLIL::SigSpec ab = a; ab.append(b); @@ -800,20 +800,20 @@ struct SatGen { if (timestep == 1) { - initial_state.add((*sigmap)(cell->get("\\Q"))); + initial_state.add((*sigmap)(cell->getPort("\\Q"))); } else { - std::vector d = importDefSigSpec(cell->get("\\D"), timestep-1); - std::vector q = importDefSigSpec(cell->get("\\Q"), timestep); + std::vector d = importDefSigSpec(cell->getPort("\\D"), timestep-1); + std::vector q = importDefSigSpec(cell->getPort("\\Q"), timestep); std::vector qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector undef_d = importUndefSigSpec(cell->get("\\D"), timestep-1); - std::vector undef_q = importUndefSigSpec(cell->get("\\Q"), timestep); + std::vector undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1); + std::vector undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -825,8 +825,8 @@ struct SatGen if (cell->type == "$assert") { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - asserts_a[pf].append((*sigmap)(cell->get("\\A"))); - asserts_en[pf].append((*sigmap)(cell->get("\\EN"))); + asserts_a[pf].append((*sigmap)(cell->getPort("\\A"))); + asserts_en[pf].append((*sigmap)(cell->getPort("\\EN"))); return true; } -- cgit v1.2.3 From 32a1cc3efdad7953af1805b245f2a0292698633a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 23:30:18 +0200 Subject: Renamed modwalker.h to modtools.h --- kernel/modtools.h | 298 +++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/modwalker.h | 298 ----------------------------------------------------- 2 files changed, 298 insertions(+), 298 deletions(-) create mode 100644 kernel/modtools.h delete mode 100644 kernel/modwalker.h (limited to 'kernel') diff --git a/kernel/modtools.h b/kernel/modtools.h new file mode 100644 index 000000000..06e96246f --- /dev/null +++ b/kernel/modtools.h @@ -0,0 +1,298 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef MODTOOLS_H +#define MODTOOLS_H + +#include "kernel/sigtools.h" +#include "kernel/celltypes.h" + +struct ModWalker +{ + struct PortBit + { + RTLIL::Cell *cell; + RTLIL::IdString port; + int offset; + + bool operator<(const PortBit &other) const { + if (cell != other.cell) + return cell < other.cell; + if (port != other.port) + return port < other.port; + return offset < other.offset; + } + }; + + RTLIL::Design *design; + RTLIL::Module *module; + + CellTypes ct; + SigMap sigmap; + + std::map> signal_drivers; + std::map> signal_consumers; + std::set signal_inputs, signal_outputs; + + std::map> cell_outputs, cell_inputs; + + void add_wire(RTLIL::Wire *wire) + { + if (wire->port_input) { + std::vector bits = sigmap(wire); + for (auto bit : bits) + if (bit.wire != NULL) + signal_inputs.insert(bit); + } + + if (wire->port_output) { + std::vector bits = sigmap(wire); + for (auto bit : bits) + if (bit.wire != NULL) + signal_outputs.insert(bit); + } + } + + void add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector bits, bool is_output, bool is_input) + { + for (int i = 0; i < int(bits.size()); i++) + if (bits[i].wire != NULL) { + PortBit pbit = { cell, port, i }; + if (is_output) { + signal_drivers[bits[i]].insert(pbit); + cell_outputs[cell].insert(bits[i]); + } + if (is_input) { + signal_consumers[bits[i]].insert(pbit); + cell_inputs[cell].insert(bits[i]); + } + } + } + + void add_cell(RTLIL::Cell *cell) + { + if (ct.cell_known(cell->type)) { + for (auto &conn : cell->connections()) + add_cell_port(cell, conn.first, sigmap(conn.second), + ct.cell_output(cell->type, conn.first), + ct.cell_input(cell->type, conn.first)); + } else { + for (auto &conn : cell->connections()) + add_cell_port(cell, conn.first, sigmap(conn.second), true, true); + } + } + + ModWalker() : design(NULL), module(NULL) + { + } + + ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) + { + setup(design, module, filter_ct); + } + + void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) + { + this->design = design; + this->module = module; + + ct.clear(); + ct.setup(design); + sigmap.set(module); + + signal_drivers.clear(); + signal_consumers.clear(); + signal_inputs.clear(); + signal_outputs.clear(); + + for (auto &it : module->wires_) + add_wire(it.second); + for (auto &it : module->cells_) + if (filter_ct == NULL || filter_ct->cell_known(it.second->type)) + add_cell(it.second); + } + + // get_* methods -- single RTLIL::SigBit + + template + inline bool get_drivers(std::set &result, RTLIL::SigBit bit) const + { + bool found = false; + if (signal_drivers.count(bit)) { + const std::set &r = signal_drivers.at(bit); + result.insert(r.begin(), r.end()); + found = true; + } + return found; + } + + template + inline bool get_consumers(std::set &result, RTLIL::SigBit bit) const + { + bool found = false; + if (signal_consumers.count(bit)) { + const std::set &r = signal_consumers.at(bit); + result.insert(r.begin(), r.end()); + found = true; + } + return found; + } + + template + inline bool get_inputs(std::set &result, RTLIL::SigBit bit) const + { + bool found = false; + if (signal_inputs.count(bit)) + result.insert(bit), found = true; + return found; + } + + template + inline bool get_outputs(std::set &result, RTLIL::SigBit bit) const + { + bool found = false; + if (signal_outputs.count(bit)) + result.insert(bit), found = true; + return found; + } + + // get_* methods -- container of RTLIL::SigBit's (always by reference) + + template + inline bool get_drivers(std::set &result, const T &bits) const + { + bool found = false; + for (RTLIL::SigBit bit : bits) + if (signal_drivers.count(bit)) { + const std::set &r = signal_drivers.at(bit); + result.insert(r.begin(), r.end()); + found = true; + } + return found; + } + + template + inline bool get_consumers(std::set &result, const T &bits) const + { + bool found = false; + for (RTLIL::SigBit bit : bits) + if (signal_consumers.count(bit)) { + const std::set &r = signal_consumers.at(bit); + result.insert(r.begin(), r.end()); + found = true; + } + return found; + } + + template + inline bool get_inputs(std::set &result, const T &bits) const + { + bool found = false; + for (RTLIL::SigBit bit : bits) + if (signal_inputs.count(bit)) + result.insert(bit), found = true; + return found; + } + + template + inline bool get_outputs(std::set &result, const T &bits) const + { + bool found = false; + for (RTLIL::SigBit bit : bits) + if (signal_outputs.count(bit)) + result.insert(bit), found = true; + return found; + } + + // get_* methods -- call by RTLIL::SigSpec (always by value) + + bool get_drivers(std::set &result, RTLIL::SigSpec signal) const + { + std::vector bits = sigmap(signal); + return get_drivers(result, bits); + } + + bool get_consumers(std::set &result, RTLIL::SigSpec signal) const + { + std::vector bits = sigmap(signal); + return get_consumers(result, bits); + } + + bool get_inputs(std::set &result, RTLIL::SigSpec signal) const + { + std::vector bits = sigmap(signal); + return get_inputs(result, bits); + } + + bool get_outputs(std::set &result, RTLIL::SigSpec signal) const + { + std::vector bits = sigmap(signal); + return get_outputs(result, bits); + } + + // has_* methods -- call by reference + + template + inline bool has_drivers(const T &sig) const { + std::set result; + return get_drivers(result, sig); + } + + template + inline bool has_consumers(const T &sig) const { + std::set result; + return get_consumers(result, sig); + } + + template + inline bool has_inputs(const T &sig) const { + std::set result; + return get_inputs(result, sig); + } + + template + inline bool has_outputs(const T &sig) const { + std::set result; + return get_outputs(result, sig); + } + + // has_* methods -- call by value + + inline bool has_drivers(RTLIL::SigSpec sig) const { + std::set result; + return get_drivers(result, sig); + } + + inline bool has_consumers(RTLIL::SigSpec sig) const { + std::set result; + return get_consumers(result, sig); + } + + inline bool has_inputs(RTLIL::SigSpec sig) const { + std::set result; + return get_inputs(result, sig); + } + + inline bool has_outputs(RTLIL::SigSpec sig) const { + std::set result; + return get_outputs(result, sig); + } +}; + +#endif diff --git a/kernel/modwalker.h b/kernel/modwalker.h deleted file mode 100644 index 09f815b83..000000000 --- a/kernel/modwalker.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifndef MODWALKER_H -#define MODWALKER_H - -#include "kernel/sigtools.h" -#include "kernel/celltypes.h" - -struct ModWalker -{ - struct PortBit - { - RTLIL::Cell *cell; - RTLIL::IdString port; - int offset; - - bool operator<(const PortBit &other) const { - if (cell != other.cell) - return cell < other.cell; - if (port != other.port) - return port < other.port; - return offset < other.offset; - } - }; - - RTLIL::Design *design; - RTLIL::Module *module; - - CellTypes ct; - SigMap sigmap; - - std::map> signal_drivers; - std::map> signal_consumers; - std::set signal_inputs, signal_outputs; - - std::map> cell_outputs, cell_inputs; - - void add_wire(RTLIL::Wire *wire) - { - if (wire->port_input) { - std::vector bits = sigmap(wire); - for (auto bit : bits) - if (bit.wire != NULL) - signal_inputs.insert(bit); - } - - if (wire->port_output) { - std::vector bits = sigmap(wire); - for (auto bit : bits) - if (bit.wire != NULL) - signal_outputs.insert(bit); - } - } - - void add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector bits, bool is_output, bool is_input) - { - for (int i = 0; i < int(bits.size()); i++) - if (bits[i].wire != NULL) { - PortBit pbit = { cell, port, i }; - if (is_output) { - signal_drivers[bits[i]].insert(pbit); - cell_outputs[cell].insert(bits[i]); - } - if (is_input) { - signal_consumers[bits[i]].insert(pbit); - cell_inputs[cell].insert(bits[i]); - } - } - } - - void add_cell(RTLIL::Cell *cell) - { - if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections()) - add_cell_port(cell, conn.first, sigmap(conn.second), - ct.cell_output(cell->type, conn.first), - ct.cell_input(cell->type, conn.first)); - } else { - for (auto &conn : cell->connections()) - add_cell_port(cell, conn.first, sigmap(conn.second), true, true); - } - } - - ModWalker() : design(NULL), module(NULL) - { - } - - ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) - { - setup(design, module, filter_ct); - } - - void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) - { - this->design = design; - this->module = module; - - ct.clear(); - ct.setup(design); - sigmap.set(module); - - signal_drivers.clear(); - signal_consumers.clear(); - signal_inputs.clear(); - signal_outputs.clear(); - - for (auto &it : module->wires_) - add_wire(it.second); - for (auto &it : module->cells_) - if (filter_ct == NULL || filter_ct->cell_known(it.second->type)) - add_cell(it.second); - } - - // get_* methods -- single RTLIL::SigBit - - template - inline bool get_drivers(std::set &result, RTLIL::SigBit bit) const - { - bool found = false; - if (signal_drivers.count(bit)) { - const std::set &r = signal_drivers.at(bit); - result.insert(r.begin(), r.end()); - found = true; - } - return found; - } - - template - inline bool get_consumers(std::set &result, RTLIL::SigBit bit) const - { - bool found = false; - if (signal_consumers.count(bit)) { - const std::set &r = signal_consumers.at(bit); - result.insert(r.begin(), r.end()); - found = true; - } - return found; - } - - template - inline bool get_inputs(std::set &result, RTLIL::SigBit bit) const - { - bool found = false; - if (signal_inputs.count(bit)) - result.insert(bit), found = true; - return found; - } - - template - inline bool get_outputs(std::set &result, RTLIL::SigBit bit) const - { - bool found = false; - if (signal_outputs.count(bit)) - result.insert(bit), found = true; - return found; - } - - // get_* methods -- container of RTLIL::SigBit's (always by reference) - - template - inline bool get_drivers(std::set &result, const T &bits) const - { - bool found = false; - for (RTLIL::SigBit bit : bits) - if (signal_drivers.count(bit)) { - const std::set &r = signal_drivers.at(bit); - result.insert(r.begin(), r.end()); - found = true; - } - return found; - } - - template - inline bool get_consumers(std::set &result, const T &bits) const - { - bool found = false; - for (RTLIL::SigBit bit : bits) - if (signal_consumers.count(bit)) { - const std::set &r = signal_consumers.at(bit); - result.insert(r.begin(), r.end()); - found = true; - } - return found; - } - - template - inline bool get_inputs(std::set &result, const T &bits) const - { - bool found = false; - for (RTLIL::SigBit bit : bits) - if (signal_inputs.count(bit)) - result.insert(bit), found = true; - return found; - } - - template - inline bool get_outputs(std::set &result, const T &bits) const - { - bool found = false; - for (RTLIL::SigBit bit : bits) - if (signal_outputs.count(bit)) - result.insert(bit), found = true; - return found; - } - - // get_* methods -- call by RTLIL::SigSpec (always by value) - - bool get_drivers(std::set &result, RTLIL::SigSpec signal) const - { - std::vector bits = sigmap(signal); - return get_drivers(result, bits); - } - - bool get_consumers(std::set &result, RTLIL::SigSpec signal) const - { - std::vector bits = sigmap(signal); - return get_consumers(result, bits); - } - - bool get_inputs(std::set &result, RTLIL::SigSpec signal) const - { - std::vector bits = sigmap(signal); - return get_inputs(result, bits); - } - - bool get_outputs(std::set &result, RTLIL::SigSpec signal) const - { - std::vector bits = sigmap(signal); - return get_outputs(result, bits); - } - - // has_* methods -- call by reference - - template - inline bool has_drivers(const T &sig) const { - std::set result; - return get_drivers(result, sig); - } - - template - inline bool has_consumers(const T &sig) const { - std::set result; - return get_consumers(result, sig); - } - - template - inline bool has_inputs(const T &sig) const { - std::set result; - return get_inputs(result, sig); - } - - template - inline bool has_outputs(const T &sig) const { - std::set result; - return get_outputs(result, sig); - } - - // has_* methods -- call by value - - inline bool has_drivers(RTLIL::SigSpec sig) const { - std::set result; - return get_drivers(result, sig); - } - - inline bool has_consumers(RTLIL::SigSpec sig) const { - std::set result; - return get_consumers(result, sig); - } - - inline bool has_inputs(RTLIL::SigSpec sig) const { - std::set result; - return get_inputs(result, sig); - } - - inline bool has_outputs(RTLIL::SigSpec sig) const { - std::set result; - return get_outputs(result, sig); - } -}; - -#endif -- cgit v1.2.3 From 97a17d39e2f0088e02ed8496d905528722115674 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Aug 2014 15:25:42 +0200 Subject: Packed SigBit::data and SigBit::offset in a union --- kernel/rtlil.cc | 4 +++- kernel/rtlil.h | 20 +++++++++++--------- 2 files changed, 14 insertions(+), 10 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 012253144..79ddd2e02 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1681,9 +1681,11 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width) RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit) { wire = bit.wire; + offset = 0; if (wire == NULL) data = RTLIL::Const(bit.data); - offset = bit.offset; + else + offset = bit.offset; width = 1; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 796d45df1..43c7e1050 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -707,15 +707,17 @@ struct RTLIL::SigChunk struct RTLIL::SigBit { RTLIL::Wire *wire; - RTLIL::State data; - int offset; - - SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { } - SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { } - SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { log_assert(wire && wire->width == 1); } - SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { log_assert(wire); } - SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { log_assert(chunk.width == 1); } - SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { } + union { + RTLIL::State data; + int offset; + }; + + SigBit() : wire(NULL), data(RTLIL::State::S0) { } + SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } + SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); } + SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); } + SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; log_assert(chunk.width == 1); } + SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; } SigBit(const RTLIL::SigSpec &sig); bool operator <(const RTLIL::SigBit &other) const { -- cgit v1.2.3 From d13eb7e0999def2da03eb6ddef805145f7fd9c9a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Aug 2014 16:53:15 +0200 Subject: Added ModIndex helper class, some changes to RTLIL::Monitor --- kernel/log.h | 5 --- kernel/modtools.h | 111 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/rtlil.cc | 36 +++++++++++------- kernel/rtlil.h | 10 ++--- kernel/sigtools.h | 13 +++++++ kernel/yosys.cc | 5 +++ kernel/yosys.h | 9 ++++- 7 files changed, 165 insertions(+), 24 deletions(-) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index 0109faf62..9fc83800c 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -57,11 +57,6 @@ void log_pop(); void log_reset_stack(); void log_flush(); -namespace RTLIL { - struct SigSpec; - struct Cell; -} - const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); const char *log_id(std::string id); diff --git a/kernel/modtools.h b/kernel/modtools.h index 06e96246f..09f2ae65e 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -20,9 +20,118 @@ #ifndef MODTOOLS_H #define MODTOOLS_H +#include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" +YOSYS_NAMESPACE_BEGIN + +struct ModIndex : public RTLIL::Monitor +{ + struct PortInfo { + const RTLIL::Cell* cell; + const RTLIL::IdString &port; + const int offset; + + PortInfo(RTLIL::Cell* _c, const RTLIL::IdString &_p, int _o) : cell(_c), port(_p), offset(_o) { } + + bool operator<(const PortInfo &other) const { + if (cell != other.cell) + return cell < other.cell; + if (offset != other.offset) + return offset < other.offset; + return port < other.port; + } + }; + + struct SigBitInfo + { + bool is_input, is_output; + std::set ports; + + SigBitInfo() : is_input(false), is_output(false) { } + }; + + SigMap sigmap; + RTLIL::Module *module; + std::map database; + bool auto_reload_module; + + void port_add(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &sig) + { + for (int i = 0; i < SIZE(sig); i++) + database[sigmap(sig[i])].ports.insert(PortInfo(cell, port, i)); + } + + void port_del(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &sig) + { + for (int i = 0; i < SIZE(sig); i++) + database[sigmap(sig[i])].ports.erase(PortInfo(cell, port, i)); + } + + const SigBitInfo &info(RTLIL::SigBit bit) + { + return database[sigmap(bit)]; + } + + void reload_module() + { + sigmap.clear(); + sigmap.set(module); + + database.clear(); + for (auto wire : module->wires()) + if (wire->port_input || wire->port_output) + for (int i = 0; i < SIZE(wire); i++) { + if (wire->port_input) + database[sigmap(RTLIL::SigBit(wire, i))].is_input = true; + if (wire->port_output) + database[sigmap(RTLIL::SigBit(wire, i))].is_output = true; + } + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) + port_add(cell, conn.first, conn.second); + + auto_reload_module = false; + } + + virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override + { + if (auto_reload_module) + reload_module(); + + port_del(cell, port, old_sig); + port_add(cell, port, sig); + } + + virtual void notify_connect(RTLIL::Module *mod, const RTLIL::SigSig&) + { + log_assert(module == mod); + auto_reload_module = true; + } + + virtual void notify_connect(RTLIL::Module *mod, const std::vector&) + { + log_assert(module == mod); + auto_reload_module = true; + } + + virtual void notify_blackout(RTLIL::Module *mod) + { + log_assert(module == mod); + auto_reload_module = true; + } + + ModIndex(RTLIL::Module *_m) : module(_m) { + auto_reload_module = true; + module->monitors.insert(this); + } + + ~ModIndex() { + module->monitors.erase(this); + } +}; + struct ModWalker { struct PortBit @@ -295,4 +404,6 @@ struct ModWalker } }; +YOSYS_NAMESPACE_END + #endif diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 79ddd2e02..137058522 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1092,11 +1092,11 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs void RTLIL::Module::new_connections(const std::vector &new_conn) { for (auto mon : monitors) - mon->notify_new_connections(this, new_conn); + mon->notify_connect(this, new_conn); if (design) for (auto mon : design->monitors) - mon->notify_new_connections(this, new_conn); + mon->notify_connect(this, new_conn); connections_ = new_conn; } @@ -1516,30 +1516,40 @@ bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const void RTLIL::Cell::unsetPort(RTLIL::IdString portname) { - std::pair new_conn(portname, RTLIL::SigSpec()); + RTLIL::SigSpec signal; + auto conn_it = connections_.find(portname); - for (auto mon : module->monitors) - mon->notify_cell_connect(this, new_conn); + if (conn_it != connections_.end()) + { + for (auto mon : module->monitors) + mon->notify_connect(this, conn_it->first, conn_it->second, signal); - if (module->design) - for (auto mon : module->design->monitors) - mon->notify_cell_connect(this, new_conn); + if (module->design) + for (auto mon : module->design->monitors) + mon->notify_connect(this, conn_it->first, conn_it->second, signal); - connections_.erase(portname); + connections_.erase(conn_it); + } } void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) { - std::pair new_conn(portname, signal); + auto conn_it = connections_.find(portname); + + if (conn_it == connections_.end()) { + connections_[portname] = RTLIL::SigSpec(); + conn_it = connections_.find(portname); + log_assert(conn_it != connections_.end()); + } for (auto mon : module->monitors) - mon->notify_cell_connect(this, new_conn); + mon->notify_connect(this, conn_it->first, conn_it->second, signal); if (module->design) for (auto mon : module->design->monitors) - mon->notify_cell_connect(this, new_conn); + mon->notify_connect(this, conn_it->first, conn_it->second, signal); - connections_[portname] = signal; + conn_it->second = signal; } const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 43c7e1050..0685f1ea2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -334,9 +334,9 @@ struct RTLIL::Monitor virtual ~Monitor() { } virtual void notify_module_add(RTLIL::Module*) { } virtual void notify_module_del(RTLIL::Module*) { } - virtual void notify_cell_connect(RTLIL::Cell*, const std::pair&) { } + virtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, RTLIL::SigSpec&) { } virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } - virtual void notify_new_connections(RTLIL::Module*, const std::vector&) { } + virtual void notify_connect(RTLIL::Module*, const std::vector&) { } virtual void notify_blackout(RTLIL::Module*) { } }; @@ -708,15 +708,15 @@ struct RTLIL::SigBit { RTLIL::Wire *wire; union { - RTLIL::State data; - int offset; + RTLIL::State data; // used if wire == NULL + int offset; // used if wire != NULL }; SigBit() : wire(NULL), data(RTLIL::State::S0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); } - SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; log_assert(chunk.width == 1); } + SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; } SigBit(const RTLIL::SigSpec &sig); diff --git a/kernel/sigtools.h b/kernel/sigtools.h index b691749a8..32ef444aa 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -391,11 +391,24 @@ struct SigMap map_bit(bit); } + RTLIL::SigBit operator()(RTLIL::SigBit bit) const + { + apply(bit); + return bit; + } + RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const { apply(sig); return sig; } + + RTLIL::SigSpec operator()(RTLIL::Wire *wire) const + { + RTLIL::SigSpec sig(wire); + apply(sig); + return sig; + } }; YOSYS_NAMESPACE_END diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 34800ce8e..671945631 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -53,6 +53,11 @@ std::string stringf(const char *fmt, ...) return string; } +int SIZE(RTLIL::Wire *wire) +{ + return wire->width; +} + void yosys_setup() { Pass::init_register(); diff --git a/kernel/yosys.h b/kernel/yosys.h index 119e7e8a6..d9db57c51 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -61,8 +61,15 @@ YOSYS_NAMESPACE_BEGIN +namespace RTLIL { + struct SigSpec; + struct Wire; + struct Cell; +} + std::string stringf(const char *fmt, ...); -#define SIZE(__obj) int(__obj.size()) +template int SIZE(const T &obj) { return obj.size(); } +int SIZE(RTLIL::Wire *wire); YOSYS_NAMESPACE_END -- cgit v1.2.3 From 1e224506be6d824ea9ed1855fa46d039e5ffefd5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Aug 2014 18:42:10 +0200 Subject: Added per-pass cpu usage statistics --- kernel/driver.cc | 42 +++++++++++++++++++++++++++++++++++++++--- kernel/log.h | 1 + kernel/register.cc | 42 +++++++++++++++++++++++++++++++++++------- kernel/register.h | 13 +++++++++++-- 4 files changed, 86 insertions(+), 12 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 01ade7d46..273be7ce1 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -43,6 +43,7 @@ int main(int argc, char **argv) bool scriptfile_tcl = false; bool got_output_filename = false; bool print_banner = true; + bool print_stats = true; bool call_abort = false; int history_offset = 0; @@ -54,7 +55,7 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "AQVSm:f:Hh:b:o:p:l:qv:ts:c:")) != -1) + while ((opt = getopt(argc, argv, "AQTVSm:f:Hh:b:o:p:l:qv:ts:c:")) != -1) { switch (opt) { @@ -64,6 +65,9 @@ int main(int argc, char **argv) case 'Q': print_banner = false; break; + case 'T': + print_stats = false; + break; case 'V': printf("%s\n", yosys_version_str); exit(0); @@ -129,12 +133,15 @@ int main(int argc, char **argv) break; default: fprintf(stderr, "\n"); - fprintf(stderr, "Usage: %s [-V -S -Q -q] [-v [-t] [-l ] [-o ] [-f ] [-h cmd] \\\n", argv[0]); + fprintf(stderr, "Usage: %s [-V -S -Q -T -q] [-v [-t] [-l ] [-o ] [-f ] [-h cmd] \\\n", argv[0]); fprintf(stderr, " %*s[{-s|-c} ] [-p [-p ..]] [-b ] [-m ] [ [..]]\n", int(strlen(argv[0])+1), ""); fprintf(stderr, "\n"); fprintf(stderr, " -Q\n"); fprintf(stderr, " suppress printing of banner (copyright, disclaimer, version)\n"); fprintf(stderr, "\n"); + fprintf(stderr, " -T\n"); + fprintf(stderr, " suppress printing of footer (log hash, version, timing statistics)\n"); + fprintf(stderr, "\n"); fprintf(stderr, " -q\n"); fprintf(stderr, " quiet operation. only write error messages to console\n"); fprintf(stderr, "\n"); @@ -284,7 +291,36 @@ int main(int argc, char **argv) } #endif - log("\nEnd of script.\n"); + if (print_stats) + { + struct rusage ru_buffer; + getrusage(RUSAGE_SELF, &ru_buffer); + log("\nEnd of script. Logfile hash: xxxxxxxxxx, CPU: user %.2fs system %.2fs\n", + ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec, + ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec); + log("%s\nTime spent:", yosys_version_str); + + int64_t total_ns = 0; + std::set> timedat; + + for (auto &it : pass_register) + if (it.second->call_counter) { + total_ns += it.second->runtime_ns + 1; + timedat.insert(make_tuple(it.second->runtime_ns + 1, it.second->call_counter, it.first)); + } + + int out_count = 0; + for (auto it = timedat.rbegin(); it != timedat.rend() && out_count < 4; it++, out_count++) { + if (out_count >= 2 && (std::get<0>(*it) < 1000000000 || int(100*std::get<0>(*it) / total_ns) < 20)) { + log(", ..."); + break; + } + log("%s %d%% %dx %s (%d sec)", out_count ? "," : "", int(100*std::get<0>(*it) / total_ns), + std::get<1>(*it), std::get<2>(*it).c_str(), int(std::get<0>(*it) / 1000000000)); + } + log("%s\n", out_count ? "" : " no commands executed"); + } + if (call_abort) abort(); diff --git a/kernel/log.h b/kernel/log.h index 9fc83800c..8e46ad493 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -170,6 +170,7 @@ struct PerformanceTimer return total_ns * 1e-9; } #else + static int64_t query() { return 0; } void reset() { } void begin() { } void end() { } diff --git a/kernel/register.cc b/kernel/register.cc index 7469b3e81..4d204069c 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -29,6 +29,7 @@ YOSYS_NAMESPACE_BEGIN bool echo_mode = false; Pass *first_queued_pass; +Pass *current_pass; std::map frontend_register; std::map pass_register; @@ -41,6 +42,7 @@ Pass::Pass(std::string name, std::string short_help) : pass_name(name), short_he next_queued_pass = first_queued_pass; first_queued_pass = this; call_counter = 0; + runtime_ns = 0; } void Pass::run_register() @@ -69,6 +71,25 @@ Pass::~Pass() { } +Pass::pre_post_exec_state_t Pass::pre_execute() +{ + pre_post_exec_state_t state; + call_counter++; + state.begin_ns = PerformanceTimer::query(); + state.parent_pass = current_pass; + current_pass = this; + return state; +} + +void Pass::post_execute(Pass::pre_post_exec_state_t state) +{ + int64_t time_ns = PerformanceTimer::query() - state.begin_ns; + runtime_ns += time_ns; + current_pass = state.parent_pass; + if (current_pass) + current_pass->runtime_ns -= time_ns; +} + void Pass::help() { log("\n"); @@ -183,8 +204,9 @@ void Pass::call(RTLIL::Design *design, std::vector args) log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str()); size_t orig_sel_stack_pos = design->selection_stack.size(); - pass_register[args[0]]->call_counter++; + auto state = pass_register[args[0]]->pre_execute(); pass_register[args[0]]->execute(args, design); + pass_register[args[0]]->post_execute(state); while (design->selection_stack.size() > orig_sel_stack_pos) design->selection_stack.pop_back(); @@ -266,8 +288,9 @@ void Frontend::execute(std::vector args, RTLIL::Design *design) do { FILE *f = NULL; next_args.clear(); - call_counter++; + auto state = pre_execute(); execute(f, std::string(), args, design); + post_execute(state); args = next_args; fclose(f); } while (!args.empty()); @@ -359,12 +382,14 @@ void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filenam log_cmd_error("No such frontend: %s\n", args[0].c_str()); if (f != NULL) { - frontend_register[args[0]]->call_counter++; + auto state = frontend_register[args[0]]->pre_execute(); frontend_register[args[0]]->execute(f, filename, args, design); + frontend_register[args[0]]->post_execute(state); } else if (filename == "-") { FILE *f_stdin = stdin; // workaround for OpenBSD 'stdin' implementation - frontend_register[args[0]]->call_counter++; + auto state = frontend_register[args[0]]->pre_execute(); frontend_register[args[0]]->execute(f_stdin, "", args, design); + frontend_register[args[0]]->post_execute(state); } else { if (!filename.empty()) args.push_back(filename); @@ -396,8 +421,9 @@ Backend::~Backend() void Backend::execute(std::vector args, RTLIL::Design *design) { FILE *f = NULL; - call_counter++; + auto state = pre_execute(); execute(f, std::string(), args, design); + post_execute(state); if (f != stdout) fclose(f); } @@ -458,12 +484,14 @@ void Backend::backend_call(RTLIL::Design *design, FILE *f, std::string filename, size_t orig_sel_stack_pos = design->selection_stack.size(); if (f != NULL) { - backend_register[args[0]]->call_counter++; + auto state = backend_register[args[0]]->pre_execute(); backend_register[args[0]]->execute(f, filename, args, design); + backend_register[args[0]]->post_execute(state); } else if (filename == "-") { FILE *f_stdout = stdout; // workaround for OpenBSD 'stdout' implementation - backend_register[args[0]]->call_counter++; + auto state = backend_register[args[0]]->pre_execute(); backend_register[args[0]]->execute(f_stdout, "", args, design); + backend_register[args[0]]->post_execute(state); } else { if (!filename.empty()) args.push_back(filename); diff --git a/kernel/register.h b/kernel/register.h index 17942ca96..93a3308ad 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -31,14 +31,23 @@ YOSYS_NAMESPACE_BEGIN struct Pass { std::string pass_name, short_help; - int call_counter; - Pass(std::string name, std::string short_help = "** document me **"); virtual ~Pass(); virtual void help(); virtual void execute(std::vector args, RTLIL::Design *design) = 0; + int call_counter; + int64_t runtime_ns; + + struct pre_post_exec_state_t { + Pass *parent_pass; + int64_t begin_ns; + }; + + pre_post_exec_state_t pre_execute(); + void post_execute(pre_post_exec_state_t state); + void cmd_log_args(const std::vector &args); void cmd_error(const std::vector &args, size_t argidx, std::string msg); void extra_args(std::vector args, size_t argidx, RTLIL::Design *design, bool select = true); -- cgit v1.2.3 From 75ffd1643c97321255bc591edf0c1a7097b8dce9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Aug 2014 19:43:28 +0200 Subject: Added logfile hash to statistics footer --- kernel/driver.cc | 68 ++++++++++++++++++++++++++++++-------------------------- kernel/log.cc | 36 ++++++++++++++++++++---------- kernel/log.h | 2 ++ kernel/yosys.cc | 16 +++++++++++-- kernel/yosys.h | 2 ++ 5 files changed, 79 insertions(+), 45 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 273be7ce1..6f9764238 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "libs/sha1/sha1.h" #include #include @@ -233,6 +234,9 @@ int main(int argc, char **argv) log("\n"); } + if (print_stats) + log_hasher = new SHA1; + yosys_setup(); if (optind == argc && passes_commands.size() == 0 && scriptfile.empty()) { @@ -262,43 +266,18 @@ int main(int argc, char **argv) if (!backend_command.empty()) run_backend(output_filename, backend_command, yosys_design); - delete yosys_design; - yosys_design = NULL; - -#ifdef COVER_ACTIVE - if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE")) - { - char filename_buffer[4096]; - FILE *f; - - if (getenv("YOSYS_COVER_DIR")) { - snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", getenv("YOSYS_COVER_DIR"), getpid()); - f = fdopen(mkstemps(filename_buffer, 4), "w"); - } else { - snprintf(filename_buffer, 4096, "%s", getenv("YOSYS_COVER_FILE")); - f = fopen(filename_buffer, "a+"); - } - - if (f == NULL) - log_error("Can't create coverage file `%s'.\n", filename_buffer); - - log("\n", filename_buffer); - - for (auto &it : get_coverage_data()) - fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); - - fclose(f); - } -#endif - if (print_stats) { + std::string hash = log_hasher->final().substr(0, 10); + delete log_hasher; + log_hasher = nullptr; + struct rusage ru_buffer; getrusage(RUSAGE_SELF, &ru_buffer); - log("\nEnd of script. Logfile hash: xxxxxxxxxx, CPU: user %.2fs system %.2fs\n", + log("\nEnd of script. Logfile hash: %s, CPU: user %.2fs system %.2fs\n", hash.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec, ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec); - log("%s\nTime spent:", yosys_version_str); + log("%s\n", yosys_version_str); int64_t total_ns = 0; std::set> timedat; @@ -310,6 +289,7 @@ int main(int argc, char **argv) } int out_count = 0; + log("Time spent:"); for (auto it = timedat.rbegin(); it != timedat.rend() && out_count < 4; it++, out_count++) { if (out_count >= 2 && (std::get<0>(*it) < 1000000000 || int(100*std::get<0>(*it) / total_ns) < 20)) { log(", ..."); @@ -321,6 +301,32 @@ int main(int argc, char **argv) log("%s\n", out_count ? "" : " no commands executed"); } +#ifdef COVER_ACTIVE + if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE")) + { + char filename_buffer[4096]; + FILE *f; + + if (getenv("YOSYS_COVER_DIR")) { + snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", getenv("YOSYS_COVER_DIR"), getpid()); + f = fdopen(mkstemps(filename_buffer, 4), "w"); + } else { + snprintf(filename_buffer, 4096, "%s", getenv("YOSYS_COVER_FILE")); + f = fopen(filename_buffer, "a+"); + } + + if (f == NULL) + log_error("Can't create coverage file `%s'.\n", filename_buffer); + + log("\n", filename_buffer); + + for (auto &it : get_coverage_data()) + fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); + + fclose(f); + } +#endif + if (call_abort) abort(); diff --git a/kernel/log.cc b/kernel/log.cc index 64dd7a92a..10eb2563c 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "libs/sha1/sha1.h" #include "backends/ilang/ilang_backend.h" #include @@ -32,6 +33,8 @@ YOSYS_NAMESPACE_BEGIN std::vector log_files; FILE *log_errfile = NULL; +SHA1 *log_hasher = NULL; + bool log_time = false; bool log_cmd_error_throw = false; int log_verbose_level; @@ -44,11 +47,20 @@ static bool next_print_log = false; void logv(const char *format, va_list ap) { - if (log_time) { - while (format[0] == '\n' && format[1] != 0) { - format++; - log("\n"); - } + while (format[0] == '\n' && format[1] != 0) { + log("\n"); + format++; + } + + std::string str = vstringf(format, ap); + + if (log_hasher) + log_hasher->update(str); + + if (log_time) + { + std::string time_str; + if (next_print_log || initial_tv.tv_sec == 0) { next_print_log = false; struct timeval tv; @@ -61,18 +73,18 @@ void logv(const char *format, va_list ap) } tv.tv_sec -= initial_tv.tv_sec; tv.tv_usec -= initial_tv.tv_usec; - log("[%05d.%06d] ", int(tv.tv_sec), int(tv.tv_usec)); + time_str += stringf("[%05d.%06d] ", int(tv.tv_sec), int(tv.tv_usec)); } + if (format[0] && format[strlen(format)-1] == '\n') next_print_log = true; - } - for (auto f : log_files) { - va_list aq; - va_copy(aq, ap); - vfprintf(f, format, aq); - va_end(aq); + for (auto f : log_files) + fputs(time_str.c_str(), f); } + + for (auto f : log_files) + fputs(str.c_str(), f); } void logv_header(const char *format, va_list ap) diff --git a/kernel/log.h b/kernel/log.h index 8e46ad493..2e968039f 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -38,6 +38,8 @@ struct log_cmd_error_expection { }; extern std::vector log_files; extern FILE *log_errfile; +extern class SHA1 *log_hasher; + extern bool log_time; extern bool log_cmd_error_throw; extern int log_verbose_level; diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 671945631..89a9cdf7f 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -37,13 +37,22 @@ Tcl_Interp *yosys_tcl_interp = NULL; std::string stringf(const char *fmt, ...) { std::string string; - char *str = NULL; va_list ap; va_start(ap, fmt); + string = vstringf(fmt, ap); + va_end(ap); + + return string; +} + +std::string vstringf(const char *fmt, va_list ap) +{ + std::string string; + char *str = NULL; + if (vasprintf(&str, fmt, ap) < 0) str = NULL; - va_end(ap); if (str != NULL) { string = str; @@ -71,6 +80,9 @@ void yosys_shutdown() { log_pop(); + delete yosys_design; + yosys_design = NULL; + for (auto f : log_files) if (f != stderr) fclose(f); diff --git a/kernel/yosys.h b/kernel/yosys.h index d9db57c51..e90dcc46e 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -43,6 +43,7 @@ #include #include #include +#include #define PRIVATE_NAMESPACE_BEGIN namespace { #define PRIVATE_NAMESPACE_END } @@ -68,6 +69,7 @@ namespace RTLIL { } std::string stringf(const char *fmt, ...); +std::string vstringf(const char *fmt, va_list ap); template int SIZE(const T &obj) { return obj.size(); } int SIZE(RTLIL::Wire *wire); -- cgit v1.2.3 From 14412e6c957a34381c33740426b35f7b90a446be Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 00:45:25 +0200 Subject: Preparations for RTLIL::IdString redesign: cleanup of existing code --- kernel/celltypes.h | 10 +++++----- kernel/log.cc | 4 ++-- kernel/log.h | 2 +- kernel/rtlil.h | 56 +++++++++++++++++++++++++++++++++++++++++++++--------- kernel/yosys.cc | 10 +++++----- kernel/yosys.h | 1 + 6 files changed, 61 insertions(+), 22 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index e1a1110d3..993863827 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -29,7 +29,7 @@ struct CellTypes { - std::set cell_types; + std::set cell_types; std::vector designs; CellTypes() @@ -168,7 +168,7 @@ struct CellTypes designs.clear(); } - bool cell_known(std::string type) + bool cell_known(RTLIL::IdString type) { if (cell_types.count(type) > 0) return true; @@ -178,7 +178,7 @@ struct CellTypes return false; } - bool cell_output(std::string type, std::string port) + bool cell_output(RTLIL::IdString type, RTLIL::IdString port) { if (cell_types.count(type) == 0) { for (auto design : designs) @@ -201,7 +201,7 @@ struct CellTypes return false; } - bool cell_input(std::string type, std::string port) + bool cell_input(RTLIL::IdString type, RTLIL::IdString port) { if (cell_types.count(type) == 0) { for (auto design : designs) @@ -219,7 +219,7 @@ struct CellTypes return false; } - static RTLIL::Const eval(std::string type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) + static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { if (type == "$sshr" && !signed1) type = "$shr"; diff --git a/kernel/log.cc b/kernel/log.cc index 10eb2563c..1595596ac 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -203,12 +203,12 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) return string_buf.back().c_str(); } -const char *log_id(std::string str) +const char *log_id(RTLIL::IdString str) { if (str.size() > 1 && str[0] == '\\' && str[1] != '$') string_buf.push_back(str.substr(1)); else - string_buf.push_back(str); + string_buf.push_back(str.str()); return string_buf.back().c_str(); } diff --git a/kernel/log.h b/kernel/log.h index 2e968039f..118ff69ba 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -60,7 +60,7 @@ void log_reset_stack(); void log_flush(); const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); -const char *log_id(std::string id); +const char *log_id(RTLIL::IdString id); template static inline const char *log_id(T *obj) { return log_id(obj->name); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0685f1ea2..b423b1bc9 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -72,9 +72,7 @@ namespace RTLIL typedef std::pair SigSig; -#ifdef NDEBUG - typedef std::string IdString; -#else +#if 1 struct IdString : public std::string { IdString() { } IdString(std::string str) : std::string(str) { @@ -100,30 +98,70 @@ namespace RTLIL void check() const { log_assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\'))); } + const std::string& str() const { + return *this; + } + }; +#else + struct IdString { + IdString(); + IdString(const char *str); + IdString(const IdString &str); + IdString(const std::string &str); + + void operator=(const char *rhs); + void operator=(const IdString &rhs); + void operator=(const std::string &rhs); + + operator const char*() const; + const std::string& str() const; + + bool operator<(const IdString &rhs) const; + bool operator==(const IdString &rhs) const; + bool operator!=(const IdString &rhs) const; + bool operator==(const char *rhs) const; + bool operator!=(const char *rhs) const; + std::string operator+(const char *other) const; + + std::string::const_iterator begin() const; + std::string::const_iterator end() const; + char at(int i) const; + const char*c_str() const; + size_t find(char c) const; + std::string substr(size_t pos = 0, size_t len = std::string::npos) const; + size_t size() const; + bool empty() const; + void clear(); }; + #endif - static IdString escape_id(std::string str) __attribute__((unused)); - static IdString escape_id(std::string str) { + static inline std::string escape_id(std::string str) { if (str.size() > 0 && str[0] != '\\' && str[0] != '$') return "\\" + str; return str; } - static std::string unescape_id(std::string str) __attribute__((unused)); - static std::string unescape_id(std::string str) { + static inline std::string unescape_id(std::string str) { if (str.size() > 1 && str[0] == '\\' && str[1] != '$') return str.substr(1); return str; } - static const char *id2cstr(std::string str) __attribute__((unused)); - static const char *id2cstr(std::string str) { + static inline const char *id2cstr(std::string str) { if (str.size() > 1 && str[0] == '\\' && str[1] != '$') return str.c_str() + 1; return str.c_str(); } + static inline std::string unescape_id(RTLIL::IdString str) { + return unescape_id(str.str()); + } + + static inline const char *id2cstr(RTLIL::IdString str) { + return id2cstr(str.str()); + } + template struct sort_by_name { bool operator()(T *a, T *b) const { return a->name < b->name; diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 89a9cdf7f..b5873d188 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -445,7 +445,7 @@ static char *readline_obj_generator(const char *text, int state) { for (auto &it : design->modules_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); } else if (design->modules_.count(design->selected_active_module) > 0) @@ -454,19 +454,19 @@ static char *readline_obj_generator(const char *text, int state) for (auto &it : module->wires_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); for (auto &it : module->memories) if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); for (auto &it : module->cells_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); for (auto &it : module->processes) if (RTLIL::unescape_id(it.first).substr(0, len) == text) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); + obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); } std::sort(obj_names.begin(), obj_names.end()); diff --git a/kernel/yosys.h b/kernel/yosys.h index e90dcc46e..f9c1848ee 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -63,6 +63,7 @@ YOSYS_NAMESPACE_BEGIN namespace RTLIL { + struct IdString; struct SigSpec; struct Wire; struct Cell; -- cgit v1.2.3 From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 13:11:01 +0200 Subject: More cleanups related to RTLIL::IdString usage --- kernel/rtlil.cc | 2 +- kernel/rtlil.h | 97 +++++++++++++++++++++------------------------------------ 2 files changed, 36 insertions(+), 63 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 137058522..af652a9d6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1998,7 +1998,7 @@ void RTLIL::SigSpec::hash() const for (auto &v : c.data.bits) DJB2(that->hash_, v); } else { - for (auto &v : c.wire->name) + for (auto &v : c.wire->name.str()) DJB2(that->hash_, v); DJB2(that->hash_, c.offset); DJB2(that->hash_, c.width); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index b423b1bc9..70e01b721 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -72,70 +72,43 @@ namespace RTLIL typedef std::pair SigSig; -#if 1 - struct IdString : public std::string { - IdString() { } - IdString(std::string str) : std::string(str) { - check(); - } - IdString(const char *s) : std::string(s) { - check(); - } - IdString &operator=(const std::string &str) { - std::string::operator=(str); - check(); - return *this; - } - IdString &operator=(const char *s) { - std::string::operator=(s); - check(); - return *this; - } - bool operator<(const IdString &rhs) { - check(), rhs.check(); - return std::string(*this) < std::string(rhs); - } - void check() const { - log_assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\'))); - } - const std::string& str() const { - return *this; - } - }; -#else - struct IdString { - IdString(); - IdString(const char *str); - IdString(const IdString &str); - IdString(const std::string &str); - - void operator=(const char *rhs); - void operator=(const IdString &rhs); - void operator=(const std::string &rhs); - - operator const char*() const; - const std::string& str() const; - - bool operator<(const IdString &rhs) const; - bool operator==(const IdString &rhs) const; - bool operator!=(const IdString &rhs) const; - bool operator==(const char *rhs) const; - bool operator!=(const char *rhs) const; - std::string operator+(const char *other) const; - - std::string::const_iterator begin() const; - std::string::const_iterator end() const; - char at(int i) const; - const char*c_str() const; - size_t find(char c) const; - std::string substr(size_t pos = 0, size_t len = std::string::npos) const; - size_t size() const; - bool empty() const; - void clear(); + struct IdString + { + private: + std::string str_; + + public: + IdString() : str_() { } + IdString(const char *str) : str_(str) { } + IdString(const IdString &str) : str_(str.str_) { } + IdString(const std::string &str) : str_(str) { } + + void operator=(const char *rhs) { str_ = rhs; } + void operator=(const IdString &rhs) { str_ = rhs.str_; } + void operator=(const std::string &rhs) { str_ = rhs; } + + const std::string& str() const { return str_; } + + // The methods below are just convinience functions for better compatibility + // with std::string. Except clear() they all just deligate to std::string. + + operator const char*() const { return str().c_str(); } + + bool operator<(const IdString &rhs) const { return str() < rhs.str(); } + bool operator==(const IdString &rhs) const { return str() == rhs.str(); } + bool operator!=(const IdString &rhs) const { return str() != rhs.str(); } + + bool operator==(const char *rhs) const { return str() == rhs; } + bool operator!=(const char *rhs) const { return str() != rhs; } + + char at(size_t i) const { return str().at(i); } + const char*c_str() const { return str().c_str(); } + std::string substr(size_t pos = 0, size_t len = std::string::npos) const { return str().substr(pos, len); } + size_t size() const { return str().size(); } + bool empty() const { return str().empty(); } + void clear() { *this = IdString(); } }; -#endif - static inline std::string escape_id(std::string str) { if (str.size() > 0 && str[0] != '\\' && str[0] != '$') return "\\" + str; -- cgit v1.2.3 From 97ad0623dfd772e8bea0728b439a8cd1f7493b7d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 13:34:07 +0200 Subject: Fixed memory corruption related to id2cstr() --- kernel/rtlil.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 70e01b721..daf888b79 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -121,7 +121,7 @@ namespace RTLIL return str; } - static inline const char *id2cstr(std::string str) { + static inline const char *id2cstr(const std::string &str) { if (str.size() > 1 && str[0] == '\\' && str[1] != '$') return str.c_str() + 1; return str.c_str(); @@ -131,7 +131,7 @@ namespace RTLIL return unescape_id(str.str()); } - static inline const char *id2cstr(RTLIL::IdString str) { + static inline const char *id2cstr(const RTLIL::IdString &str) { return id2cstr(str.str()); } -- cgit v1.2.3 From 60f3dc99237afc051560d18f38625337dc80ac80 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 15:11:35 +0200 Subject: Implemented new reference counting RTLIL::IdString --- kernel/rtlil.cc | 8 +++-- kernel/rtlil.h | 97 +++++++++++++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 90 insertions(+), 15 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index af652a9d6..80f63ce74 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -26,6 +26,11 @@ YOSYS_NAMESPACE_BEGIN +std::vector RTLIL::IdString::global_refcount_storage_; +std::vector RTLIL::IdString::global_id_storage_; +std::map RTLIL::IdString::global_id_index_; +std::vector RTLIL::IdString::global_free_idx_list_; + RTLIL::Const::Const() { flags = RTLIL::CONST_FLAG_NONE; @@ -1998,8 +2003,7 @@ void RTLIL::SigSpec::hash() const for (auto &v : c.data.bits) DJB2(that->hash_, v); } else { - for (auto &v : c.wire->name.str()) - DJB2(that->hash_, v); + DJB2(that->hash_, c.wire->name.index_); DJB2(that->hash_, c.offset); DJB2(that->hash_, c.width); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index daf888b79..d95cf11f2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -74,30 +74,101 @@ namespace RTLIL struct IdString { - private: - std::string str_; - - public: - IdString() : str_() { } - IdString(const char *str) : str_(str) { } - IdString(const IdString &str) : str_(str.str_) { } - IdString(const std::string &str) : str_(str) { } + // the global string cache - void operator=(const char *rhs) { str_ = rhs; } - void operator=(const IdString &rhs) { str_ = rhs.str_; } - void operator=(const std::string &rhs) { str_ = rhs; } + static std::vector global_refcount_storage_; + static std::vector global_id_storage_; + static std::map global_id_index_; + static std::vector global_free_idx_list_; - const std::string& str() const { return str_; } + static inline int get_reference(int idx) + { + global_refcount_storage_.at(idx)++; + return idx; + } + + static inline int get_reference(const std::string &str) + { + if (!str.empty()) { + log_assert(str.size() >= 2); + log_assert(str[0] == '$' || str[0] == '\\'); + } + + auto it = global_id_index_.find(str); + if (it != global_id_index_.end()) { + global_refcount_storage_.at(it->second)++; + return it->second; + } + + if (global_free_idx_list_.empty()) { + log_assert(global_id_storage_.size() < 0x40000000); + global_free_idx_list_.push_back(global_id_storage_.size()); + global_id_storage_.push_back(std::string()); + global_refcount_storage_.push_back(0); + } + + int idx = global_free_idx_list_.back(); + global_free_idx_list_.pop_back(); + global_id_storage_.at(idx) = str; + global_id_index_[global_id_storage_.at(idx)] = idx; + global_refcount_storage_.at(idx)++; + return idx; + } + + static inline void put_reference(int idx) + { + if (--global_refcount_storage_.at(idx) != 0) + return; + + global_id_index_.erase(global_id_storage_.at(idx)); + global_id_storage_.at(idx).clear(); + global_free_idx_list_.push_back(idx); + } + + // The actual IdString objects just is a single int + + int index_; + + IdString() : index_(get_reference("")) { } + IdString(const char *str) : index_(get_reference(str)) { } + IdString(const IdString &str) : index_(get_reference(str.index_)) { } + IdString(const std::string &str) : index_(get_reference(str)) { } + ~IdString() { put_reference(index_); } + + void operator=(const IdString &rhs) { + put_reference(index_); + index_ = get_reference(rhs.index_); + } + + void operator=(const char *rhs) { + IdString id(rhs); + *this = id; + } + + void operator=(const std::string &rhs) { + IdString id(rhs); + *this = id; + } + + const std::string& str() const { + return global_id_storage_.at(index_); + } + + bool operator<(const IdString &rhs) const { + return index_ < rhs.index_; + } // The methods below are just convinience functions for better compatibility // with std::string. Except clear() they all just deligate to std::string. operator const char*() const { return str().c_str(); } - bool operator<(const IdString &rhs) const { return str() < rhs.str(); } bool operator==(const IdString &rhs) const { return str() == rhs.str(); } bool operator!=(const IdString &rhs) const { return str() != rhs.str(); } + bool operator==(const std::string &rhs) const { return str() == rhs; } + bool operator!=(const std::string &rhs) const { return str() != rhs; } + bool operator==(const char *rhs) const { return str() == rhs; } bool operator!=(const char *rhs) const { return str() != rhs; } -- cgit v1.2.3 From e590ffc84dac1cb1ea833c5e7a71e958b63f7352 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 15:44:10 +0200 Subject: Improvements in new RTLIL::IdString implementation --- kernel/log.cc | 10 ++++---- kernel/log.h | 2 -- kernel/rtlil.cc | 4 +-- kernel/rtlil.h | 78 +++++++++++++++++++++++++++++++++++++++------------------ kernel/yosys.h | 4 +++ 5 files changed, 65 insertions(+), 33 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 1595596ac..f67d64c25 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -205,11 +205,11 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) const char *log_id(RTLIL::IdString str) { - if (str.size() > 1 && str[0] == '\\' && str[1] != '$') - string_buf.push_back(str.substr(1)); - else - string_buf.push_back(str.str()); - return string_buf.back().c_str(); + const char *p = str; + log_assert(RTLIL::IdString::global_refcount_storage_[str.index_] > 1); + if (p[0] == '\\' && p[1] != '$' && p[1] != 0) + return p+1; + return p; } void log_cell(RTLIL::Cell *cell, std::string indent) diff --git a/kernel/log.h b/kernel/log.h index 118ff69ba..037a62a3b 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -22,8 +22,6 @@ #ifndef LOG_H #define LOG_H -#include -#include #include #include #include diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 80f63ce74..9ee8123ff 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -27,8 +27,8 @@ YOSYS_NAMESPACE_BEGIN std::vector RTLIL::IdString::global_refcount_storage_; -std::vector RTLIL::IdString::global_id_storage_; -std::map RTLIL::IdString::global_id_index_; +std::vector RTLIL::IdString::global_id_storage_; +std::map RTLIL::IdString::global_id_index_; std::vector RTLIL::IdString::global_free_idx_list_; RTLIL::Const::Const() diff --git a/kernel/rtlil.h b/kernel/rtlil.h index d95cf11f2..9430da311 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -76,9 +76,18 @@ namespace RTLIL { // the global string cache + struct char_ptr_cmp { + bool operator()(const char *a, const char *b) { + for (int i = 0; a[i] || b[i]; i++) + if (a[i] != b[i]) + return a[i] < b[i]; + return false; + } + }; + static std::vector global_refcount_storage_; - static std::vector global_id_storage_; - static std::map global_id_index_; + static std::vector global_id_storage_; + static std::map global_id_index_; static std::vector global_free_idx_list_; static inline int get_reference(int idx) @@ -87,14 +96,14 @@ namespace RTLIL return idx; } - static inline int get_reference(const std::string &str) + static inline int get_reference(const char *p) { - if (!str.empty()) { - log_assert(str.size() >= 2); - log_assert(str[0] == '$' || str[0] == '\\'); + if (p[0]) { + log_assert(p[1] != 0); + log_assert(p[0] == '$' || p[0] == '\\'); } - auto it = global_id_index_.find(str); + auto it = global_id_index_.find((char*)p); if (it != global_id_index_.end()) { global_refcount_storage_.at(it->second)++; return it->second; @@ -103,13 +112,13 @@ namespace RTLIL if (global_free_idx_list_.empty()) { log_assert(global_id_storage_.size() < 0x40000000); global_free_idx_list_.push_back(global_id_storage_.size()); - global_id_storage_.push_back(std::string()); + global_id_storage_.push_back(nullptr); global_refcount_storage_.push_back(0); } int idx = global_free_idx_list_.back(); global_free_idx_list_.pop_back(); - global_id_storage_.at(idx) = str; + global_id_storage_.at(idx) = strdup(p); global_id_index_[global_id_storage_.at(idx)] = idx; global_refcount_storage_.at(idx)++; return idx; @@ -121,7 +130,7 @@ namespace RTLIL return; global_id_index_.erase(global_id_storage_.at(idx)); - global_id_storage_.at(idx).clear(); + free(global_id_storage_.at(idx)); global_free_idx_list_.push_back(idx); } @@ -132,7 +141,7 @@ namespace RTLIL IdString() : index_(get_reference("")) { } IdString(const char *str) : index_(get_reference(str)) { } IdString(const IdString &str) : index_(get_reference(str.index_)) { } - IdString(const std::string &str) : index_(get_reference(str)) { } + IdString(const std::string &str) : index_(get_reference(str.c_str())) { } ~IdString() { put_reference(index_); } void operator=(const IdString &rhs) { @@ -150,21 +159,26 @@ namespace RTLIL *this = id; } - const std::string& str() const { + const char*c_str() const { + return global_id_storage_.at(index_); + } + + operator const char*() const { return global_id_storage_.at(index_); } + std::string str() const { + return std::string(global_id_storage_.at(index_)); + } + bool operator<(const IdString &rhs) const { return index_ < rhs.index_; } - // The methods below are just convinience functions for better compatibility - // with std::string. Except clear() they all just deligate to std::string. + bool operator==(const IdString &rhs) const { return index_ == rhs.index_; } + bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; } - operator const char*() const { return str().c_str(); } - - bool operator==(const IdString &rhs) const { return str() == rhs.str(); } - bool operator!=(const IdString &rhs) const { return str() != rhs.str(); } + // The methods below are just convinience functions for better compatibility with std::string. bool operator==(const std::string &rhs) const { return str() == rhs; } bool operator!=(const std::string &rhs) const { return str() != rhs; } @@ -172,12 +186,28 @@ namespace RTLIL bool operator==(const char *rhs) const { return str() == rhs; } bool operator!=(const char *rhs) const { return str() != rhs; } - char at(size_t i) const { return str().at(i); } - const char*c_str() const { return str().c_str(); } - std::string substr(size_t pos = 0, size_t len = std::string::npos) const { return str().substr(pos, len); } - size_t size() const { return str().size(); } - bool empty() const { return str().empty(); } - void clear() { *this = IdString(); } + char at(size_t i) const { + return c_str()[i]; + } + + std::string substr(size_t pos = 0, size_t len = std::string::npos) const { + if (len == std::string::npos) + return std::string(c_str() + pos); + else + return std::string(c_str() + pos, len); + } + + size_t size() const { + return str().size(); + } + + bool empty() const { + return c_str()[0] == 0; + } + + void clear() { + *this = IdString(); + } }; static inline std::string escape_id(std::string str) { diff --git a/kernel/yosys.h b/kernel/yosys.h index f9c1848ee..34777c9a4 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -43,7 +43,11 @@ #include #include #include + #include +#include +#include +#include #define PRIVATE_NAMESPACE_BEGIN namespace { #define PRIVATE_NAMESPACE_END } -- cgit v1.2.3 From 08392aad8f8e7c5bbcfa010c19786b1f318028b6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 15:52:21 +0200 Subject: Limit size of log_signal buffer to 100 elements --- kernel/log.cc | 7 +++++++ kernel/rtlil.h | 4 ++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index f67d64c25..9cabc6a83 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -41,6 +41,7 @@ int log_verbose_level; std::vector header_count; std::list string_buf; +int string_buf_size = 0; static struct timeval initial_tv = { 0, 0 }; static bool next_print_log = false; @@ -166,6 +167,7 @@ void log_pop() { header_count.pop_back(); string_buf.clear(); + string_buf_size = 0; log_flush(); } @@ -174,6 +176,7 @@ void log_reset_stack() while (header_count.size() > 1) header_count.pop_back(); string_buf.clear(); + string_buf_size = 0; log_flush(); } @@ -197,6 +200,10 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) fputc(0, f); fclose(f); + if (string_buf_size < 100) + string_buf_size++; + else + string_buf.pop_front(); string_buf.push_back(ptr); free(ptr); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9430da311..7b989385e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -74,7 +74,7 @@ namespace RTLIL struct IdString { - // the global string cache + // the global id string cache struct char_ptr_cmp { bool operator()(const char *a, const char *b) { @@ -134,7 +134,7 @@ namespace RTLIL global_free_idx_list_.push_back(idx); } - // The actual IdString objects just is a single int + // the actual IdString object is just is a single int int index_; -- cgit v1.2.3 From 768eb846c4473040dc07bf62ce631c8a21474ae8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 16:03:18 +0200 Subject: More bugfixes related to new RTLIL::IdString --- kernel/log.cc | 17 ++++++++++------- kernel/rtlil.h | 29 ++++++++++++++++++++--------- kernel/yosys.cc | 2 +- 3 files changed, 31 insertions(+), 17 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 9cabc6a83..01f6207ec 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -90,22 +90,25 @@ void logv(const char *format, va_list ap) void logv_header(const char *format, va_list ap) { + bool pop_errfile = false; + log("\n"); if (header_count.size() > 0) header_count.back()++; + + if (int(header_count.size()) <= log_verbose_level && log_errfile != NULL) { + log_files.push_back(log_errfile); + pop_errfile = true; + } + for (int c : header_count) log("%d.", c); log(" "); logv(format, ap); log_flush(); - if (int(header_count.size()) <= log_verbose_level && log_errfile != NULL) { - for (int c : header_count) - fprintf(log_errfile, "%d.", c); - fprintf(log_errfile, " "); - vfprintf(log_errfile, format, ap); - fflush(log_errfile); - } + if (pop_errfile) + log_files.pop_back(); } void logv_error(const char *format, va_list ap) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7b989385e..6529603eb 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -126,11 +126,14 @@ namespace RTLIL static inline void put_reference(int idx) { + log_assert(global_refcount_storage_.at(idx) > 0); + if (--global_refcount_storage_.at(idx) != 0) return; global_id_index_.erase(global_id_storage_.at(idx)); free(global_id_storage_.at(idx)); + global_id_storage_.at(idx) = nullptr; global_free_idx_list_.push_back(idx); } @@ -191,7 +194,7 @@ namespace RTLIL } std::string substr(size_t pos = 0, size_t len = std::string::npos) const { - if (len == std::string::npos) + if (len == std::string::npos || len >= strlen(c_str() + pos)) return std::string(c_str() + pos); else return std::string(c_str() + pos, len); @@ -208,6 +211,16 @@ namespace RTLIL void clear() { *this = IdString(); } + + // The following is a helper key_compare class. Instead of for example std::set + // use std::set> if the order of cells in the + // set has an influence on the algorithm. + + template struct compare_ptr_by_name { + bool operator()(const T *a, const T *b) { + return (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name); + } + }; }; static inline std::string escape_id(std::string str) { @@ -222,18 +235,12 @@ namespace RTLIL return str; } - static inline const char *id2cstr(const std::string &str) { - if (str.size() > 1 && str[0] == '\\' && str[1] != '$') - return str.c_str() + 1; - return str.c_str(); - } - static inline std::string unescape_id(RTLIL::IdString str) { return unescape_id(str.str()); } static inline const char *id2cstr(const RTLIL::IdString &str) { - return id2cstr(str.str()); + return log_id(str); } template struct sort_by_name { @@ -833,7 +840,11 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigSpec &sig); bool operator <(const RTLIL::SigBit &other) const { - return (wire != other.wire) ? (wire < other.wire) : wire ? (offset < other.offset) : (data < other.data); + if (wire == other.wire) + return wire ? (offset < other.offset) : (data < other.data); + if (wire != nullptr && other.wire != nullptr) + return wire->name < other.wire->name; + return wire < other.wire; } bool operator ==(const RTLIL::SigBit &other) const { diff --git a/kernel/yosys.cc b/kernel/yosys.cc index b5873d188..dff31db07 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -122,7 +122,7 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter) str += stringf("(%d) ", recursion_counter); str += "yosys"; if (!design->selected_active_module.empty()) - str += stringf(" [%s]", RTLIL::id2cstr(design->selected_active_module)); + str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str()); if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) { if (design->selected_active_module.empty()) str += "*"; -- cgit v1.2.3 From 04727c7e0fb4c00b38999da192e4ada2a6f9474a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 18:58:40 +0200 Subject: No implicit conversion from IdString to anything else --- kernel/log.cc | 2 +- kernel/register.cc | 4 ++-- kernel/rtlil.cc | 28 ++++++++++++++-------------- kernel/rtlil.h | 10 +++++----- 4 files changed, 22 insertions(+), 22 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 01f6207ec..81cc26da3 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -215,7 +215,7 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) const char *log_id(RTLIL::IdString str) { - const char *p = str; + const char *p = str.c_str(); log_assert(RTLIL::IdString::global_refcount_storage_[str.index_] > 1); if (p[0] == '\\' && p[1] != '$' && p[1] != 0) return p+1; diff --git a/kernel/register.cc b/kernel/register.cc index 4d204069c..868dbb949 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -240,7 +240,7 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command) { std::string backup_selected_active_module = design->selected_active_module; - design->selected_active_module = module->name; + design->selected_active_module = module->name.str(); design->selection_stack.push_back(RTLIL::Selection(false)); design->selection_stack.back().select(module); @@ -253,7 +253,7 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector args) { std::string backup_selected_active_module = design->selected_active_module; - design->selected_active_module = module->name; + design->selected_active_module = module->name.str(); design->selection_stack.push_back(RTLIL::Selection(false)); design->selection_stack.back().select(module); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9ee8123ff..2838449bb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -286,7 +286,7 @@ void RTLIL::Design::check() for (auto &it : modules_) { log_assert(this == it.second->design); log_assert(it.first == it.second->name); - log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(!it.first.empty()); it.second->check(); } #endif @@ -499,7 +499,7 @@ namespace { void check() { - if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || + if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") return; @@ -818,38 +818,38 @@ void RTLIL::Module::check() for (auto &it : wires_) { log_assert(this == it.second->module); log_assert(it.first == it.second->name); - log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(!it.first.empty()); log_assert(it.second->width >= 0); log_assert(it.second->port_id >= 0); for (auto &it2 : it.second->attributes) { - log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(!it2.first.empty()); } } for (auto &it : memories) { log_assert(it.first == it.second->name); - log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(!it.first.empty()); log_assert(it.second->width >= 0); log_assert(it.second->size >= 0); for (auto &it2 : it.second->attributes) { - log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(!it2.first.empty()); } } for (auto &it : cells_) { log_assert(this == it.second->module); log_assert(it.first == it.second->name); - log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); - log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$')); + log_assert(!it.first.empty()); + log_assert(!it.second->type.empty()); for (auto &it2 : it.second->connections()) { - log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(!it2.first.empty()); it2.second.check(); } for (auto &it2 : it.second->attributes) { - log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(!it2.first.empty()); } for (auto &it2 : it.second->parameters) { - log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$')); + log_assert(!it2.first.empty()); } InternalCellChecker checker(this, it.second); checker.check(); @@ -857,7 +857,7 @@ void RTLIL::Module::check() for (auto &it : processes) { log_assert(it.first == it.second->name); - log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(!it.first.empty()); // FIXME: More checks here.. } @@ -868,7 +868,7 @@ void RTLIL::Module::check() } for (auto &it : attributes) { - log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); + log_assert(!it.first.empty()); } #endif } @@ -1597,7 +1597,7 @@ void RTLIL::Cell::check() void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { - if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || + if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") return; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6529603eb..502969a1f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -162,11 +162,7 @@ namespace RTLIL *this = id; } - const char*c_str() const { - return global_id_storage_.at(index_); - } - - operator const char*() const { + const char *c_str() const { return global_id_storage_.at(index_); } @@ -193,6 +189,10 @@ namespace RTLIL return c_str()[i]; } + char operator[](size_t i) const { + return c_str()[i]; + } + std::string substr(size_t pos = 0, size_t len = std::string::npos) const { if (len == std::string::npos || len >= strlen(c_str() + pos)) return std::string(c_str() + pos); -- cgit v1.2.3 From 8e7361f128ce00a742412931efcf7cbe5795a39a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 19:08:02 +0200 Subject: Removed at() method from RTLIL::IdString --- kernel/rtlil.cc | 4 ++-- kernel/rtlil.h | 9 ++++----- 2 files changed, 6 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2838449bb..56c631f3b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -490,9 +490,9 @@ namespace { } for (auto &conn : cell->connections()) { - if (conn.first.size() != 2 || conn.first.at(0) != '\\') + if (conn.first.size() != 2 || conn.first[0] != '\\') error(__LINE__); - if (strchr(ports, conn.first.at(1)) == NULL) + if (strchr(ports, conn.first[1]) == NULL) error(__LINE__); } } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 502969a1f..ab15024e0 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -185,12 +185,11 @@ namespace RTLIL bool operator==(const char *rhs) const { return str() == rhs; } bool operator!=(const char *rhs) const { return str() != rhs; } - char at(size_t i) const { - return c_str()[i]; - } - char operator[](size_t i) const { - return c_str()[i]; + const char *p = c_str(); + for (; i != 0; i--, p++) + log_assert(*p != 0); + return *p; } std::string substr(size_t pos = 0, size_t len = std::string::npos) const { -- cgit v1.2.3 From b6acbc82e6a2954d453188a9997da2a30731ddac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 20:54:30 +0200 Subject: Bugfix in "techmap -extern" --- kernel/rtlil.cc | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 56c631f3b..792474af4 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -815,25 +815,34 @@ namespace { void RTLIL::Module::check() { #ifndef NDEBUG + std::vector ports_declared; for (auto &it : wires_) { log_assert(this == it.second->module); log_assert(it.first == it.second->name); log_assert(!it.first.empty()); log_assert(it.second->width >= 0); log_assert(it.second->port_id >= 0); - for (auto &it2 : it.second->attributes) { + for (auto &it2 : it.second->attributes) log_assert(!it2.first.empty()); - } + if (it.second->port_id) { + log_assert(it.second->port_input || it.second->port_output); + if (SIZE(ports_declared) < it.second->port_id) + ports_declared.resize(it.second->port_id); + log_assert(ports_declared[it.second->port_id-1] == false); + ports_declared[it.second->port_id-1] = true; + } else + log_assert(!it.second->port_input && !it.second->port_output); } + for (auto port_declared : ports_declared) + log_assert(port_declared == true); for (auto &it : memories) { log_assert(it.first == it.second->name); log_assert(!it.first.empty()); log_assert(it.second->width >= 0); log_assert(it.second->size >= 0); - for (auto &it2 : it.second->attributes) { + for (auto &it2 : it.second->attributes) log_assert(!it2.first.empty()); - } } for (auto &it : cells_) { @@ -845,12 +854,10 @@ void RTLIL::Module::check() log_assert(!it2.first.empty()); it2.second.check(); } - for (auto &it2 : it.second->attributes) { + for (auto &it2 : it.second->attributes) log_assert(!it2.first.empty()); - } - for (auto &it2 : it.second->parameters) { + for (auto &it2 : it.second->parameters) log_assert(!it2.first.empty()); - } InternalCellChecker checker(this, it.second); checker.check(); } @@ -867,9 +874,8 @@ void RTLIL::Module::check() it.second.check(); } - for (auto &it : attributes) { + for (auto &it : attributes) log_assert(!it.first.empty()); - } #endif } -- cgit v1.2.3 From bc947d4c7b9b7691e2aeab608c78c4658314cec2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 21:54:30 +0200 Subject: Fixed a va_list corruption in logv_error() --- kernel/log.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 81cc26da3..09673dc2e 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -113,12 +113,11 @@ void logv_header(const char *format, va_list ap) void logv_error(const char *format, va_list ap) { + if (log_errfile != NULL) + log_files.push_back(log_errfile); + log("ERROR: "); logv(format, ap); - if (log_errfile != NULL) { - fprintf(log_errfile, "ERROR: "); - vfprintf(log_errfile, format, ap); - } log_flush(); exit(1); } -- cgit v1.2.3 From 75423169c59022b3680aa3bf7de0877bc43a8082 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Aug 2014 14:59:13 +0200 Subject: Added ID() macro for static IdStrings --- kernel/yosys.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index 34777c9a4..f9bbc0e44 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -103,6 +103,9 @@ RTLIL::IdString new_id(std::string file, int line, std::string func); #define NEW_ID \ YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__) +#define ID(_str) \ + ([]() { static YOSYS_NAMESPACE_PREFIX RTLIL::IdString _id(_str); return _id; })() + RTLIL::Design *yosys_get_design(); std::string proc_self_dirname(); std::string proc_share_dirname(); -- cgit v1.2.3 From 653edd7a2f857d09bd8cecc48cc9ac76aea33098 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Aug 2014 15:00:38 +0200 Subject: Added query() API to ModIndex --- kernel/modtools.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/modtools.h b/kernel/modtools.h index 09f2ae65e..56bc1882d 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -29,11 +29,11 @@ YOSYS_NAMESPACE_BEGIN struct ModIndex : public RTLIL::Monitor { struct PortInfo { - const RTLIL::Cell* cell; - const RTLIL::IdString &port; - const int offset; + RTLIL::Cell* cell; + RTLIL::IdString port; + int offset; - PortInfo(RTLIL::Cell* _c, const RTLIL::IdString &_p, int _o) : cell(_c), port(_p), offset(_o) { } + PortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { } bool operator<(const PortInfo &other) const { if (cell != other.cell) @@ -57,13 +57,13 @@ struct ModIndex : public RTLIL::Monitor std::map database; bool auto_reload_module; - void port_add(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &sig) + void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig) { for (int i = 0; i < SIZE(sig); i++) database[sigmap(sig[i])].ports.insert(PortInfo(cell, port, i)); } - void port_del(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &sig) + void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig) { for (int i = 0; i < SIZE(sig); i++) database[sigmap(sig[i])].ports.erase(PortInfo(cell, port, i)); @@ -122,14 +122,52 @@ struct ModIndex : public RTLIL::Monitor auto_reload_module = true; } - ModIndex(RTLIL::Module *_m) : module(_m) { + ModIndex(RTLIL::Module *_m) : module(_m) + { auto_reload_module = true; module->monitors.insert(this); } - ~ModIndex() { + ~ModIndex() + { module->monitors.erase(this); } + + SigBitInfo *query(RTLIL::SigBit bit) + { + if (auto_reload_module) + reload_module(); + auto it = database.find(sigmap(bit)); + if (it == database.end()) + return nullptr; + else + return &it->second; + } + + bool query_is_input(RTLIL::SigBit bit) + { + const SigBitInfo *info = query(bit); + if (info == nullptr) + return false; + return info->is_input; + } + + bool query_is_output(RTLIL::SigBit bit) + { + const SigBitInfo *info = query(bit); + if (info == nullptr) + return false; + return info->is_output; + } + + std::set &query_ports(RTLIL::SigBit bit) + { + static std::set empty_result_set; + SigBitInfo *info = query(bit); + if (info == nullptr) + return empty_result_set; + return info->ports; + } }; struct ModWalker -- cgit v1.2.3 From ebbbe7fc8360ca0bd8f840d3df1b77ab2fb569b6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 4 Aug 2014 15:08:35 +0200 Subject: Added RTLIL::IdString::in(...) --- kernel/rtlil.h | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index ab15024e0..8dfcbcaa0 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -170,20 +170,20 @@ namespace RTLIL return std::string(global_id_storage_.at(index_)); } - bool operator<(const IdString &rhs) const { + bool operator<(IdString rhs) const { return index_ < rhs.index_; } - bool operator==(const IdString &rhs) const { return index_ == rhs.index_; } - bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; } + bool operator==(IdString rhs) const { return index_ == rhs.index_; } + bool operator!=(IdString rhs) const { return index_ != rhs.index_; } // The methods below are just convinience functions for better compatibility with std::string. bool operator==(const std::string &rhs) const { return str() == rhs; } bool operator!=(const std::string &rhs) const { return str() != rhs; } - bool operator==(const char *rhs) const { return str() == rhs; } - bool operator!=(const char *rhs) const { return str() != rhs; } + bool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; } + bool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; } char operator[](size_t i) const { const char *p = c_str(); @@ -220,6 +220,19 @@ namespace RTLIL return (a == nullptr || b == nullptr) ? (a < b) : (a->name < b->name); } }; + + // often one needs to check if a given IdString is part of a list (for example a list + // of cell types). the following functions helps with that. + + template + bool in(T first, Args... rest) { + return in(first) || in(rest...); + } + + bool in(IdString rhs) { return *this == rhs; } + bool in(const char *rhs) { return *this == rhs; } + bool in(const std::string &rhs) { return *this == rhs; } + bool in(const std::set &rhs) { return rhs.count(*this) != 0; } }; static inline std::string escape_id(std::string str) { -- cgit v1.2.3 From 523df7314502e2674df5287289dcf8eb204c17ac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Aug 2014 14:47:03 +0200 Subject: Added support for truncating of wires to wreduce pass --- kernel/modtools.h | 24 ++++++++++++++++-------- kernel/rtlil.cc | 30 ++++++++++++++++++++++++++++++ kernel/rtlil.h | 7 +++++++ 3 files changed, 53 insertions(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/modtools.h b/kernel/modtools.h index 56bc1882d..fde59d142 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -59,14 +59,20 @@ struct ModIndex : public RTLIL::Monitor void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig) { - for (int i = 0; i < SIZE(sig); i++) - database[sigmap(sig[i])].ports.insert(PortInfo(cell, port, i)); + for (int i = 0; i < SIZE(sig); i++) { + RTLIL::SigBit bit = sigmap(sig[i]); + if (bit.wire) + database[bit].ports.insert(PortInfo(cell, port, i)); + } } void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig) { - for (int i = 0; i < SIZE(sig); i++) - database[sigmap(sig[i])].ports.erase(PortInfo(cell, port, i)); + for (int i = 0; i < SIZE(sig); i++) { + RTLIL::SigBit bit = sigmap(sig[i]); + if (bit.wire) + database[bit].ports.erase(PortInfo(cell, port, i)); + } } const SigBitInfo &info(RTLIL::SigBit bit) @@ -83,10 +89,11 @@ struct ModIndex : public RTLIL::Monitor for (auto wire : module->wires()) if (wire->port_input || wire->port_output) for (int i = 0; i < SIZE(wire); i++) { - if (wire->port_input) - database[sigmap(RTLIL::SigBit(wire, i))].is_input = true; - if (wire->port_output) - database[sigmap(RTLIL::SigBit(wire, i))].is_output = true; + RTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i)); + if (bit.wire && wire->port_input) + database[bit].is_input = true; + if (bit.wire && wire->port_output) + database[bit].is_output = true; } for (auto cell : module->cells()) for (auto &conn : cell->connections()) @@ -137,6 +144,7 @@ struct ModIndex : public RTLIL::Monitor { if (auto_reload_module) reload_module(); + auto it = database.find(sigmap(bit)); if (it == database.end()) return nullptr; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 792474af4..8ff564515 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1071,6 +1071,36 @@ void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name) log_abort(); } +void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2) +{ + log_assert(wires_[w1->name] == w1); + log_assert(wires_[w2->name] == w2); + log_assert(refcount_wires_ == 0); + + wires_.erase(w1->name); + wires_.erase(w2->name); + + std::swap(w1->name, w2->name); + + wires_[w1->name] = w1; + wires_[w2->name] = w2; +} + +void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2) +{ + log_assert(cells_[c1->name] == c1); + log_assert(cells_[c2->name] == c2); + log_assert(refcount_cells_ == 0); + + cells_.erase(c1->name); + cells_.erase(c2->name); + + std::swap(c1->name, c2->name); + + cells_[c1->name] = c1; + cells_[c2->name] = c2; +} + static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) { if (a->port_id && !b->port_id) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8dfcbcaa0..8ec599417 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -590,6 +590,10 @@ public: std::vector selected_wires() const; std::vector selected_cells() const; + template bool selected(T *member) const { + return design->selected_member(name, member->name); + } + RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } @@ -604,6 +608,9 @@ public: void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); + void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); -- cgit v1.2.3 From 0b8b8d41eb07fd048cbe68acfe4b724e314bbb41 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 7 Aug 2014 22:37:01 +0200 Subject: Fixed build with gcc-4.6 --- kernel/modtools.h | 2 +- kernel/register.h | 4 ++-- kernel/yosys.h | 8 ++++++++ 3 files changed, 11 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/modtools.h b/kernel/modtools.h index fde59d142..58cdd5b0e 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -102,7 +102,7 @@ struct ModIndex : public RTLIL::Monitor auto_reload_module = false; } - virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override + virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) OVERRIDE { if (auto_reload_module) reload_module(); diff --git a/kernel/register.h b/kernel/register.h index 93a3308ad..d7e4281c2 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -77,7 +77,7 @@ struct Frontend : Pass Frontend(std::string name, std::string short_help = "** document me **"); virtual void run_register(); virtual ~Frontend(); - virtual void execute(std::vector args, RTLIL::Design *design) override final; + virtual void execute(std::vector args, RTLIL::Design *design) OVERRIDE FINAL; virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; static std::vector next_args; @@ -93,7 +93,7 @@ struct Backend : Pass Backend(std::string name, std::string short_help = "** document me **"); virtual void run_register(); virtual ~Backend(); - virtual void execute(std::vector args, RTLIL::Design *design) override final; + virtual void execute(std::vector args, RTLIL::Design *design) OVERRIDE FINAL; virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; void extra_args(FILE *&f, std::string &filename, std::vector args, size_t argidx); diff --git a/kernel/yosys.h b/kernel/yosys.h index f9bbc0e44..e12069b4c 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -64,6 +64,14 @@ # define USING_YOSYS_NAMESPACE #endif +#if __cplusplus >= 201103L +# define OVERRIDE override +# define FINAL final +#else +# define OVERRIDE +# define FINAL +#endif + YOSYS_NAMESPACE_BEGIN namespace RTLIL { -- cgit v1.2.3 From 5215723c64037ba1ee7884423aee1b9c307b5850 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 11 Aug 2014 15:55:41 +0200 Subject: Another build fix by americanrouter (via reddit) --- kernel/log.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 09673dc2e..1f0826039 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -238,6 +238,7 @@ void log_cell(RTLIL::Cell *cell, std::string indent) // --------------------------------------------------- // This is the magic behind the code coverage counters // --------------------------------------------------- +#ifdef COVER_ACTIVE std::map> extra_coverage_data; @@ -283,5 +284,7 @@ std::map> get_coverage_data() return coverage_data; } +#endif + YOSYS_NAMESPACE_END -- cgit v1.2.3 From e5ac8fdf2bf9d4bed41daf420aa8a94018c0ded4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Aug 2014 15:39:48 +0200 Subject: Fixed SigBit(RTLIL::Wire *wire) constructor --- kernel/rtlil.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8ec599417..1e967f26c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -852,7 +852,7 @@ struct RTLIL::SigBit SigBit() : wire(NULL), data(RTLIL::State::S0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } - SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); } + SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); } SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; } -- cgit v1.2.3 From 13f2f36884fa3e4a8329dab2556af7000cb085df Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 11:39:46 +0200 Subject: RIP $safe_pmux --- kernel/celltypes.h | 3 +-- kernel/consteval.h | 7 ++----- kernel/rtlil.cc | 7 +++---- kernel/rtlil.h | 6 ++---- kernel/satgen.h | 10 +--------- 5 files changed, 9 insertions(+), 24 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 993863827..23d06f820 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -98,7 +98,6 @@ struct CellTypes cell_types.insert("$pmux"); cell_types.insert("$slice"); cell_types.insert("$concat"); - cell_types.insert("$safe_pmux"); cell_types.insert("$lut"); cell_types.insert("$assert"); } @@ -307,7 +306,7 @@ struct CellTypes static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &sel) { - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_") { + if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") { RTLIL::Const ret = arg1; for (size_t i = 0; i < sel.bits.size(); i++) if (sel.bits[i] == RTLIL::State::S1) { diff --git a/kernel/consteval.h b/kernel/consteval.h index 529d8962d..dbe13ea7e 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -104,7 +104,7 @@ struct ConstEval if (cell->hasPort("\\B")) sig_b = cell->getPort("\\B"); - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_") + if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") { std::vector y_candidates; int count_maybe_set_s_bits = 0; @@ -125,10 +125,7 @@ struct ConstEval count_set_s_bits++; } - if (cell->type == "$safe_pmux" && count_set_s_bits > 1) - y_candidates.clear(); - - if ((cell->type == "$safe_pmux" && count_maybe_set_s_bits > 1) || count_set_s_bits == 0) + if (count_set_s_bits == 0) y_candidates.push_back(sig_a); std::vector y_values; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8ff564515..201c717e4 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -608,7 +608,7 @@ namespace { return; } - if (cell->type == "$pmux" || cell->type == "$safe_pmux") { + if (cell->type == "$pmux") { port("\\A", param("\\WIDTH")); port("\\B", param("\\WIDTH") * param("\\S_WIDTH")); port("\\S", param("\\S_WIDTH")); @@ -1293,7 +1293,6 @@ DEF_METHOD(LogicOr, 1, "$logic_or") } DEF_METHOD(Mux, "$mux", 0) DEF_METHOD(Pmux, "$pmux", 1) -DEF_METHOD(SafePmux, "$safe_pmux", 1) #undef DEF_METHOD #define DEF_METHOD_2(_func, _type, _P1, _P2) \ @@ -1637,10 +1636,10 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") return; - if (type == "$mux" || type == "$pmux" || type == "$safe_pmux") + if (type == "$mux" || type == "$pmux") { parameters["\\WIDTH"] = SIZE(connections_["\\Y"]); - if (type == "$pmux" || type == "$safe_pmux") + if (type == "$pmux") parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]); check(); return; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1e967f26c..10da74636 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -662,9 +662,8 @@ public: RTLIL::Cell* addLogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addLogicOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); - RTLIL::Cell* addMux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); - RTLIL::Cell* addPmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); - RTLIL::Cell* addSafePmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); + RTLIL::Cell* addMux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); + RTLIL::Cell* addPmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); RTLIL::Cell* addSlice (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset); RTLIL::Cell* addConcat (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); @@ -743,7 +742,6 @@ public: RTLIL::SigSpec Mux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); RTLIL::SigSpec Pmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); - RTLIL::SigSpec SafePmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); RTLIL::SigSpec InvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a); RTLIL::SigSpec AndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); diff --git a/kernel/satgen.h b/kernel/satgen.h index 1ada1e16a..8284cdeb2 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -316,7 +316,7 @@ struct SatGen return true; } - if (cell->type == "$pmux" || cell->type == "$safe_pmux") + if (cell->type == "$pmux") { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); @@ -330,8 +330,6 @@ struct SatGen std::vector part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size()); tmp = ez->vec_ite(s.at(i), part_of_b, tmp); } - if (cell->type == "$safe_pmux") - tmp = ez->vec_ite(ez->onehot(s, true), tmp, a); ez->assume(ez->vec_eq(tmp, yy)); if (model_undef) @@ -370,12 +368,6 @@ struct SatGen int maybe_a = ez->NOT(maybe_one_hot); - if (cell->type == "$safe_pmux") { - maybe_a = ez->OR(maybe_a, maybe_many_hot); - bits_set = ez->vec_ite(sure_many_hot, ez->vec_or(a, undef_a), bits_set); - bits_clr = ez->vec_ite(sure_many_hot, ez->vec_or(ez->vec_not(a), undef_a), bits_clr); - } - bits_set = ez->vec_ite(maybe_a, ez->vec_or(bits_set, ez->vec_or(bits_set, ez->vec_or(a, undef_a))), bits_set); bits_clr = ez->vec_ite(maybe_a, ez->vec_or(bits_clr, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(a), undef_a))), bits_clr); -- cgit v1.2.3 From 746aac540b815099c6a63077010555369d7fdd5a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 15:46:51 +0200 Subject: Refactoring of CellType class --- kernel/celltypes.h | 240 +++++++++++++++++++++++------------------------------ kernel/rtlil.cc | 16 ++-- 2 files changed, 111 insertions(+), 145 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 23d06f820..6beaa3fed 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -27,195 +27,165 @@ #include #include +struct CellType +{ + RTLIL::IdString type; + std::set inputs, outputs; + bool maybe_has_internal_state; +}; + struct CellTypes { - std::set cell_types; - std::vector designs; + std::map cell_types; CellTypes() { } - CellTypes(const RTLIL::Design *design) + CellTypes(RTLIL::Design *design) { setup(design); } - void setup(const RTLIL::Design *design = NULL) + void setup(RTLIL::Design *design = NULL) { if (design) setup_design(design); + setup_internals(); setup_internals_mem(); setup_stdcells(); setup_stdcells_mem(); } - void setup_design(const RTLIL::Design *design) + void setup_type(RTLIL::IdString type, const std::set &inputs, const std::set &outputs, bool maybe_has_internal_state) + { + CellType ct = {type, inputs, outputs, maybe_has_internal_state}; + cell_types[ct.type] = ct; + } + + void setup_module(RTLIL::Module *module) + { + std::set inputs, outputs; + for (auto wire : module->wires()) { + if (wire->port_input) + inputs.insert(wire->name); + if (wire->port_output) + outputs.insert(wire->name); + } + setup_type(module->name, inputs, outputs, true); + } + + void setup_design(RTLIL::Design *design) { - designs.push_back(design); + for (auto module : design->modules()) + setup_module(module); } void setup_internals() { - cell_types.insert("$not"); - cell_types.insert("$pos"); - cell_types.insert("$bu0"); - cell_types.insert("$neg"); - cell_types.insert("$and"); - cell_types.insert("$or"); - cell_types.insert("$xor"); - cell_types.insert("$xnor"); - cell_types.insert("$reduce_and"); - cell_types.insert("$reduce_or"); - cell_types.insert("$reduce_xor"); - cell_types.insert("$reduce_xnor"); - cell_types.insert("$reduce_bool"); - cell_types.insert("$shl"); - cell_types.insert("$shr"); - cell_types.insert("$sshl"); - cell_types.insert("$sshr"); - cell_types.insert("$shift"); - cell_types.insert("$shiftx"); - cell_types.insert("$lt"); - cell_types.insert("$le"); - cell_types.insert("$eq"); - cell_types.insert("$ne"); - cell_types.insert("$eqx"); - cell_types.insert("$nex"); - cell_types.insert("$ge"); - cell_types.insert("$gt"); - cell_types.insert("$add"); - cell_types.insert("$sub"); - cell_types.insert("$mul"); - cell_types.insert("$div"); - cell_types.insert("$mod"); - cell_types.insert("$pow"); - cell_types.insert("$logic_not"); - cell_types.insert("$logic_and"); - cell_types.insert("$logic_or"); - cell_types.insert("$mux"); - cell_types.insert("$pmux"); - cell_types.insert("$slice"); - cell_types.insert("$concat"); - cell_types.insert("$lut"); - cell_types.insert("$assert"); + std::vector unary_ops = { + "$not", "$pos", "$bu0", "$neg", + "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", + "$logic_not", "$slice" + }; + + std::vector binary_ops = { + "$and", "$or", "$xor", "$xnor", + "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", + "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", + "$add", "$sub", "$mul", "$div", "$mod", "$pow", + "$logic_and", "$logic_or", "$concat" + }; + + for (auto type : unary_ops) + setup_type(type, {"\\A"}, {"\\Y"}, false); + + for (auto type : binary_ops) + setup_type(type, {"\\A", "\\B"}, {"\\Y"}, false); + + for (auto type : std::vector({"$mux", "$pmux"})) + setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, false); + + setup_type("$lut", {"\\I"}, {"\\O"}, false); + setup_type("$assert", {"\\A", "\\EN"}, {}, false); } void setup_internals_mem() { - cell_types.insert("$sr"); - cell_types.insert("$dff"); - cell_types.insert("$dffsr"); - cell_types.insert("$adff"); - cell_types.insert("$dlatch"); - cell_types.insert("$dlatchsr"); - cell_types.insert("$memrd"); - cell_types.insert("$memwr"); - cell_types.insert("$mem"); - cell_types.insert("$fsm"); + setup_type("$sr", {"\\SET", "\\CLR"}, {"\\Q"}, true); + setup_type("$dff", {"\\CLK", "\\D"}, {"\\Q"}, true); + setup_type("$dffsr", {"\\CLK", "\\SET", "\\CLR", "\\D"}, {"\\Q"}, true); + setup_type("$adff", {"\\CLK", "\\ARST", "\\D"}, {"\\Q"}, true); + setup_type("$dlatch", {"\\EN", "\\D"}, {"\\Q"}, true); + setup_type("$dlatchsr", {"\\EN", "\\SET", "\\CLR", "\\D"}, {"\\Q"}, true); + + setup_type("$memrd", {"\\CLK", "\\ADDR"}, {"\\DATA"}, true); + setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, {}, true); + setup_type("$mem", {"\\RD_CLK", "\\RD_ADDR", "\\WR_CLK", "\\WR_EN", "\\WR_ADDR", "\\WR_DATA"}, {"\\RD_DATA"}, true); + + setup_type("$fsm", {"\\CLK", "\\ARST", "\\CTRL_IN"}, {"\\CTRL_OUT"}, true); } void setup_stdcells() { - cell_types.insert("$_INV_"); - cell_types.insert("$_AND_"); - cell_types.insert("$_OR_"); - cell_types.insert("$_XOR_"); - cell_types.insert("$_MUX_"); + setup_type("$_INV_", {"\\A"}, {"\\Y"}, false); + setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, false); + setup_type("$_OR_", {"\\A", "\\B"}, {"\\Y"}, false); + setup_type("$_XOR_", {"\\A", "\\B"}, {"\\Y"}, false); + setup_type("$_MUX_", {"\\A", "\\B", "\\S"}, {"\\Y"}, false); } void setup_stdcells_mem() { - cell_types.insert("$_SR_NN_"); - cell_types.insert("$_SR_NP_"); - cell_types.insert("$_SR_PN_"); - cell_types.insert("$_SR_PP_"); - cell_types.insert("$_DFF_N_"); - cell_types.insert("$_DFF_P_"); - cell_types.insert("$_DFF_NN0_"); - cell_types.insert("$_DFF_NN1_"); - cell_types.insert("$_DFF_NP0_"); - cell_types.insert("$_DFF_NP1_"); - cell_types.insert("$_DFF_PN0_"); - cell_types.insert("$_DFF_PN1_"); - cell_types.insert("$_DFF_PP0_"); - cell_types.insert("$_DFF_PP1_"); - cell_types.insert("$_DFFSR_NNN_"); - cell_types.insert("$_DFFSR_NNP_"); - cell_types.insert("$_DFFSR_NPN_"); - cell_types.insert("$_DFFSR_NPP_"); - cell_types.insert("$_DFFSR_PNN_"); - cell_types.insert("$_DFFSR_PNP_"); - cell_types.insert("$_DFFSR_PPN_"); - cell_types.insert("$_DFFSR_PPP_"); - cell_types.insert("$_DLATCH_N_"); - cell_types.insert("$_DLATCH_P_"); - cell_types.insert("$_DLATCHSR_NNN_"); - cell_types.insert("$_DLATCHSR_NNP_"); - cell_types.insert("$_DLATCHSR_NPN_"); - cell_types.insert("$_DLATCHSR_NPP_"); - cell_types.insert("$_DLATCHSR_PNN_"); - cell_types.insert("$_DLATCHSR_PNP_"); - cell_types.insert("$_DLATCHSR_PPN_"); - cell_types.insert("$_DLATCHSR_PPP_"); + std::vector list_np = {'N', 'P'}, list_01 = {'0', '1'}; + + for (auto c1 : list_np) + for (auto c2 : list_np) + setup_type(stringf("$_SR_%c%c_", c1, c2), {"\\S", "\\R"}, {"\\Q"}, true); + + for (auto c1 : list_np) + setup_type(stringf("$_DFF_%c_", c1), {"\\C", "\\D"}, {"\\Q"}, true); + + for (auto c1 : list_np) + for (auto c2 : list_np) + for (auto c3 : list_01) + setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {"\\C", "\\R", "\\D"}, {"\\Q"}, true); + + for (auto c1 : list_np) + for (auto c2 : list_np) + for (auto c3 : list_np) + setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {"\\C", "\\S", "\\R", "\\D"}, {"\\Q"}, true); + + for (auto c1 : list_np) + setup_type(stringf("$_DLATCH_%c_", c1), {"\\E", "\\D"}, {"\\Q"}, true); + + for (auto c1 : list_np) + for (auto c2 : list_np) + for (auto c3 : list_np) + setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {"\\E", "\\S", "\\R", "\\D"}, {"\\Q"}, true); } void clear() { cell_types.clear(); - designs.clear(); } bool cell_known(RTLIL::IdString type) { - if (cell_types.count(type) > 0) - return true; - for (auto design : designs) - if (design->modules_.count(type) > 0) - return true; - return false; + return cell_types.count(type) != 0; } bool cell_output(RTLIL::IdString type, RTLIL::IdString port) { - if (cell_types.count(type) == 0) { - for (auto design : designs) - if (design->modules_.count(type) > 0) { - if (design->modules_.at(type)->wires_.count(port)) - return design->modules_.at(type)->wires_.at(port)->port_output; - return false; - } - return false; - } - - if (port == "\\Y" || port == "\\Q" || port == "\\RD_DATA") - return true; - if (type == "$memrd" && port == "\\DATA") - return true; - if (type == "$fsm" && port == "\\CTRL_OUT") - return true; - if (type == "$lut" && port == "\\O") - return true; - return false; + auto it = cell_types.find(type); + return it != cell_types.end() && it->second.outputs.count(port) != 0; } bool cell_input(RTLIL::IdString type, RTLIL::IdString port) { - if (cell_types.count(type) == 0) { - for (auto design : designs) - if (design->modules_.count(type) > 0) { - if (design->modules_.at(type)->wires_.count(port)) - return design->modules_.at(type)->wires_.at(port)->port_input; - return false; - } - return false; - } - - if (cell_types.count(type) > 0) - return !cell_output(type, port); - - return false; + auto it = cell_types.find(type); + return it != cell_types.end() && it->second.inputs.count(port) != 0; } static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 201c717e4..fdb33ed82 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -503,7 +503,7 @@ namespace { cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") return; - if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") { + if (cell->type.in("$not", "$pos", "$bu0", "$neg")) { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); port("\\Y", param("\\Y_WIDTH")); @@ -511,7 +511,7 @@ namespace { return; } - if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") { + if (cell->type.in("$and", "$or", "$xor", "$xnor")) { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); port("\\A", param("\\A_WIDTH")); @@ -521,8 +521,7 @@ namespace { return; } - if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" || - cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") { + if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); port("\\Y", param("\\Y_WIDTH")); @@ -530,8 +529,7 @@ namespace { return; } - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || - cell->type == "$shift" || cell->type == "$shiftx") { + if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); port("\\A", param("\\A_WIDTH")); @@ -541,8 +539,7 @@ namespace { return; } - if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || - cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") { + if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); port("\\A", param("\\A_WIDTH")); @@ -552,8 +549,7 @@ namespace { return; } - if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || - cell->type == "$mod" || cell->type == "$pow") { + if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); port("\\A", param("\\A_WIDTH")); -- cgit v1.2.3 From 1bf7a18fec76cf46a5b8710a75371e23b68d147d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 16:13:42 +0200 Subject: Added module->ports --- kernel/celltypes.h | 3 ++- kernel/rtlil.cc | 10 +++++++++- kernel/rtlil.h | 2 ++ 3 files changed, 13 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 6beaa3fed..5486f6acb 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -67,7 +67,8 @@ struct CellTypes void setup_module(RTLIL::Module *module) { std::set inputs, outputs; - for (auto wire : module->wires()) { + for (RTLIL::IdString wire_name : module->ports) { + RTLIL::Wire *wire = module->wire(wire_name); if (wire->port_input) inputs.insert(wire->name); if (wire->port_output) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index fdb33ed82..96ae0f97a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -821,6 +821,8 @@ void RTLIL::Module::check() for (auto &it2 : it.second->attributes) log_assert(!it2.first.empty()); if (it.second->port_id) { + log_assert(SIZE(ports) >= it.second->port_id); + log_assert(ports.at(it.second->port_id-1) == it.first); log_assert(it.second->port_input || it.second->port_output); if (SIZE(ports_declared) < it.second->port_id) ports_declared.resize(it.second->port_id); @@ -831,6 +833,7 @@ void RTLIL::Module::check() } for (auto port_declared : ports_declared) log_assert(port_declared == true); + log_assert(SIZE(ports) == SIZE(ports_declared)); for (auto &it : memories) { log_assert(it.first == it.second->name); @@ -915,6 +918,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const RewriteSigSpecWorker rewriteSigSpecWorker; rewriteSigSpecWorker.mod = new_mod; new_mod->rewrite_sigspecs(rewriteSigSpecWorker); + new_mod->fixup_ports(); } RTLIL::Module *RTLIL::Module::clone() const @@ -1154,8 +1158,12 @@ void RTLIL::Module::fixup_ports() w.second->port_id = 0; std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare); - for (size_t i = 0; i < all_ports.size(); i++) + + ports.clear(); + for (size_t i = 0; i < all_ports.size(); i++) { + ports.push_back(all_ports[i]->name); all_ports[i]->port_id = i+1; + } } RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 10da74636..0093b8a1b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -575,6 +575,8 @@ public: void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); void new_connections(const std::vector &new_conn); const std::vector &connections() const; + + std::vector ports; void fixup_ports(); template void rewrite_sigspecs(T functor); -- cgit v1.2.3 From 2f44d8ccf853870a661b5e528c7e3ad3e17ca21e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 22:32:18 +0200 Subject: Added sig.{replace,remove,extract} variants for std::{map,set} pattern --- kernel/rtlil.cc | 77 +++++++++++++++++++++++++++++++++++++++------------------ kernel/rtlil.h | 12 ++++++++- 2 files changed, 64 insertions(+), 25 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 96ae0f97a..297537f00 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2071,26 +2071,40 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const { - cover("kernel.rtlil.sigspec.replace"); + log_assert(pattern.width_ == with.width_); - unpack(); pattern.unpack(); with.unpack(); - log_assert(other != NULL); - log_assert(width_ == other->width_); - other->unpack(); - - log_assert(pattern.width_ == with.width_); + std::map rules; - std::map pattern_map; for (int i = 0; i < SIZE(pattern.bits_); i++) if (pattern.bits_[i].wire != NULL) - pattern_map[pattern.bits_[i]] = with.bits_[i]; + rules[pattern.bits_[i]] = with.bits_[i]; + + replace(rules, other); +} - for (int i = 0; i < SIZE(bits_); i++) - if (pattern_map.count(bits_[i])) - other->bits_[i] = pattern_map.at(bits_[i]); +void RTLIL::SigSpec::replace(const std::map &rules) +{ + replace(rules, this); +} + +void RTLIL::SigSpec::replace(const std::map &rules, RTLIL::SigSpec *other) const +{ + cover("kernel.rtlil.sigspec.replace"); + + log_assert(other != NULL); + log_assert(width_ == other->width_); + + unpack(); + other->unpack(); + + for (int i = 0; i < SIZE(bits_); i++) { + auto it = rules.find(bits_[i]); + if (it != rules.end()) + other->bits_[i] = it->second; + } other->check(); } @@ -2107,6 +2121,23 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other } void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) +{ + std::set pattern_bits = pattern.to_sigbit_set(); + remove2(pattern_bits, other); +} + +void RTLIL::SigSpec::remove(const std::set &pattern) +{ + remove2(pattern, NULL); +} + +void RTLIL::SigSpec::remove(const std::set &pattern, RTLIL::SigSpec *other) const +{ + RTLIL::SigSpec tmp = *this; + tmp.remove2(pattern, other); +} + +void RTLIL::SigSpec::remove2(const std::set &pattern, RTLIL::SigSpec *other) { if (other) cover("kernel.rtlil.sigspec.remove_other"); @@ -2120,11 +2151,10 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe other->unpack(); } - std::set pattern_bits = pattern.to_sigbit_set(); std::vector new_bits, new_other_bits; for (int i = 0; i < SIZE(bits_); i++) { - if (bits_[i].wire != NULL && pattern_bits.count(bits_[i])) + if (bits_[i].wire != NULL && pattern.count(bits_[i])) continue; if (other != NULL) new_other_bits.push_back(other->bits_[i]); @@ -2142,33 +2172,32 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe check(); } -RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const +RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const +{ + std::set pattern_bits = pattern.to_sigbit_set(); + return extract(pattern_bits, other); +} + +RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set &pattern, const RTLIL::SigSpec *other) const { if (other) cover("kernel.rtlil.sigspec.extract_other"); else cover("kernel.rtlil.sigspec.extract"); - pack(); - pattern.pack(); - - if (other != NULL) - other->pack(); - log_assert(other == NULL || width_ == other->width_); - std::set pat = pattern.to_sigbit_set(); std::vector bits_match = to_sigbit_vector(); RTLIL::SigSpec ret; if (other) { std::vector bits_other = other->to_sigbit_vector(); for (int i = 0; i < width_; i++) - if (bits_match[i].wire && pat.count(bits_match[i])) + if (bits_match[i].wire && pattern.count(bits_match[i])) ret.append_bit(bits_other[i]); } else { for (int i = 0; i < width_; i++) - if (bits_match[i].wire && pat.count(bits_match[i])) + if (bits_match[i].wire && pattern.count(bits_match[i])) ret.append_bit(bits_match[i]); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0093b8a1b..8f780c822 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -968,15 +968,25 @@ public: void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; + + void replace(const std::map &rules); + void replace(const std::map &rules, RTLIL::SigSpec *other) const; + void replace(int offset, const RTLIL::SigSpec &with); void remove(const RTLIL::SigSpec &pattern); void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); + + void remove(const std::set &pattern); + void remove(const std::set &pattern, RTLIL::SigSpec *other) const; + void remove2(const std::set &pattern, RTLIL::SigSpec *other); + void remove(int offset, int length = 1); void remove_const(); - RTLIL::SigSpec extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other = NULL) const; + RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; + RTLIL::SigSpec extract(const std::set &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(int offset, int length = 1) const; void append(const RTLIL::SigSpec &signal); -- cgit v1.2.3 From 978a933b6af8863200096bd3a56780e3378e4848 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 23:14:47 +0200 Subject: Added RTLIL::SigSpec::to_sigbit_map() --- kernel/rtlil.cc | 16 ++++++++++++++++ kernel/rtlil.h | 1 + 2 files changed, 17 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 297537f00..f4f32f600 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2687,6 +2687,22 @@ std::vector RTLIL::SigSpec::to_sigbit_vector() const return bits_; } +std::map RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const +{ + cover("kernel.rtlil.sigspec.to_sigbit_map"); + + unpack(); + other.unpack(); + + log_assert(width_ == other.width_); + + std::map new_map; + for (int i = 0; i < width_; i++) + new_map[bits_[i]] = other.bits_[i]; + + return new_map; +} + RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const { cover("kernel.rtlil.sigspec.to_single_sigbit"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8f780c822..3a0f0ff8c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1020,6 +1020,7 @@ public: std::set to_sigbit_set() const; std::vector to_sigbit_vector() const; + std::map to_sigbit_map(const RTLIL::SigSpec &other) const; RTLIL::SigBit to_single_sigbit() const; static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); -- cgit v1.2.3 From 8ff71b5ae506306d7981eb118874cd4f407b2bf8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 02:08:02 +0200 Subject: Added Frontend "+/" filename syntax for files from proc_share_dir --- kernel/register.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 868dbb949..a9e21e6dd 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -339,8 +339,11 @@ void Frontend::extra_args(FILE *&f, std::string &filename, std::vector Date: Fri, 15 Aug 2014 02:40:46 +0200 Subject: More idstring sort_by_* helpers and fixed tpl ordering in techmap --- kernel/rtlil.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 3a0f0ff8c..2c4b26f53 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -255,12 +255,24 @@ namespace RTLIL return log_id(str); } - template struct sort_by_name { + template struct sort_by_name_id { bool operator()(T *a, T *b) const { return a->name < b->name; } }; + template struct sort_by_name_str { + bool operator()(T *a, T *b) const { + return strcmp(a->name.c_str(), b->name.c_str()) < 0; + } + }; + + struct sort_by_id_str { + bool operator()(RTLIL::IdString a, RTLIL::IdString b) const { + return strcmp(a.c_str(), b.c_str()) < 0; + } + }; + // see calc.cc for the implementation of this functions RTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); -- cgit v1.2.3 From f092b5014895dc5dc62b8103fcedf94cfa9f85a8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 14:11:40 +0200 Subject: Renamed $_INV_ cell type to $_NOT_ --- kernel/celltypes.h | 4 ++-- kernel/rtlil.cc | 4 ++-- kernel/rtlil.h | 4 ++-- kernel/satgen.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 5486f6acb..e30ceb8b1 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -130,7 +130,7 @@ struct CellTypes void setup_stdcells() { - setup_type("$_INV_", {"\\A"}, {"\\Y"}, false); + setup_type("$_NOT_", {"\\A"}, {"\\Y"}, false); setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, false); setup_type("$_OR_", {"\\A", "\\B"}, {"\\Y"}, false); setup_type("$_XOR_", {"\\A", "\\B"}, {"\\Y"}, false); @@ -241,7 +241,7 @@ struct CellTypes HANDLE_CELL_TYPE(neg) #undef HANDLE_CELL_TYPE - if (type == "$_INV_") + if (type == "$_NOT_") return const_not(arg1, arg2, false, false, 1); if (type == "$_AND_") return const_and(arg1, arg2, false, false, 1); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f4f32f600..614ea770b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -758,7 +758,7 @@ namespace { return; } - if (cell->type == "$_INV_") { check_gate("AY"); return; } + if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } if (cell->type == "$_OR_") { check_gate("ABY"); return; } if (cell->type == "$_XOR_") { check_gate("ABY"); return; } @@ -1338,7 +1338,7 @@ DEF_METHOD(Pmux, "$pmux", 1) add ## _func(name, sig1, sig2, sig3, sig4); \ return sig4; \ } -DEF_METHOD_2(InvGate, "$_INV_", A, Y) +DEF_METHOD_2(NotGate, "$_NOT_", A, Y) DEF_METHOD_3(AndGate, "$_AND_", A, B, Y) DEF_METHOD_3(OrGate, "$_OR_", A, B, Y) DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 2c4b26f53..43e36cbde 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -694,7 +694,7 @@ public: RTLIL::Cell* addDlatchsr (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true); - RTLIL::Cell* addInvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y); + RTLIL::Cell* addNotGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y); RTLIL::Cell* addAndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); RTLIL::Cell* addOrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); RTLIL::Cell* addXorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); @@ -757,7 +757,7 @@ public: RTLIL::SigSpec Mux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); RTLIL::SigSpec Pmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); - RTLIL::SigSpec InvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a); + RTLIL::SigSpec NotGate (RTLIL::IdString name, RTLIL::SigSpec sig_a); RTLIL::SigSpec AndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); RTLIL::SigSpec OrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); RTLIL::SigSpec XorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); diff --git a/kernel/satgen.h b/kernel/satgen.h index 8284cdeb2..b57edd9fe 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -271,7 +271,7 @@ struct SatGen return true; } - if (cell->type == "$_INV_" || cell->type == "$not") + if (cell->type == "$_NOT_" || cell->type == "$not") { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); -- cgit v1.2.3 From b64b38eea2e9a7de30d6045f069c86bf4446134f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 14:18:40 +0200 Subject: Renamed $lut ports to follow A-Y naming scheme --- kernel/celltypes.h | 3 +-- kernel/rtlil.cc | 8 ++++---- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index e30ceb8b1..402d6ea76 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -88,7 +88,7 @@ struct CellTypes std::vector unary_ops = { "$not", "$pos", "$bu0", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", - "$logic_not", "$slice" + "$logic_not", "$slice", "$lut" }; std::vector binary_ops = { @@ -108,7 +108,6 @@ struct CellTypes for (auto type : std::vector({"$mux", "$pmux"})) setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, false); - setup_type("$lut", {"\\I"}, {"\\O"}, false); setup_type("$assert", {"\\A", "\\EN"}, {}, false); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 614ea770b..d118b6257 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -615,8 +615,8 @@ namespace { if (cell->type == "$lut") { param("\\LUT"); - port("\\I", param("\\WIDTH")); - port("\\O", 1); + port("\\A", param("\\WIDTH")); + port("\\Y", 1); check_expected(); return; } @@ -1388,8 +1388,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R RTLIL::Cell *cell = addCell(name, "$lut"); cell->parameters["\\LUT"] = lut; cell->parameters["\\WIDTH"] = sig_i.size(); - cell->setPort("\\I", sig_i); - cell->setPort("\\O", sig_o); + cell->setPort("\\A", sig_i); + cell->setPort("\\Y", sig_o); return cell; } -- cgit v1.2.3 From dbdf89c7054a3f249d7579cb50d10b72b1ac592d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 15:34:00 +0200 Subject: Added log_spacer() --- kernel/driver.cc | 3 ++- kernel/log.cc | 18 +++++++++++++++++- kernel/log.h | 1 + 3 files changed, 20 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 6f9764238..d59e68a50 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -274,7 +274,8 @@ int main(int argc, char **argv) struct rusage ru_buffer; getrusage(RUSAGE_SELF, &ru_buffer); - log("\nEnd of script. Logfile hash: %s, CPU: user %.2fs system %.2fs\n", hash.c_str(), + log_spacer(); + log("End of script. Logfile hash: %s, CPU: user %.2fs system %.2fs\n", hash.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec, ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec); log("%s\n", yosys_version_str); diff --git a/kernel/log.cc b/kernel/log.cc index 1f0826039..b742a5495 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -45,6 +45,7 @@ int string_buf_size = 0; static struct timeval initial_tv = { 0, 0 }; static bool next_print_log = false; +static int log_newline_count = 0; void logv(const char *format, va_list ap) { @@ -55,6 +56,15 @@ void logv(const char *format, va_list ap) std::string str = vstringf(format, ap); + if (str.empty()) + return; + + size_t nnl_pos = str.find_last_not_of('\n'); + if (nnl_pos == std::string::npos) + log_newline_count += SIZE(str); + else + log_newline_count = SIZE(str) - nnl_pos - 1; + if (log_hasher) log_hasher->update(str); @@ -92,7 +102,7 @@ void logv_header(const char *format, va_list ap) { bool pop_errfile = false; - log("\n"); + log_spacer(); if (header_count.size() > 0) header_count.back()++; @@ -160,6 +170,12 @@ void log_cmd_error(const char *format, ...) logv_error(format, ap); } +void log_spacer() +{ + while (log_newline_count < 2) + log("\n"); +} + void log_push() { header_count.push_back(0); diff --git a/kernel/log.h b/kernel/log.h index 037a62a3b..b1c44b46b 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -51,6 +51,7 @@ void log_header(const char *format, ...) __attribute__ ((format (printf, 1, 2))) void log_error(const char *format, ...) __attribute__ ((format (printf, 1, 2))) __attribute__ ((noreturn)); void log_cmd_error(const char *format, ...) __attribute__ ((format (printf, 1, 2))) __attribute__ ((noreturn)); +void log_spacer(); void log_push(); void log_pop(); -- cgit v1.2.3 From 56a30cf42c6a40f265a67df6e2c5fa74657fbf5b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 16:12:14 +0200 Subject: Added CellTypes::cell_evaluable() --- kernel/celltypes.h | 68 +++++++++++++++++++++++++++++------------------------- 1 file changed, 37 insertions(+), 31 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 402d6ea76..ad5eae2e8 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -31,7 +31,7 @@ struct CellType { RTLIL::IdString type; std::set inputs, outputs; - bool maybe_has_internal_state; + bool is_evaluable; }; struct CellTypes @@ -58,9 +58,9 @@ struct CellTypes setup_stdcells_mem(); } - void setup_type(RTLIL::IdString type, const std::set &inputs, const std::set &outputs, bool maybe_has_internal_state) + void setup_type(RTLIL::IdString type, const std::set &inputs, const std::set &outputs, bool is_evaluable = false) { - CellType ct = {type, inputs, outputs, maybe_has_internal_state}; + CellType ct = {type, inputs, outputs, is_evaluable}; cell_types[ct.type] = ct; } @@ -74,7 +74,7 @@ struct CellTypes if (wire->port_output) outputs.insert(wire->name); } - setup_type(module->name, inputs, outputs, true); + setup_type(module->name, inputs, outputs); } void setup_design(RTLIL::Design *design) @@ -100,40 +100,40 @@ struct CellTypes }; for (auto type : unary_ops) - setup_type(type, {"\\A"}, {"\\Y"}, false); + setup_type(type, {"\\A"}, {"\\Y"}, true); for (auto type : binary_ops) - setup_type(type, {"\\A", "\\B"}, {"\\Y"}, false); + setup_type(type, {"\\A", "\\B"}, {"\\Y"}, true); for (auto type : std::vector({"$mux", "$pmux"})) - setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, false); + setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, true); - setup_type("$assert", {"\\A", "\\EN"}, {}, false); + setup_type("$assert", {"\\A", "\\EN"}, {}, true); } void setup_internals_mem() { - setup_type("$sr", {"\\SET", "\\CLR"}, {"\\Q"}, true); - setup_type("$dff", {"\\CLK", "\\D"}, {"\\Q"}, true); - setup_type("$dffsr", {"\\CLK", "\\SET", "\\CLR", "\\D"}, {"\\Q"}, true); - setup_type("$adff", {"\\CLK", "\\ARST", "\\D"}, {"\\Q"}, true); - setup_type("$dlatch", {"\\EN", "\\D"}, {"\\Q"}, true); - setup_type("$dlatchsr", {"\\EN", "\\SET", "\\CLR", "\\D"}, {"\\Q"}, true); - - setup_type("$memrd", {"\\CLK", "\\ADDR"}, {"\\DATA"}, true); - setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, {}, true); - setup_type("$mem", {"\\RD_CLK", "\\RD_ADDR", "\\WR_CLK", "\\WR_EN", "\\WR_ADDR", "\\WR_DATA"}, {"\\RD_DATA"}, true); - - setup_type("$fsm", {"\\CLK", "\\ARST", "\\CTRL_IN"}, {"\\CTRL_OUT"}, true); + setup_type("$sr", {"\\SET", "\\CLR"}, {"\\Q"}); + setup_type("$dff", {"\\CLK", "\\D"}, {"\\Q"}); + setup_type("$dffsr", {"\\CLK", "\\SET", "\\CLR", "\\D"}, {"\\Q"}); + setup_type("$adff", {"\\CLK", "\\ARST", "\\D"}, {"\\Q"}); + setup_type("$dlatch", {"\\EN", "\\D"}, {"\\Q"}); + setup_type("$dlatchsr", {"\\EN", "\\SET", "\\CLR", "\\D"}, {"\\Q"}); + + setup_type("$memrd", {"\\CLK", "\\ADDR"}, {"\\DATA"}); + setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, {}); + setup_type("$mem", {"\\RD_CLK", "\\RD_ADDR", "\\WR_CLK", "\\WR_EN", "\\WR_ADDR", "\\WR_DATA"}, {"\\RD_DATA"}); + + setup_type("$fsm", {"\\CLK", "\\ARST", "\\CTRL_IN"}, {"\\CTRL_OUT"}); } void setup_stdcells() { - setup_type("$_NOT_", {"\\A"}, {"\\Y"}, false); - setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, false); - setup_type("$_OR_", {"\\A", "\\B"}, {"\\Y"}, false); - setup_type("$_XOR_", {"\\A", "\\B"}, {"\\Y"}, false); - setup_type("$_MUX_", {"\\A", "\\B", "\\S"}, {"\\Y"}, false); + setup_type("$_NOT_", {"\\A"}, {"\\Y"}, true); + setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, true); + setup_type("$_OR_", {"\\A", "\\B"}, {"\\Y"}, true); + setup_type("$_XOR_", {"\\A", "\\B"}, {"\\Y"}, true); + setup_type("$_MUX_", {"\\A", "\\B", "\\S"}, {"\\Y"}, true); } void setup_stdcells_mem() @@ -142,28 +142,28 @@ struct CellTypes for (auto c1 : list_np) for (auto c2 : list_np) - setup_type(stringf("$_SR_%c%c_", c1, c2), {"\\S", "\\R"}, {"\\Q"}, true); + setup_type(stringf("$_SR_%c%c_", c1, c2), {"\\S", "\\R"}, {"\\Q"}); for (auto c1 : list_np) - setup_type(stringf("$_DFF_%c_", c1), {"\\C", "\\D"}, {"\\Q"}, true); + setup_type(stringf("$_DFF_%c_", c1), {"\\C", "\\D"}, {"\\Q"}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) - setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {"\\C", "\\R", "\\D"}, {"\\Q"}, true); + setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {"\\C", "\\R", "\\D"}, {"\\Q"}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {"\\C", "\\S", "\\R", "\\D"}, {"\\Q"}, true); + setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {"\\C", "\\S", "\\R", "\\D"}, {"\\Q"}); for (auto c1 : list_np) - setup_type(stringf("$_DLATCH_%c_", c1), {"\\E", "\\D"}, {"\\Q"}, true); + setup_type(stringf("$_DLATCH_%c_", c1), {"\\E", "\\D"}, {"\\Q"}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {"\\E", "\\S", "\\R", "\\D"}, {"\\Q"}, true); + setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {"\\E", "\\S", "\\R", "\\D"}, {"\\Q"}); } void clear() @@ -188,6 +188,12 @@ struct CellTypes return it != cell_types.end() && it->second.inputs.count(port) != 0; } + bool cell_evaluable(RTLIL::IdString type) + { + auto it = cell_types.find(type); + return it != cell_types.end() && it->second.is_evaluable; + } + static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { if (type == "$sshr" && !signed1) -- cgit v1.2.3 From 47c2637a961839f1eb1a0386f7e54d94be50bc10 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 18:18:30 +0200 Subject: Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ --- kernel/celltypes.h | 49 ++++++++++++++++++++++++++---- kernel/consteval.h | 17 ++++++++++- kernel/rtlil.cc | 17 +++++++---- kernel/satgen.h | 88 +++++++++++++++++++++++++++++++++++++++++++++++++----- 4 files changed, 152 insertions(+), 19 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index ad5eae2e8..8c2e9a48e 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -131,9 +131,16 @@ struct CellTypes { setup_type("$_NOT_", {"\\A"}, {"\\Y"}, true); setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, true); + setup_type("$_NAND_", {"\\A", "\\B"}, {"\\Y"}, true); setup_type("$_OR_", {"\\A", "\\B"}, {"\\Y"}, true); + setup_type("$_NOR_", {"\\A", "\\B"}, {"\\Y"}, true); setup_type("$_XOR_", {"\\A", "\\B"}, {"\\Y"}, true); + setup_type("$_XNOR_", {"\\A", "\\B"}, {"\\Y"}, true); setup_type("$_MUX_", {"\\A", "\\B", "\\S"}, {"\\Y"}, true); + setup_type("$_AOI3_", {"\\A", "\\B", "\\C"}, {"\\Y"}, true); + setup_type("$_OAI3_", {"\\A", "\\B", "\\C"}, {"\\Y"}, true); + setup_type("$_AOI4_", {"\\A", "\\B", "\\C", "\\D"}, {"\\Y"}, true); + setup_type("$_OAI4_", {"\\A", "\\B", "\\C", "\\D"}, {"\\Y"}, true); } void setup_stdcells_mem() @@ -194,6 +201,14 @@ struct CellTypes return it != cell_types.end() && it->second.is_evaluable; } + static RTLIL::Const eval_not(RTLIL::Const v) + { + for (auto &bit : v.bits) + if (bit == RTLIL::S0) bit = RTLIL::S1; + else if (bit == RTLIL::S1) bit = RTLIL::S0; + return v; + } + static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { if (type == "$sshr" && !signed1) @@ -247,13 +262,19 @@ struct CellTypes #undef HANDLE_CELL_TYPE if (type == "$_NOT_") - return const_not(arg1, arg2, false, false, 1); + return eval_not(arg1); if (type == "$_AND_") return const_and(arg1, arg2, false, false, 1); + if (type == "$_NAND_") + return eval_not(const_and(arg1, arg2, false, false, 1)); if (type == "$_OR_") return const_or(arg1, arg2, false, false, 1); + if (type == "$_NOR_") + return eval_not(const_and(arg1, arg2, false, false, 1)); if (type == "$_XOR_") return const_xor(arg1, arg2, false, false, 1); + if (type == "$_XNOR_") + return const_xnor(arg1, arg2, false, false, 1); log_abort(); } @@ -280,21 +301,37 @@ struct CellTypes return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len); } - static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &sel) + static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3) { - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") { + if (cell->type.in("$mux", "$pmux", "$_MUX_")) { RTLIL::Const ret = arg1; - for (size_t i = 0; i < sel.bits.size(); i++) - if (sel.bits[i] == RTLIL::State::S1) { + for (size_t i = 0; i < arg3.bits.size(); i++) + if (arg3.bits[i] == RTLIL::State::S1) { std::vector bits(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size()); ret = RTLIL::Const(bits); } return ret; } - log_assert(sel.bits.size() == 0); + if (cell->type == "$_AOI3_") + return eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1)); + if (cell->type == "$_OAI3_") + return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1)); + + log_assert(arg3.bits.size() == 0); return eval(cell, arg1, arg2); } + + static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4) + { + if (cell->type == "$_AOI4_") + return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); + if (cell->type == "$_OAI4_") + return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); + + log_assert(arg4.bits.size() == 0); + return eval(cell, arg1, arg2, arg3); + } }; #endif diff --git a/kernel/consteval.h b/kernel/consteval.h index dbe13ea7e..d42c2b0f1 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -156,11 +156,26 @@ struct ConstEval } else { + RTLIL::SigSpec sig_c, sig_d; + + if (cell->type.in("$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_")) { + if (cell->hasPort("\\C")) + sig_c = cell->getPort("\\C"); + if (cell->hasPort("\\D")) + sig_d = cell->getPort("\\D"); + } + if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) return false; if (sig_b.size() > 0 && !eval(sig_b, undef, cell)) return false; - set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const())); + if (sig_c.size() > 0 && !eval(sig_c, undef, cell)) + return false; + if (sig_d.size() > 0 && !eval(sig_d, undef, cell)) + return false; + + set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), + sig_c.as_const(), sig_d.as_const())); } return true; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d118b6257..3df7d83c4 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -758,11 +758,18 @@ namespace { return; } - if (cell->type == "$_NOT_") { check_gate("AY"); return; } - if (cell->type == "$_AND_") { check_gate("ABY"); return; } - if (cell->type == "$_OR_") { check_gate("ABY"); return; } - if (cell->type == "$_XOR_") { check_gate("ABY"); return; } - if (cell->type == "$_MUX_") { check_gate("ABSY"); return; } + if (cell->type == "$_NOT_") { check_gate("AY"); return; } + if (cell->type == "$_AND_") { check_gate("ABY"); return; } + if (cell->type == "$_NAND_") { check_gate("ABY"); return; } + if (cell->type == "$_OR_") { check_gate("ABY"); return; } + if (cell->type == "$_NOR_") { check_gate("ABY"); return; } + if (cell->type == "$_XOR_") { check_gate("ABY"); return; } + if (cell->type == "$_XNOR_") { check_gate("ABY"); return; } + if (cell->type == "$_MUX_") { check_gate("ABSY"); return; } + if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; } + if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; } + if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; } + if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; } if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; } if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; } diff --git a/kernel/satgen.h b/kernel/satgen.h index b57edd9fe..c02900a6c 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -175,6 +175,11 @@ struct SatGen } } + void undefGating(int y, int yy, int undef) + { + ez->assume(ez->OR(undef, ez->IFF(y, yy))); + } + bool importCell(RTLIL::Cell *cell, int timestep = -1) { bool arith_undef_handled = false; @@ -211,9 +216,8 @@ struct SatGen arith_undef_handled = true; } - if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_" || - cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || - cell->type == "$add" || cell->type == "$sub") + if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", + "$and", "$or", "$xor", "$xnor", "$add", "$sub")) { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); @@ -224,11 +228,15 @@ struct SatGen if (cell->type == "$and" || cell->type == "$_AND_") ez->assume(ez->vec_eq(ez->vec_and(a, b), yy)); + if (cell->type == "$_NAND_") + ez->assume(ez->vec_eq(ez->vec_not(ez->vec_and(a, b)), yy)); if (cell->type == "$or" || cell->type == "$_OR_") ez->assume(ez->vec_eq(ez->vec_or(a, b), yy)); + if (cell->type == "$_NOR_") + ez->assume(ez->vec_eq(ez->vec_not(ez->vec_or(a, b)), yy)); if (cell->type == "$xor" || cell->type == "$_XOR_") ez->assume(ez->vec_eq(ez->vec_xor(a, b), yy)); - if (cell->type == "$xnor") + if (cell->type == "$xnor" || cell->type == "$_XNOR_") ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), yy)); if (cell->type == "$add") ez->assume(ez->vec_eq(ez->vec_add(a, b), yy)); @@ -242,19 +250,19 @@ struct SatGen std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell, false); - if (cell->type == "$and" || cell->type == "$_AND_") { + if (cell->type.in("$and", "$_AND_", "$_NAND_")) { std::vector a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)); std::vector b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b)); std::vector yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0))); ez->assume(ez->vec_eq(yX, undef_y)); } - else if (cell->type == "$or" || cell->type == "$_OR_") { + else if (cell->type.in("$or", "$_OR_", "$_NOR_")) { std::vector a1 = ez->vec_and(a, ez->vec_not(undef_a)); std::vector b1 = ez->vec_and(b, ez->vec_not(undef_b)); std::vector yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a1, b1))); ez->assume(ez->vec_eq(yX, undef_y)); } - else if (cell->type == "$xor" || cell->type == "$_XOR_" || cell->type == "$xnor") { + else if (cell->type.in("$xor", "$xnor", "$_XOR_", "$_XNOR_")) { std::vector yX = ez->vec_or(undef_a, undef_b); ez->assume(ez->vec_eq(yX, undef_y)); } @@ -271,6 +279,72 @@ struct SatGen return true; } + if (cell->type.in("$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_")) + { + bool aoi_mode = cell->type.in("$_AOI3_", "$_AOI4_"); + bool three_mode = cell->type.in("$_AOI3_", "$_OAI3_"); + + int a = importDefSigSpec(cell->getPort("\\A"), timestep).at(0); + int b = importDefSigSpec(cell->getPort("\\B"), timestep).at(0); + int c = importDefSigSpec(cell->getPort("\\C"), timestep).at(0); + int d = three_mode ? (aoi_mode ? ez->TRUE : ez->FALSE) : importDefSigSpec(cell->getPort("\\D"), timestep).at(0); + int y = importDefSigSpec(cell->getPort("\\Y"), timestep).at(0); + int yy = model_undef ? ez->literal() : y; + + if (cell->type.in("$_AOI3_", "$_AOI4_")) + ez->assume(ez->IFF(ez->NOT(ez->OR(ez->AND(a, b), ez->AND(c, d))), yy)); + else + ez->assume(ez->IFF(ez->NOT(ez->AND(ez->OR(a, b), ez->OR(c, d))), yy)); + + if (model_undef) + { + int undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep).at(0); + int undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep).at(0); + int undef_c = importUndefSigSpec(cell->getPort("\\C"), timestep).at(0); + int undef_d = three_mode ? ez->FALSE : importUndefSigSpec(cell->getPort("\\D"), timestep).at(0); + int undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep).at(0); + + if (aoi_mode) + { + int a0 = ez->AND(ez->NOT(a), ez->NOT(undef_a)); + int b0 = ez->AND(ez->NOT(b), ez->NOT(undef_b)); + int c0 = ez->AND(ez->NOT(c), ez->NOT(undef_c)); + int d0 = ez->AND(ez->NOT(d), ez->NOT(undef_d)); + + int ab = ez->AND(a, b), cd = ez->AND(c, d); + int undef_ab = ez->AND(ez->OR(undef_a, undef_b), ez->NOT(ez->OR(a0, b0))); + int undef_cd = ez->AND(ez->OR(undef_c, undef_d), ez->NOT(ez->OR(c0, d0))); + + int ab1 = ez->AND(ab, ez->NOT(undef_ab)); + int cd1 = ez->AND(cd, ez->NOT(undef_cd)); + int yX = ez->AND(ez->OR(undef_ab, undef_cd), ez->NOT(ez->OR(ab1, cd1))); + + ez->assume(ez->IFF(yX, undef_y)); + } + else + { + int a1 = ez->AND(a, ez->NOT(undef_a)); + int b1 = ez->AND(b, ez->NOT(undef_b)); + int c1 = ez->AND(c, ez->NOT(undef_c)); + int d1 = ez->AND(d, ez->NOT(undef_d)); + + int ab = ez->OR(a, b), cd = ez->OR(c, d); + int undef_ab = ez->AND(ez->OR(undef_a, undef_b), ez->NOT(ez->OR(a1, b1))); + int undef_cd = ez->AND(ez->OR(undef_c, undef_d), ez->NOT(ez->OR(c1, d1))); + + int ab0 = ez->AND(ez->NOT(ab), ez->NOT(undef_ab)); + int cd0 = ez->AND(ez->NOT(cd), ez->NOT(undef_cd)); + int yX = ez->AND(ez->OR(undef_ab, undef_cd), ez->NOT(ez->OR(ab0, cd0))); + + ez->assume(ez->IFF(yX, undef_y)); + } + + undefGating(y, yy, undef_y); + } + + return true; + } + if (cell->type == "$_NOT_" || cell->type == "$not") { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); -- cgit v1.2.3 From 7f734ecc098a2a113ced835cefc9d4e1982f08d0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 23:50:36 +0200 Subject: Added module->uniquify() --- kernel/rtlil.cc | 22 ++++++++++++++++++++++ kernel/rtlil.h | 3 +++ 2 files changed, 25 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3df7d83c4..60c514d19 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1108,6 +1108,28 @@ void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2) cells_[c2->name] = c2; } +RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name) +{ + int index = 0; + return uniquify(name, index); +} + +RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index) +{ + if (index == 0) { + if (count_id(name) == 0) + return name; + index++; + } + + while (1) { + RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index); + if (count_id(new_name) == 0) + return new_name; + index++; + } +} + static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b) { if (a->port_id && !b->port_id) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 43e36cbde..7e052b091 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -625,6 +625,9 @@ public: void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + RTLIL::IdString uniquify(RTLIL::IdString name); + RTLIL::IdString uniquify(RTLIL::IdString name, int &index); + RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); -- cgit v1.2.3 From 410d043dd86a2ca1f6c56a3e2a4d175dc0af8739 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 17 Aug 2014 00:55:35 +0200 Subject: Renamed toposort.h to utils.h --- kernel/toposort.h | 104 ------------------------------------------------------ kernel/utils.h | 104 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 104 deletions(-) delete mode 100644 kernel/toposort.h create mode 100644 kernel/utils.h (limited to 'kernel') diff --git a/kernel/toposort.h b/kernel/toposort.h deleted file mode 100644 index 4226e270e..000000000 --- a/kernel/toposort.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifndef TOPOSORT_H -#define TOPOSORT_H - -template -struct TopoSort -{ - bool analyze_loops, found_loops; - std::map> database; - std::set> loops; - std::vector sorted; - - TopoSort() - { - analyze_loops = true; - found_loops = false; - } - - void node(T n) - { - if (database.count(n) == 0) - database[n] = std::set(); - } - - void edge(T left, T right) - { - node(left); - database[right].insert(left); - } - - void sort_worker(const T &n, std::set &marked_cells, std::set &active_cells, std::vector &active_stack) - { - if (active_cells.count(n)) { - found_loops = false; - if (analyze_loops) { - std::set loop; - for (int i = SIZE(active_stack)-1; i >= 0; i--) { - loop.insert(active_stack[i]); - if (active_stack[i] == n) - break; - } - loops.insert(loop); - } - return; - } - - if (marked_cells.count(n)) - return; - - if (!database.at(n).empty()) - { - if (analyze_loops) - active_stack.push_back(n); - active_cells.insert(n); - - for (auto &left_n : database.at(n)) - sort_worker(left_n, marked_cells, active_cells, active_stack); - - if (analyze_loops) - active_stack.pop_back(); - active_cells.erase(n); - } - - marked_cells.insert(n); - sorted.push_back(n); - } - - bool sort() - { - loops.clear(); - sorted.clear(); - found_loops = false; - - std::set marked_cells; - std::set active_cells; - std::vector active_stack; - - for (auto &it : database) - sort_worker(it.first, marked_cells, active_cells, active_stack); - - log_assert(SIZE(sorted) == SIZE(database)); - return !found_loops; - } -}; - -#endif diff --git a/kernel/utils.h b/kernel/utils.h new file mode 100644 index 000000000..4226e270e --- /dev/null +++ b/kernel/utils.h @@ -0,0 +1,104 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef TOPOSORT_H +#define TOPOSORT_H + +template +struct TopoSort +{ + bool analyze_loops, found_loops; + std::map> database; + std::set> loops; + std::vector sorted; + + TopoSort() + { + analyze_loops = true; + found_loops = false; + } + + void node(T n) + { + if (database.count(n) == 0) + database[n] = std::set(); + } + + void edge(T left, T right) + { + node(left); + database[right].insert(left); + } + + void sort_worker(const T &n, std::set &marked_cells, std::set &active_cells, std::vector &active_stack) + { + if (active_cells.count(n)) { + found_loops = false; + if (analyze_loops) { + std::set loop; + for (int i = SIZE(active_stack)-1; i >= 0; i--) { + loop.insert(active_stack[i]); + if (active_stack[i] == n) + break; + } + loops.insert(loop); + } + return; + } + + if (marked_cells.count(n)) + return; + + if (!database.at(n).empty()) + { + if (analyze_loops) + active_stack.push_back(n); + active_cells.insert(n); + + for (auto &left_n : database.at(n)) + sort_worker(left_n, marked_cells, active_cells, active_stack); + + if (analyze_loops) + active_stack.pop_back(); + active_cells.erase(n); + } + + marked_cells.insert(n); + sorted.push_back(n); + } + + bool sort() + { + loops.clear(); + sorted.clear(); + found_loops = false; + + std::set marked_cells; + std::set active_cells; + std::vector active_stack; + + for (auto &it : database) + sort_worker(it.first, marked_cells, active_cells, active_stack); + + log_assert(SIZE(sorted) == SIZE(database)); + return !found_loops; + } +}; + +#endif -- cgit v1.2.3 From 9bacc0b54c0901dfd34c2230d3295720653c0a7a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 17 Aug 2014 00:56:47 +0200 Subject: Added stackmap<> container --- kernel/utils.h | 110 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- kernel/yosys.h | 1 + 2 files changed, 109 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/utils.h b/kernel/utils.h index 4226e270e..7f10619bc 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -17,8 +17,114 @@ * */ -#ifndef TOPOSORT_H -#define TOPOSORT_H +// This file contains various c++ utility routines and helper classes that +// do not depend on any other components of yosys (except stuff like log_*). + +#include "kernel/yosys.h" + +#ifndef UTILS_H +#define UTILS_H + +// ------------------------------------------------ +// A map-like container, but you can save and restore the state +// ------------------------------------------------ + +template> +struct stackmap +{ +private: + std::vector> backup_state; + std::map current_state; + static T empty_tuple; + +public: + stackmap() { } + stackmap(const std::map &other) : current_state(other) { } + + template + void operator=(const Other &other) + { + for (auto &it : current_state) + if (!backup_state.empty() && backup_state.back().count(it.first) == 0) + backup_state.back()[it.first] = new T(it.second); + current_state.clear(); + + for (auto &it : other) + set(it.first, it.second); + } + + bool has(const Key &k) + { + return current_state.count(k) != 0; + } + + void set(const Key &k, const T &v) + { + if (!backup_state.empty() && backup_state.back().count(k) == 0) + backup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr; + current_state[k] = v; + } + + void unset(const Key &k) + { + if (!backup_state.empty() && backup_state.back().count(k) == 0) + backup_state.back()[k] = current_state.count(k) ? new T(current_state.at(k)) : nullptr; + current_state.erase(k); + } + + const T &get(const Key &k) + { + if (current_state.count(k) == 0) + return empty_tuple; + return current_state.at(k); + } + + void reset(const Key &k) + { + for (int i = SIZE(backup_state)-1; i >= 0; i--) + if (backup_state[i].count(k) != 0) { + if (backup_state[i].at(k) == nullptr) + current_state.erase(k); + else + current_state[k] = *backup_state[i].at(k); + return; + } + current_state.erase(k); + } + + const std::map &stdmap() + { + return current_state; + } + + void save() + { + backup_state.resize(backup_state.size()+1); + } + + void restore() + { + log_assert(!backup_state.empty()); + for (auto &it : backup_state.back()) + if (it.second != nullptr) { + current_state[it.first] = *it.second; + delete it.second; + } else + current_state.erase(it.first); + backup_state.pop_back(); + } + + ~stackmap() + { + while (!backup_state.empty()) + restore(); + } +}; + + +// ------------------------------------------------ +// A simple class for topological sorting +// ------------------------------------------------ template struct TopoSort diff --git a/kernel/yosys.h b/kernel/yosys.h index e12069b4c..79c90628c 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -42,6 +42,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From f3326a642178b66ba98b6371245077ff93ffe215 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 17 Aug 2014 02:16:56 +0200 Subject: Improved sig.remove2() performance --- kernel/rtlil.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 60c514d19..e4bf4f9f3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2182,14 +2182,23 @@ void RTLIL::SigSpec::remove2(const std::set &pattern, RTLIL::SigS std::vector new_bits, new_other_bits; + new_bits.resize(SIZE(bits_)); + if (other != NULL) + new_other_bits.resize(SIZE(bits_)); + + int k = 0; for (int i = 0; i < SIZE(bits_); i++) { if (bits_[i].wire != NULL && pattern.count(bits_[i])) continue; if (other != NULL) - new_other_bits.push_back(other->bits_[i]); - new_bits.push_back(bits_[i]); + new_other_bits[k] = other->bits_[i]; + new_bits[k++] = bits_[i]; } + new_bits.resize(k); + if (other != NULL) + new_other_bits.resize(k); + bits_.swap(new_bits); width_ = SIZE(bits_); -- cgit v1.2.3 From aa7a3ed83f0972bd6da3b272e7bbc9efb1409067 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 17 Aug 2014 02:25:59 +0200 Subject: Fixed proc_{self,share}_dirname error handling --- kernel/yosys.cc | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index dff31db07..599c92d52 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -207,8 +207,7 @@ std::string proc_self_dirname () char path [PATH_MAX]; ssize_t buflen = readlink("/proc/self/exe", path, sizeof(path)); if (buflen < 0) { - log_cmd_error("readlink(\"/proc/self/exe\") failed: %s", strerror(errno)); - log_abort(); + log_error("readlink(\"/proc/self/exe\") failed: %s\n", strerror(errno)); } while (buflen > 0 && path[buflen-1] != '/') buflen--; @@ -239,8 +238,7 @@ std::string proc_share_dirname () proc_share_path = proc_self_path + "../share/yosys/"; if (access(proc_share_path.c_str(), X_OK) == 0) return proc_share_path; - log_cmd_error("proc_share_dirname: unable to determine share/ directory!"); - log_abort(); + log_error("proc_share_dirname: unable to determine share/ directory!\n"); } bool fgetline(FILE *f, std::string &buffer) -- cgit v1.2.3 From b37d70dfd7fbc7cacc2b5fc9f3915e27da5eec07 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 19 Aug 2014 13:44:56 +0200 Subject: Added mod->addGate() methods for new gate types --- kernel/rtlil.cc | 129 +++++++++++++++++++++++++++++++++----------------------- kernel/rtlil.h | 34 ++++++++++----- 2 files changed, 100 insertions(+), 63 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index e4bf4f9f3..24cce6b8b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1239,10 +1239,10 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\A_SIGNED"] = is_signed; \ - cell->parameters["\\A_WIDTH"] = sig_a.size(); \ - cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->setPort("\\A", sig_a); \ - cell->setPort("\\Y", sig_y); \ + cell->parameters["\\A_WIDTH"] = sig_a.size(); \ + cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ + cell->setPort("\\A", sig_a); \ + cell->setPort("\\Y", sig_y); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \ @@ -1267,12 +1267,12 @@ DEF_METHOD(LogicNot, 1, "$logic_not") RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\A_SIGNED"] = is_signed; \ cell->parameters["\\B_SIGNED"] = is_signed; \ - cell->parameters["\\A_WIDTH"] = sig_a.size(); \ - cell->parameters["\\B_WIDTH"] = sig_b.size(); \ - cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->setPort("\\A", sig_a); \ - cell->setPort("\\B", sig_b); \ - cell->setPort("\\Y", sig_y); \ + cell->parameters["\\A_WIDTH"] = sig_a.size(); \ + cell->parameters["\\B_WIDTH"] = sig_b.size(); \ + cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ + cell->setPort("\\A", sig_a); \ + cell->setPort("\\B", sig_b); \ + cell->setPort("\\Y", sig_y); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \ @@ -1309,72 +1309,95 @@ DEF_METHOD(LogicOr, 1, "$logic_or") #define DEF_METHOD(_func, _type, _pmux) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \ - RTLIL::Cell *cell = addCell(name, _type); \ + RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\WIDTH"] = sig_a.size(); \ cell->parameters["\\WIDTH"] = sig_b.size(); \ if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ - cell->setPort("\\A", sig_a); \ - cell->setPort("\\B", sig_b); \ - cell->setPort("\\S", sig_s); \ - cell->setPort("\\Y", sig_y); \ - return cell; \ + cell->setPort("\\A", sig_a); \ + cell->setPort("\\B", sig_b); \ + cell->setPort("\\S", sig_s); \ + cell->setPort("\\Y", sig_y); \ + return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \ RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \ - add ## _func(name, sig_a, sig_b, sig_s, sig_y); \ - return sig_y; \ + add ## _func(name, sig_a, sig_b, sig_s, sig_y); \ + return sig_y; \ } DEF_METHOD(Mux, "$mux", 0) DEF_METHOD(Pmux, "$pmux", 1) #undef DEF_METHOD #define DEF_METHOD_2(_func, _type, _P1, _P2) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ - RTLIL::Cell *cell = addCell(name, _type); \ - cell->setPort("\\" #_P1, sig1); \ - cell->setPort("\\" #_P2, sig2); \ - return cell; \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \ + RTLIL::Cell *cell = addCell(name, _type); \ + cell->setPort("\\" #_P1, sig1); \ + cell->setPort("\\" #_P2, sig2); \ + return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \ - RTLIL::SigSpec sig2 = addWire(NEW_ID); \ - add ## _func(name, sig1, sig2); \ - return sig2; \ + RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \ + RTLIL::SigBit sig2 = addWire(NEW_ID); \ + add ## _func(name, sig1, sig2); \ + return sig2; \ } #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ - RTLIL::Cell *cell = addCell(name, _type); \ - cell->setPort("\\" #_P1, sig1); \ - cell->setPort("\\" #_P2, sig2); \ - cell->setPort("\\" #_P3, sig3); \ - return cell; \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \ + RTLIL::Cell *cell = addCell(name, _type); \ + cell->setPort("\\" #_P1, sig1); \ + cell->setPort("\\" #_P2, sig2); \ + cell->setPort("\\" #_P3, sig3); \ + return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \ - RTLIL::SigSpec sig3 = addWire(NEW_ID); \ - add ## _func(name, sig1, sig2, sig3); \ - return sig3; \ + RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \ + RTLIL::SigBit sig3 = addWire(NEW_ID); \ + add ## _func(name, sig1, sig2, sig3); \ + return sig3; \ } #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \ - RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \ - RTLIL::Cell *cell = addCell(name, _type); \ - cell->setPort("\\" #_P1, sig1); \ - cell->setPort("\\" #_P2, sig2); \ - cell->setPort("\\" #_P3, sig3); \ - cell->setPort("\\" #_P4, sig4); \ - return cell; \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \ + RTLIL::Cell *cell = addCell(name, _type); \ + cell->setPort("\\" #_P1, sig1); \ + cell->setPort("\\" #_P2, sig2); \ + cell->setPort("\\" #_P3, sig3); \ + cell->setPort("\\" #_P4, sig4); \ + return cell; \ + } \ + RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \ + RTLIL::SigBit sig4 = addWire(NEW_ID); \ + add ## _func(name, sig1, sig2, sig3, sig4); \ + return sig4; \ + } +#define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \ + RTLIL::Cell *cell = addCell(name, _type); \ + cell->setPort("\\" #_P1, sig1); \ + cell->setPort("\\" #_P2, sig2); \ + cell->setPort("\\" #_P3, sig3); \ + cell->setPort("\\" #_P4, sig4); \ + cell->setPort("\\" #_P5, sig5); \ + return cell; \ } \ - RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \ - RTLIL::SigSpec sig4 = addWire(NEW_ID); \ - add ## _func(name, sig1, sig2, sig3, sig4); \ - return sig4; \ + RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \ + RTLIL::SigBit sig5 = addWire(NEW_ID); \ + add ## _func(name, sig1, sig2, sig3, sig4, sig5); \ + return sig5; \ } -DEF_METHOD_2(NotGate, "$_NOT_", A, Y) -DEF_METHOD_3(AndGate, "$_AND_", A, B, Y) -DEF_METHOD_3(OrGate, "$_OR_", A, B, Y) -DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y) -DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y) +DEF_METHOD_2(NotGate, "$_NOT_", A, Y) +DEF_METHOD_3(AndGate, "$_AND_", A, B, Y) +DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y) +DEF_METHOD_3(OrGate, "$_OR_", A, B, Y) +DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y) +DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y) +DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y) +DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y) +DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y) +DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y) +DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y) +DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y) #undef DEF_METHOD_2 #undef DEF_METHOD_3 #undef DEF_METHOD_4 +#undef DEF_METHOD_5 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed) { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7e052b091..8b3306f6f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -697,11 +697,18 @@ public: RTLIL::Cell* addDlatchsr (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true); - RTLIL::Cell* addNotGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y); - RTLIL::Cell* addAndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); - RTLIL::Cell* addOrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); - RTLIL::Cell* addXorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); - RTLIL::Cell* addMuxGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y); + RTLIL::Cell* addNotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y); + RTLIL::Cell* addAndGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y); + RTLIL::Cell* addNandGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y); + RTLIL::Cell* addOrGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y); + RTLIL::Cell* addNorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y); + RTLIL::Cell* addXorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y); + RTLIL::Cell* addXnorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y); + RTLIL::Cell* addMuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y); + RTLIL::Cell* addAoi3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y); + RTLIL::Cell* addOai3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y); + RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y); + RTLIL::Cell* addOai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y); RTLIL::Cell* addDffGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true); RTLIL::Cell* addDffsrGate (RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, @@ -760,11 +767,18 @@ public: RTLIL::SigSpec Mux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); RTLIL::SigSpec Pmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); - RTLIL::SigSpec NotGate (RTLIL::IdString name, RTLIL::SigSpec sig_a); - RTLIL::SigSpec AndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); - RTLIL::SigSpec OrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); - RTLIL::SigSpec XorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b); - RTLIL::SigSpec MuxGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s); + RTLIL::SigBit NotGate (RTLIL::IdString name, RTLIL::SigBit sig_a); + RTLIL::SigBit AndGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b); + RTLIL::SigBit NandGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b); + RTLIL::SigBit OrGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b); + RTLIL::SigBit NorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b); + RTLIL::SigBit XorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b); + RTLIL::SigBit XnorGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b); + RTLIL::SigBit MuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s); + RTLIL::SigBit Aoi3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c); + RTLIL::SigBit Oai3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c); + RTLIL::SigBit Aoi4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d); + RTLIL::SigBit Oai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d); }; struct RTLIL::Wire -- cgit v1.2.3 From a3494fa9ed32d7ff2b826dfc921e3a0139158880 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Aug 2014 13:58:36 +0200 Subject: Added "plugin" command --- kernel/driver.cc | 15 +++++---------- kernel/yosys.cc | 7 +++++++ kernel/yosys.h | 5 +++++ 3 files changed, 17 insertions(+), 10 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index d59e68a50..6bd60d7b5 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -38,7 +37,7 @@ int main(int argc, char **argv) std::string frontend_command = "auto"; std::string backend_command = "auto"; std::vector passes_commands; - std::vector loaded_modules; + std::vector plugin_filenames; std::string output_filename = ""; std::string scriptfile = ""; bool scriptfile_tcl = false; @@ -82,11 +81,7 @@ int main(int argc, char **argv) passes_commands.push_back("opt"); break; case 'm': - loaded_modules.push_back(dlopen(optarg, RTLD_LAZY|RTLD_GLOBAL)); - if (loaded_modules.back() == NULL) { - fprintf(stderr, "Can't load module `%s': %s\n", optarg, dlerror()); - exit(1); - } + plugin_filenames.push_back(optarg); break; case 'f': frontend_command = optarg; @@ -239,6 +234,9 @@ int main(int argc, char **argv) yosys_setup(); + for (auto &fn : plugin_filenames) + load_plugin(fn, {}); + if (optind == argc && passes_commands.size() == 0 && scriptfile.empty()) { if (!got_output_filename) backend_command = ""; @@ -346,9 +344,6 @@ int main(int argc, char **argv) yosys_shutdown(); - for (auto mod : loaded_modules) - dlclose(mod); - return 0; } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 599c92d52..ce2487314 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -98,6 +99,12 @@ void yosys_shutdown() yosys_tcl_interp = NULL; } #endif + + for (auto &it : loaded_plugins) + dlclose(it.second); + + loaded_plugins.clear(); + loaded_plugin_aliases.clear(); } RTLIL::IdString new_id(std::string file, int line, std::string func) diff --git a/kernel/yosys.h b/kernel/yosys.h index 79c90628c..c6cbcabc9 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -132,6 +132,11 @@ extern const char *yosys_version_str; extern std::map saved_designs; extern std::vector pushed_designs; +// from passes/cmds/pluginc.cc +extern std::map loaded_plugins; +extern std::map loaded_plugin_aliases; +void load_plugin(std::string filename, std::vector aliases); + YOSYS_NAMESPACE_END #endif -- cgit v1.2.3 From 98442e019d745f1d61983c071decfa3ebc1ff0cf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Aug 2014 16:09:13 +0200 Subject: Added emscripten (emcc) support to build system and some build fixes --- kernel/celltypes.h | 4 ++-- kernel/compatibility.cc | 2 +- kernel/driver.cc | 10 ++++++++-- kernel/rtlil.cc | 4 ++++ kernel/rtlil.h | 5 ++--- kernel/yosys.cc | 25 +++++++++++++++++++++++-- 6 files changed, 40 insertions(+), 10 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 8c2e9a48e..515da25ce 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -108,7 +108,7 @@ struct CellTypes for (auto type : std::vector({"$mux", "$pmux"})) setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, true); - setup_type("$assert", {"\\A", "\\EN"}, {}, true); + setup_type("$assert", {"\\A", "\\EN"}, std::set(), true); } void setup_internals_mem() @@ -121,7 +121,7 @@ struct CellTypes setup_type("$dlatchsr", {"\\EN", "\\SET", "\\CLR", "\\D"}, {"\\Q"}); setup_type("$memrd", {"\\CLK", "\\ADDR"}, {"\\DATA"}); - setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, {}); + setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, std::set()); setup_type("$mem", {"\\RD_CLK", "\\RD_ADDR", "\\WR_CLK", "\\WR_EN", "\\WR_ADDR", "\\WR_DATA"}, {"\\RD_DATA"}); setup_type("$fsm", {"\\CLK", "\\ARST", "\\CTRL_IN"}, {"\\CTRL_OUT"}); diff --git a/kernel/compatibility.cc b/kernel/compatibility.cc index 2ef023eb3..4c4cbd6de 100644 --- a/kernel/compatibility.cc +++ b/kernel/compatibility.cc @@ -26,7 +26,7 @@ #include #include -#if !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) +#if !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L || defined(EMSCRIPTEN)) typedef struct memstream { off_t pos; diff --git a/kernel/driver.cc b/kernel/driver.cc index 6bd60d7b5..e778e1389 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -20,8 +20,10 @@ #include "kernel/yosys.h" #include "libs/sha1/sha1.h" -#include -#include +#ifdef YOSYS_ENABLE_READLINE +# include +# include +#endif #include #include @@ -46,6 +48,7 @@ int main(int argc, char **argv) bool print_stats = true; bool call_abort = false; +#ifdef YOSYS_ENABLE_READLINE int history_offset = 0; std::string history_file; if (getenv("HOME") != NULL) { @@ -53,6 +56,7 @@ int main(int argc, char **argv) read_history(history_file.c_str()); history_offset = where_history(); } +#endif int opt; while ((opt = getopt(argc, argv, "AQTVSm:f:Hh:b:o:p:l:qv:ts:c:")) != -1) @@ -329,6 +333,7 @@ int main(int argc, char **argv) if (call_abort) abort(); +#ifdef YOSYS_ENABLE_READLINE if (!history_file.empty()) { if (history_offset > 0) { history_truncate_file(history_file.c_str(), 100); @@ -341,6 +346,7 @@ int main(int argc, char **argv) HIST_ENTRY **hist_list = history_list(); if (hist_list != NULL) free(hist_list); +#endif yosys_shutdown(); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 24cce6b8b..22bff7bdb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1605,6 +1605,10 @@ RTLIL::Memory::Memory() size = 0; } +RTLIL::Cell::Cell() : module(nullptr) +{ +} + bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const { return connections_.count(portname) != 0; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8b3306f6f..ebfe4ca29 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -77,7 +77,7 @@ namespace RTLIL // the global id string cache struct char_ptr_cmp { - bool operator()(const char *a, const char *b) { + bool operator()(const char *a, const char *b) const { for (int i = 0; a[i] || b[i]; i++) if (a[i] != b[i]) return a[i] < b[i]; @@ -815,8 +815,7 @@ struct RTLIL::Cell protected: // use module->addCell() and module->remove() to create or destroy cells friend struct RTLIL::Module; - Cell() : module(nullptr) { }; - ~Cell() { }; + Cell(); public: // do not simply copy cells diff --git a/kernel/yosys.cc b/kernel/yosys.cc index ce2487314..7b8173b6a 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -19,12 +19,15 @@ #include "kernel/yosys.h" -#include -#include +#ifdef YOSYS_ENABLE_READLINE +# include +# include +#endif #include #include #include +#include YOSYS_NAMESPACE_BEGIN @@ -232,6 +235,11 @@ std::string proc_self_dirname () buflen--; return std::string(path, buflen); } +#elif defined(EMSCRIPTEN) +std::string proc_self_dirname () +{ + return "/"; +} #else #error Dont know how to determine process executable base path! #endif @@ -416,6 +424,7 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig Backend::backend_call(design, NULL, filename, command); } +#ifdef YOSYS_ENABLE_READLINE static char *readline_cmd_generator(const char *text, int state) { static std::map::iterator it; @@ -493,6 +502,7 @@ static char **readline_completion(const char *text, int start, int) return rl_completion_matches(text, readline_obj_generator); return NULL; } +#endif void shell(RTLIL::Design *design) { @@ -501,16 +511,25 @@ void shell(RTLIL::Design *design) recursion_counter++; log_cmd_error_throw = true; +#ifdef YOSYS_ENABLE_READLINE rl_readline_name = "yosys"; rl_attempted_completion_function = readline_completion; rl_basic_word_break_characters = " \t\n"; +#endif char *command = NULL; +#ifdef YOSYS_ENABLE_READLINE while ((command = readline(create_prompt(design, recursion_counter))) != NULL) +#else + char command_buffer[4096]; + while ((command = fgets(command_buffer, 4096, stdin)) != NULL) +#endif { if (command[strspn(command, " \t\r\n")] == 0) continue; +#ifdef YOSYS_ENABLE_READLINE add_history(command); +#endif char *p = command + strspn(command, " \t\r\n"); if (!strncmp(p, "exit", 4)) { @@ -576,6 +595,7 @@ struct ShellPass : public Pass { } } ShellPass; +#ifdef YOSYS_ENABLE_READLINE struct HistoryPass : public Pass { HistoryPass() : Pass("history", "show last interactive commands") { } virtual void help() { @@ -593,6 +613,7 @@ struct HistoryPass : public Pass { log("%s\n", (*list)->line); } } HistoryPass; +#endif struct ScriptPass : public Pass { ScriptPass() : Pass("script", "execute commands from script file") { } -- cgit v1.2.3 From 5dce303a2a2c27d50e99856b6f33467798e13020 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 13:54:21 +0200 Subject: Changed backend-api from FILE to std::ostream --- kernel/log.cc | 25 ++++++------------------- kernel/register.cc | 28 ++++++++++++++++------------ kernel/register.h | 16 ++++++---------- kernel/rtlil.cc | 11 +++-------- kernel/yosys.h | 5 +++++ 5 files changed, 36 insertions(+), 49 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index b742a5495..2b4b5db5b 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -210,20 +210,14 @@ void log_dump_val_worker(RTLIL::SigSpec v) { const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) { - char *ptr; - size_t size; - - FILE *f = open_memstream(&ptr, &size); - ILANG_BACKEND::dump_sigspec(f, sig, autoint); - fputc(0, f); - fclose(f); + std::stringstream buf; + ILANG_BACKEND::dump_sigspec(buf, sig, autoint); if (string_buf_size < 100) string_buf_size++; else string_buf.pop_front(); - string_buf.push_back(ptr); - free(ptr); + string_buf.push_back(buf.str()); return string_buf.back().c_str(); } @@ -239,16 +233,9 @@ const char *log_id(RTLIL::IdString str) void log_cell(RTLIL::Cell *cell, std::string indent) { - char *ptr; - size_t size; - - FILE *f = open_memstream(&ptr, &size); - ILANG_BACKEND::dump_cell(f, indent, cell); - fputc(0, f); - fclose(f); - - log("%s", ptr); - free(ptr); + std::stringstream buf; + ILANG_BACKEND::dump_cell(buf, indent, cell); + log("%s", buf.str().c_str()); } // --------------------------------------------------- diff --git a/kernel/register.cc b/kernel/register.cc index a9e21e6dd..95ed0cbd1 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -423,15 +423,15 @@ Backend::~Backend() void Backend::execute(std::vector args, RTLIL::Design *design) { - FILE *f = NULL; + std::ostream *f = NULL; auto state = pre_execute(); execute(f, std::string(), args, design); post_execute(state); - if (f != stdout) - fclose(f); + if (f != &std::cout) + delete f; } -void Backend::extra_args(FILE *&f, std::string &filename, std::vector args, size_t argidx) +void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector args, size_t argidx) { bool called_with_fp = f != NULL; @@ -446,14 +446,18 @@ void Backend::extra_args(FILE *&f, std::string &filename, std::vectoropen(filename.c_str(), std::ofstream::trunc); + if (ff->fail()) { + delete ff; log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + } + f = ff; } if (called_with_fp) @@ -463,11 +467,11 @@ void Backend::extra_args(FILE *&f, std::string &filename, std::vector args; char *s = strdup(command.c_str()); @@ -477,7 +481,7 @@ void Backend::backend_call(RTLIL::Design *design, FILE *f, std::string filename, backend_call(design, f, filename, args); } -void Backend::backend_call(RTLIL::Design *design, FILE *f, std::string filename, std::vector args) +void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector args) { if (args.size() == 0) return; @@ -491,9 +495,9 @@ void Backend::backend_call(RTLIL::Design *design, FILE *f, std::string filename, backend_register[args[0]]->execute(f, filename, args, design); backend_register[args[0]]->post_execute(state); } else if (filename == "-") { - FILE *f_stdout = stdout; // workaround for OpenBSD 'stdout' implementation + std::ostream *f_cout = &std::cout; auto state = backend_register[args[0]]->pre_execute(); - backend_register[args[0]]->execute(f_stdout, "", args, design); + backend_register[args[0]]->execute(f_cout, "", args, design); backend_register[args[0]]->post_execute(state); } else { if (!filename.empty()) diff --git a/kernel/register.h b/kernel/register.h index d7e4281c2..f2c6ad29e 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -17,15 +17,11 @@ * */ +#include "kernel/yosys.h" + #ifndef REGISTER_H #define REGISTER_H -#include "kernel/yosys.h" -#include -#include -#include -#include - YOSYS_NAMESPACE_BEGIN struct Pass @@ -94,12 +90,12 @@ struct Backend : Pass virtual void run_register(); virtual ~Backend(); virtual void execute(std::vector args, RTLIL::Design *design) OVERRIDE FINAL; - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; + virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; - void extra_args(FILE *&f, std::string &filename, std::vector args, size_t argidx); + void extra_args(std::ostream *&f, std::string &filename, std::vector args, size_t argidx); - static void backend_call(RTLIL::Design *design, FILE *f, std::string filename, std::string command); - static void backend_call(RTLIL::Design *design, FILE *f, std::string filename, std::vector args); + static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command); + static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector args); }; // implemented in passes/cmds/select.cc diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 22bff7bdb..28a451345 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -412,17 +412,12 @@ namespace { void error(int linenr) { - char *ptr; - size_t size; - - FILE *f = open_memstream(&ptr, &size); - ILANG_BACKEND::dump_cell(f, " ", cell); - fputc(0, f); - fclose(f); + std::stringstream buf; + ILANG_BACKEND::dump_cell(buf, " ", cell); log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s", module ? module->name.c_str() : "", module ? "." : "", - cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr); + cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str()); } int param(const char *name) diff --git a/kernel/yosys.h b/kernel/yosys.h index c6cbcabc9..bfadb5ffc 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -45,6 +45,11 @@ #include #include +#include +#include +#include +#include + #include #include #include -- cgit v1.2.3 From 19cff41eb4261b20374058f16807a229af46f304 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 15:03:55 +0200 Subject: Changed frontend-api from FILE to std::istream --- kernel/register.cc | 23 ++++++++++++++--------- kernel/register.h | 8 ++++---- kernel/yosys.h | 1 + 3 files changed, 19 insertions(+), 13 deletions(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 95ed0cbd1..5f4e71d1f 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -286,20 +286,20 @@ void Frontend::execute(std::vector args, RTLIL::Design *design) { log_assert(next_args.empty()); do { - FILE *f = NULL; + std::istream *f = NULL; next_args.clear(); auto state = pre_execute(); execute(f, std::string(), args, design); post_execute(state); args = next_args; - fclose(f); + delete f; } while (!args.empty()); } FILE *Frontend::current_script_file = NULL; std::string Frontend::last_here_document; -void Frontend::extra_args(FILE *&f, std::string &filename, std::vector args, size_t argidx) +void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector args, size_t argidx) { bool called_with_fp = f != NULL; @@ -338,11 +338,16 @@ void Frontend::extra_args(FILE *&f, std::string &filename, std::vectoropen(filename.c_str()); + if (ff->fail()) + delete ff; + else + f = ff; } if (f == NULL) log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); @@ -367,7 +372,7 @@ void Frontend::extra_args(FILE *&f, std::string &filename, std::vector args; char *s = strdup(command.c_str()); @@ -377,7 +382,7 @@ void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filenam frontend_call(design, f, filename, args); } -void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filename, std::vector args) +void Frontend::frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector args) { if (args.size() == 0) return; @@ -389,9 +394,9 @@ void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filenam frontend_register[args[0]]->execute(f, filename, args, design); frontend_register[args[0]]->post_execute(state); } else if (filename == "-") { - FILE *f_stdin = stdin; // workaround for OpenBSD 'stdin' implementation + std::istream *f_cin = &std::cin; auto state = frontend_register[args[0]]->pre_execute(); - frontend_register[args[0]]->execute(f_stdin, "", args, design); + frontend_register[args[0]]->execute(f_cin, "", args, design); frontend_register[args[0]]->post_execute(state); } else { if (!filename.empty()) diff --git a/kernel/register.h b/kernel/register.h index f2c6ad29e..a49675ed2 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -74,13 +74,13 @@ struct Frontend : Pass virtual void run_register(); virtual ~Frontend(); virtual void execute(std::vector args, RTLIL::Design *design) OVERRIDE FINAL; - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; + virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; static std::vector next_args; - void extra_args(FILE *&f, std::string &filename, std::vector args, size_t argidx); + void extra_args(std::istream *&f, std::string &filename, std::vector args, size_t argidx); - static void frontend_call(RTLIL::Design *design, FILE *f, std::string filename, std::string command); - static void frontend_call(RTLIL::Design *design, FILE *f, std::string filename, std::vector args); + static void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::string command); + static void frontend_call(RTLIL::Design *design, std::istream *f, std::string filename, std::vector args); }; struct Backend : Pass diff --git a/kernel/yosys.h b/kernel/yosys.h index bfadb5ffc..87c99d1f6 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -47,6 +47,7 @@ #include #include +#include #include #include -- cgit v1.2.3 From 58367cd87a5d2bac1de81512f60939c080b3b9ef Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 15:14:58 +0200 Subject: Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore --- kernel/compatibility.cc | 135 ------------------------------------------------ kernel/compatibility.h | 37 ------------- kernel/log.cc | 10 ++++ kernel/log.h | 1 + kernel/register.cc | 24 +++------ kernel/yosys.h | 1 - 6 files changed, 19 insertions(+), 189 deletions(-) delete mode 100644 kernel/compatibility.cc delete mode 100644 kernel/compatibility.h (limited to 'kernel') diff --git a/kernel/compatibility.cc b/kernel/compatibility.cc deleted file mode 100644 index 4c4cbd6de..000000000 --- a/kernel/compatibility.cc +++ /dev/null @@ -1,135 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -/** - * POSIX.2008 fake implementation for pre-POSIX.2008 systems. (OSX, BSD, MINGW, CYGWIN, older Linux &c.) - */ - -#include -#include -#include -#include - -#if !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L || defined(EMSCRIPTEN)) - -typedef struct memstream { - off_t pos; - off_t size; - char * buffer; - char ** bufp; - size_t * sizep; - bool realloc; -} memstream_t; - -static int memstream_read (void * cookie, char * buf, int size) -{ - memstream_t * mem = (memstream_t *) cookie; - off_t available = mem->size - mem->pos; - if (available < 0) - available = 0; - if (size > available) - size = available; - memcpy(buf, mem->buffer + mem->pos, size); - mem->pos += size; - return size; -} - -static int memstream_write (void * cookie, const char * buf, int size) -{ - memstream_t * mem = (memstream_t *) cookie; - off_t available = mem->size - mem->pos; - if (size > available) { - if (mem->realloc) { - mem->buffer = (char *) realloc(mem->buffer, mem->pos + size + 1); - memset(mem->buffer + mem->size, 0, mem->pos + size + 1 - mem->size); - mem->size = mem->pos + size; - if (mem->bufp) - *(mem->bufp) = mem->buffer; - if (mem->sizep) - *(mem->sizep) = mem->size; - } else { - size = available; - } - } - memcpy(mem->buffer + mem->pos, buf, sizeof(char) * size); - mem->pos += size; - return size; -} - -static fpos_t memstream_seek (void * cookie, fpos_t offset, int whence) -{ - memstream_t * mem = (memstream_t *) cookie; - switch (whence) { - case SEEK_SET: - if (offset < 0) - goto error_inval; - mem->pos = offset; - return 0; - case SEEK_CUR: - if (mem->pos + offset < 0) - goto error_inval; - mem->pos += offset; - return 0; - case SEEK_END: - if (mem->size + offset < 0) - goto error_inval; - mem->pos = mem->size + offset; - break; - default: - goto error_inval; - } - return mem->pos; -error_inval: - errno = EINVAL; - return -1; -} - -static int memstream_close (void * cookie) -{ - memstream_t * mem = (memstream_t *) cookie; - if (mem->bufp) - *(mem->bufp) = mem->buffer; - if (mem->sizep) - *(mem->sizep) = mem->size; - free(cookie); - return 0; -} - -FILE * compat_fmemopen (void * buf, size_t size, const char * mode) -{ - memstream_t * mem = (memstream_t *) malloc(sizeof(memstream_t)); - memset(mem, 0, sizeof(memstream_t)); - mem->size = size; - mem->buffer = (char *) buf; - (void) mode; - return funopen(mem, memstream_read, memstream_write, memstream_seek, memstream_close); -} - -FILE * compat_open_memstream (char ** bufp, size_t * sizep) -{ - memstream_t * mem = (memstream_t *) malloc(sizeof(memstream_t)); - memset(mem, 0, sizeof(memstream_t)); - mem->bufp = bufp; - mem->sizep = sizep; - mem->realloc = true; - return funopen(mem, memstream_read, memstream_write, memstream_seek, memstream_close); -} - -#endif /* !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) */ - diff --git a/kernel/compatibility.h b/kernel/compatibility.h deleted file mode 100644 index c7603c8a5..000000000 --- a/kernel/compatibility.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifndef COMPATIBILITY_H -#define COMPATIBILITY_H - -#include -#include - -#if !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) - -#define open_memstream compat_open_memstream -#define fmemopen compat_fmemopen - -FILE * compat_open_memstream (char ** bufp, size_t * sizep); -FILE * compat_fmemopen (void * buf, size_t size, const char * mode); - -#endif /* !(_XOPEN_SOURCE >= 700 || _POSIX_C_SOURCE >= 200809L) */ - -#endif /* COMPATIBILITY_H */ - diff --git a/kernel/log.cc b/kernel/log.cc index 2b4b5db5b..1b0eb6649 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -32,6 +32,7 @@ YOSYS_NAMESPACE_BEGIN std::vector log_files; +std::vector log_streams; FILE *log_errfile = NULL; SHA1 *log_hasher = NULL; @@ -92,10 +93,16 @@ void logv(const char *format, va_list ap) for (auto f : log_files) fputs(time_str.c_str(), f); + + for (auto f : log_streams) + *f << time_str; } for (auto f : log_files) fputs(str.c_str(), f); + + for (auto f : log_streams) + *f << str; } void logv_header(const char *format, va_list ap) @@ -202,6 +209,9 @@ void log_flush() { for (auto f : log_files) fflush(f); + + for (auto f : log_streams) + f->flush(); } void log_dump_val_worker(RTLIL::SigSpec v) { diff --git a/kernel/log.h b/kernel/log.h index b1c44b46b..e2b4db87b 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -35,6 +35,7 @@ YOSYS_NAMESPACE_BEGIN struct log_cmd_error_expection { }; extern std::vector log_files; +extern std::vector log_streams; extern FILE *log_errfile; extern class SHA1 *log_hasher; diff --git a/kernel/register.cc b/kernel/register.cc index 5f4e71d1f..a53bd84c7 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -612,15 +612,11 @@ struct HelpPass : public Pass { FILE *f = fopen("command-reference-manual.tex", "wt"); fprintf(f, "%% Generated using the yosys 'help -write-tex-command-reference-manual' command.\n\n"); for (auto &it : pass_register) { - size_t memsize; - char *memptr; - FILE *memf = open_memstream(&memptr, &memsize); - log_files.push_back(memf); + std::ostringstream buf; + log_streams.push_back(&buf); it.second->help(); - log_files.pop_back(); - fclose(memf); - write_tex(f, it.first, it.second->short_help, memptr); - free(memptr); + log_streams.pop_back(); + write_tex(f, it.first, it.second->short_help, buf.str()); } fclose(f); } @@ -628,15 +624,11 @@ struct HelpPass : public Pass { else if (args[1] == "-write-web-command-reference-manual") { FILE *f = fopen("templates/cmd_index.in", "wt"); for (auto &it : pass_register) { - size_t memsize; - char *memptr; - FILE *memf = open_memstream(&memptr, &memsize); - log_files.push_back(memf); + std::ostringstream buf; + log_streams.push_back(&buf); it.second->help(); - log_files.pop_back(); - fclose(memf); - write_html(f, it.first, it.second->short_help, memptr); - free(memptr); + log_streams.pop_back(); + write_html(f, it.first, it.second->short_help, buf.str()); } fclose(f); } diff --git a/kernel/yosys.h b/kernel/yosys.h index 87c99d1f6..9a4826caa 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -98,7 +98,6 @@ YOSYS_NAMESPACE_END #include "kernel/log.h" #include "kernel/rtlil.h" #include "kernel/register.h" -#include "kernel/compatibility.h" YOSYS_NAMESPACE_BEGIN -- cgit v1.2.3 From eda603105e2aa72441bfc07662774a20f3b978fe Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Aug 2014 15:14:00 +0200 Subject: Added is_signed argument to SigSpec.as_int() and Const.as_int() --- kernel/rtlil.cc | 11 +++++++---- kernel/rtlil.h | 4 ++-- 2 files changed, 9 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 28a451345..df4d8b092 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -92,12 +92,15 @@ bool RTLIL::Const::as_bool() const return false; } -int RTLIL::Const::as_int() const +int RTLIL::Const::as_int(bool is_signed) const { - int ret = 0; + int32_t ret = 0; for (size_t i = 0; i < bits.size() && i < 32; i++) if (bits[i] == RTLIL::S1) ret |= 1 << i; + if (is_signed && bits.back() == RTLIL::S1) + for (size_t i = bits.size(); i < 32; i++) + ret |= 1 << i; return ret; } @@ -2647,14 +2650,14 @@ bool RTLIL::SigSpec::as_bool() const return false; } -int RTLIL::SigSpec::as_int() const +int RTLIL::SigSpec::as_int(bool is_signed) const { cover("kernel.rtlil.sigspec.as_int"); pack(); log_assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) - return chunks_[0].data.as_int(); + return chunks_[0].data.as_int(is_signed); return 0; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index ebfe4ca29..d58873570 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -436,7 +436,7 @@ struct RTLIL::Const bool operator !=(const RTLIL::Const &other) const; bool as_bool() const; - int as_int() const; + int as_int(bool is_signed = false) const; std::string as_string() const; std::string decode_string() const; @@ -1038,7 +1038,7 @@ public: bool has_marked_bits() const; bool as_bool() const; - int as_int() const; + int as_int(bool is_signed = false) const; std::string as_string() const; RTLIL::Const as_const() const; RTLIL::Wire *as_wire() const; -- cgit v1.2.3 From dfbd7dd15a1520ce0c01d2722aaacbf7b7be71fa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 18:17:22 +0200 Subject: Fixed module->addPmux() --- kernel/rtlil.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index df4d8b092..7ba6911a2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1309,7 +1309,6 @@ DEF_METHOD(LogicOr, 1, "$logic_or") RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \ RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters["\\WIDTH"] = sig_a.size(); \ - cell->parameters["\\WIDTH"] = sig_b.size(); \ if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ cell->setPort("\\A", sig_a); \ cell->setPort("\\B", sig_b); \ -- cgit v1.2.3 From 4724d94fbce587b39cd7343dc8de3b859311f55c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 18:59:05 +0200 Subject: Added $alu cell type --- kernel/celltypes.h | 2 ++ kernel/rtlil.cc | 14 ++++++++++++++ 2 files changed, 16 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 515da25ce..c1bb1d036 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -108,6 +108,8 @@ struct CellTypes for (auto type : std::vector({"$mux", "$pmux"})) setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, true); + setup_type("$alu", {"\\A", "\\B", "\\CI", "\\BI"}, {"\\X", "\\Y", "\\CO"}, true); + setup_type("$assert", {"\\A", "\\EN"}, std::set(), true); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7ba6911a2..96b651d89 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -557,6 +557,20 @@ namespace { return; } + if (cell->type == "$alu") { + param_bool("\\A_SIGNED"); + param_bool("\\B_SIGNED"); + port("\\A", param("\\A_WIDTH")); + port("\\B", param("\\B_WIDTH")); + port("\\CI", 1); + port("\\BI", 1); + port("\\X", param("\\Y_WIDTH")); + port("\\Y", param("\\Y_WIDTH")); + port("\\CO", param("\\Y_WIDTH")); + check_expected(); + return; + } + if (cell->type == "$logic_not") { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); -- cgit v1.2.3 From 2a1b08aeb34b7d5f2df1a43c9ef1f99abacb9cae Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 19:37:12 +0200 Subject: Added design->scratchpad --- kernel/rtlil.cc | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/rtlil.h | 11 +++++++++++ 2 files changed, 72 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 96b651d89..72eced914 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -273,6 +273,67 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) return module; } +void RTLIL::Design::scratchpad_unset(std::string varname) +{ + scratchpad.erase(varname); +} + +void RTLIL::Design::scratchpad_set_int(std::string varname, int value) +{ + scratchpad[varname] = stringf("%d", value); +} + +void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value) +{ + scratchpad[varname] = value ? "true" : "false"; +} + +void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value) +{ + scratchpad[varname] = value; +} + +int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const +{ + if (scratchpad.count(varname) == 0) + return default_value; + + std::string str = scratchpad.at(varname); + + if (str == "0" || str == "false") + return 0; + + if (str == "1" || str == "true") + return 1; + + char *endptr = nullptr; + long int parsed_value = strtol(str.c_str(), &endptr, 10); + return *endptr ? default_value : parsed_value; +} + +bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const +{ + if (scratchpad.count(varname) == 0) + return default_value; + + std::string str = scratchpad.at(varname); + + if (str == "0" || str == "false") + return false; + + if (str == "1" || str == "true") + return true; + + return default_value; +} + +std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const +{ + if (scratchpad.count(varname) == 0) + return default_value; + return scratchpad.at(varname); +} + void RTLIL::Design::remove(RTLIL::Module *module) { for (auto mon : monitors) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index d58873570..e35c3c681 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -486,6 +486,7 @@ struct RTLIL::Monitor struct RTLIL::Design { std::set monitors; + std::map scratchpad; int refcount_modules_; std::map modules_; @@ -508,6 +509,16 @@ struct RTLIL::Design RTLIL::Module *addModule(RTLIL::IdString name); void remove(RTLIL::Module *module); + void scratchpad_unset(std::string varname); + + void scratchpad_set_int(std::string varname, int value); + void scratchpad_set_bool(std::string varname, bool value); + void scratchpad_set_string(std::string varname, std::string value); + + int scratchpad_get_int(std::string varname, int default_value = 0) const; + bool scratchpad_get_bool(std::string varname, bool default_value = false) const; + std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + void check(); void optimize(); -- cgit v1.2.3 From 8649b57b6f4c3a4322acaf73f5c02d5119629c1e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 31 Aug 2014 17:06:36 +0200 Subject: Added $lut support in test_cell, techmap, satgen --- kernel/rtlil.cc | 10 +++++++--- kernel/satgen.h | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 57 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 72eced914..403bb6d28 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1768,8 +1768,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") return; - if (type == "$mux" || type == "$pmux") - { + if (type == "$mux" || type == "$pmux") { parameters["\\WIDTH"] = SIZE(connections_["\\Y"]); if (type == "$pmux") parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]); @@ -1777,7 +1776,12 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } - bool signedness_ab = type != "$slice" && type != "$concat"; + if (type == "$lut") { + parameters["\\WIDTH"] = SIZE(connections_["\\A"]); + return; + } + + bool signedness_ab = !type.in("$slice", "$concat"); if (connections_.count("\\A")) { if (signedness_ab) { diff --git a/kernel/satgen.h b/kernel/satgen.h index c02900a6c..5d1c11c9e 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -841,6 +841,56 @@ struct SatGen return true; } + if (cell->type == "$lut") + { + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + + std::vector lut; + for (auto bit : cell->getParam("\\LUT").bits) + lut.push_back(bit == RTLIL::S1 ? ez->TRUE : ez->FALSE); + while (SIZE(lut) < (1 << SIZE(a))) + lut.push_back(ez->FALSE); + lut.resize(1 << SIZE(a)); + + if (model_undef) + { + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector t(lut), u(SIZE(t), ez->FALSE); + + for (int i = SIZE(a)-1; i >= 0; i--) + { + std::vector t0(t.begin(), t.begin() + SIZE(t)/2); + std::vector t1(t.begin() + SIZE(t)/2, t.end()); + + std::vector u0(u.begin(), u.begin() + SIZE(u)/2); + std::vector u1(u.begin() + SIZE(u)/2, u.end()); + + t = ez->vec_ite(a[i], t1, t0); + u = ez->vec_ite(undef_a[i], ez->vec_or(ez->vec_xor(t0, t1), ez->vec_or(u0, u1)), ez->vec_ite(a[i], u1, u0)); + } + + log_assert(SIZE(t) == 1); + log_assert(SIZE(u) == 1); + undefGating(y, t, u); + ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort("\\Y"), timestep), u)); + } + else + { + std::vector t = lut; + for (int i = SIZE(a)-1; i >= 0; i--) + { + std::vector t0(t.begin(), t.begin() + SIZE(t)/2); + std::vector t1(t.begin() + SIZE(t)/2, t.end()); + t = ez->vec_ite(a[i], t1, t0); + } + + log_assert(SIZE(t) == 1); + ez->assume(ez->vec_eq(y, t)); + } + return true; + } + if (cell->type == "$slice") { RTLIL::SigSpec a = cell->getPort("\\A"); @@ -903,4 +953,3 @@ struct SatGen }; #endif - -- cgit v1.2.3 From 0b6769af3f7578dfb31c801014413174bd230208 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 31 Aug 2014 17:07:07 +0200 Subject: Typo fixes in cell->*Param() API --- kernel/rtlil.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e35c3c681..907600408 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -848,10 +848,10 @@ public: const std::map &connections() const; // access cell parameters - bool hasParam(RTLIL::IdString portname) const; - void unsetParam(RTLIL::IdString portname); - void setParam(RTLIL::IdString portname, RTLIL::Const value); - const RTLIL::Const &getParam(RTLIL::IdString portname) const; + bool hasParam(RTLIL::IdString paramname) const; + void unsetParam(RTLIL::IdString paramname); + void setParam(RTLIL::IdString paramname, RTLIL::Const value); + const RTLIL::Const &getParam(RTLIL::IdString paramname) const; void check(); void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); -- cgit v1.2.3 From a1c7d4a8e24c14eae7f1f7e383f18b25a190875b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 31 Aug 2014 17:42:38 +0200 Subject: Added eval model for $lut cells --- kernel/celltypes.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index c1bb1d036..4a8be04d3 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -297,6 +297,32 @@ struct CellTypes return ret; } + if (cell->type == "$lut") + { + int width = cell->parameters.at("\\WIDTH").as_int(); + + std::vector t = cell->parameters.at("\\LUT").bits; + while (SIZE(t) < (1 << width)) + t.push_back(RTLIL::S0); + t.resize(1 << width); + + for (int i = width-1; i >= 0; i--) { + RTLIL::State sel = arg1.bits.at(i); + std::vector new_t; + if (sel == RTLIL::S0) + new_t = std::vector(t.begin(), t.begin() + SIZE(t)/2); + else if (sel == RTLIL::S1) + new_t = std::vector(t.begin() + SIZE(t)/2, t.end()); + else + for (int j = 0; j < SIZE(t)/2; j++) + new_t.push_back(t[j] == t[j + SIZE(t)/2] ? t[j] : RTLIL::Sx); + t.swap(new_t); + } + + log_assert(SIZE(t) == 1); + return t; + } + bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool(); int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1; -- cgit v1.2.3 From be44157c0f07c3bcca2363b5ce95a71fe7ad6dd9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 31 Aug 2014 18:07:48 +0200 Subject: Added RTLIL::Const::size() --- kernel/rtlil.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 907600408..935329384 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -440,6 +440,8 @@ struct RTLIL::Const std::string as_string() const; std::string decode_string() const; + + inline int size() const { return bits.size(); } }; struct RTLIL::Selection -- cgit v1.2.3 From 83ec3fa2045cac1f29ea4bfb2c8c052c31b083a1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 31 Aug 2014 18:08:26 +0200 Subject: Fixed return size of const_*() eval functions --- kernel/calc.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/calc.cc b/kernel/calc.cc index 29717aad5..7bfdb8955 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -35,6 +35,8 @@ static void extend(RTLIL::Const &arg, int width, bool is_signed) while (int(arg.bits.size()) < width) arg.bits.push_back(padding); + + arg.bits.resize(width); } static void extend_u0(RTLIL::Const &arg, int width, bool is_signed) @@ -46,6 +48,8 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed) while (int(arg.bits.size()) < width) arg.bits.push_back(padding); + + arg.bits.resize(width); } static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos) @@ -312,7 +316,7 @@ RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2 RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; - extend_u0(arg1_ext, result_len, signed1); + extend_u0(arg1_ext, std::max(result_len, SIZE(arg1)), signed1); return const_shift_worker(arg1_ext, arg2, false, +1, result_len); } -- cgit v1.2.3 From e07698818dfe3c8e5f87b13090c7e70d22189e2a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 11:36:02 +0200 Subject: Using std::vector instead of RTLIL::Const for RTLIL::SigChunk::data --- kernel/rtlil.cc | 62 +++++++++++++++++++++++++++------------------------------ kernel/rtlil.h | 6 +++--- 2 files changed, 32 insertions(+), 36 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 403bb6d28..f237f57ef 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1819,8 +1819,8 @@ RTLIL::SigChunk::SigChunk() RTLIL::SigChunk::SigChunk(const RTLIL::Const &value) { wire = NULL; - data = value; - width = data.bits.size(); + data = value.bits; + width = SIZE(data); offset = 0; } @@ -1843,24 +1843,24 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width) RTLIL::SigChunk::SigChunk(const std::string &str) { wire = NULL; - data = RTLIL::Const(str); - width = data.bits.size(); + data = RTLIL::Const(str).bits; + width = SIZE(data); offset = 0; } RTLIL::SigChunk::SigChunk(int val, int width) { wire = NULL; - data = RTLIL::Const(val, width); - this->width = data.bits.size(); + data = RTLIL::Const(val, width).bits; + this->width = SIZE(data); offset = 0; } RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width) { wire = NULL; - data = RTLIL::Const(bit, width); - this->width = data.bits.size(); + data = RTLIL::Const(bit, width).bits; + this->width = SIZE(data); offset = 0; } @@ -1869,7 +1869,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit) wire = bit.wire; offset = 0; if (wire == NULL) - data = RTLIL::Const(bit.data); + data = RTLIL::Const(bit.data).bits; else offset = bit.offset; width = 1; @@ -1884,7 +1884,7 @@ RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const ret.width = length; } else { for (int i = 0; i < length; i++) - ret.data.bits.push_back(data.bits[offset+i]); + ret.data.push_back(data[offset+i]); ret.width = length; } return ret; @@ -1905,16 +1905,12 @@ bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const if (width != other.width) return width < other.width; - return data.bits < other.data.bits; + return data < other.data; } bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const { - if (wire != other.wire || width != other.width || offset != other.offset) - return false; - if (data.bits != other.data.bits) - return false; - return true; + return wire == other.wire && width == other.width && offset == other.offset && data == other.data; } bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const @@ -1964,7 +1960,7 @@ const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other) for (auto &bit : other.bits_) { if (last && bit.wire == last->wire) { if (bit.wire == NULL) { - last->data.bits.push_back(bit.data); + last->data.push_back(bit.data); last->width++; continue; } else if (last_end_offset == bit.offset) { @@ -2120,7 +2116,7 @@ void RTLIL::SigSpec::pack() const for (auto &bit : old_bits) { if (last && bit.wire == last->wire) { if (bit.wire == NULL) { - last->data.bits.push_back(bit.data); + last->data.push_back(bit.data); last->width++; continue; } else if (last_end_offset == bit.offset) { @@ -2171,7 +2167,7 @@ void RTLIL::SigSpec::hash() const that->hash_ = 5381; for (auto &c : that->chunks_) if (c.wire == NULL) { - for (auto &v : c.data.bits) + for (auto &v : c.data) DJB2(that->hash_, v); } else { DJB2(that->hash_, c.wire->name.index_); @@ -2444,8 +2440,8 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) { auto &my_last_c = chunks_.back(); if (my_last_c.wire == NULL && other_c.wire == NULL) { - auto &this_data = my_last_c.data.bits; - auto &other_data = other_c.data.bits; + auto &this_data = my_last_c.data; + auto &other_data = other_c.data; this_data.insert(this_data.end(), other_data.begin(), other_data.end()); my_last_c.width += other_c.width; } else @@ -2472,7 +2468,7 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) else if (bit.wire == NULL) if (chunks_.back().wire == NULL) { - chunks_.back().data.bits.push_back(bit.data); + chunks_.back().data.push_back(bit.data); chunks_.back().width++; } else chunks_.push_back(bit); @@ -2558,14 +2554,14 @@ void RTLIL::SigSpec::check() const if (i > 0) log_assert(chunks_[i-1].wire != NULL); log_assert(chunk.offset == 0); - log_assert(chunk.data.bits.size() == (size_t)chunk.width); + log_assert(chunk.data.size() == (size_t)chunk.width); } else { if (i > 0 && chunks_[i-1].wire == chunk.wire) log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width); log_assert(chunk.offset >= 0); log_assert(chunk.width >= 0); log_assert(chunk.offset + chunk.width <= chunk.wire->width); - log_assert(chunk.data.bits.size() == 0); + log_assert(chunk.data.size() == 0); } w += chunk.width; } @@ -2681,8 +2677,8 @@ bool RTLIL::SigSpec::is_fully_def() const for (auto it = chunks_.begin(); it != chunks_.end(); it++) { if (it->width > 0 && it->wire != NULL) return false; - for (size_t i = 0; i < it->data.bits.size(); i++) - if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1) + for (size_t i = 0; i < it->data.size(); i++) + if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1) return false; } return true; @@ -2696,8 +2692,8 @@ bool RTLIL::SigSpec::is_fully_undef() const for (auto it = chunks_.begin(); it != chunks_.end(); it++) { if (it->width > 0 && it->wire != NULL) return false; - for (size_t i = 0; i < it->data.bits.size(); i++) - if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz) + for (size_t i = 0; i < it->data.size(); i++) + if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz) return false; } return true; @@ -2710,8 +2706,8 @@ bool RTLIL::SigSpec::has_marked_bits() const pack(); for (auto it = chunks_.begin(); it != chunks_.end(); it++) if (it->width > 0 && it->wire == NULL) { - for (size_t i = 0; i < it->data.bits.size(); i++) - if (it->data.bits[i] == RTLIL::State::Sm) + for (size_t i = 0; i < it->data.size(); i++) + if (it->data[i] == RTLIL::State::Sm) return true; } return false; @@ -2724,7 +2720,7 @@ bool RTLIL::SigSpec::as_bool() const pack(); log_assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) - return chunks_[0].data.as_bool(); + return RTLIL::Const(chunks_[0].data).as_bool(); return false; } @@ -2735,7 +2731,7 @@ int RTLIL::SigSpec::as_int(bool is_signed) const pack(); log_assert(is_fully_const() && SIZE(chunks_) <= 1); if (width_) - return chunks_[0].data.as_int(is_signed); + return RTLIL::Const(chunks_[0].data).as_int(is_signed); return 0; } @@ -2751,7 +2747,7 @@ std::string RTLIL::SigSpec::as_string() const for (int j = 0; j < chunk.width; j++) str += "?"; else - str += chunk.data.as_string(); + str += RTLIL::Const(chunk.data).as_string(); } return str; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 935329384..b8733c4ec 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -864,7 +864,7 @@ public: struct RTLIL::SigChunk { RTLIL::Wire *wire; - RTLIL::Const data; // only used if wire == NULL, LSB at index 0 + std::vector data; // only used if wire == NULL, LSB at index 0 int width, offset; SigChunk(); @@ -895,8 +895,8 @@ struct RTLIL::SigBit SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); } - SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; } - SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; } + SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } + SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; } SigBit(const RTLIL::SigSpec &sig); bool operator <(const RTLIL::SigBit &other) const { -- cgit v1.2.3 From bae09dca2ba4d582bf7258b6419d4268f65f1476 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 16:35:25 +0200 Subject: Added SAT model for $alu cells --- kernel/satgen.h | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 69 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index 5d1c11c9e..beb037686 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -183,9 +183,9 @@ struct SatGen bool importCell(RTLIL::Cell *cell, int timestep = -1) { bool arith_undef_handled = false; - bool is_arith_compare = cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt"; + bool is_arith_compare = cell->type.in("$lt", "$le", "$ge", "$gt"); - if (model_undef && (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || is_arith_compare)) + if (model_undef && (cell->type.in("$add", "$sub", "$mul", "$div", "$mod") || is_arith_compare)) { std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); @@ -891,6 +891,73 @@ struct SatGen return true; } + if (cell->type == "$alu") + { + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector x = importDefSigSpec(cell->getPort("\\X"), timestep); + std::vector ci = importDefSigSpec(cell->getPort("\\CI"), timestep); + std::vector bi = importDefSigSpec(cell->getPort("\\BI"), timestep); + std::vector co = importDefSigSpec(cell->getPort("\\CO"), timestep); + + extendSignalWidth(a, b, y, cell); + extendSignalWidth(a, b, x, cell); + extendSignalWidth(a, b, co, cell); + + std::vector def_y = model_undef ? ez->vec_var(y.size()) : y; + std::vector def_x = model_undef ? ez->vec_var(x.size()) : x; + std::vector def_co = model_undef ? ez->vec_var(co.size()) : co; + + log_assert(SIZE(y) == SIZE(x)); + log_assert(SIZE(y) == SIZE(co)); + log_assert(SIZE(ci) == 1); + log_assert(SIZE(bi) == 1); + + for (int i = 0; i < SIZE(y); i++) + { + int s1 = a.at(i), s2 = ez->XOR(b.at(i), bi.at(0)), s3 = i ? co.at(i-1) : ci.at(0); + ez->SET(def_x.at(i), ez->XOR(s1, s2)); + ez->SET(def_y.at(i), ez->XOR(def_x.at(i), s3)); + ez->SET(def_co.at(i), ez->OR(ez->AND(s1, s2), ez->AND(s1, s3), ez->AND(s2, s3))); + } + + if (model_undef) + { + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_ci = importUndefSigSpec(cell->getPort("\\CI"), timestep); + std::vector undef_bi = importUndefSigSpec(cell->getPort("\\BI"), timestep); + + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep); + std::vector undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep); + + extendSignalWidth(undef_a, undef_b, undef_y, cell, true); + extendSignalWidth(undef_a, undef_b, undef_x, cell, true); + extendSignalWidth(undef_a, undef_b, undef_co, cell, true); + + std::vector all_inputs_undef; + all_inputs_undef.insert(all_inputs_undef.end(), undef_a.begin(), undef_a.end()); + all_inputs_undef.insert(all_inputs_undef.end(), undef_b.begin(), undef_b.end()); + all_inputs_undef.insert(all_inputs_undef.end(), undef_ci.begin(), undef_ci.end()); + all_inputs_undef.insert(all_inputs_undef.end(), undef_bi.begin(), undef_bi.end()); + int undef_any = ez->expression(ezSAT::OpOr, all_inputs_undef); + + for (int i = 0; i < SIZE(undef_y); i++) { + ez->SET(undef_y.at(i), undef_any); + ez->SET(undef_x.at(i), ez->OR(undef_a.at(i), undef_b.at(i), undef_bi.at(0))); + ez->SET(undef_co.at(i), undef_any); + } + + undefGating(y, def_y, undef_y); + undefGating(x, def_x, undef_x); + undefGating(co, def_co, undef_co); + } + log_ping(); + return true; + } + if (cell->type == "$slice") { RTLIL::SigSpec a = cell->getPort("\\A"); -- cgit v1.2.3 From 2fcf66b91d324758eb58807592702b6844bd37ab Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 16:35:46 +0200 Subject: Added ConstEval model for $alu cells --- kernel/consteval.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index d42c2b0f1..fb54b72f6 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -154,6 +154,62 @@ struct ConstEval else set(sig_y, y_values.front()); } + else if (cell->type == "$alu") + { + bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); + bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool(); + + RTLIL::SigSpec sig_ci = cell->getPort("\\CI"); + RTLIL::SigSpec sig_bi = cell->getPort("\\BI"); + + if (!eval(sig_a, undef, cell)) + return false; + + if (!eval(sig_b, undef, cell)) + return false; + + if (!eval(sig_ci, undef, cell)) + return false; + + if (!eval(sig_bi, undef, cell)) + return false; + + RTLIL::SigSpec sig_x = cell->getPort("\\X"); + RTLIL::SigSpec sig_co = cell->getPort("\\CO"); + + bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def()); + sig_a.extend(SIZE(sig_y), signed_a); + sig_b.extend(SIZE(sig_y), signed_b); + + bool carry = sig_ci[0] == RTLIL::S1; + bool b_inv = sig_bi[0] == RTLIL::S1; + + for (int i = 0; i < SIZE(sig_y); i++) + { + RTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] }; + + if (!x_inputs.is_fully_def()) { + set(sig_x[i], RTLIL::Sx); + } else { + bool bit_a = sig_a[i] == RTLIL::S1; + bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv; + bool bit_x = bit_a != bit_b; + set(sig_x[i], bit_x ? RTLIL::S1 : RTLIL::S0); + } + + if (any_input_undef) { + set(sig_y[i], RTLIL::Sx); + set(sig_co[i], RTLIL::Sx); + } else { + bool bit_a = sig_a[i] == RTLIL::S1; + bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv; + bool bit_y = (bit_a != bit_b) != carry; + carry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry); + set(sig_y[i], bit_y ? RTLIL::S1 : RTLIL::S0); + set(sig_co[i], carry ? RTLIL::S1 : RTLIL::S0); + } + } + } else { RTLIL::SigSpec sig_c, sig_d; -- cgit v1.2.3 From c38283dbd033ba95554600bbaa850de707ab2a78 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 17:48:41 +0200 Subject: Small bug fixes in $not, $neg, and $shiftx models --- kernel/calc.cc | 5 ++--- kernel/satgen.h | 7 ++++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/calc.cc b/kernel/calc.cc index 7bfdb8955..4048e4a1f 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -591,10 +591,9 @@ RTLIL::Const RTLIL::const_bu0(const RTLIL::Const &arg1, const RTLIL::Const&, boo RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; - extend(arg1_ext, result_len, signed1); - RTLIL::Const zero(RTLIL::State::S0, 1); - return RTLIL::const_sub(zero, arg1_ext, false, signed1, result_len); + + return RTLIL::const_sub(zero, arg1_ext, true, signed1, result_len); } YOSYS_NAMESPACE_END diff --git a/kernel/satgen.h b/kernel/satgen.h index beb037686..3685cd6e6 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -357,7 +357,7 @@ struct SatGen if (model_undef) { std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); - extendSignalWidthUnary(undef_a, undef_y, cell, true); + extendSignalWidthUnary(undef_a, undef_y, cell, false); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); } @@ -671,7 +671,7 @@ struct SatGen int extend_bit = ez->FALSE; - if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool()) + if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool()) extend_bit = a.back(); while (y.size() < a.size()) @@ -703,7 +703,8 @@ struct SatGen std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); std::vector undef_a_shifted; - if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool()) + extend_bit = cell->type == "$shiftx" ? ez->TRUE : ez->FALSE; + if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool()) extend_bit = undef_a.back(); while (undef_y.size() < undef_a.size()) -- cgit v1.2.3 From da360771a193707b59eac9b95b3bfe1652a057aa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 22:49:24 +0200 Subject: Create a default selection stack in RTLIL::Design::Design() --- kernel/rtlil.cc | 1 + kernel/yosys.cc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f237f57ef..35cd54b46 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -228,6 +228,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) RTLIL::Design::Design() { refcount_modules_ = 0; + selection_stack.push_back(RTLIL::Selection()); } RTLIL::Design::~Design() diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7b8173b6a..0ecb4cdaf 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -74,9 +74,7 @@ int SIZE(RTLIL::Wire *wire) void yosys_setup() { Pass::init_register(); - yosys_design = new RTLIL::Design; - yosys_design->selection_stack.push_back(RTLIL::Selection()); log_push(); } -- cgit v1.2.3 From 50ac2848239cf5969b80c427a95b6098fd1e2f1c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Sep 2014 13:39:46 +0200 Subject: Fixes in $alu SAT- and eval-models --- kernel/consteval.h | 4 ++-- kernel/satgen.h | 7 +++---- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index fb54b72f6..c73a0b351 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -178,8 +178,8 @@ struct ConstEval RTLIL::SigSpec sig_co = cell->getPort("\\CO"); bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def()); - sig_a.extend(SIZE(sig_y), signed_a); - sig_b.extend(SIZE(sig_y), signed_b); + sig_a.extend_u0(SIZE(sig_y), signed_a); + sig_b.extend_u0(SIZE(sig_y), signed_b); bool carry = sig_ci[0] == RTLIL::S1; bool b_inv = sig_bi[0] == RTLIL::S1; diff --git a/kernel/satgen.h b/kernel/satgen.h index 3685cd6e6..c7f1680d4 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -934,9 +934,9 @@ struct SatGen std::vector undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep); std::vector undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep); - extendSignalWidth(undef_a, undef_b, undef_y, cell, true); - extendSignalWidth(undef_a, undef_b, undef_x, cell, true); - extendSignalWidth(undef_a, undef_b, undef_co, cell, true); + extendSignalWidth(undef_a, undef_b, undef_y, cell); + extendSignalWidth(undef_a, undef_b, undef_x, cell); + extendSignalWidth(undef_a, undef_b, undef_co, cell); std::vector all_inputs_undef; all_inputs_undef.insert(all_inputs_undef.end(), undef_a.begin(), undef_a.end()); @@ -955,7 +955,6 @@ struct SatGen undefGating(x, def_x, undef_x); undefGating(co, def_co, undef_co); } - log_ping(); return true; } -- cgit v1.2.3 From b9cb483f3e2a498ee75a422e09164a920918362b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Sep 2014 21:20:59 +0200 Subject: Using $pos models for $bu0 --- kernel/calc.cc | 2 +- kernel/satgen.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/calc.cc b/kernel/calc.cc index 4048e4a1f..da03f6164 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -575,7 +575,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2 RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; - extend(arg1_ext, result_len, signed1); + extend_u0(arg1_ext, result_len, signed1); return arg1_ext; } diff --git a/kernel/satgen.h b/kernel/satgen.h index c7f1680d4..eed3adaad 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -470,7 +470,7 @@ struct SatGen { std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); - extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0"); + extendSignalWidthUnary(undef_a, undef_y, cell); if (cell->type == "$pos" || cell->type == "$bu0") { ez->assume(ez->vec_eq(undef_a, undef_y)); -- cgit v1.2.3 From 8927aa6148f5575b2da9bfb76afb4af076fe18f3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 4 Sep 2014 02:07:52 +0200 Subject: Removed $bu0 cell type --- kernel/calc.cc | 21 --------------------- kernel/celltypes.h | 5 ++--- kernel/rtlil.cc | 3 +-- kernel/rtlil.h | 2 -- kernel/satgen.h | 6 +++--- 5 files changed, 6 insertions(+), 31 deletions(-) (limited to 'kernel') diff --git a/kernel/calc.cc b/kernel/calc.cc index da03f6164..41179d045 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -26,19 +26,6 @@ YOSYS_NAMESPACE_BEGIN -static void extend(RTLIL::Const &arg, int width, bool is_signed) -{ - RTLIL::State padding = RTLIL::State::S0; - - if (arg.bits.size() > 0 && (is_signed || arg.bits.back() > RTLIL::State::S1)) - padding = arg.bits.back(); - - while (int(arg.bits.size()) < width) - arg.bits.push_back(padding); - - arg.bits.resize(width); -} - static void extend_u0(RTLIL::Const &arg, int width, bool is_signed) { RTLIL::State padding = RTLIL::State::S0; @@ -580,14 +567,6 @@ RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, boo return arg1_ext; } -RTLIL::Const RTLIL::const_bu0(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) -{ - RTLIL::Const arg1_ext = arg1; - extend_u0(arg1_ext, result_len, signed1); - - return arg1_ext; -} - RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 4a8be04d3..a8d88603e 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -86,7 +86,7 @@ struct CellTypes void setup_internals() { std::vector unary_ops = { - "$not", "$pos", "$bu0", "$neg", + "$not", "$pos", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", "$logic_not", "$slice", "$lut" }; @@ -219,7 +219,7 @@ struct CellTypes type = "$shl"; if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && type != "$shift" && type != "$shiftx" && - type != "$pos" && type != "$neg" && type != "$not" && type != "$bu0") { + type != "$pos" && type != "$neg" && type != "$not") { if (!signed1 || !signed2) signed1 = false, signed2 = false; } @@ -259,7 +259,6 @@ struct CellTypes HANDLE_CELL_TYPE(mod) HANDLE_CELL_TYPE(pow) HANDLE_CELL_TYPE(pos) - HANDLE_CELL_TYPE(bu0) HANDLE_CELL_TYPE(neg) #undef HANDLE_CELL_TYPE diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 35cd54b46..08c79beae 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -563,7 +563,7 @@ namespace { cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") return; - if (cell->type.in("$not", "$pos", "$bu0", "$neg")) { + if (cell->type.in("$not", "$pos", "$neg")) { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); port("\\Y", param("\\Y_WIDTH")); @@ -1326,7 +1326,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth } DEF_METHOD(Not, sig_a.size(), "$not") DEF_METHOD(Pos, sig_a.size(), "$pos") -DEF_METHOD(Bu0, sig_a.size(), "$bu0") DEF_METHOD(Neg, sig_a.size(), "$neg") DEF_METHOD(ReduceAnd, 1, "$reduce_and") DEF_METHOD(ReduceOr, 1, "$reduce_or") diff --git a/kernel/rtlil.h b/kernel/rtlil.h index b8733c4ec..c48837691 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -314,7 +314,6 @@ namespace RTLIL RTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); - RTLIL::Const const_bu0 (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); @@ -651,7 +650,6 @@ public: RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); - RTLIL::Cell* addBu0 (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false); RTLIL::Cell* addAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false); diff --git a/kernel/satgen.h b/kernel/satgen.h index eed3adaad..ae155a2eb 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -451,7 +451,7 @@ struct SatGen return true; } - if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") + if (cell->type == "$pos" || cell->type == "$neg") { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); @@ -459,7 +459,7 @@ struct SatGen std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == "$pos" || cell->type == "$bu0") { + if (cell->type == "$pos") { ez->assume(ez->vec_eq(a, yy)); } else { std::vector zero(a.size(), ez->FALSE); @@ -472,7 +472,7 @@ struct SatGen std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); extendSignalWidthUnary(undef_a, undef_y, cell); - if (cell->type == "$pos" || cell->type == "$bu0") { + if (cell->type == "$pos") { ez->assume(ez->vec_eq(undef_a, undef_y)); } else { int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); -- cgit v1.2.3 From 79cbf9067c07ed810b3466174278d77b9a05b46d Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Sat, 6 Sep 2014 08:47:06 +0200 Subject: Corrected spelling mistakes found by lintian --- kernel/register.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index a53bd84c7..2f7b89ffd 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -132,7 +132,7 @@ void Pass::extra_args(std::vector args, size_t argidx, RTLIL::Desig std::string arg = args[argidx]; if (arg.substr(0, 1) == "-") - cmd_error(args, argidx, "Unkown option or option in arguments."); + cmd_error(args, argidx, "Unknown option or option in arguments."); if (!select) cmd_error(args, argidx, "Extra argument."); @@ -309,7 +309,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector Date: Sat, 6 Sep 2014 15:47:46 +0200 Subject: Added $macc cell type --- kernel/celltypes.h | 11 ++-- kernel/macc.h | 171 +++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/rtlil.cc | 14 ++++- 3 files changed, 189 insertions(+), 7 deletions(-) create mode 100644 kernel/macc.h (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index a8d88603e..74e9f1fd5 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -20,12 +20,9 @@ #ifndef CELLTYPES_H #define CELLTYPES_H -#include -#include -#include +#include -#include -#include +YOSYS_NAMESPACE_BEGIN struct CellType { @@ -96,7 +93,7 @@ struct CellTypes "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", "$add", "$sub", "$mul", "$div", "$mod", "$pow", - "$logic_and", "$logic_or", "$concat" + "$logic_and", "$logic_or", "$concat", "$macc" }; for (auto type : unary_ops) @@ -361,5 +358,7 @@ struct CellTypes } }; +YOSYS_NAMESPACE_END + #endif diff --git a/kernel/macc.h b/kernel/macc.h new file mode 100644 index 000000000..362acab29 --- /dev/null +++ b/kernel/macc.h @@ -0,0 +1,171 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef MACC_H +#define MACC_H + +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +struct Macc +{ + struct port_t { + RTLIL::SigSpec in_a, in_b; + bool is_signed, do_subtract; + }; + + std::vector ports; + RTLIL::SigSpec bit_ports; + + void from_cell(RTLIL::Cell *cell) + { + RTLIL::SigSpec port_a = cell->getPort("\\A"); + + ports.clear(); + bit_ports = cell->getPort("\\B"); + + std::vector config_bits = cell->getParam("\\CONFIG").bits; + int config_width = cell->getParam("\\CONFIG_WIDTH").as_int(); + int config_cursor = 0; + + log_assert(SIZE(config_bits) >= config_width); + + int num_bits = 0; + if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 1; + if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 2; + if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 4; + if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 8; + + int port_a_cursor = 0; + while (port_a_cursor < SIZE(port_a)) + { + log_assert(config_cursor + 2 + 2*num_bits <= config_width); + + port_t this_port; + this_port.is_signed = config_bits[config_cursor++] == RTLIL::S1; + this_port.do_subtract = config_bits[config_cursor++] == RTLIL::S1; + + int size_a = 0; + for (int i = 0; i < num_bits; i++) + if (config_bits[config_cursor++] == RTLIL::S1) + size_a |= 1 << i; + + this_port.in_a = port_a.extract(port_a_cursor, size_a); + port_a_cursor += size_a; + + int size_b = 0; + for (int i = 0; i < num_bits; i++) + if (config_bits[config_cursor++] == RTLIL::S1) + size_b |= 1 << i; + + this_port.in_b = port_a.extract(port_a_cursor, size_b); + port_a_cursor += size_b; + + if (size_a || size_b) + ports.push_back(this_port); + } + + log_assert(config_cursor == config_width); + log_assert(port_a_cursor == SIZE(port_a)); + } + + void to_cell(RTLIL::Cell *cell) const + { + RTLIL::SigSpec port_a; + std::vector config_bits; + int max_size = 0, num_bits = 0; + + for (auto &port : ports) { + max_size = std::max(max_size, SIZE(port.in_a)); + max_size = std::max(max_size, SIZE(port.in_b)); + } + + while (max_size) + num_bits++, max_size /= 2; + + log_assert(num_bits < 16); + config_bits.push_back(num_bits & 1 ? RTLIL::S1 : RTLIL::S0); + config_bits.push_back(num_bits & 2 ? RTLIL::S1 : RTLIL::S0); + config_bits.push_back(num_bits & 4 ? RTLIL::S1 : RTLIL::S0); + config_bits.push_back(num_bits & 8 ? RTLIL::S1 : RTLIL::S0); + + for (auto &port : ports) + { + if (SIZE(port.in_a) == 0) + continue; + + config_bits.push_back(port.is_signed ? RTLIL::S1 : RTLIL::S0); + config_bits.push_back(port.do_subtract ? RTLIL::S1 : RTLIL::S0); + + int size_a = SIZE(port.in_a); + for (int i = 0; i < num_bits; i++) + config_bits.push_back(size_a & (1 << i) ? RTLIL::S1 : RTLIL::S0); + + int size_b = SIZE(port.in_b); + for (int i = 0; i < num_bits; i++) + config_bits.push_back(size_b & (1 << i) ? RTLIL::S1 : RTLIL::S0); + + port_a.append(port.in_a); + port_a.append(port.in_b); + } + + cell->setPort("\\A", port_a); + cell->setPort("\\B", bit_ports); + cell->setParam("\\CONFIG", config_bits); + cell->setParam("\\CONFIG_WIDTH", SIZE(config_bits)); + cell->setParam("\\A_WIDTH", SIZE(port_a)); + cell->setParam("\\B_WIDTH", SIZE(bit_ports)); + } + + bool eval(RTLIL::Const &result) const + { + for (auto &bit : result.bits) + bit = RTLIL::S0; + + for (auto &port : ports) + { + if (!port.in_a.is_fully_const() || !port.in_b.is_fully_const()) + return false; + + RTLIL::Const summand; + if (SIZE(port.in_b) == 0) + summand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, SIZE(result)); + else + summand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, SIZE(result)); + + if (port.do_subtract) + result = const_sub(result, summand, port.is_signed, port.is_signed, SIZE(result)); + else + result = const_add(result, summand, port.is_signed, port.is_signed, SIZE(result)); + } + + for (auto bit : bit_ports) { + if (bit.wire) + return false; + result = const_add(result, bit.data, false, false, SIZE(result)); + } + + return true; + } +}; + +YOSYS_NAMESPACE_END + +#endif diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 08c79beae..97a2946a6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/macc.h" #include "frontends/verilog/verilog_frontend.h" #include "backends/ilang/ilang_backend.h" @@ -633,6 +634,17 @@ namespace { return; } + if (cell->type == "$macc") { + param("\\CONFIG"); + param("\\CONFIG_WIDTH"); + port("\\A", param("\\A_WIDTH")); + port("\\B", param("\\B_WIDTH")); + port("\\Y", param("\\Y_WIDTH")); + check_expected(); + Macc().from_cell(cell); + return; + } + if (cell->type == "$logic_not") { param_bool("\\A_SIGNED"); port("\\A", param("\\A_WIDTH")); @@ -1781,7 +1793,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } - bool signedness_ab = !type.in("$slice", "$concat"); + bool signedness_ab = !type.in("$slice", "$concat", "$macc"); if (connections_.count("\\A")) { if (signedness_ab) { -- cgit v1.2.3 From fa64942018a39085301d7f24832ad0ad7b0d22f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 6 Sep 2014 19:44:11 +0200 Subject: Added $macc SAT model --- kernel/satgen.h | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index ae155a2eb..3429f8239 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -23,6 +23,7 @@ #include "kernel/rtlil.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" +#include "kernel/macc.h" #include "libs/ezsat/ezminisat.h" typedef ezMiniSAT ezDefaultSAT; @@ -762,6 +763,76 @@ struct SatGen return true; } + if (cell->type == "$macc") + { + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + + Macc macc; + macc.from_cell(cell); + + std::vector tmp(SIZE(y), ez->FALSE); + + for (auto &port : macc.ports) + { + std::vector in_a = importDefSigSpec(port.in_a, timestep); + std::vector in_b = importDefSigSpec(port.in_b, timestep); + + while (SIZE(in_a) < SIZE(y)) + in_a.push_back(port.is_signed && !in_a.empty() ? in_a.back() : ez->FALSE); + in_a.resize(SIZE(y)); + + if (SIZE(in_b)) + { + while (SIZE(in_b) < SIZE(y)) + in_b.push_back(port.is_signed && !in_b.empty() ? in_b.back() : ez->FALSE); + in_b.resize(SIZE(y)); + + for (int i = 0; i < SIZE(in_b); i++) { + std::vector shifted_a(in_a.size(), ez->FALSE); + for (int j = i; j < int(in_a.size()); j++) + shifted_a.at(j) = in_a.at(j-i); + if (port.do_subtract) + tmp = ez->vec_ite(in_b.at(i), ez->vec_sub(tmp, shifted_a), tmp); + else + tmp = ez->vec_ite(in_b.at(i), ez->vec_add(tmp, shifted_a), tmp); + } + } + else + { + if (port.do_subtract) + tmp = ez->vec_sub(tmp, in_a); + else + tmp = ez->vec_add(tmp, in_a); + } + } + + for (int i = 0; i < SIZE(b); i++) { + std::vector val(SIZE(y), ez->FALSE); + val.at(0) = b.at(i); + tmp = ez->vec_add(tmp, val); + } + + if (model_undef) + { + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + + int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); + int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); + + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + ez->assume(ez->vec_eq(undef_y, std::vector(SIZE(y), ez->OR(undef_any_a, undef_any_b)))); + + undefGating(y, tmp, undef_y); + } + else + ez->assume(ez->vec_eq(y, tmp)); + + return true; + } + if (cell->type == "$div" || cell->type == "$mod") { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); -- cgit v1.2.3 From 98e6463ca78d8c0a342c9b86d9223dbeb45c093c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 6 Sep 2014 19:44:28 +0200 Subject: Added $macc eval model --- kernel/consteval.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index c73a0b351..f995c9cc2 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -23,6 +23,7 @@ #include "kernel/rtlil.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" +#include "kernel/macc.h" struct ConstEval { @@ -210,6 +211,27 @@ struct ConstEval } } } + else if (cell->type == "$macc") + { + Macc macc; + macc.from_cell(cell); + + if (!eval(macc.bit_ports, undef, cell)) + return false; + + for (auto &port : macc.ports) { + if (!eval(port.in_a, undef, cell)) + return false; + if (!eval(port.in_b, undef, cell)) + return false; + } + + RTLIL::Const result(0, SIZE(cell->getPort("\\Y"))); + if (!macc.eval(result)) + log_abort(); + + set(cell->getPort("\\Y"), result); + } else { RTLIL::SigSpec sig_c, sig_d; -- cgit v1.2.3 From d46bac330520f91ee5bf8027abe98a8f9389f696 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Sep 2014 12:15:39 +0200 Subject: Added "$fa" cell type --- kernel/celltypes.h | 1 + kernel/consteval.h | 25 +++++++++++++++++++++++++ kernel/rtlil.cc | 15 +++++++++++++++ kernel/satgen.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 90 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 74e9f1fd5..b42cf4e9a 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -106,6 +106,7 @@ struct CellTypes setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, true); setup_type("$alu", {"\\A", "\\B", "\\CI", "\\BI"}, {"\\X", "\\Y", "\\CO"}, true); + setup_type("$fa", {"\\A", "\\B", "\\C"}, {"\\X", "\\Y"}, true); setup_type("$assert", {"\\A", "\\EN"}, std::set(), true); } diff --git a/kernel/consteval.h b/kernel/consteval.h index f995c9cc2..7423f950f 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -155,6 +155,31 @@ struct ConstEval else set(sig_y, y_values.front()); } + else if (cell->type == "$fa") + { + RTLIL::SigSpec sig_c = cell->getPort("\\C"); + RTLIL::SigSpec sig_x = cell->getPort("\\X"); + int width = SIZE(sig_c); + + if (!eval(sig_a, undef, cell)) + return false; + + if (!eval(sig_b, undef, cell)) + return false; + + if (!eval(sig_c, undef, cell)) + return false; + + RTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width); + RTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width); + + RTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width); + RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width); + RTLIL::Const val_x = const_or(t2, t3, false, false, width); + + set(sig_y, val_y); + set(sig_x, val_x); + } else if (cell->type == "$alu") { bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 97a2946a6..b5cede8b2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -620,6 +620,16 @@ namespace { return; } + if (cell->type == "$fa") { + port("\\A", param("\\WIDTH")); + port("\\B", param("\\WIDTH")); + port("\\C", param("\\WIDTH")); + port("\\X", param("\\WIDTH")); + port("\\Y", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$alu") { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); @@ -1793,6 +1803,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } + if (type == "$fa") { + parameters["\\WIDTH"] = SIZE(connections_["\\Y"]); + return; + } + bool signedness_ab = !type.in("$slice", "$concat", "$macc"); if (connections_.count("\\A")) { diff --git a/kernel/satgen.h b/kernel/satgen.h index 3429f8239..4aabe4378 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -963,6 +963,55 @@ struct SatGen return true; } + if (cell->type == "$fa") + { + std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); + std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector c = importDefSigSpec(cell->getPort("\\C"), timestep); + std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector x = importDefSigSpec(cell->getPort("\\X"), timestep); + + std::vector yy = model_undef ? ez->vec_var(y.size()) : y; + std::vector xx = model_undef ? ez->vec_var(x.size()) : x; + + std::vector t1 = ez->vec_xor(a, b); + ez->assume(ez->vec_eq(yy, ez->vec_xor(t1, c))); + + std::vector t2 = ez->vec_and(a, b); + std::vector t3 = ez->vec_and(c, t1); + ez->assume(ez->vec_eq(xx, ez->vec_or(t2, t3))); + + if (model_undef) + { + std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_c = importUndefSigSpec(cell->getPort("\\C"), timestep); + + std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep); + + ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); + + std::vector undef_t1 = ez->vec_or(undef_a, undef_b); + + std::vector a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)); + std::vector b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b)); + std::vector undef_t2 = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0))); + + std::vector c0 = ez->vec_and(ez->vec_not(c), ez->vec_not(undef_c)); + std::vector t10 = ez->vec_and(ez->vec_not(t1), ez->vec_not(undef_t1)); + std::vector undef_t3 = ez->vec_and(ez->vec_or(undef_c, undef_t1), ez->vec_not(ez->vec_or(c0, t10))); + + std::vector t21 = ez->vec_and(t2, ez->vec_not(undef_t2)); + std::vector t31 = ez->vec_and(t3, ez->vec_not(undef_t3)); + ez->assume(ez->vec_eq(undef_x, ez->vec_and(ez->vec_or(undef_t2, undef_t3), ez->vec_not(ez->vec_or(t21, t31))))); + + undefGating(y, yy, undef_y); + undefGating(x, xx, undef_x); + } + return true; + } + if (cell->type == "$alu") { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); -- cgit v1.2.3 From af0c8873bbc13eea10b3d705061b4cf68fe27c17 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Sep 2014 13:28:23 +0200 Subject: Added $lcu cell type --- kernel/celltypes.h | 1 + kernel/consteval.h | 37 +++++++++++++++++++++++++++++++++++++ kernel/rtlil.cc | 14 ++++++++++++++ kernel/satgen.h | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index b42cf4e9a..85c21ef3c 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -105,6 +105,7 @@ struct CellTypes for (auto type : std::vector({"$mux", "$pmux"})) setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, true); + setup_type("$lcu", {"\\P", "\\G", "\\CI"}, {"\\CO"}, true); setup_type("$alu", {"\\A", "\\B", "\\CI", "\\BI"}, {"\\X", "\\Y", "\\CO"}, true); setup_type("$fa", {"\\A", "\\B", "\\C"}, {"\\X", "\\Y"}, true); diff --git a/kernel/consteval.h b/kernel/consteval.h index 7423f950f..6e507bd51 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -86,6 +86,43 @@ struct ConstEval bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef) { + if (cell->type == "$lcu") + { + RTLIL::SigSpec sig_p = cell->getPort("\\P"); + RTLIL::SigSpec sig_g = cell->getPort("\\G"); + RTLIL::SigSpec sig_ci = cell->getPort("\\CI"); + RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort("\\CO"))); + + if (sig_co.is_fully_const()) + return true; + + if (!eval(sig_p, undef, cell)) + return false; + + if (!eval(sig_g, undef, cell)) + return false; + + if (!eval(sig_ci, undef, cell)) + return false; + + if (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def()) + { + RTLIL::Const coval(RTLIL::Sx, SIZE(sig_co)); + bool carry = sig_ci.as_bool(); + + for (int i = 0; i < SIZE(coval); i++) { + carry = (sig_g[i] == RTLIL::S1) || (sig_p[i] == RTLIL::S1 && carry); + coval.bits[i] = carry ? RTLIL::S1 : RTLIL::S0; + } + + set(sig_co, coval); + } + else + set(sig_co, RTLIL::Const(RTLIL::Sx, SIZE(sig_co))); + + return true; + } + RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; log_assert(cell->hasPort("\\Y")); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b5cede8b2..ec4375f2f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -630,6 +630,15 @@ namespace { return; } + if (cell->type == "$lcu") { + port("\\P", param("\\WIDTH")); + port("\\G", param("\\WIDTH")); + port("\\CI", 1); + port("\\CO", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$alu") { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); @@ -1808,6 +1817,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } + if (type == "$lcu") { + parameters["\\WIDTH"] = SIZE(connections_["\\CO"]); + return; + } + bool signedness_ab = !type.in("$slice", "$concat", "$macc"); if (connections_.count("\\A")) { diff --git a/kernel/satgen.h b/kernel/satgen.h index 4aabe4378..91f8ab40d 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -1012,6 +1012,38 @@ struct SatGen return true; } + if (cell->type == "$lcu") + { + std::vector p = importDefSigSpec(cell->getPort("\\P"), timestep); + std::vector g = importDefSigSpec(cell->getPort("\\G"), timestep); + std::vector ci = importDefSigSpec(cell->getPort("\\CI"), timestep); + std::vector co = importDefSigSpec(cell->getPort("\\CO"), timestep); + + std::vector yy = model_undef ? ez->vec_var(co.size()) : co; + + for (int i = 0; i < SIZE(co); i++) + ez->SET(yy[i], ez->OR(g[i], ez->AND(p[i], i ? yy[i-1] : ci[0]))); + + if (model_undef) + { + std::vector undef_p = importUndefSigSpec(cell->getPort("\\P"), timestep); + std::vector undef_g = importUndefSigSpec(cell->getPort("\\G"), timestep); + std::vector undef_ci = importUndefSigSpec(cell->getPort("\\CI"), timestep); + std::vector undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep); + + int undef_any_p = ez->expression(ezSAT::OpOr, undef_p); + int undef_any_g = ez->expression(ezSAT::OpOr, undef_g); + int undef_any_ci = ez->expression(ezSAT::OpOr, undef_ci); + int undef_co_bit = ez->OR(undef_any_p, undef_any_g, undef_any_ci); + + std::vector undef_co_bits(undef_co.size(), undef_co_bit); + ez->assume(ez->vec_eq(undef_co_bits, undef_co)); + + undefGating(co, yy, undef_co); + } + return true; + } + if (cell->type == "$alu") { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); -- cgit v1.2.3 From fcb46138cebd57587d35489cef3a3a48ebe40bcf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Sep 2014 16:59:39 +0200 Subject: Simplified $fa undef model --- kernel/consteval.h | 4 ++++ kernel/satgen.h | 15 +-------------- 2 files changed, 5 insertions(+), 14 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 6e507bd51..2d29d3f7e 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -214,6 +214,10 @@ struct ConstEval RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width); RTLIL::Const val_x = const_or(t2, t3, false, false, width); + for (int i = 0; i < SIZE(val_y); i++) + if (val_y.bits[i] == RTLIL::Sx) + val_x.bits[i] = RTLIL::Sx; + set(sig_y, val_y); set(sig_x, val_x); } diff --git a/kernel/satgen.h b/kernel/satgen.h index 91f8ab40d..692c6e7fb 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -991,20 +991,7 @@ struct SatGen std::vector undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep); ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); - - std::vector undef_t1 = ez->vec_or(undef_a, undef_b); - - std::vector a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)); - std::vector b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b)); - std::vector undef_t2 = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0))); - - std::vector c0 = ez->vec_and(ez->vec_not(c), ez->vec_not(undef_c)); - std::vector t10 = ez->vec_and(ez->vec_not(t1), ez->vec_not(undef_t1)); - std::vector undef_t3 = ez->vec_and(ez->vec_or(undef_c, undef_t1), ez->vec_not(ez->vec_or(c0, t10))); - - std::vector t21 = ez->vec_and(t2, ez->vec_not(undef_t2)); - std::vector t31 = ez->vec_and(t3, ez->vec_not(undef_t3)); - ez->assume(ez->vec_eq(undef_x, ez->vec_and(ez->vec_or(undef_t2, undef_t3), ez->vec_not(ez->vec_or(t21, t31))))); + ez->assume(ez->vec_eq(undef_x, undef_y)); undefGating(y, yy, undef_y); undefGating(x, xx, undef_x); -- cgit v1.2.3 From 7815f81c320a025c5b92677e375c12951dcbd14b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 16:09:06 +0200 Subject: Added "synth" command --- kernel/driver.cc | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index e778e1389..f26d9ef82 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -76,13 +76,7 @@ int main(int argc, char **argv) printf("%s\n", yosys_version_str); exit(0); case 'S': - passes_commands.push_back("hierarchy"); - passes_commands.push_back("proc"); - passes_commands.push_back("opt"); - passes_commands.push_back("memory"); - passes_commands.push_back("opt"); - passes_commands.push_back("techmap"); - passes_commands.push_back("opt"); + passes_commands.push_back("synth"); break; case 'm': plugin_filenames.push_back(optarg); @@ -187,10 +181,10 @@ int main(int argc, char **argv) fprintf(stderr, " -V\n"); fprintf(stderr, " print version information and exit\n"); fprintf(stderr, "\n"); - fprintf(stderr, "The option -S is an alias for the following options that perform a simple\n"); - fprintf(stderr, "transformation of the input to a gate-level netlist.\n"); + fprintf(stderr, "The option -S is an shortcut for calling the \"synth\" command, a default\n"); + fprintf(stderr, "script for transforming the verilog input to a gate-level netlist. For example:\n"); fprintf(stderr, "\n"); - fprintf(stderr, " -p hierarchy -p proc -p opt -p memory -p opt -p techmap -p opt\n"); + fprintf(stderr, " yosys -o output.blif -S input.v\n"); fprintf(stderr, "\n"); fprintf(stderr, "For more complex synthesis jobs it is recommended to use the read_* and write_*\n"); fprintf(stderr, "commands in a script file instead of specifying input and output files on the\n"); -- cgit v1.2.3 From 2442eb38327f42e1e786f7dd9ddf1838bf2bf4b4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 17:04:39 +0200 Subject: Fixed monitor notifications for removed cell --- kernel/rtlil.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ec4375f2f..6556b82ee 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1148,6 +1148,9 @@ void RTLIL::Module::remove(const std::set &wires) void RTLIL::Module::remove(RTLIL::Cell *cell) { + while (!cell->connections_.empty()) + cell->unsetPort(cell->connections_.begin()->first); + log_assert(cells_.count(cell->name) != 0); log_assert(refcount_cells_ == 0); cells_.erase(cell->name); -- cgit v1.2.3 From b470c480e97fe112810d04a6051d1029ce1e8c29 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 15 Sep 2014 12:22:03 +0200 Subject: Added the obvious optimizations to alumacc $macc generator --- kernel/macc.h | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'kernel') diff --git a/kernel/macc.h b/kernel/macc.h index 362acab29..271141112 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -34,6 +34,66 @@ struct Macc std::vector ports; RTLIL::SigSpec bit_ports; + void optimize(int width) + { + std::vector new_ports; + RTLIL::SigSpec new_bit_ports; + RTLIL::Const off(0, width); + + for (auto &port : ports) + { + if (SIZE(port.in_a) == 0 && SIZE(port.in_b) == 0) + continue; + + if (SIZE(port.in_a) == 1 && SIZE(port.in_b) == 0 && !port.is_signed && !port.do_subtract) { + bit_ports.append(port.in_a); + continue; + } + + if (port.in_a.is_fully_const() && port.in_b.is_fully_const()) { + RTLIL::Const v = port.in_a.as_const(); + if (SIZE(port.in_b)) + v = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width); + if (port.do_subtract) + off = const_sub(off, v, port.is_signed, port.is_signed, width); + else + off = const_add(off, v, port.is_signed, port.is_signed, width); + continue; + } + + if (port.is_signed) { + while (SIZE(port.in_a) > 1 && port.in_a[SIZE(port.in_a)-1] == port.in_a[SIZE(port.in_a)-2]) + port.in_a.remove(SIZE(port.in_a)-1); + while (SIZE(port.in_b) > 1 && port.in_b[SIZE(port.in_b)-1] == port.in_b[SIZE(port.in_b)-2]) + port.in_b.remove(SIZE(port.in_b)-1); + } else { + while (SIZE(port.in_a) > 1 && port.in_a[SIZE(port.in_a)-1] == RTLIL::S0) + port.in_a.remove(SIZE(port.in_a)-1); + while (SIZE(port.in_b) > 1 && port.in_b[SIZE(port.in_b)-1] == RTLIL::S0) + port.in_b.remove(SIZE(port.in_b)-1); + } + + new_ports.push_back(port); + } + + for (auto &bit : bit_ports) + if (bit == RTLIL::S1) + off = const_add(off, RTLIL::Const(1, width), false, false, width); + else if (bit != RTLIL::S0) + new_bit_ports.append(bit); + + if (off.as_bool()) { + port_t port; + port.in_a = off; + port.is_signed = false; + port.do_subtract = false; + new_ports.push_back(port); + } + + new_ports.swap(ports); + bit_ports = new_bit_ports; + } + void from_cell(RTLIL::Cell *cell) { RTLIL::SigSpec port_a = cell->getPort("\\A"); -- cgit v1.2.3 From fa96cf4a1694afb1ac83e9fc9b894420fc210b97 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 16 Sep 2014 11:26:44 +0200 Subject: Added new CodingReadme file (replaces CodingStyle and CHECKLISTS) --- kernel/yosys.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index 9a4826caa..b571e177f 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -32,6 +32,8 @@ // // This header is very boring. It just defines some general things that // belong nowhere else and includes the interesting headers. +// +// Find more information in the "CodingReadme" file. #ifndef YOSYS_H -- cgit v1.2.3 From 00964f2f618d241a2e5cd32f4e7dbbcf55de4fb4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 19 Sep 2014 15:50:55 +0200 Subject: Initialize RTLIL::Const from std::vector --- kernel/rtlil.cc | 7 +++++++ kernel/rtlil.h | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6556b82ee..00be796f8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -65,6 +65,13 @@ RTLIL::Const::Const(RTLIL::State bit, int width) bits.push_back(bit); } +RTLIL::Const::Const(const std::vector &bits) +{ + flags = RTLIL::CONST_FLAG_NONE; + for (auto b : bits) + this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0); +} + bool RTLIL::Const::operator <(const RTLIL::Const &other) const { if (bits.size() != other.bits.size()) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c48837691..a0ae8f082 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -428,7 +428,8 @@ struct RTLIL::Const Const(std::string str); Const(int val, int width = 32); Const(RTLIL::State bit, int width = 1); - Const(std::vector bits) : bits(bits) { flags = CONST_FLAG_NONE; }; + Const(const std::vector &bits) : bits(bits) { flags = CONST_FLAG_NONE; }; + Const(const std::vector &bits); bool operator <(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const; -- cgit v1.2.3 From edf11c635a40c2cfb291089be509b2f31737958b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Sep 2014 12:57:33 +0200 Subject: Assert on new logic loops in "share" pass --- kernel/utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/utils.h b/kernel/utils.h index 7f10619bc..a03caf804 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -155,7 +155,7 @@ struct TopoSort void sort_worker(const T &n, std::set &marked_cells, std::set &active_cells, std::vector &active_stack) { if (active_cells.count(n)) { - found_loops = false; + found_loops = true; if (analyze_loops) { std::set loop; for (int i = SIZE(active_stack)-1; i >= 0; i--) { -- cgit v1.2.3