From a27fa1833e6dadf02645a12febb78853b5786151 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 25 Jun 2018 17:08:29 +0200 Subject: added wrappers for Design, Modules, Cells and Wires --- kernel/python_wrappers.cc | 244 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 kernel/python_wrappers.cc (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc new file mode 100644 index 000000000..d6c1a7796 --- /dev/null +++ b/kernel/python_wrappers.cc @@ -0,0 +1,244 @@ +#ifdef WITH_PYTHON + +#include "yosys.h" +#include + +void yosys_setup() +{ + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + + Yosys::yosys_setup(); + Yosys::yosys_banner(); +} + +void run(std::string command) +{ + Yosys::run_pass(command); +} + +void yosys_shutdown() +{ + Yosys::yosys_shutdown(); +} + +struct YosysCell +{ + unsigned int hashid; + + YosysCell(unsigned int hashid) + { + this->hashid = hashid; + } + + YosysCell(Yosys::RTLIL::Cell* ref) + { + this->hashid = ref->hashidx_; + } + + Yosys::RTLIL::Cell* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + for(auto &mod_it : active_design->modules_) + { + for(auto &cell_it : mod_it.second->cells_) + if(cell_it.second->hashidx_ == this->hashid) + return cell_it.second; + } + return NULL; + } +}; + +std::ostream &operator<<(std::ostream &ostr, const YosysCell &cell) +{ + ostr << "Cell with id " << cell.hashid; + return ostr; +} + +struct YosysWire +{ + unsigned int hashid; + + YosysWire(unsigned int hashid) + { + this->hashid = hashid; + } + + YosysWire(Yosys::RTLIL::Wire* ref) + { + this->hashid = ref->hashidx_; + } + + Yosys::RTLIL::Wire* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + for(auto &mod_it : active_design->modules_) + { + for(auto &wire_it : mod_it.second->wires_) + if(wire_it.second->hashidx_ == this->hashid) + return wire_it.second; + } + return NULL; + } +}; + +std::ostream &operator<<(std::ostream &ostr, const YosysWire &wire) +{ + ostr << "Wire with id " << wire.hashid; + return ostr; +} + + +struct YosysModule +{ + unsigned int hashid; + + YosysModule(unsigned int hashid) + { + this->hashid = hashid; + } + + YosysModule(Yosys::RTLIL::Module* ref) + { + this->hashid = ref->hashidx_; + } + + Yosys::RTLIL::Module* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + for(auto &mod_it : active_design->modules_) + { + if(mod_it.second->hashidx_ == this->hashid) + return mod_it.second; + } + return NULL; + } + + boost::python::list get_cells() + { + Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + boost::python::list result; + if(cpp_mod == NULL) + return result; + for(auto &cell_it : cpp_mod->cells_) + { + result.append(new YosysCell(cell_it.second)); + } + return result; + } + + boost::python::list get_wires() + { + Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + boost::python::list result; + if(cpp_mod == NULL) + return result; + for(auto &wire_it : cpp_mod->wires_) + { + result.append(new YosysWire(wire_it.second)); + } + return result; + } +}; + +std::ostream &operator<<(std::ostream &ostr, const YosysModule &module) +{ + ostr << "Module with id " << module.hashid; + return ostr; +} + +struct YosysDesign +{ + unsigned int hashid; + + YosysDesign(unsigned int hashid) + { + this->hashid = hashid; + } + + YosysDesign() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design != NULL) + { + printf("design is not null and has id %u\n", active_design->hashidx_); + this->hashid = active_design->hashidx_; + /* + for (auto &mod_it : active_design->modules_) + { + printf("found module in design!!!\n"); + //design->add(it.second->clone()); + + for (auto &wire_it : mod_it.second->wires_) + { + printf("found wire in module!!!\n"); + } + + for (auto &cell_it : mod_it.second->cells_) + { + printf("found cell in module!!!\n"); + } + }*/ + } + } + + boost::python::list get_modules() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + boost::python::list result; + if(active_design == NULL) + return result; + for(auto &mod_it : active_design->modules_) + { + result.append(new YosysModule(mod_it.second)); + } + return result; + } +}; + +std::ostream &operator<<(std::ostream &ostr, const YosysDesign &design) +{ + ostr << "Design with id " << design.hashid; + return ostr; +} + +BOOST_PYTHON_MODULE(libyosys) +{ + using namespace boost::python; + + class_("YosysDesign", init()) + .def(init<>()) + .def("get_modules", &YosysDesign::get_modules) + ; + + class_("YosysModule", init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_cells", &YosysModule::get_cells) + .def("get_wires", &YosysModule::get_wires) + ; + + class_("YosysCell", init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("YosysWire", init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + + def("yosys_setup",yosys_setup); + def("run",run); + def("yosys_shutdown",yosys_shutdown); +} + +#endif + -- cgit v1.2.3 From ccb4dcd013c1fbe005b8e8212efd22a4f0f63ff0 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 28 Jun 2018 14:44:28 +0200 Subject: changed references from hash-ids to IdString names --- kernel/python_wrappers.cc | 96 ++++++++++++++++------------------------------- 1 file changed, 32 insertions(+), 64 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index d6c1a7796..ae141c808 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -3,6 +3,11 @@ #include "yosys.h" #include +struct YosysDesign; +struct YosysModule; +struct YosysCell; +struct YosysWire; + void yosys_setup() { Yosys::log_streams.push_back(&std::cout); @@ -24,16 +29,13 @@ void yosys_shutdown() struct YosysCell { - unsigned int hashid; - - YosysCell(unsigned int hashid) - { - this->hashid = hashid; - } + Yosys::RTLIL::IdString name; + Yosys::RTLIL::IdString parent_name; YosysCell(Yosys::RTLIL::Cell* ref) { - this->hashid = ref->hashidx_; + this->name = ref->name; + this->parent_name = ref->module->name; } Yosys::RTLIL::Cell* get_cpp_obj() @@ -41,34 +43,27 @@ struct YosysCell Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); if(active_design == NULL) return NULL; - for(auto &mod_it : active_design->modules_) - { - for(auto &cell_it : mod_it.second->cells_) - if(cell_it.second->hashidx_ == this->hashid) - return cell_it.second; - } - return NULL; + if(active_design->modules_[this->parent_name] == NULL) + return NULL; + return active_design->modules_[this->parent_name]->cells_[this->name]; } }; std::ostream &operator<<(std::ostream &ostr, const YosysCell &cell) { - ostr << "Cell with id " << cell.hashid; + ostr << "Cell with name " << cell.name.c_str(); return ostr; } struct YosysWire { - unsigned int hashid; - - YosysWire(unsigned int hashid) - { - this->hashid = hashid; - } + Yosys::RTLIL::IdString name; + Yosys::RTLIL::IdString parent_name; YosysWire(Yosys::RTLIL::Wire* ref) { - this->hashid = ref->hashidx_; + this->name = ref->name; + this->parent_name = ref->module->name; } Yosys::RTLIL::Wire* get_cpp_obj() @@ -76,35 +71,27 @@ struct YosysWire Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); if(active_design == NULL) return NULL; - for(auto &mod_it : active_design->modules_) - { - for(auto &wire_it : mod_it.second->wires_) - if(wire_it.second->hashidx_ == this->hashid) - return wire_it.second; - } - return NULL; + if(active_design->modules_[this->parent_name] == NULL) + return NULL; + return active_design->modules_[this->parent_name]->wires_[this->name]; } }; std::ostream &operator<<(std::ostream &ostr, const YosysWire &wire) { - ostr << "Wire with id " << wire.hashid; + ostr << "Wire with name " << wire.name.c_str(); return ostr; } - struct YosysModule { - unsigned int hashid; - - YosysModule(unsigned int hashid) - { - this->hashid = hashid; - } + Yosys::RTLIL::IdString name; + unsigned int parent_hashid; YosysModule(Yosys::RTLIL::Module* ref) { - this->hashid = ref->hashidx_; + this->name = ref->name; + this->parent_hashid = ref->design->hashidx_; } Yosys::RTLIL::Module* get_cpp_obj() @@ -112,12 +99,9 @@ struct YosysModule Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); if(active_design == NULL) return NULL; - for(auto &mod_it : active_design->modules_) - { - if(mod_it.second->hashidx_ == this->hashid) - return mod_it.second; - } - return NULL; + if(active_design->hashidx_ != this->parent_hashid) + printf("Somehow the active design changed!\n"); + return active_design->modules_[this->name]; } boost::python::list get_cells() @@ -149,7 +133,7 @@ struct YosysModule std::ostream &operator<<(std::ostream &ostr, const YosysModule &module) { - ostr << "Module with id " << module.hashid; + ostr << "Module with name " << module.name.c_str(); return ostr; } @@ -169,22 +153,6 @@ struct YosysDesign { printf("design is not null and has id %u\n", active_design->hashidx_); this->hashid = active_design->hashidx_; - /* - for (auto &mod_it : active_design->modules_) - { - printf("found module in design!!!\n"); - //design->add(it.second->clone()); - - for (auto &wire_it : mod_it.second->wires_) - { - printf("found wire in module!!!\n"); - } - - for (auto &cell_it : mod_it.second->cells_) - { - printf("found cell in module!!!\n"); - } - }*/ } } @@ -217,19 +185,19 @@ BOOST_PYTHON_MODULE(libyosys) .def("get_modules", &YosysDesign::get_modules) ; - class_("YosysModule", init()) + class_("YosysModule", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("get_cells", &YosysModule::get_cells) .def("get_wires", &YosysModule::get_wires) ; - class_("YosysCell", init()) + class_("YosysCell", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; - class_("YosysWire", init()) + class_("YosysWire", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; -- cgit v1.2.3 From 7911379d4a3806af8141e5737e217a2b05368d6c Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 28 Jun 2018 15:07:21 +0200 Subject: Introduced namespace and removed class-prefixes to increase readability --- kernel/python_wrappers.cc | 328 +++++++++++++++++++++++----------------------- 1 file changed, 165 insertions(+), 163 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index ae141c808..78011a8c5 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -3,210 +3,212 @@ #include "yosys.h" #include -struct YosysDesign; -struct YosysModule; -struct YosysCell; -struct YosysWire; - -void yosys_setup() -{ - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; - - Yosys::yosys_setup(); - Yosys::yosys_banner(); -} +namespace YOSYS_PYTHON { -void run(std::string command) -{ - Yosys::run_pass(command); -} + struct Design; + struct Module; + struct Cell; + struct Wire; -void yosys_shutdown() -{ - Yosys::yosys_shutdown(); -} + void yosys_setup() + { + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; -struct YosysCell -{ - Yosys::RTLIL::IdString name; - Yosys::RTLIL::IdString parent_name; + Yosys::yosys_setup(); + Yosys::yosys_banner(); + } - YosysCell(Yosys::RTLIL::Cell* ref) + void run(std::string command) { - this->name = ref->name; - this->parent_name = ref->module->name; + Yosys::run_pass(command); } - - Yosys::RTLIL::Cell* get_cpp_obj() + + void yosys_shutdown() { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->modules_[this->parent_name] == NULL) - return NULL; - return active_design->modules_[this->parent_name]->cells_[this->name]; + Yosys::yosys_shutdown(); } -}; -std::ostream &operator<<(std::ostream &ostr, const YosysCell &cell) -{ - ostr << "Cell with name " << cell.name.c_str(); - return ostr; -} - -struct YosysWire -{ - Yosys::RTLIL::IdString name; - Yosys::RTLIL::IdString parent_name; - - YosysWire(Yosys::RTLIL::Wire* ref) + struct Cell { - this->name = ref->name; - this->parent_name = ref->module->name; - } + Yosys::RTLIL::IdString name; + Yosys::RTLIL::IdString parent_name; + + Cell(Yosys::RTLIL::Cell* ref) + { + this->name = ref->name; + this->parent_name = ref->module->name; + } - Yosys::RTLIL::Wire* get_cpp_obj() + Yosys::RTLIL::Cell* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + if(active_design->modules_[this->parent_name] == NULL) + return NULL; + return active_design->modules_[this->parent_name]->cells_[this->name]; + } + }; + + std::ostream &operator<<(std::ostream &ostr, const Cell &cell) { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->modules_[this->parent_name] == NULL) - return NULL; - return active_design->modules_[this->parent_name]->wires_[this->name]; + ostr << "Cell with name " << cell.name.c_str(); + return ostr; } -}; -std::ostream &operator<<(std::ostream &ostr, const YosysWire &wire) -{ - ostr << "Wire with name " << wire.name.c_str(); - return ostr; -} + struct Wire + { + Yosys::RTLIL::IdString name; + Yosys::RTLIL::IdString parent_name; -struct YosysModule -{ - Yosys::RTLIL::IdString name; - unsigned int parent_hashid; + Wire(Yosys::RTLIL::Wire* ref) + { + this->name = ref->name; + this->parent_name = ref->module->name; + } + + Yosys::RTLIL::Wire* get_cpp_obj() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + if(active_design->modules_[this->parent_name] == NULL) + return NULL; + return active_design->modules_[this->parent_name]->wires_[this->name]; + } + }; - YosysModule(Yosys::RTLIL::Module* ref) + std::ostream &operator<<(std::ostream &ostr, const Wire &wire) { - this->name = ref->name; - this->parent_hashid = ref->design->hashidx_; + ostr << "Wire with name " << wire.name.c_str(); + return ostr; } - Yosys::RTLIL::Module* get_cpp_obj() + struct Module { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->hashidx_ != this->parent_hashid) - printf("Somehow the active design changed!\n"); - return active_design->modules_[this->name]; - } + Yosys::RTLIL::IdString name; + unsigned int parent_hashid; - boost::python::list get_cells() - { - Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); - boost::python::list result; - if(cpp_mod == NULL) - return result; - for(auto &cell_it : cpp_mod->cells_) + Module(Yosys::RTLIL::Module* ref) { - result.append(new YosysCell(cell_it.second)); + this->name = ref->name; + this->parent_hashid = ref->design->hashidx_; } - return result; - } - boost::python::list get_wires() - { - Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); - boost::python::list result; - if(cpp_mod == NULL) - return result; - for(auto &wire_it : cpp_mod->wires_) + Yosys::RTLIL::Module* get_cpp_obj() { - result.append(new YosysWire(wire_it.second)); + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design == NULL) + return NULL; + if(active_design->hashidx_ != this->parent_hashid) + printf("Somehow the active design changed!\n"); + return active_design->modules_[this->name]; } - return result; - } -}; -std::ostream &operator<<(std::ostream &ostr, const YosysModule &module) -{ - ostr << "Module with name " << module.name.c_str(); - return ostr; -} + boost::python::list get_cells() + { + Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + boost::python::list result; + if(cpp_mod == NULL) + return result; + for(auto &cell_it : cpp_mod->cells_) + { + result.append(new Cell(cell_it.second)); + } + return result; + } -struct YosysDesign -{ - unsigned int hashid; + boost::python::list get_wires() + { + Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); + boost::python::list result; + if(cpp_mod == NULL) + return result; + for(auto &wire_it : cpp_mod->wires_) + { + result.append(new Wire(wire_it.second)); + } + return result; + } + }; - YosysDesign(unsigned int hashid) + std::ostream &operator<<(std::ostream &ostr, const Module &module) { - this->hashid = hashid; + ostr << "Module with name " << module.name.c_str(); + return ostr; } - YosysDesign() + struct Design { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design != NULL) + unsigned int hashid; + + Design(unsigned int hashid) { - printf("design is not null and has id %u\n", active_design->hashidx_); - this->hashid = active_design->hashidx_; + this->hashid = hashid; } - } - boost::python::list get_modules() - { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - boost::python::list result; - if(active_design == NULL) - return result; - for(auto &mod_it : active_design->modules_) + Design() { - result.append(new YosysModule(mod_it.second)); + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design != NULL) + { + printf("design is not null and has id %u\n", active_design->hashidx_); + this->hashid = active_design->hashidx_; + } } - return result; - } -}; -std::ostream &operator<<(std::ostream &ostr, const YosysDesign &design) -{ - ostr << "Design with id " << design.hashid; - return ostr; -} - -BOOST_PYTHON_MODULE(libyosys) -{ - using namespace boost::python; - - class_("YosysDesign", init()) - .def(init<>()) - .def("get_modules", &YosysDesign::get_modules) - ; - - class_("YosysModule", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_cells", &YosysModule::get_cells) - .def("get_wires", &YosysModule::get_wires) - ; - - class_("YosysCell", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - ; + boost::python::list get_modules() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + boost::python::list result; + if(active_design == NULL) + return result; + for(auto &mod_it : active_design->modules_) + { + result.append(new Module(mod_it.second)); + } + return result; + } + }; - class_("YosysWire", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - ; + std::ostream &operator<<(std::ostream &ostr, const Design &design) + { + ostr << "Design with id " << design.hashid; + return ostr; + } + BOOST_PYTHON_MODULE(libyosys) + { + using namespace boost::python; + + class_("Design", init()) + .def(init<>()) + .def("get_modules", &Design::get_modules) + ; + + class_("Module", no_init) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_cells", &Module::get_cells) + .def("get_wires", &Module::get_wires) + ; + + class_("Cell", no_init) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("Wire", no_init) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + + def("yosys_setup",yosys_setup); + def("run",run); + def("yosys_shutdown",yosys_shutdown); + } - def("yosys_setup",yosys_setup); - def("run",run); - def("yosys_shutdown",yosys_shutdown); } - #endif - -- cgit v1.2.3 From 8ebaeecd83b22db5c196356844f01ce69d0b4bea Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 9 Jul 2018 15:48:06 +0200 Subject: multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues --- kernel/python_wrappers.cc | 92 ++++++++++++++++++++++++----------------------- kernel/rtlil.cc | 55 ++++++++++++++++++++++++++++ kernel/rtlil.h | 16 +++++++++ 3 files changed, 118 insertions(+), 45 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 78011a8c5..c778f3919 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -31,79 +31,64 @@ namespace YOSYS_PYTHON { struct Cell { - Yosys::RTLIL::IdString name; - Yosys::RTLIL::IdString parent_name; + unsigned int id; Cell(Yosys::RTLIL::Cell* ref) { - this->name = ref->name; - this->parent_name = ref->module->name; + this->id = ref->hashidx_; } - Yosys::RTLIL::Cell* get_cpp_obj() + Yosys::RTLIL::Cell* get_cpp_obj() const { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->modules_[this->parent_name] == NULL) - return NULL; - return active_design->modules_[this->parent_name]->cells_[this->name]; + return Yosys::RTLIL::Cell::get_all_cells()->at(this->id); } }; std::ostream &operator<<(std::ostream &ostr, const Cell &cell) { - ostr << "Cell with name " << cell.name.c_str(); + if(cell.get_cpp_obj() != NULL) + ostr << "Cell with name " << cell.get_cpp_obj()->name.c_str(); + else + ostr << "deleted cell"; return ostr; } struct Wire { - Yosys::RTLIL::IdString name; - Yosys::RTLIL::IdString parent_name; + unsigned int id; Wire(Yosys::RTLIL::Wire* ref) { - this->name = ref->name; - this->parent_name = ref->module->name; + this->id = ref->hashidx_; } - Yosys::RTLIL::Wire* get_cpp_obj() + Yosys::RTLIL::Wire* get_cpp_obj() const { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->modules_[this->parent_name] == NULL) - return NULL; - return active_design->modules_[this->parent_name]->wires_[this->name]; + return Yosys::RTLIL::Wire::get_all_wires()->at(this->id); } }; std::ostream &operator<<(std::ostream &ostr, const Wire &wire) { - ostr << "Wire with name " << wire.name.c_str(); + if(wire.get_cpp_obj() != NULL) + ostr << "Wire with name " << wire.get_cpp_obj()->name.c_str(); + else + ostr << "deleted wire"; return ostr; } struct Module { - Yosys::RTLIL::IdString name; - unsigned int parent_hashid; + unsigned int id; Module(Yosys::RTLIL::Module* ref) { - this->name = ref->name; - this->parent_hashid = ref->design->hashidx_; + this->id = ref->hashidx_; } - Yosys::RTLIL::Module* get_cpp_obj() + Yosys::RTLIL::Module* get_cpp_obj() const { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design == NULL) - return NULL; - if(active_design->hashidx_ != this->parent_hashid) - printf("Somehow the active design changed!\n"); - return active_design->modules_[this->name]; + return Yosys::RTLIL::Module::get_all_modules()->at(this->id); } boost::python::list get_cells() @@ -135,7 +120,10 @@ namespace YOSYS_PYTHON { std::ostream &operator<<(std::ostream &ostr, const Module &module) { - ostr << "Module with name " << module.name.c_str(); + if(module.get_cpp_obj() != NULL) + ostr << "Module with name " << module.get_cpp_obj()->name.c_str(); + else + ostr << "deleted module"; return ostr; } @@ -150,21 +138,24 @@ namespace YOSYS_PYTHON { Design() { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design != NULL) - { - printf("design is not null and has id %u\n", active_design->hashidx_); - this->hashid = active_design->hashidx_; - } + Yosys::RTLIL::Design* new_design = new Yosys::RTLIL::Design(); + this->hashid = new_design->hashidx_; + } + + Yosys::RTLIL::Design* get_cpp_obj() + { + return Yosys::RTLIL::Design::get_all_designs()->at(hashid); } boost::python::list get_modules() { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); boost::python::list result; - if(active_design == NULL) + if(cpp_design == NULL) + { return result; - for(auto &mod_it : active_design->modules_) + } + for(auto &mod_it : cpp_design->modules_) { result.append(new Module(mod_it.second)); } @@ -178,6 +169,16 @@ namespace YOSYS_PYTHON { return ostr; } + unsigned int get_active_design_id() + { + Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); + if(active_design != NULL) + { + return active_design->hashidx_; + } + return 0; + } + BOOST_PYTHON_MODULE(libyosys) { using namespace boost::python; @@ -207,6 +208,7 @@ namespace YOSYS_PYTHON { def("yosys_setup",yosys_setup); def("run",run); + def("get_active_design_id",get_active_design_id); def("yosys_shutdown",yosys_shutdown); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a4fa2cf04..df6e0af62 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -358,6 +358,10 @@ RTLIL::Design::Design() refcount_modules_ = 0; selection_stack.push_back(RTLIL::Selection()); + +#ifdef WITH_PYTHON + RTLIL::Design::get_all_designs()->insert(std::pair(hashidx_, this)); +#endif } RTLIL::Design::~Design() @@ -368,8 +372,19 @@ RTLIL::Design::~Design() delete n; for (auto n : verilog_globals) delete n; +#ifdef WITH_PYTHON + RTLIL::Design::get_all_designs()->erase(hashidx_); +#endif } +#ifdef WITH_PYTHON +static std::map *all_designs = new std::map(); +std::map *RTLIL::Design::get_all_designs(void) +{ + return all_designs; +} +#endif + RTLIL::ObjRange RTLIL::Design::modules() { return RTLIL::ObjRange(&modules_, &refcount_modules_); @@ -625,6 +640,11 @@ RTLIL::Module::Module() design = nullptr; refcount_wires_ = 0; refcount_cells_ = 0; + +#ifdef WITH_PYTHON + std::cout << "inserting module with name " << this->name.c_str() << "\n"; + RTLIL::Module::get_all_modules()->insert(std::pair(hashidx_, this)); +#endif } RTLIL::Module::~Module() @@ -637,7 +657,18 @@ RTLIL::Module::~Module() delete it->second; for (auto it = processes.begin(); it != processes.end(); ++it) delete it->second; +#ifdef WITH_PYTHON + RTLIL::Module::get_all_modules()->erase(hashidx_); +#endif +} + +#ifdef WITH_PYTHON +static std::map *all_modules = new std::map(); +std::map *RTLIL::Module::get_all_modules(void) +{ + return all_modules; } +#endif RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, bool mayfail) { @@ -2187,8 +2218,20 @@ RTLIL::Wire::Wire() port_input = false; port_output = false; upto = false; + +#ifdef WITH_PYTHON + RTLIL::Wire::get_all_wires()->insert(std::pair(hashidx_, this)); +#endif } +#ifdef WITH_PYTHON +static std::map *all_wires = new std::map(); +std::map *RTLIL::Wire::get_all_wires(void) +{ + return all_wires; +} +#endif + RTLIL::Memory::Memory() { static unsigned int hashidx_count = 123456789; @@ -2208,7 +2251,19 @@ RTLIL::Cell::Cell() : module(nullptr) // log("#memtrace# %p\n", this); memhasher(); + +#ifdef WITH_PYTHON + RTLIL::Cell::get_all_cells()->insert(std::pair(hashidx_, this)); +#endif +} + +#ifdef WITH_PYTHON +static std::map *all_cells = new std::map(); +std::map *RTLIL::Cell::get_all_cells(void) +{ + return all_cells; } +#endif bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 54d0b8c22..232a8c13a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -874,6 +874,10 @@ struct RTLIL::Design } } +#ifdef WITH_PYTHON + static std::map *get_all_designs(void); +#endif + std::vector selected_modules() const; std::vector selected_whole_modules() const; std::vector selected_whole_modules_warn() const; @@ -1130,6 +1134,10 @@ public: RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = ""); + +#ifdef WITH_PYTHON + static std::map *get_all_modules(void); +#endif }; struct RTLIL::Wire : public RTLIL::AttrObject @@ -1152,6 +1160,10 @@ public: RTLIL::IdString name; int width, start_offset, port_id; bool port_input, port_output, upto; + +#ifdef WITH_PYTHON + static std::map *get_all_wires(void); +#endif }; struct RTLIL::Memory : public RTLIL::AttrObject @@ -1214,6 +1226,10 @@ public: } template void rewrite_sigspecs(T &functor); + +#ifdef WITH_PYTHON + static std::map *get_all_cells(void); +#endif }; struct RTLIL::CaseRule -- cgit v1.2.3 From da8083dbd07404fb765e0ffebed6f5477b6d99ad Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 9 Jul 2018 16:01:56 +0200 Subject: commands can now be run on arbitrary designs, not only on the active one --- kernel/python_wrappers.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index c778f3919..04aebb1b8 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -161,6 +161,13 @@ namespace YOSYS_PYTHON { } return result; } + + void run(std::string command) + { + Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); + if(cpp_design != NULL) + Yosys::run_pass(command, cpp_design); + } }; std::ostream &operator<<(std::ostream &ostr, const Design &design) @@ -184,8 +191,11 @@ namespace YOSYS_PYTHON { using namespace boost::python; class_("Design", init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def(init<>()) .def("get_modules", &Design::get_modules) + .def("run",&Design::run) ; class_("Module", no_init) -- cgit v1.2.3 From 55df7fff19cfaa42197effc31ac8de07f9090924 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 9 Jul 2018 16:02:10 +0200 Subject: removed debug output --- kernel/rtlil.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index df6e0af62..5cef90206 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -642,7 +642,6 @@ RTLIL::Module::Module() refcount_cells_ = 0; #ifdef WITH_PYTHON - std::cout << "inserting module with name " << this->name.c_str() << "\n"; RTLIL::Module::get_all_modules()->insert(std::pair(hashidx_, this)); #endif } -- cgit v1.2.3 From e7d3f3cd464fe323872285bed40e6f347683147b Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 10 Jul 2018 08:52:36 +0200 Subject: added destructors for wires and cells --- kernel/rtlil.cc | 14 ++++++++++++++ kernel/rtlil.h | 3 ++- 2 files changed, 16 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5cef90206..6e8b51682 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2223,6 +2223,13 @@ RTLIL::Wire::Wire() #endif } +RTLIL::Wire::~Wire() +{ +#ifdef WITH_PYTHON + RTLIL::Wire::get_all_wires()->erase(hashidx_); +#endif +} + #ifdef WITH_PYTHON static std::map *all_wires = new std::map(); std::map *RTLIL::Wire::get_all_wires(void) @@ -2256,6 +2263,13 @@ RTLIL::Cell::Cell() : module(nullptr) #endif } +RTLIL::Cell::~Cell() +{ +#ifdef WITH_PYTHON + RTLIL::Cell::get_all_cells()->erase(hashidx_); +#endif +} + #ifdef WITH_PYTHON static std::map *all_cells = new std::map(); std::map *RTLIL::Cell::get_all_cells(void) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 232a8c13a..e71a5fceb 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1149,7 +1149,7 @@ protected: // use module->addWire() and module->remove() to create or destroy wires friend struct RTLIL::Module; Wire(); - ~Wire() { }; + ~Wire(); public: // do not simply copy wires @@ -1186,6 +1186,7 @@ protected: // use module->addCell() and module->remove() to create or destroy cells friend struct RTLIL::Module; Cell(); + ~Cell(); public: // do not simply copy cells -- cgit v1.2.3 From 0371519c3977fcf4ffc71315cb9e0aae3ee967a2 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 10 Jul 2018 12:51:02 +0200 Subject: Added Monitor class that can monitor all changes in a Design or in a Module --- kernel/python_wrappers.cc | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 04aebb1b8..4ba2a1185 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -1,6 +1,10 @@ #ifdef WITH_PYTHON #include "yosys.h" +#include +#include +#include +#include #include namespace YOSYS_PYTHON { @@ -9,6 +13,7 @@ namespace YOSYS_PYTHON { struct Module; struct Cell; struct Wire; + struct Monitor; void yosys_setup() { @@ -116,6 +121,8 @@ namespace YOSYS_PYTHON { } return result; } + + void register_monitor(Monitor* const m); }; std::ostream &operator<<(std::ostream &ostr, const Module &module) @@ -168,8 +175,113 @@ namespace YOSYS_PYTHON { if(cpp_design != NULL) Yosys::run_pass(command, cpp_design); } + + void register_monitor(Monitor* const m); }; + struct Monitor : public Yosys::RTLIL::Monitor + { + + virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_add(new Module(module)); + } + + virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_del(new Module(module)); + } + + virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE + { + //log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE + { + //log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + { + //log("#TRACE# New connections in module %s:\n", log_id(module)); + //for (auto &sigsig : sigsig_vec) + // log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); + } + + virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_blackout(new Module(module)); + } + + //virtual void notify_connect(Cell*, const Yosys::RTLIL::IdString&, const Yosys::RTLIL::SigSpec&, Yosys::RTLIL::SigSpec&) { } + //virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } + //virtual void notify_connect(RTLIL::Module*, const std::vector&) { } + + virtual void py_notify_module_add(Module*){}; + virtual void py_notify_module_del(Module*){}; + virtual void py_notify_blackout(Module*){}; + + }; + + struct MonitorWrap : Monitor, boost::python::wrapper + { + void py_notify_module_add(Module* m) + { + if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) + py_notify_module_add(m); + else + Monitor::py_notify_module_add(m); + } + + void default_py_notify_module_add(Module* m) + { + this->Monitor::py_notify_module_add(m); + } + + void py_notify_module_del(Module* m) + { + if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) + py_notify_module_del(m); + else + Monitor::py_notify_module_del(m); + } + + void default_py_notify_module_del(Module* m) + { + this->Monitor::py_notify_module_del(m); + } + + void py_notify_blackout(Module* m) + { + if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) + py_notify_blackout(m); + else + Monitor::py_notify_blackout(m); + } + + void default_py_notify_blackout(Module* m) + { + this->Monitor::py_notify_blackout(m); + } + }; + + void Design::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Design* cpp_design = this->get_cpp_obj(); + if(cpp_design == NULL) + return; + cpp_design->monitors.insert(m); + } + + void Module::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Module* cpp_design = this->get_cpp_obj(); + if(cpp_design == NULL) + return; + cpp_design->monitors.insert(m); + } + std::ostream &operator<<(std::ostream &ostr, const Design &design) { ostr << "Design with id " << design.hashid; @@ -196,6 +308,7 @@ namespace YOSYS_PYTHON { .def(init<>()) .def("get_modules", &Design::get_modules) .def("run",&Design::run) + .def("register_monitor", &Design::register_monitor) ; class_("Module", no_init) @@ -203,6 +316,7 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("get_cells", &Module::get_cells) .def("get_wires", &Module::get_wires) + .def("register_monitor", &Module::register_monitor) ; class_("Cell", no_init) @@ -215,6 +329,11 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; + class_("Monitor") + .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) + .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) + .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + ; def("yosys_setup",yosys_setup); def("run",run); -- cgit v1.2.3 From 1a60126a3468c525ac31de930dfb139b70512a34 Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Thu, 19 Jul 2018 09:40:20 -0700 Subject: Provide source-location logging. o Provide log_file_warning() and log_file_error() that prefix the log message with :: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil. --- kernel/log.cc | 84 ++++++++++++++++++++++++++++------------------------------- kernel/log.h | 5 ++++ 2 files changed, 45 insertions(+), 44 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 6d562b9e6..0ee2170a0 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -203,7 +203,8 @@ void logv_header(RTLIL::Design *design, const char *format, va_list ap) log_files.pop_back(); } -void logv_warning(const char *format, va_list ap) +static void logv_warning_with_prefix(const char *prefix, + const char *format, va_list ap) { std::string message = vstringf(format, ap); bool suppressed = false; @@ -214,7 +215,7 @@ void logv_warning(const char *format, va_list ap) if (suppressed) { - log("Suppressed warning: %s", message.c_str()); + log("Suppressed %s%s", prefix, message.c_str()); } else { @@ -224,7 +225,7 @@ void logv_warning(const char *format, va_list ap) if (log_warnings.count(message)) { - log("Warning: %s", message.c_str()); + log("%s%s", prefix, message.c_str()); log_flush(); } else @@ -232,7 +233,7 @@ void logv_warning(const char *format, va_list ap) if (log_errfile != NULL && !log_quiet_warnings) log_files.push_back(log_errfile); - log("Warning: %s", message.c_str()); + log("%s%s", prefix, message.c_str()); log_flush(); if (log_errfile != NULL && !log_quiet_warnings) @@ -245,49 +246,30 @@ void logv_warning(const char *format, va_list ap) } } -void logv_warning_noprefix(const char *format, va_list ap) +void logv_warning(const char *format, va_list ap) { - std::string message = vstringf(format, ap); - bool suppressed = false; - - for (auto &re : log_nowarn_regexes) - if (std::regex_search(message, re)) - suppressed = true; - - if (suppressed) - { - log("%s", message.c_str()); - } - else - { - for (auto &re : log_werror_regexes) - if (std::regex_search(message, re)) - log_error("%s", message.c_str()); - - if (log_warnings.count(message)) - { - log("%s", message.c_str()); - log_flush(); - } - else - { - if (log_errfile != NULL && !log_quiet_warnings) - log_files.push_back(log_errfile); - - log("%s", message.c_str()); - log_flush(); - - if (log_errfile != NULL && !log_quiet_warnings) - log_files.pop_back(); + logv_warning_with_prefix("Warning: ", format, ap); +} - log_warnings.insert(message); - } +void logv_warning_noprefix(const char *format, va_list ap) +{ + logv_warning_with_prefix("", format, ap); +} - log_warnings_count++; - } +void log_file_warning(const std::string &filename, int lineno, + const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string prefix = stringf("%s:%d: Warning: ", + filename.c_str(), lineno); + logv_warning_with_prefix(prefix.c_str(), format, ap); + va_end(ap); } -void logv_error(const char *format, va_list ap) +YS_ATTRIBUTE(noreturn) +static void logv_error_with_prefix(const char *prefix, + const char *format, va_list ap) { #ifdef EMSCRIPTEN auto backup_log_files = log_files; @@ -302,7 +284,7 @@ void logv_error(const char *format, va_list ap) f = stderr; log_last_error = vstringf(format, ap); - log("ERROR: %s", log_last_error.c_str()); + log("%s%s", prefix, log_last_error.c_str()); log_flush(); if (log_error_atexit) @@ -318,6 +300,21 @@ void logv_error(const char *format, va_list ap) #endif } +void logv_error(const char *format, va_list ap) +{ + logv_error_with_prefix("ERROR: ", format, ap); +} + +void log_file_error(const string &filename, int lineno, + const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string prefix = stringf("%s:%d: ERROR: ", + filename.c_str(), lineno); + logv_error_with_prefix(prefix.c_str(), format, ap); +} + void log(const char *format, ...) { va_list ap; @@ -636,4 +633,3 @@ dict> get_coverage_data() #endif YOSYS_NAMESPACE_END - diff --git a/kernel/log.h b/kernel/log.h index a2aacfd4d..0b4905c3a 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -73,8 +73,13 @@ YS_NORETURN void logv_error(const char *format, va_list ap) YS_ATTRIBUTE(noretur void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3)); void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); + +// Log with filename to report a problem in a source file. +void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); + void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); +void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4), noreturn); YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); void log_spacer(); -- cgit v1.2.3 From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Fri, 20 Jul 2018 23:41:18 -0700 Subject: Consistent use of 'override' for virtual methods in derived classes. o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) --- kernel/celledges.h | 6 +++--- kernel/modtools.h | 10 +++++----- kernel/register.cc | 11 +++++------ kernel/register.h | 14 +++++++------- kernel/rtlil.h | 2 +- kernel/satgen.h | 2 +- kernel/yosys.cc | 16 ++++++++-------- kernel/yosys.h | 2 +- 8 files changed, 31 insertions(+), 32 deletions(-) (limited to 'kernel') diff --git a/kernel/celledges.h b/kernel/celledges.h index 6aab9ed43..2cc297cb2 100644 --- a/kernel/celledges.h +++ b/kernel/celledges.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf @@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[from_sigbit].insert(to_sigbit); @@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[to_sigbit].insert(from_sigbit); diff --git a/kernel/modtools.h b/kernel/modtools.h index ffcb48d44..409562eb9 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf @@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor #endif } - virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE { log_assert(module == cell->module); @@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor port_add(cell, port, sig); } - virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE { log_assert(module == mod); @@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor } } - virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector&) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector&) YS_OVERRIDE { log_assert(module == mod); auto_reload_module = true; } - virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE + void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE { log_assert(module == mod); auto_reload_module = true; diff --git a/kernel/register.cc b/kernel/register.cc index e30414f44..402a5b3ea 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -615,7 +615,7 @@ static struct CellHelpMessages { struct HelpPass : public Pass { HelpPass() : Pass("help", "display help messages") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" help ................ list all commands\n"); @@ -684,7 +684,7 @@ struct HelpPass : public Pass { fclose(f); } - virtual void execute(std::vector args, RTLIL::Design*) + void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE { if (args.size() == 1) { log("\n"); @@ -768,7 +768,7 @@ struct HelpPass : public Pass { struct EchoPass : public Pass { EchoPass() : Pass("echo", "turning echoing back of commands on and off") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" echo on\n"); @@ -781,7 +781,7 @@ struct EchoPass : public Pass { log("Do not print all commands to log before executing them. (default)\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design*) + void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE { if (args.size() > 2) cmd_error(args, 2, "Unexpected argument."); @@ -806,10 +806,9 @@ struct MinisatSatSolver : public SatSolver { MinisatSatSolver() : SatSolver("minisat") { yosys_satsolver = this; } - virtual ezSAT *create() YS_OVERRIDE { + ezSAT *create() YS_OVERRIDE { return new ezMiniSAT(); } } MinisatSatSolver; YOSYS_NAMESPACE_END - diff --git a/kernel/register.h b/kernel/register.h index 8024c56a0..c74029823 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf @@ -88,9 +88,9 @@ struct Frontend : Pass std::string frontend_name; Frontend(std::string name, std::string short_help = "** document me **"); - virtual void run_register() YS_OVERRIDE; - virtual ~Frontend(); - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; + void run_register() YS_OVERRIDE; + ~Frontend() YS_OVERRIDE; + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; static std::vector next_args; @@ -104,9 +104,9 @@ struct Backend : Pass { std::string backend_name; Backend(std::string name, std::string short_help = "** document me **"); - virtual void run_register() YS_OVERRIDE; - virtual ~Backend(); - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; + void run_register() YS_OVERRIDE; + ~Backend() YS_OVERRIDE; + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; void extra_args(std::ostream *&f, std::string &filename, std::vector args, size_t argidx); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 54d0b8c22..027faf416 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf diff --git a/kernel/satgen.h b/kernel/satgen.h index 8d760fff7..210cca3f3 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 750a154e6..2a8ab2005 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -636,7 +636,7 @@ extern Tcl_Interp *yosys_get_tcl_interp() struct TclPass : public Pass { TclPass() : Pass("tcl", "execute a TCL script file") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" tcl \n"); log("\n"); @@ -649,7 +649,7 @@ struct TclPass : public Pass { log("in order to avoid a name collision with the built in commands.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing script file.\n"); if (args.size() > 2) @@ -1111,7 +1111,7 @@ void shell(RTLIL::Design *design) struct ShellPass : public Pass { ShellPass() : Pass("shell", "enter interactive command mode") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" shell\n"); log("\n"); @@ -1143,7 +1143,7 @@ struct ShellPass : public Pass { log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { extra_args(args, 1, design, false); shell(design); } @@ -1152,7 +1152,7 @@ struct ShellPass : public Pass { #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) struct HistoryPass : public Pass { HistoryPass() : Pass("history", "show last interactive commands") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" history\n"); log("\n"); @@ -1161,7 +1161,7 @@ struct HistoryPass : public Pass { log("from executed scripts.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { extra_args(args, 1, design, false); #ifdef YOSYS_ENABLE_READLINE for(HIST_ENTRY **list = history_list(); *list != NULL; list++) @@ -1176,7 +1176,7 @@ struct HistoryPass : public Pass { struct ScriptCmdPass : public Pass { ScriptCmdPass() : Pass("script", "execute commands from script file") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" script [:]\n"); log("\n"); @@ -1191,7 +1191,7 @@ struct ScriptCmdPass : public Pass { log("marked with that label (until the next label) is executed.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing script file.\n"); else if (args.size() == 2) diff --git a/kernel/yosys.h b/kernel/yosys.h index 14cbcd610..c9f973318 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf -- cgit v1.2.3 From 57d2197703da12750fb508736ccfaf59b847ea22 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 1 Aug 2018 08:05:39 +0200 Subject: Cleaned up comments --- kernel/python_wrappers.cc | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 4ba2a1185..ba7be9106 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -194,19 +194,17 @@ namespace YOSYS_PYTHON { virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE { - //log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE { - //log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE { - //log("#TRACE# New connections in module %s:\n", log_id(module)); - //for (auto &sigsig : sigsig_vec) - // log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); + //@TODO: Implement once necessary classes are wrapped } virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE @@ -214,10 +212,6 @@ namespace YOSYS_PYTHON { py_notify_blackout(new Module(module)); } - //virtual void notify_connect(Cell*, const Yosys::RTLIL::IdString&, const Yosys::RTLIL::SigSpec&, Yosys::RTLIL::SigSpec&) { } - //virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { } - //virtual void notify_connect(RTLIL::Module*, const std::vector&) { } - virtual void py_notify_module_add(Module*){}; virtual void py_notify_module_del(Module*){}; virtual void py_notify_blackout(Module*){}; -- cgit v1.2.3 From 79d7e608cfcc7fe19647313521eed908f3784503 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 1 Aug 2018 10:08:23 +0200 Subject: Setup is called automatically when the module is loaded, shutdown when python exits --- kernel/python_wrappers.cc | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index ba7be9106..718e3f5c1 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -15,25 +15,11 @@ namespace YOSYS_PYTHON { struct Wire; struct Monitor; - void yosys_setup() - { - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; - - Yosys::yosys_setup(); - Yosys::yosys_banner(); - } - void run(std::string command) { Yosys::run_pass(command); } - void yosys_shutdown() - { - Yosys::yosys_shutdown(); - } - struct Cell { unsigned int id; @@ -292,10 +278,29 @@ namespace YOSYS_PYTHON { return 0; } + struct Initializer + { + Initializer() { + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + Yosys::yosys_setup(); + Yosys::yosys_banner(); + } + + Initializer(Initializer const &) {} + + ~Initializer() { + Yosys::yosys_shutdown(); + } + }; + BOOST_PYTHON_MODULE(libyosys) { using namespace boost::python; + class_("Initializer"); + scope().attr("_hidden") = new Initializer(); + class_("Design", init()) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) @@ -329,10 +334,8 @@ namespace YOSYS_PYTHON { .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) ; - def("yosys_setup",yosys_setup); def("run",run); def("get_active_design_id",get_active_design_id); - def("yosys_shutdown",yosys_shutdown); } } -- cgit v1.2.3 From 416946a16ad9ddbbf67747ba02a935f4f5d8dc40 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 1 Aug 2018 10:27:35 +0200 Subject: Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more --- kernel/python_wrappers.cc | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 718e3f5c1..1ba2c011a 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -23,15 +23,20 @@ namespace YOSYS_PYTHON { struct Cell { unsigned int id; + Yosys::RTLIL::Cell* ref_obj; Cell(Yosys::RTLIL::Cell* ref) { this->id = ref->hashidx_; + this->ref_obj = ref; } Yosys::RTLIL::Cell* get_cpp_obj() const { - return Yosys::RTLIL::Cell::get_all_cells()->at(this->id); + Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->id); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } }; @@ -47,15 +52,20 @@ namespace YOSYS_PYTHON { struct Wire { unsigned int id; + Yosys::RTLIL::Wire* ref_obj; Wire(Yosys::RTLIL::Wire* ref) { this->id = ref->hashidx_; + this->ref_obj = ref; } Yosys::RTLIL::Wire* get_cpp_obj() const { - return Yosys::RTLIL::Wire::get_all_wires()->at(this->id); + Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->id); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } }; @@ -71,15 +81,20 @@ namespace YOSYS_PYTHON { struct Module { unsigned int id; + Yosys::RTLIL::Module* ref_obj; Module(Yosys::RTLIL::Module* ref) { this->id = ref->hashidx_; + this->ref_obj = ref; } Yosys::RTLIL::Module* get_cpp_obj() const { - return Yosys::RTLIL::Module::get_all_modules()->at(this->id); + Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->id); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } boost::python::list get_cells() @@ -122,22 +137,28 @@ namespace YOSYS_PYTHON { struct Design { - unsigned int hashid; + unsigned int id; + Yosys::RTLIL::Design* ref_obj; Design(unsigned int hashid) { - this->hashid = hashid; + this->id = hashid; + this->ref_obj = Yosys::RTLIL::Design::get_all_designs()->at(this->id); } Design() { Yosys::RTLIL::Design* new_design = new Yosys::RTLIL::Design(); - this->hashid = new_design->hashidx_; + this->id = new_design->hashidx_; + this->ref_obj = new_design; } Yosys::RTLIL::Design* get_cpp_obj() { - return Yosys::RTLIL::Design::get_all_designs()->at(hashid); + Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->id); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } boost::python::list get_modules() @@ -264,7 +285,7 @@ namespace YOSYS_PYTHON { std::ostream &operator<<(std::ostream &ostr, const Design &design) { - ostr << "Design with id " << design.hashid; + ostr << "Design with id " << design.id; return ostr; } -- cgit v1.2.3 From bf7b73acfc2b5e46206e5688b8a6e8d9b0d60d8f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 13 Aug 2018 15:18:46 +0200 Subject: Added Wrappers for: -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h --- kernel/python_wrappers.cc | 3143 ++++++++++++++++++++++++++++++++++++++++++--- kernel/rtlil.cc | 32 +- kernel/rtlil.h | 14 +- 3 files changed, 2985 insertions(+), 204 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 1ba2c011a..18b0010ae 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -6,342 +6,2869 @@ #include #include #include +#include + +using namespace Yosys; namespace YOSYS_PYTHON { - struct Design; - struct Module; + struct IdString; + struct Const; + struct CaseRule; + struct SwitchRule; + struct SyncRule; + struct Process; + struct SigChunk; + struct SigBit; + struct SigSpec; struct Cell; struct Wire; + struct Memory; + struct Module; + struct Design; struct Monitor; + typedef Yosys::RTLIL::State State; void run(std::string command) { Yosys::run_pass(command); } - struct Cell + struct IdString { - unsigned int id; - Yosys::RTLIL::Cell* ref_obj; + Yosys::RTLIL::IdString* ref_obj; - Cell(Yosys::RTLIL::Cell* ref) + IdString(Yosys::RTLIL::IdString* ref = new Yosys::RTLIL::IdString()) { - this->id = ref->hashidx_; - this->ref_obj = ref; + this->ref_obj = new Yosys::RTLIL::IdString(*ref); } - - Yosys::RTLIL::Cell* get_cpp_obj() const + + ~IdString() { - Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->id); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; + delete(this->ref_obj); + } + + IdString(Yosys::RTLIL::IdString ref) + { + this->ref_obj = new Yosys::RTLIL::IdString(ref); + } + + IdString(const std::string &str) + { + this->ref_obj = new Yosys::RTLIL::IdString(str); } + + Yosys::RTLIL::IdString* get_cpp_obj() const + { + return ref_obj; + } + + //WRAPPED static inline int get_reference(int idx) + static inline int get_reference(int idx); + + //WRAPPED static inline void put_reference(int idx) + static inline void put_reference(int idx); + + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } + bool in_IdString(IdString *rhs); + + //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } + bool in_std_string(std::string rhs); }; - std::ostream &operator<<(std::ostream &ostr, const Cell &cell) + std::ostream &operator<<(std::ostream &ostr, const IdString &ref) { - if(cell.get_cpp_obj() != NULL) - ostr << "Cell with name " << cell.get_cpp_obj()->name.c_str(); - else - ostr << "deleted cell"; + ostr << ref.ref_obj->str(); return ostr; } - - struct Wire + struct Const { - unsigned int id; - Yosys::RTLIL::Wire* ref_obj; + Yosys::RTLIL::Const* ref_obj; - Wire(Yosys::RTLIL::Wire* ref) + Const(Yosys::RTLIL::Const* ref = new Yosys::RTLIL::Const()) { - this->id = ref->hashidx_; - this->ref_obj = ref; + this->ref_obj = new Yosys::RTLIL::Const(*ref); } - - Yosys::RTLIL::Wire* get_cpp_obj() const + + ~Const() { - Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->id); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; + delete(this->ref_obj); + } + + Const(Yosys::RTLIL::Const ref) + { + this->ref_obj = new Yosys::RTLIL::Const(ref); + } + + Yosys::RTLIL::Const* get_cpp_obj() const + { + return ref_obj; } + + //WRAPPED int as_int(bool is_signed = false) const; + int as_int(bool is_signed = false); + + //WRAPPED static Const from_string(std::string str); + static Const from_string(std::string str); + + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { + inline Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); }; - std::ostream &operator<<(std::ostream &ostr, const Wire &wire) + std::ostream &operator<<(std::ostream &ostr, const Const &ref) { - if(wire.get_cpp_obj() != NULL) - ostr << "Wire with name " << wire.get_cpp_obj()->name.c_str(); - else - ostr << "deleted wire"; + ostr << ref.ref_obj->as_string(); return ostr; } - - struct Module + struct CaseRule { - unsigned int id; - Yosys::RTLIL::Module* ref_obj; + Yosys::RTLIL::CaseRule* ref_obj; - Module(Yosys::RTLIL::Module* ref) + CaseRule(Yosys::RTLIL::CaseRule* ref = new Yosys::RTLIL::CaseRule()) { - this->id = ref->hashidx_; - this->ref_obj = ref; + this->ref_obj = ref->clone(); } - Yosys::RTLIL::Module* get_cpp_obj() const + ~CaseRule() { - Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->id); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; + delete(this->ref_obj); } - boost::python::list get_cells() + CaseRule(Yosys::RTLIL::CaseRule ref) { - Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); - boost::python::list result; - if(cpp_mod == NULL) - return result; - for(auto &cell_it : cpp_mod->cells_) - { - result.append(new Cell(cell_it.second)); - } - return result; + this->ref_obj = ref.clone(); } - boost::python::list get_wires() + Yosys::RTLIL::CaseRule* get_cpp_obj() const { - Yosys::RTLIL::Module* cpp_mod = this->get_cpp_obj(); - boost::python::list result; - if(cpp_mod == NULL) - return result; - for(auto &wire_it : cpp_mod->wires_) - { - result.append(new Wire(wire_it.second)); - } - return result; + return ref_obj; } - - void register_monitor(Monitor* const m); }; - std::ostream &operator<<(std::ostream &ostr, const Module &module) + std::ostream &operator<<(std::ostream &ostr, const CaseRule &ref) { - if(module.get_cpp_obj() != NULL) - ostr << "Module with name " << module.get_cpp_obj()->name.c_str(); - else - ostr << "deleted module"; + ostr << "CaseRule object at " << ref.ref_obj; return ostr; } - - struct Design + struct SwitchRule { - unsigned int id; - Yosys::RTLIL::Design* ref_obj; + Yosys::RTLIL::SwitchRule* ref_obj; - Design(unsigned int hashid) + SwitchRule(Yosys::RTLIL::SwitchRule* ref = new Yosys::RTLIL::SwitchRule()) { - this->id = hashid; - this->ref_obj = Yosys::RTLIL::Design::get_all_designs()->at(this->id); + this->ref_obj = ref->clone(); } - Design() + ~SwitchRule() { - Yosys::RTLIL::Design* new_design = new Yosys::RTLIL::Design(); - this->id = new_design->hashidx_; - this->ref_obj = new_design; + delete(this->ref_obj); } - Yosys::RTLIL::Design* get_cpp_obj() + SwitchRule(Yosys::RTLIL::SwitchRule ref) { - Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->id); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; + this->ref_obj = ref.clone(); } - boost::python::list get_modules() + Yosys::RTLIL::SwitchRule* get_cpp_obj() const { - Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); - boost::python::list result; - if(cpp_design == NULL) - { - return result; - } - for(auto &mod_it : cpp_design->modules_) - { - result.append(new Module(mod_it.second)); - } - return result; + return ref_obj; } + }; - void run(std::string command) + std::ostream &operator<<(std::ostream &ostr, const SwitchRule &ref) + { + ostr << "SwitchRule object at " << ref.ref_obj; + return ostr; + } + struct SyncRule + { + Yosys::RTLIL::SyncRule* ref_obj; + + SyncRule(Yosys::RTLIL::SyncRule* ref = new Yosys::RTLIL::SyncRule()) { - Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); - if(cpp_design != NULL) - Yosys::run_pass(command, cpp_design); + this->ref_obj = ref->clone(); } - void register_monitor(Monitor* const m); + ~SyncRule() + { + delete(this->ref_obj); + } + + SyncRule(Yosys::RTLIL::SyncRule ref) + { + this->ref_obj = ref.clone(); + } + + Yosys::RTLIL::SyncRule* get_cpp_obj() const + { + return ref_obj; + } }; - struct Monitor : public Yosys::RTLIL::Monitor + std::ostream &operator<<(std::ostream &ostr, const SyncRule &ref) + { + ostr << "SyncRule object at " << ref.ref_obj; + return ostr; + } + struct Process { + Yosys::RTLIL::Process* ref_obj; + + Process(Yosys::RTLIL::Process* ref = new Yosys::RTLIL::Process()) + { + this->ref_obj = ref->clone(); + } - virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE + ~Process() { - py_notify_module_add(new Module(module)); + delete(this->ref_obj); } - virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE + Process(Yosys::RTLIL::Process ref) { - py_notify_module_del(new Module(module)); + this->ref_obj = ref.clone(); } - virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE + Yosys::RTLIL::Process* get_cpp_obj() const { - //@TODO: Implement once necessary classes are wrapped + return ref_obj; } + }; + + std::ostream &operator<<(std::ostream &ostr, const Process &ref) + { + ostr << "Process with name " << ref.ref_obj->name.c_str(); + return ostr; + } + struct SigChunk + { + Yosys::RTLIL::SigChunk* ref_obj; - virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE + SigChunk(Yosys::RTLIL::SigChunk* ref = new Yosys::RTLIL::SigChunk()) { - //@TODO: Implement once necessary classes are wrapped + this->ref_obj = new Yosys::RTLIL::SigChunk(*ref); } - virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + ~SigChunk() { - //@TODO: Implement once necessary classes are wrapped + delete(this->ref_obj); } - virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE + SigChunk(Yosys::RTLIL::SigChunk ref) { - py_notify_blackout(new Module(module)); + this->ref_obj = new Yosys::RTLIL::SigChunk(ref); } - virtual void py_notify_module_add(Module*){}; - virtual void py_notify_module_del(Module*){}; - virtual void py_notify_blackout(Module*){}; + Yosys::RTLIL::SigChunk* get_cpp_obj() const + { + return ref_obj; + } + //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; + SigChunk extract(int offset, int length); }; - struct MonitorWrap : Monitor, boost::python::wrapper + std::ostream &operator<<(std::ostream &ostr, const SigChunk &ref) { - void py_notify_module_add(Module* m) + ostr << "SigChunk object at " << ref.ref_obj; + return ostr; + } + struct SigBit + { + Yosys::RTLIL::SigBit* ref_obj; + + SigBit(Yosys::RTLIL::SigBit* ref = new Yosys::RTLIL::SigBit()) + { + this->ref_obj = new Yosys::RTLIL::SigBit(*ref); + } + + ~SigBit() + { + delete(this->ref_obj); + } + + SigBit(Yosys::RTLIL::SigBit ref) { - if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) - py_notify_module_add(m); - else - Monitor::py_notify_module_add(m); + this->ref_obj = new Yosys::RTLIL::SigBit(ref); } - void default_py_notify_module_add(Module* m) + Yosys::RTLIL::SigBit* get_cpp_obj() const { - this->Monitor::py_notify_module_add(m); + return ref_obj; } + }; + + std::ostream &operator<<(std::ostream &ostr, const SigBit &ref) + { + ostr << "SigBit object at " << ref.ref_obj; + return ostr; + } + struct SigSpec + { + Yosys::RTLIL::SigSpec* ref_obj; - void py_notify_module_del(Module* m) + SigSpec(Yosys::RTLIL::SigSpec* ref = new Yosys::RTLIL::SigSpec()) { - if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) - py_notify_module_del(m); - else - Monitor::py_notify_module_del(m); + this->ref_obj = new Yosys::RTLIL::SigSpec(*ref); } - void default_py_notify_module_del(Module* m) + ~SigSpec() { - this->Monitor::py_notify_module_del(m); + delete(this->ref_obj); } - void py_notify_blackout(Module* m) + SigSpec(Yosys::RTLIL::SigSpec ref) { - if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) - py_notify_blackout(m); - else - Monitor::py_notify_blackout(m); + this->ref_obj = new Yosys::RTLIL::SigSpec(ref); } - void default_py_notify_blackout(Module* m) + Yosys::RTLIL::SigSpec* get_cpp_obj() const { - this->Monitor::py_notify_blackout(m); + return ref_obj; } + + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); + void replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with); + + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; + void replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other); + + //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); + void replace_int_SigSpec(int offset, SigSpec *with); + + //WRAPPED void remove(const RTLIL::SigSpec &pattern); + void remove_SigSpec(SigSpec *pattern); + + //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; + void remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); + + //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); + void remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); + + //WRAPPED void remove(const pool &pattern); + void remove_pool_SigBit(boost::python::list *pattern); + + //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; + void remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + + //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); + void remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + + //WRAPPED void remove(int offset, int length = 1); + void remove_int_int(int offset, int length = 1); + + //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; + SigSpec extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); + + //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; + SigSpec extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + + //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; + SigSpec extract_int_int(int offset, int length = 1); + + //WRAPPED void append(const RTLIL::SigSpec &signal); + void append(SigSpec *signal); + + //WRAPPED void append_bit(const RTLIL::SigBit &bit); + void append_bit(SigBit *bit); + + //WRAPPED void extend_u0(int width, bool is_signed = false); + void extend_u0(int width, bool is_signed = false); + + //WRAPPED RTLIL::SigSpec repeat(int num) const; + SigSpec repeat(int num); + + //WRAPPED int as_int(bool is_signed = false) const; + int as_int(bool is_signed = false); + + //WRAPPED bool match(std::string pattern) const; + bool match(std::string pattern); + + //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + static bool parse(SigSpec *sig, Module *module, std::string str); + + //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); + static bool parse_sel(SigSpec *sig, Design *design, Module *module, std::string str); + + //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + static bool parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str); }; - void Design::register_monitor(Monitor* const m) + std::ostream &operator<<(std::ostream &ostr, const SigSpec &ref) { - Yosys::RTLIL::Design* cpp_design = this->get_cpp_obj(); - if(cpp_design == NULL) - return; - cpp_design->monitors.insert(m); + ostr << "SigSpec object at " << ref.ref_obj; + return ostr; } - - void Module::register_monitor(Monitor* const m) + struct Cell { - Yosys::RTLIL::Module* cpp_design = this->get_cpp_obj(); - if(cpp_design == NULL) - return; - cpp_design->monitors.insert(m); - } + unsigned int hashidx_; + Yosys::RTLIL::Cell* ref_obj; + + Cell(Yosys::RTLIL::Cell* ref) + { + this->hashidx_ = ref->hashidx_; + this->ref_obj = ref; + } + + Yosys::RTLIL::Cell* get_cpp_obj() const + { + Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->hashidx_); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; + } + + //WRAPPED bool hasPort(RTLIL::IdString portname) const; + bool hasPort(IdString *portname); + + //WRAPPED void unsetPort(RTLIL::IdString portname); + void unsetPort(IdString *portname); + + //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); + void setPort(IdString *portname, SigSpec *signal); + + //WRAPPED bool input(RTLIL::IdString portname) const; + bool input(IdString *portname); + + //WRAPPED bool output(RTLIL::IdString portname) const; + bool output(IdString *portname); + + //WRAPPED bool hasParam(RTLIL::IdString paramname) const; + bool hasParam(IdString *paramname); + + //WRAPPED void unsetParam(RTLIL::IdString paramname); + void unsetParam(IdString *paramname); + + //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); + void setParam(IdString *paramname, Const *value); - std::ostream &operator<<(std::ostream &ostr, const Design &design) + //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + }; + + std::ostream &operator<<(std::ostream &ostr, const Cell &ref) { - ostr << "Design with id " << design.id; + if(ref.get_cpp_obj() != NULL) + ostr << "Cell with name " << ref.get_cpp_obj()->name.c_str(); + else + ostr << "deleted Cell"; return ostr; } - - unsigned int get_active_design_id() + struct Wire { - Yosys::RTLIL::Design* active_design = Yosys::yosys_get_design(); - if(active_design != NULL) + unsigned int hashidx_; + Yosys::RTLIL::Wire* ref_obj; + + Wire(Yosys::RTLIL::Wire* ref) { - return active_design->hashidx_; + this->hashidx_ = ref->hashidx_; + this->ref_obj = ref; } - return 0; - } - struct Initializer - { - Initializer() { - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; - Yosys::yosys_setup(); - Yosys::yosys_banner(); + Yosys::RTLIL::Wire* get_cpp_obj() const + { + Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->hashidx_); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } + }; - Initializer(Initializer const &) {} + std::ostream &operator<<(std::ostream &ostr, const Wire &ref) + { + if(ref.get_cpp_obj() != NULL) + ostr << "Wire with name " << ref.get_cpp_obj()->name.c_str(); + else + ostr << "deleted Wire"; + return ostr; + } + struct Memory + { + unsigned int hashidx_; + Yosys::RTLIL::Memory* ref_obj; - ~Initializer() { - Yosys::yosys_shutdown(); + Memory(Yosys::RTLIL::Memory* ref) + { + this->hashidx_ = ref->hashidx_; + this->ref_obj = ref; + } + + Yosys::RTLIL::Memory* get_cpp_obj() const + { + Yosys::RTLIL::Memory* ret = Yosys::RTLIL::Memory::get_all_memorys()->at(this->hashidx_); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; } }; - BOOST_PYTHON_MODULE(libyosys) + std::ostream &operator<<(std::ostream &ostr, const Memory &ref) { - using namespace boost::python; + if(ref.get_cpp_obj() != NULL) + ostr << "Memory with name " << ref.get_cpp_obj()->name.c_str(); + else + ostr << "deleted Memory"; + return ostr; + } + struct Module + { + unsigned int hashidx_; + Yosys::RTLIL::Module* ref_obj; - class_("Initializer"); - scope().attr("_hidden") = new Initializer(); + Module(Yosys::RTLIL::Module* ref = new Yosys::RTLIL::Module()) + { + this->hashidx_ = ref->hashidx_; + this->ref_obj = ref; + } - class_("Design", init()) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def(init<>()) - .def("get_modules", &Design::get_modules) - .def("run",&Design::run) - .def("register_monitor", &Design::register_monitor) - ; + Yosys::RTLIL::Module* get_cpp_obj() const + { + Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->hashidx_); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; + } - class_("Module", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) + boost::python::list get_cells() + { + Yosys::RTLIL::Module* cpp_obj = get_cpp_obj(); + boost::python::list result; + if(cpp_obj == NULL) + { + return result; + } + for(auto &mod_it : cpp_obj->cells_) + { + result.append(new Cell(mod_it.second)); + } + return result; + } + + boost::python::list get_wires() + { + Yosys::RTLIL::Module* cpp_obj = get_cpp_obj(); + boost::python::list result; + if(cpp_obj == NULL) + { + return result; + } + for(auto &mod_it : cpp_obj->wires_) + { + result.append(new Wire(mod_it.second)); + } + return result; + } + + void register_monitor(Monitor* const m); + + //WRAPPED void connect(const RTLIL::SigSig &conn); + void connect_SigSig(PyObject *conn); + + //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + void connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs); + + //WRAPPED void new_connections(const std::vector &new_conn); + void new_connections(boost::python::list *new_conn); + + //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; + void cloneInto(Module *new_mod); + + //WRAPPED void remove(const pool &wires); + void remove_pool_Wire(boost::python::list *wires); + + //WRAPPED void remove(RTLIL::Cell *cell); + void remove_Cell(Cell *cell); + + //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); + void rename_Wire_IdString(Wire *wire, IdString *new_name); + + //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); + void rename_Cell_IdString(Cell *cell, IdString *new_name); + + //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + void rename_IdString_IdString(IdString *old_name, IdString *new_name); + + //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); + void swap_names_Wire_Wire(Wire *w1, Wire *w2); + + //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + void swap_names_Cell_Cell(Cell *c1, Cell *c2); + + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); + IdString uniquify_IdString(IdString *name); + + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); + IdString uniquify_IdString_int(IdString *name, int index); + + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + Wire addWire_IdString_int(IdString *name, int width = 1); + + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + Wire addWire_IdString_Wire(IdString *name, Wire *other); + + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + Cell addCell_IdString_IdString(IdString *name, IdString *type); + + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + Cell addCell_IdString_Cell(IdString *name, Cell *other); + + //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + Cell addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed = false, bool b_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); + Cell addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src = ""); + + //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); + Cell addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src = ""); + + //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); + + //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + Cell addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + Cell addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + Cell addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + Cell addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = ""); + + //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + Cell addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + Cell addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + Cell addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + Cell addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Not(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Pos(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Neg(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec LogicNot(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + SigSpec Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + SigSpec Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = ""); + + //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + SigBit BufGate(IdString *name, SigBit *sig_a, std::string src = ""); + + //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + SigBit NotGate(IdString *name, SigBit *sig_a, std::string src = ""); + + //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); + + //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); + SigBit MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src = ""); + + //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + SigBit Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = ""); + + //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + SigBit Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = ""); + + //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + SigBit Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = ""); + + //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + SigBit Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Anyconst(IdString *name, int width = 1, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Anyseq(IdString *name, int width = 1, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Allconst(IdString *name, int width = 1, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Allseq(IdString *name, int width = 1, std::string src = ""); + + //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); + SigSpec Initstate(IdString *name, std::string src = ""); + }; + + std::ostream &operator<<(std::ostream &ostr, const Module &ref) + { + if(ref.get_cpp_obj() != NULL) + ostr << "Module with name " << ref.get_cpp_obj()->name.c_str(); + else + ostr << "deleted Module"; + return ostr; + } + struct Design + { + unsigned int hashidx_; + Yosys::RTLIL::Design* ref_obj; + + Design(Yosys::RTLIL::Design* ref = new Yosys::RTLIL::Design()) + { + this->hashidx_ = ref->hashidx_; + this->ref_obj = ref; + } + + Yosys::RTLIL::Design* get_cpp_obj() const + { + Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->hashidx_); + if(ret != NULL && ret == this->ref_obj) + return ret; + return NULL; + } + + boost::python::list get_modules() + { + Yosys::RTLIL::Design* cpp_obj = get_cpp_obj(); + boost::python::list result; + if(cpp_obj == NULL) + { + return result; + } + for(auto &mod_it : cpp_obj->modules_) + { + result.append(new Module(mod_it.second)); + } + return result; + } + + void run(std::string command) + { + Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); + if(cpp_design != NULL) + Yosys::run_pass(command, cpp_design); + + } + + void register_monitor(Monitor* const m); + + //WRAPPED RTLIL::Module *module(RTLIL::IdString name); + Module module(IdString *name); + + //WRAPPED bool has(RTLIL::IdString id) const { + bool has(IdString *id); + + //WRAPPED void add(RTLIL::Module *module); + void add(Module *module); + + //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); + Module addModule(IdString *name); + + //WRAPPED void remove(RTLIL::Module *module); + void remove(Module *module); + + //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); + void rename(Module *module, IdString *new_name); + + //WRAPPED void scratchpad_unset(std::string varname); + void scratchpad_unset(std::string varname); + + //WRAPPED void scratchpad_set_int(std::string varname, int value); + void scratchpad_set_int(std::string varname, int value); + + //WRAPPED void scratchpad_set_bool(std::string varname, bool value); + void scratchpad_set_bool(std::string varname, bool value); + + //WRAPPED void scratchpad_set_string(std::string varname, std::string value); + void scratchpad_set_string(std::string varname, std::string value); + + //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; + int scratchpad_get_int(std::string varname, int default_value = 0); + + //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; + bool scratchpad_get_bool(std::string varname, bool default_value = false); + + //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()); + + //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; + bool selected_module_IdString(IdString *mod_name); + + //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; + bool selected_whole_module_IdString(IdString *mod_name); + + //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + bool selected_member(IdString *mod_name, IdString *memb_name); + + //WRAPPED bool selected_module(RTLIL::Module *mod) const; + bool selected_module_Module(Module *mod); + + //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; + bool selected_whole_module_Module(Module *mod); + }; + + std::ostream &operator<<(std::ostream &ostr, const Design &ref) + { + if(ref.get_cpp_obj() != NULL) + ostr << "Design with identifier " << ref.hashidx_; + else + ostr << "deleted Design"; + return ostr; + } + + //WRAPPED static inline std::string escape_id(std::string str) { + inline std::string escape_id(std::string str) + { + return Yosys::RTLIL::escape_id(str); + } + + //WRAPPED static inline std::string unescape_id(std::string str) { + inline std::string unescape_id_std_string(std::string str) + { + return Yosys::RTLIL::unescape_id(str); + } + + //WRAPPED static inline std::string unescape_id(RTLIL::IdString str) { + inline std::string unescape_id_IdString(IdString *str) + { + return Yosys::RTLIL::unescape_id(*str->get_cpp_obj()); + } + + //WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_reduce_bool(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_reduce_bool(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_logic_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_logic_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_logic_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_logic_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_logic_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_logic_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_shl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_shl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_shr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_shr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_sshl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_sshl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_sshr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_sshr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_shift(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_shift(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_shiftx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_shiftx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_lt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_lt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_le(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_le(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_eq(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_eq(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_ne(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_ne(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_eqx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_eqx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_nex(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_nex(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_ge(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_ge(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_gt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_gt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_add(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_add(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_sub(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_sub(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_mul(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_mul(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_div(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_div(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_mod(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_mod(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_pow(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_pow(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_pos(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_pos(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + //WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + Const const_neg(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) + { + return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); + } + + struct Monitor : public Yosys::RTLIL::Monitor + { + + virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_add(new Module(module)); + } + + virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_del(new Module(module)); + } + + virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE + { + Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); + Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); + py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig)); + delete tmp_port; + delete tmp_old_sig; + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE + { + Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); + Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); + py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second))); + delete first; + delete second; + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + { + boost::python::list sigsig_list; + for(auto sigsig : sigsig_vec) + sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second))); + py_notify_connect_list(new Module(module), sigsig_list); + } + + virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_blackout(new Module(module)); + } + + virtual void py_notify_module_add(Module*){}; + virtual void py_notify_module_del(Module*){}; + virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){}; + virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; + virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; + virtual void py_notify_blackout(Module*){}; + }; + + struct MonitorWrap : Monitor, boost::python::wrapper + { + void py_notify_module_add(Module* m) + { + if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) + py_notify_module_add(m); + else + Monitor::py_notify_module_add(m); + } + + void default_py_notify_module_add(Module* m) + { + this->Monitor::py_notify_module_add(m); + } + + void py_notify_module_del(Module* m) + { + if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) + py_notify_module_del(m); + else + Monitor::py_notify_module_del(m); + } + + void default_py_notify_module_del(Module* m) + { + this->Monitor::py_notify_module_del(m); + } + + void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + { + if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) + py_notify_connect_cell(cell, port, old_sig, sig); + else + Monitor::py_notify_connect_cell(cell, port, old_sig, sig); + } + + void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + { + this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); + } + + void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + { + if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) + py_notify_connect_tuple(module, sigsig); + else + Monitor::py_notify_connect_tuple(module, sigsig); + } + + void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + { + this->Monitor::py_notify_connect_tuple(module, sigsig); + } + + void py_notify_connect_list(Module* module, boost::python::list sigsig_list) + { + if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) + py_notify_connect_list(module, sigsig_list); + else + Monitor::py_notify_connect_list(module, sigsig_list); + } + + void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list) + { + this->Monitor::py_notify_connect_list(module, sigsig_list); + } + + void py_notify_blackout(Module* m) + { + if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) + py_notify_blackout(m); + else + Monitor::py_notify_blackout(m); + } + + void default_py_notify_blackout(Module* m) + { + this->Monitor::py_notify_blackout(m); + } + }; + + void Module::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Module* cpp_module = this->get_cpp_obj(); + if(cpp_module == NULL) + return; + cpp_module->monitors.insert(m); + } + + void Design::register_monitor(Monitor* const m) + { + Yosys::RTLIL::Design* cpp_design = this->get_cpp_obj(); + if(cpp_design == NULL) + return; + cpp_design->monitors.insert(m); + } + + //WRAPPED static inline int get_reference(int idx) + inline int IdString::get_reference(int idx) + { + return Yosys::RTLIL::IdString::get_reference(idx); + } + + //WRAPPED static inline void put_reference(int idx) + inline void IdString::put_reference(int idx) + { + Yosys::RTLIL::IdString::put_reference(idx); + } + + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } + bool IdString::in_IdString(IdString *rhs) + { + return this->get_cpp_obj()->in(*rhs->get_cpp_obj()); + } + + //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } + bool IdString::in_std_string(std::string rhs) + { + return this->get_cpp_obj()->in(rhs); + } + + //WRAPPED int as_int(bool is_signed = false) const; + int Const::as_int(bool is_signed) + { + return this->get_cpp_obj()->as_int(is_signed); + } + + //WRAPPED static Const from_string(std::string str); + Const Const::from_string(std::string str) + { + return Const(Yosys::RTLIL::Const::from_string(str)); + } + + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { + inline Const Const::extract(int offset, int len, State padding) + { + return Const(this->get_cpp_obj()->extract(offset, len, padding)); + } + + //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; + SigChunk SigChunk::extract(int offset, int length) + { + return SigChunk(this->get_cpp_obj()->extract(offset, length)); + } + + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); + void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with) + { + this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj()); + } + + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; + void SigSpec::replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other) + { + this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj(), other->get_cpp_obj()); + } + + //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); + void SigSpec::replace_int_SigSpec(int offset, SigSpec *with) + { + this->get_cpp_obj()->replace(offset, *with->get_cpp_obj()); + } + + //WRAPPED void remove(const RTLIL::SigSpec &pattern); + void SigSpec::remove_SigSpec(SigSpec *pattern) + { + this->get_cpp_obj()->remove(*pattern->get_cpp_obj()); + } + + //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; + void SigSpec::remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) + { + this->get_cpp_obj()->remove(*pattern->get_cpp_obj(), other->get_cpp_obj()); + } + + //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); + void SigSpec::remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) + { + this->get_cpp_obj()->remove2(*pattern->get_cpp_obj(), other->get_cpp_obj()); + } + + //WRAPPED void remove(const pool &pattern); + void SigSpec::remove_pool_SigBit(boost::python::list *pattern) + { + pool pattern_; + for(int i = 0; i < len(*pattern); ++i) + { + } + this->get_cpp_obj()->remove(pattern_); + } + + //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; + void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + { + pool pattern_; + for(int i = 0; i < len(*pattern); ++i) + { + } + this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj()); + } + + //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); + void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + { + pool pattern_; + for(int i = 0; i < len(*pattern); ++i) + { + } + this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj()); + } + + //WRAPPED void remove(int offset, int length = 1); + void SigSpec::remove_int_int(int offset, int length) + { + this->get_cpp_obj()->remove(offset, length); + } + + //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; + SigSpec SigSpec::extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) + { + return SigSpec(this->get_cpp_obj()->extract(*pattern->get_cpp_obj(), other->get_cpp_obj())); + } + + //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; + SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + { + pool pattern_; + for(int i = 0; i < len(*pattern); ++i) + { + } + return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj())); + } + + //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; + SigSpec SigSpec::extract_int_int(int offset, int length) + { + return SigSpec(this->get_cpp_obj()->extract(offset, length)); + } + + //WRAPPED void append(const RTLIL::SigSpec &signal); + void SigSpec::append(SigSpec *signal) + { + this->get_cpp_obj()->append(*signal->get_cpp_obj()); + } + + //WRAPPED void append_bit(const RTLIL::SigBit &bit); + void SigSpec::append_bit(SigBit *bit) + { + this->get_cpp_obj()->append_bit(*bit->get_cpp_obj()); + } + + //WRAPPED void extend_u0(int width, bool is_signed = false); + void SigSpec::extend_u0(int width, bool is_signed) + { + this->get_cpp_obj()->extend_u0(width, is_signed); + } + + //WRAPPED RTLIL::SigSpec repeat(int num) const; + SigSpec SigSpec::repeat(int num) + { + return SigSpec(this->get_cpp_obj()->repeat(num)); + } + + //WRAPPED int as_int(bool is_signed = false) const; + int SigSpec::as_int(bool is_signed) + { + return this->get_cpp_obj()->as_int(is_signed); + } + + //WRAPPED bool match(std::string pattern) const; + bool SigSpec::match(std::string pattern) + { + return this->get_cpp_obj()->match(pattern); + } + + //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + bool SigSpec::parse(SigSpec *sig, Module *module, std::string str) + { + return Yosys::RTLIL::SigSpec::parse(*sig->get_cpp_obj(), module->get_cpp_obj(), str); + } + + //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); + bool SigSpec::parse_sel(SigSpec *sig, Design *design, Module *module, std::string str) + { + return Yosys::RTLIL::SigSpec::parse_sel(*sig->get_cpp_obj(), design->get_cpp_obj(), module->get_cpp_obj(), str); + } + + //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + bool SigSpec::parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str) + { + return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); + } + + //WRAPPED bool hasPort(RTLIL::IdString portname) const; + bool Cell::hasPort(IdString *portname) + { + return this->get_cpp_obj()->hasPort(*portname->get_cpp_obj()); + } + + //WRAPPED void unsetPort(RTLIL::IdString portname); + void Cell::unsetPort(IdString *portname) + { + this->get_cpp_obj()->unsetPort(*portname->get_cpp_obj()); + } + + //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); + void Cell::setPort(IdString *portname, SigSpec *signal) + { + this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj()); + } + + //WRAPPED bool input(RTLIL::IdString portname) const; + bool Cell::input(IdString *portname) + { + return this->get_cpp_obj()->input(*portname->get_cpp_obj()); + } + + //WRAPPED bool output(RTLIL::IdString portname) const; + bool Cell::output(IdString *portname) + { + return this->get_cpp_obj()->output(*portname->get_cpp_obj()); + } + + //WRAPPED bool hasParam(RTLIL::IdString paramname) const; + bool Cell::hasParam(IdString *paramname) + { + return this->get_cpp_obj()->hasParam(*paramname->get_cpp_obj()); + } + + //WRAPPED void unsetParam(RTLIL::IdString paramname); + void Cell::unsetParam(IdString *paramname) + { + this->get_cpp_obj()->unsetParam(*paramname->get_cpp_obj()); + } + + //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); + void Cell::setParam(IdString *paramname, Const *value) + { + this->get_cpp_obj()->setParam(*paramname->get_cpp_obj(), *value->get_cpp_obj()); + } + + //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + void Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) + { + this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed); + } + + //WRAPPED void connect(const RTLIL::SigSig &conn); + void Module::connect_SigSig(PyObject* conn) + { + if(!PyTuple_Check(conn) or PyTuple_Size(conn) != 2) + throw std::logic_error("Tuple of two SigSpecs required"); + SigSpec conn_sp0 = boost::python::extract(PyTuple_GetItem(conn, 0)); + SigSpec conn_sp1 = boost::python::extract(PyTuple_GetItem(conn, 1)); + Yosys::RTLIL::SigSig conn_(conn_sp0.get_cpp_obj(), conn_sp1.get_cpp_obj()); + this->get_cpp_obj()->connect(conn_); + } + + //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + void Module::connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs) + { + this->get_cpp_obj()->connect(*lhs->get_cpp_obj(), *rhs->get_cpp_obj()); + } + + //WRAPPED void new_connections(const std::vector &new_conn); + void Module::new_connections(boost::python::list *new_conn) + { + std::vector new_conn_; + for(int i = 0; i < len(*new_conn); ++i) + { + } + this->get_cpp_obj()->new_connections(new_conn_); + } + + //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; + void Module::cloneInto(Module *new_mod) + { + this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj()); + } + + //WRAPPED void remove(const pool &wires); + void Module::remove_pool_Wire(boost::python::list *wires) + { + pool wires_; + for(int i = 0; i < len(*wires); ++i) + { + } + this->get_cpp_obj()->remove(wires_); + } + + //WRAPPED void remove(RTLIL::Cell *cell); + void Module::remove_Cell(Cell *cell) + { + this->get_cpp_obj()->remove(cell->get_cpp_obj()); + } + + //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); + void Module::rename_Wire_IdString(Wire *wire, IdString *new_name) + { + this->get_cpp_obj()->rename(wire->get_cpp_obj(), *new_name->get_cpp_obj()); + } + + //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); + void Module::rename_Cell_IdString(Cell *cell, IdString *new_name) + { + this->get_cpp_obj()->rename(cell->get_cpp_obj(), *new_name->get_cpp_obj()); + } + + //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + void Module::rename_IdString_IdString(IdString *old_name, IdString *new_name) + { + this->get_cpp_obj()->rename(*old_name->get_cpp_obj(), *new_name->get_cpp_obj()); + } + + //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); + void Module::swap_names_Wire_Wire(Wire *w1, Wire *w2) + { + this->get_cpp_obj()->swap_names(w1->get_cpp_obj(), w2->get_cpp_obj()); + } + + //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + void Module::swap_names_Cell_Cell(Cell *c1, Cell *c2) + { + this->get_cpp_obj()->swap_names(c1->get_cpp_obj(), c2->get_cpp_obj()); + } + + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); + IdString Module::uniquify_IdString(IdString *name) + { + return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj())); + } + + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); + IdString Module::uniquify_IdString_int(IdString *name, int index) + { + return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj(), index)); + } + + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + Wire Module::addWire_IdString_int(IdString *name, int width) + { + return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), width)); + } + + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + Wire Module::addWire_IdString_Wire(IdString *name, Wire *other) + { + return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), other->get_cpp_obj())); + } + + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + Cell Module::addCell_IdString_IdString(IdString *name, IdString *type) + { + return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), *type->get_cpp_obj())); + } + + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + Cell Module::addCell_IdString_Cell(IdString *name, Cell *other) + { + return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), other->get_cpp_obj())); + } + + //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addPos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addNeg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addShl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addShr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addSshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addSshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addShift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addShiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addEq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addNe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addEqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addNex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addGe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addGt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addAdd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addSub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addMul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addDiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addMod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + Cell Module::addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed, bool b_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addPow(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), a_signed, b_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + Cell Module::addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) + { + return Cell(this->get_cpp_obj()->addLogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addMux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addPmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); + Cell Module::addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src) + { + return Cell(this->get_cpp_obj()->addSlice(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *offset->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addConcat(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); + Cell Module::addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src) + { + return Cell(this->get_cpp_obj()->addLut(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *lut->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addTribuf(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addAssert(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addAssume(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addLive(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addFair(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + Cell Module::addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) + { + return Cell(this->get_cpp_obj()->addCover(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + Cell Module::addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addEquiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell Module::addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addSr(*name->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_q->get_cpp_obj(), set_polarity, clr_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + Cell Module::addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) + { + return Cell(this->get_cpp_obj()->addFf(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + Cell Module::addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + Cell Module::addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addBufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addNotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addAndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addNandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addOrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addNorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addXorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addXnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addAndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addOrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addMuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addAoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addOai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addAoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + Cell Module::addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) + { + return Cell(this->get_cpp_obj()->addOai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + Cell Module::addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) + { + return Cell(this->get_cpp_obj()->addFfGate(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + Cell Module::addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + Cell Module::addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); + } + + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Not(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Pos(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Pos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Neg(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Neg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->And(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Or(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Xor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Xnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->ReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Shl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Shr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Sshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Sshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Shift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Shiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Lt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Le(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Eq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Ne(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Eqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Nex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Ge(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Gt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Add(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Sub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Mul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Div(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->Mod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + SigSpec Module::LogicNot(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->LogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->LogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + SigSpec Module::LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) + { + return SigSpec(this->get_cpp_obj()->LogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); + } + + //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + SigSpec Module::Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) + { + return SigSpec(this->get_cpp_obj()->Mux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + SigSpec Module::Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) + { + return SigSpec(this->get_cpp_obj()->Pmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + SigBit Module::BufGate(IdString *name, SigBit *sig_a, std::string src) + { + return SigBit(this->get_cpp_obj()->BufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + SigBit Module::NotGate(IdString *name, SigBit *sig_a, std::string src) + { + return SigBit(this->get_cpp_obj()->NotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->AndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->NandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->OrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->NorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->XorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->XnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->AndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + SigBit Module::OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) + { + return SigBit(this->get_cpp_obj()->OrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); + SigBit Module::MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src) + { + return SigBit(this->get_cpp_obj()->MuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + SigBit Module::Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) + { + return SigBit(this->get_cpp_obj()->Aoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + SigBit Module::Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) + { + return SigBit(this->get_cpp_obj()->Oai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + SigBit Module::Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) + { + return SigBit(this->get_cpp_obj()->Aoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + SigBit Module::Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) + { + return SigBit(this->get_cpp_obj()->Oai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Module::Anyconst(IdString *name, int width, std::string src) + { + return SigSpec(this->get_cpp_obj()->Anyconst(*name->get_cpp_obj(), width, src)); + } + + //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Module::Anyseq(IdString *name, int width, std::string src) + { + return SigSpec(this->get_cpp_obj()->Anyseq(*name->get_cpp_obj(), width, src)); + } + + //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Module::Allconst(IdString *name, int width, std::string src) + { + return SigSpec(this->get_cpp_obj()->Allconst(*name->get_cpp_obj(), width, src)); + } + + //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + SigSpec Module::Allseq(IdString *name, int width, std::string src) + { + return SigSpec(this->get_cpp_obj()->Allseq(*name->get_cpp_obj(), width, src)); + } + + //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); + SigSpec Module::Initstate(IdString *name, std::string src) + { + return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src)); + } + + //WRAPPED RTLIL::Module *module(RTLIL::IdString name); + Module Design::module(IdString *name) + { + return Module(this->get_cpp_obj()->module(*name->get_cpp_obj())); + } + + //WRAPPED bool has(RTLIL::IdString id) const { + bool Design::has(IdString *id) + { + return this->get_cpp_obj()->has(*id->get_cpp_obj()); + } + + //WRAPPED void add(RTLIL::Module *module); + void Design::add(Module *module) + { + this->get_cpp_obj()->add(module->get_cpp_obj()); + } + + //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); + Module Design::addModule(IdString *name) + { + return Module(this->get_cpp_obj()->addModule(*name->get_cpp_obj())); + } + + //WRAPPED void remove(RTLIL::Module *module); + void Design::remove(Module *module) + { + this->get_cpp_obj()->remove(module->get_cpp_obj()); + } + + //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); + void Design::rename(Module *module, IdString *new_name) + { + this->get_cpp_obj()->rename(module->get_cpp_obj(), *new_name->get_cpp_obj()); + } + + //WRAPPED void scratchpad_unset(std::string varname); + void Design::scratchpad_unset(std::string varname) + { + this->get_cpp_obj()->scratchpad_unset(varname); + } + + //WRAPPED void scratchpad_set_int(std::string varname, int value); + void Design::scratchpad_set_int(std::string varname, int value) + { + this->get_cpp_obj()->scratchpad_set_int(varname, value); + } + + //WRAPPED void scratchpad_set_bool(std::string varname, bool value); + void Design::scratchpad_set_bool(std::string varname, bool value) + { + this->get_cpp_obj()->scratchpad_set_bool(varname, value); + } + + //WRAPPED void scratchpad_set_string(std::string varname, std::string value); + void Design::scratchpad_set_string(std::string varname, std::string value) + { + this->get_cpp_obj()->scratchpad_set_string(varname, value); + } + + //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; + int Design::scratchpad_get_int(std::string varname, int default_value) + { + return this->get_cpp_obj()->scratchpad_get_int(varname, default_value); + } + + //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; + bool Design::scratchpad_get_bool(std::string varname, bool default_value) + { + return this->get_cpp_obj()->scratchpad_get_bool(varname, default_value); + } + + //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + std::string Design::scratchpad_get_string(std::string varname, std::string default_value) + { + return this->get_cpp_obj()->scratchpad_get_string(varname, default_value); + } + + //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; + bool Design::selected_module_IdString(IdString *mod_name) + { + return this->get_cpp_obj()->selected_module(*mod_name->get_cpp_obj()); + } + + //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; + bool Design::selected_whole_module_IdString(IdString *mod_name) + { + return this->get_cpp_obj()->selected_whole_module(*mod_name->get_cpp_obj()); + } + + //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + bool Design::selected_member(IdString *mod_name, IdString *memb_name) + { + return this->get_cpp_obj()->selected_member(*mod_name->get_cpp_obj(), *memb_name->get_cpp_obj()); + } + + //WRAPPED bool selected_module(RTLIL::Module *mod) const; + bool Design::selected_module_Module(Module *mod) + { + return this->get_cpp_obj()->selected_module(mod->get_cpp_obj()); + } + + //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; + bool Design::selected_whole_module_Module(Module *mod) + { + return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj()); + } + + struct Initializer + { + Initializer() { + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + Yosys::yosys_setup(); + Yosys::yosys_banner(); + } + + Initializer(Initializer const &) {} + + ~Initializer() { + Yosys::yosys_shutdown(); + } + }; + + BOOST_PYTHON_MODULE(libyosys) + { + using namespace boost::python; + + enum_("State") + .value("S0",Yosys::RTLIL::S0) + .value("S1",Yosys::RTLIL::S1) + .value("Sx",Yosys::RTLIL::Sx) + .value("Sz",Yosys::RTLIL::Sz) + .value("Sa",Yosys::RTLIL::Sa) + .value("Sm",Yosys::RTLIL::Sm) + ; + + enum_("SyncType") + .value("ST0",Yosys::RTLIL::ST0) + .value("ST1",Yosys::RTLIL::ST1) + .value("STp",Yosys::RTLIL::STp) + .value("STn",Yosys::RTLIL::STn) + .value("STe",Yosys::RTLIL::STe) + .value("STa",Yosys::RTLIL::STa) + .value("STg",Yosys::RTLIL::STg) + .value("STi",Yosys::RTLIL::STi) + ; + + enum_("ConstFlags") + .value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE) + .value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING) + .value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED) + .value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL) + ; + + class_("Monitor") + .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) + .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) + .def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell) + .def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple) + .def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list) + .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + ; + + class_("Initializer"); + scope().attr("_hidden") = new Initializer(); + + class_("IdString") + .def(init()) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_cells", &Module::get_cells) - .def("get_wires", &Module::get_wires) - .def("register_monitor", &Module::register_monitor) + .def("get_reference", &IdString::get_reference) + .def("put_reference", &IdString::put_reference) + .def("in_IdString", &IdString::in_IdString) + .def("in_std_string", &IdString::in_std_string) + ; + + class_("Const") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("as_int", &Const::as_int) + .def("from_string", &Const::from_string) + .def("extract", &Const::extract) + ; + + class_("CaseRule") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("SwitchRule") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("SyncRule") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("Process") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("SigChunk") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("extract", &SigChunk::extract) + ; + + class_("SigBit") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("SigSpec") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec) + .def("replace_SigSpec_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec_SigSpec) + .def("replace_int_SigSpec", &SigSpec::replace_int_SigSpec) + .def("remove_SigSpec", &SigSpec::remove_SigSpec) + .def("remove_SigSpec_SigSpec", &SigSpec::remove_SigSpec_SigSpec) + .def("remove2_SigSpec_SigSpec", &SigSpec::remove2_SigSpec_SigSpec) + .def("remove_pool_SigBit", &SigSpec::remove_pool_SigBit) + .def("remove_pool_SigBit_SigSpec", &SigSpec::remove_pool_SigBit_SigSpec) + .def("remove2_pool_SigBit_SigSpec", &SigSpec::remove2_pool_SigBit_SigSpec) + .def("remove_int_int", &SigSpec::remove_int_int) + .def("extract_SigSpec_SigSpec", &SigSpec::extract_SigSpec_SigSpec) + .def("extract_pool_SigBit_SigSpec", &SigSpec::extract_pool_SigBit_SigSpec) + .def("extract_int_int", &SigSpec::extract_int_int) + .def("append", &SigSpec::append) + .def("append_bit", &SigSpec::append_bit) + .def("extend_u0", &SigSpec::extend_u0) + .def("repeat", &SigSpec::repeat) + .def("as_int", &SigSpec::as_int) + .def("match", &SigSpec::match) + .def("parse", &SigSpec::parse) + .def("parse_sel", &SigSpec::parse_sel) + .def("parse_rhs", &SigSpec::parse_rhs) ; class_("Cell", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hasPort", &Cell::hasPort) + .def("unsetPort", &Cell::unsetPort) + .def("setPort", &Cell::setPort) + .def("input", &Cell::input) + .def("output", &Cell::output) + .def("hasParam", &Cell::hasParam) + .def("unsetParam", &Cell::unsetParam) + .def("setParam", &Cell::setParam) + .def("fixup_parameters", &Cell::fixup_parameters) ; class_("Wire", no_init) @@ -349,14 +2876,230 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) ; - class_("Monitor") - .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) - .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) - .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + class_("Memory", no_init) + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + ; + + class_("Module") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_cells", &Module::get_cells) + .def("get_wires", &Module::get_wires) + .def("register_monitor", &Module::register_monitor) + .def("connect_SigSig", &Module::connect_SigSig) + .def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec) + .def("new_connections", &Module::new_connections) + .def("cloneInto", &Module::cloneInto) + .def("remove_pool_Wire", &Module::remove_pool_Wire) + .def("remove_Cell", &Module::remove_Cell) + .def("rename_Wire_IdString", &Module::rename_Wire_IdString) + .def("rename_Cell_IdString", &Module::rename_Cell_IdString) + .def("rename_IdString_IdString", &Module::rename_IdString_IdString) + .def("swap_names_Wire_Wire", &Module::swap_names_Wire_Wire) + .def("swap_names_Cell_Cell", &Module::swap_names_Cell_Cell) + .def("uniquify_IdString", &Module::uniquify_IdString) + .def("uniquify_IdString_int", &Module::uniquify_IdString_int) + .def("addWire_IdString_int", &Module::addWire_IdString_int) + .def("addWire_IdString_Wire", &Module::addWire_IdString_Wire) + .def("addCell_IdString_IdString", &Module::addCell_IdString_IdString) + .def("addCell_IdString_Cell", &Module::addCell_IdString_Cell) + .def("addNot", &Module::addNot) + .def("addPos", &Module::addPos) + .def("addNeg", &Module::addNeg) + .def("addAnd", &Module::addAnd) + .def("addOr", &Module::addOr) + .def("addXor", &Module::addXor) + .def("addXnor", &Module::addXnor) + .def("addReduceAnd", &Module::addReduceAnd) + .def("addReduceOr", &Module::addReduceOr) + .def("addReduceXor", &Module::addReduceXor) + .def("addReduceXnor", &Module::addReduceXnor) + .def("addReduceBool", &Module::addReduceBool) + .def("addShl", &Module::addShl) + .def("addShr", &Module::addShr) + .def("addSshl", &Module::addSshl) + .def("addSshr", &Module::addSshr) + .def("addShift", &Module::addShift) + .def("addShiftx", &Module::addShiftx) + .def("addLt", &Module::addLt) + .def("addLe", &Module::addLe) + .def("addEq", &Module::addEq) + .def("addNe", &Module::addNe) + .def("addEqx", &Module::addEqx) + .def("addNex", &Module::addNex) + .def("addGe", &Module::addGe) + .def("addGt", &Module::addGt) + .def("addAdd", &Module::addAdd) + .def("addSub", &Module::addSub) + .def("addMul", &Module::addMul) + .def("addDiv", &Module::addDiv) + .def("addMod", &Module::addMod) + .def("addPow", &Module::addPow) + .def("addLogicNot", &Module::addLogicNot) + .def("addLogicAnd", &Module::addLogicAnd) + .def("addLogicOr", &Module::addLogicOr) + .def("addMux", &Module::addMux) + .def("addPmux", &Module::addPmux) + .def("addSlice", &Module::addSlice) + .def("addConcat", &Module::addConcat) + .def("addLut", &Module::addLut) + .def("addTribuf", &Module::addTribuf) + .def("addAssert", &Module::addAssert) + .def("addAssume", &Module::addAssume) + .def("addLive", &Module::addLive) + .def("addFair", &Module::addFair) + .def("addCover", &Module::addCover) + .def("addEquiv", &Module::addEquiv) + .def("addSr", &Module::addSr) + .def("addFf", &Module::addFf) + .def("addDff", &Module::addDff) + .def("addDffe", &Module::addDffe) + .def("addDlatch", &Module::addDlatch) + .def("addBufGate", &Module::addBufGate) + .def("addNotGate", &Module::addNotGate) + .def("addAndGate", &Module::addAndGate) + .def("addNandGate", &Module::addNandGate) + .def("addOrGate", &Module::addOrGate) + .def("addNorGate", &Module::addNorGate) + .def("addXorGate", &Module::addXorGate) + .def("addXnorGate", &Module::addXnorGate) + .def("addAndnotGate", &Module::addAndnotGate) + .def("addOrnotGate", &Module::addOrnotGate) + .def("addMuxGate", &Module::addMuxGate) + .def("addAoi3Gate", &Module::addAoi3Gate) + .def("addOai3Gate", &Module::addOai3Gate) + .def("addAoi4Gate", &Module::addAoi4Gate) + .def("addOai4Gate", &Module::addOai4Gate) + .def("addFfGate", &Module::addFfGate) + .def("addDffGate", &Module::addDffGate) + .def("addDffeGate", &Module::addDffeGate) + .def("addDlatchGate", &Module::addDlatchGate) + .def("Not", &Module::Not) + .def("Pos", &Module::Pos) + .def("Neg", &Module::Neg) + .def("And", &Module::And) + .def("Or", &Module::Or) + .def("Xor", &Module::Xor) + .def("Xnor", &Module::Xnor) + .def("ReduceAnd", &Module::ReduceAnd) + .def("ReduceOr", &Module::ReduceOr) + .def("ReduceXor", &Module::ReduceXor) + .def("ReduceXnor", &Module::ReduceXnor) + .def("ReduceBool", &Module::ReduceBool) + .def("Shl", &Module::Shl) + .def("Shr", &Module::Shr) + .def("Sshl", &Module::Sshl) + .def("Sshr", &Module::Sshr) + .def("Shift", &Module::Shift) + .def("Shiftx", &Module::Shiftx) + .def("Lt", &Module::Lt) + .def("Le", &Module::Le) + .def("Eq", &Module::Eq) + .def("Ne", &Module::Ne) + .def("Eqx", &Module::Eqx) + .def("Nex", &Module::Nex) + .def("Ge", &Module::Ge) + .def("Gt", &Module::Gt) + .def("Add", &Module::Add) + .def("Sub", &Module::Sub) + .def("Mul", &Module::Mul) + .def("Div", &Module::Div) + .def("Mod", &Module::Mod) + .def("LogicNot", &Module::LogicNot) + .def("LogicAnd", &Module::LogicAnd) + .def("LogicOr", &Module::LogicOr) + .def("Mux", &Module::Mux) + .def("Pmux", &Module::Pmux) + .def("BufGate", &Module::BufGate) + .def("NotGate", &Module::NotGate) + .def("AndGate", &Module::AndGate) + .def("NandGate", &Module::NandGate) + .def("OrGate", &Module::OrGate) + .def("NorGate", &Module::NorGate) + .def("XorGate", &Module::XorGate) + .def("XnorGate", &Module::XnorGate) + .def("AndnotGate", &Module::AndnotGate) + .def("OrnotGate", &Module::OrnotGate) + .def("MuxGate", &Module::MuxGate) + .def("Aoi3Gate", &Module::Aoi3Gate) + .def("Oai3Gate", &Module::Oai3Gate) + .def("Aoi4Gate", &Module::Aoi4Gate) + .def("Oai4Gate", &Module::Oai4Gate) + .def("Anyconst", &Module::Anyconst) + .def("Anyseq", &Module::Anyseq) + .def("Allconst", &Module::Allconst) + .def("Allseq", &Module::Allseq) + .def("Initstate", &Module::Initstate) ; + class_("Design") + .def(boost::python::self_ns::str(boost::python::self_ns::self)) + .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_modules", &Design::get_modules) + .def("run", &Design::run) + .def("register_monitor", &Design::register_monitor) + .def("module", &Design::module) + .def("has", &Design::has) + .def("add", &Design::add) + .def("addModule", &Design::addModule) + .def("remove", &Design::remove) + .def("rename", &Design::rename) + .def("scratchpad_unset", &Design::scratchpad_unset) + .def("scratchpad_set_int", &Design::scratchpad_set_int) + .def("scratchpad_set_bool", &Design::scratchpad_set_bool) + .def("scratchpad_set_string", &Design::scratchpad_set_string) + .def("scratchpad_get_int", &Design::scratchpad_get_int) + .def("scratchpad_get_bool", &Design::scratchpad_get_bool) + .def("scratchpad_get_string", &Design::scratchpad_get_string) + .def("selected_module_IdString", &Design::selected_module_IdString) + .def("selected_whole_module_IdString", &Design::selected_whole_module_IdString) + .def("selected_member", &Design::selected_member) + .def("selected_module_Module", &Design::selected_module_Module) + .def("selected_whole_module_Module", &Design::selected_whole_module_Module) + ; + + def("escape_id", escape_id); + def("unescape_id_std_string", unescape_id_std_string); + def("unescape_id_IdString", unescape_id_IdString); + def("const_not", const_not); + def("const_and", const_and); + def("const_or", const_or); + def("const_xor", const_xor); + def("const_xnor", const_xnor); + def("const_reduce_and", const_reduce_and); + def("const_reduce_or", const_reduce_or); + def("const_reduce_xor", const_reduce_xor); + def("const_reduce_xnor", const_reduce_xnor); + def("const_reduce_bool", const_reduce_bool); + def("const_logic_not", const_logic_not); + def("const_logic_and", const_logic_and); + def("const_logic_or", const_logic_or); + def("const_shl", const_shl); + def("const_shr", const_shr); + def("const_sshl", const_sshl); + def("const_sshr", const_sshr); + def("const_shift", const_shift); + def("const_shiftx", const_shiftx); + def("const_lt", const_lt); + def("const_le", const_le); + def("const_eq", const_eq); + def("const_ne", const_ne); + def("const_eqx", const_eqx); + def("const_nex", const_nex); + def("const_ge", const_ge); + def("const_gt", const_gt); + def("const_add", const_add); + def("const_sub", const_sub); + def("const_mul", const_mul); + def("const_div", const_div); + def("const_mod", const_mod); + def("const_pow", const_pow); + def("const_pos", const_pos); + def("const_neg", const_neg); + def("run",run); - def("get_active_design_id",get_active_design_id); + } } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6e8b51682..bcda931d2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -74,6 +74,13 @@ RTLIL::Const::Const(const std::vector &bits) this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0); } +RTLIL::Const::Const(const RTLIL::Const &c) +{ + flags = c.flags; + for (auto b : c.bits) + this->bits.push_back(b); +} + bool RTLIL::Const::operator <(const RTLIL::Const &other) const { if (bits.size() != other.bits.size()) @@ -2247,6 +2254,9 @@ RTLIL::Memory::Memory() width = 1; start_offset = 0; size = 0; +#ifdef WITH_PYTHON + RTLIL::Memory::get_all_memorys()->insert(std::pair(hashidx_, this)); +#endif } RTLIL::Cell::Cell() : module(nullptr) @@ -2534,6 +2544,14 @@ RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit) width = 1; } +RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data) +{ + wire = sigchunk.wire; + data = sigchunk.data; + width = sigchunk.width; + offset = sigchunk.offset; +} + RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const { RTLIL::SigChunk ret; @@ -3907,6 +3925,18 @@ RTLIL::Process *RTLIL::Process::clone() const return new_proc; } +RTLIL::Memory::~Memory() +{ +#ifdef WITH_PYTHON + RTLIL::Memory::get_all_memorys()->erase(hashidx_); +#endif +} +#ifdef WITH_PYTHON +static std::map *all_memorys = new std::map(); +std::map *RTLIL::Memory::get_all_memorys(void) +{ + return all_memorys; +} +#endif YOSYS_NAMESPACE_END - diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e71a5fceb..89413a166 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -463,6 +463,7 @@ struct RTLIL::Const Const(RTLIL::State bit, int width = 1); Const(const std::vector &bits) : bits(bits) { flags = CONST_FLAG_NONE; } Const(const std::vector &bits); + Const(const RTLIL::Const &c); bool operator <(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const; @@ -529,6 +530,7 @@ struct RTLIL::SigChunk SigChunk(int val, int width = 32); SigChunk(RTLIL::State bit, int width = 1); SigChunk(RTLIL::SigBit bit); + SigChunk(const RTLIL::SigChunk &sigchunk); RTLIL::SigChunk extract(int offset, int length) const; @@ -553,6 +555,7 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigChunk &chunk); SigBit(const RTLIL::SigChunk &chunk, int index); SigBit(const RTLIL::SigSpec &sig); + SigBit(const RTLIL::SigBit &sigbit); bool operator <(const RTLIL::SigBit &other) const; bool operator ==(const RTLIL::SigBit &other) const; @@ -874,13 +877,13 @@ struct RTLIL::Design } } -#ifdef WITH_PYTHON - static std::map *get_all_designs(void); -#endif std::vector selected_modules() const; std::vector selected_whole_modules() const; std::vector selected_whole_modules_warn() const; +#ifdef WITH_PYTHON + static std::map *get_all_designs(void); +#endif }; struct RTLIL::Module : public RTLIL::AttrObject @@ -1175,6 +1178,10 @@ struct RTLIL::Memory : public RTLIL::AttrObject RTLIL::IdString name; int width, start_offset, size; +#ifdef WITH_PYTHON + ~Memory(); + static std::map *get_all_memorys(void); +#endif }; struct RTLIL::Cell : public RTLIL::AttrObject @@ -1287,6 +1294,7 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; } +inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){if(wire) offset = sigbit.offset;} inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const { if (wire == other.wire) -- cgit v1.2.3 From 80d7e007ff4cbe0a9669224751c68e5325fbed0a Mon Sep 17 00:00:00 2001 From: litghost <537074+litghost@users.noreply.github.com> Date: Mon, 13 Aug 2018 14:02:53 -0700 Subject: Map .eblif extension as blif. Signed-off-by: litghost <537074+litghost@users.noreply.github.com> --- kernel/yosys.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 750a154e6..dca277532 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -825,6 +825,8 @@ void run_frontend(std::string filename, std::string command, std::string *backen command = "vhdl"; else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif") command = "blif"; + else if (filename.size() > 5 && filename.substr(filename.size()-6) == ".eblif") + command = "blif"; else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".json") command = "json"; else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") -- cgit v1.2.3 From d79a2808cf2446fa21d91a6141f6fbe2318c03ec Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 16 Aug 2018 16:00:11 +0200 Subject: Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script --- kernel/python_wrappers.cc | 66 ++++++++++++++++++++++++++++++++++++++++++++++- kernel/yosys.cc | 26 +++++++++++++++++++ kernel/yosys.h | 5 ++++ 3 files changed, 96 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 18b0010ae..197be0853 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -34,6 +34,11 @@ namespace YOSYS_PYTHON { Yosys::run_pass(command); } + void log(std::string text) + { + Yosys::log(text.c_str()); + } + struct IdString { Yosys::RTLIL::IdString* ref_obj; @@ -1388,7 +1393,7 @@ namespace YOSYS_PYTHON { virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; virtual void py_notify_blackout(Module*){}; - }; + }; struct MonitorWrap : Monitor, boost::python::wrapper { @@ -1471,6 +1476,59 @@ namespace YOSYS_PYTHON { } }; + struct PyPass : public Yosys::Pass + { + PyPass(std::string name, std::string short_help) : Yosys::Pass(name, short_help) { } + + virtual void execute(vector args, Yosys::RTLIL::Design* d) YS_OVERRIDE + { + boost::python::list py_args; + for(auto arg : args) + py_args.append(arg); + py_execute(py_args, new Design(d)); + } + + virtual void help() YS_OVERRIDE + { + py_help(); + } + + virtual void py_execute(boost::python::list args, Design* d){} + virtual void py_help(){} + }; + + struct PassWrap : PyPass, boost::python::wrapper + { + + PassWrap(std::string name, std::string short_help) : PyPass(name, short_help) { } + + void py_execute(boost::python::list args, Design* d) + { + if(boost::python::override py_execute = this->get_override("py_execute")) + py_execute(args, d); + else + PyPass::py_execute(args, d); + } + + void default_py_execute(boost::python::list args, Design* d) + { + this->PyPass::py_execute(args, d); + } + + void py_help() + { + if(boost::python::override py_help = this->get_override("py_help")) + py_help(); + else + PyPass::py_help(); + } + + void default_py_help() + { + this->PyPass::py_help(); + } + }; + void Module::register_monitor(Monitor* const m) { Yosys::RTLIL::Module* cpp_module = this->get_cpp_obj(); @@ -2778,6 +2836,11 @@ namespace YOSYS_PYTHON { .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) ; + class_("Pass", init()) + .def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute) + .def("py_help", &PyPass::py_help, &PassWrap::default_py_help) + ; + class_("Initializer"); scope().attr("_hidden") = new Initializer(); @@ -3099,6 +3162,7 @@ namespace YOSYS_PYTHON { def("const_neg", const_neg); def("run",run); + def("log",log); } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 750a154e6..8e16ba01d 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -469,21 +469,40 @@ int GetSize(RTLIL::Wire *wire) return wire->width; } +bool already_setup = false; + void yosys_setup() { + if(already_setup) + return; + already_setup = true; // if there are already IdString objects then we have a global initialization order bug IdString empty_id; log_assert(empty_id.index_ == 0); IdString::get_reference(empty_id.index_); + #ifdef WITH_PYTHON + Py_Initialize(); + PyRun_SimpleString("import sys"); + PyRun_SimpleString("sys.path.append(\"./\")"); + //PyRun_SimpleString("import libyosys"); + //PyRun_SimpleString("sys.path.append(\"./plugins\")"); + //PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); + #endif + Pass::init_register(); yosys_design = new RTLIL::Design; yosys_celltypes.setup(); log_push(); } +bool already_shutdown = false; + void yosys_shutdown() { + if(already_shutdown) + return; + already_shutdown = true; log_pop(); delete yosys_design; @@ -511,9 +530,16 @@ void yosys_shutdown() dlclose(it.second); loaded_plugins.clear(); +#ifdef WITH_PYTHON + loaded_python_plugins.clear(); +#endif loaded_plugin_aliases.clear(); #endif +#ifdef WITH_PYTHON + Py_Finalize(); +#endif + IdString empty_id; IdString::put_reference(empty_id.index_); } diff --git a/kernel/yosys.h b/kernel/yosys.h index 14cbcd610..4380a5b69 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -66,6 +66,8 @@ #include #include +#include + #ifndef _YOSYS_ # error It looks like you are trying to build Yosys without the config defines set. \ When building Yosys with a custom make system, make sure you set all the \ @@ -317,6 +319,9 @@ extern std::vector pushed_designs; // from passes/cmds/pluginc.cc extern std::map loaded_plugins; +#ifdef WITH_PYTHON +extern std::map loaded_python_plugins; +#endif extern std::map loaded_plugin_aliases; void load_plugin(std::string filename, std::vector aliases); -- cgit v1.2.3 From 5864db3c2bf353d4ee124d35aa2f911c4249edbc Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 14:44:03 +0200 Subject: Fixed issue when using a python plugin in the yosys shell --- kernel/python_wrappers.cc | 11 +++++++---- kernel/yosys.cc | 16 ++++++++++++++++ kernel/yosys.h | 5 +++++ 3 files changed, 28 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 197be0853..af1f80929 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -2783,10 +2783,13 @@ namespace YOSYS_PYTHON { struct Initializer { Initializer() { - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; - Yosys::yosys_setup(); - Yosys::yosys_banner(); + if(!Yosys::yosys_already_setup()) + { + Yosys::log_streams.push_back(&std::cout); + Yosys::log_error_stderr = true; + Yosys::yosys_setup(); + Yosys::yosys_banner(); + } } Initializer(Initializer const &) {} diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 8e16ba01d..8380fe75d 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -55,6 +55,16 @@ # include #endif +#ifdef WITH_PYTHON +#if PY_MAJOR_VERSION >= 3 +# define INIT_MODULE PyInit_libyosys + extern "C" PyObject* INIT_MODULE(); +#else +# define INIT_MODULE initlibyosys + extern "C" void INIT_MODULE(); +#endif +#endif + #include #include @@ -482,6 +492,7 @@ void yosys_setup() IdString::get_reference(empty_id.index_); #ifdef WITH_PYTHON + PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); Py_Initialize(); PyRun_SimpleString("import sys"); PyRun_SimpleString("sys.path.append(\"./\")"); @@ -496,6 +507,11 @@ void yosys_setup() log_push(); } +bool yosys_already_setup() +{ + return already_setup; +} + bool already_shutdown = false; void yosys_shutdown() diff --git a/kernel/yosys.h b/kernel/yosys.h index 4380a5b69..6ed0f8b20 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -278,6 +278,11 @@ namespace hashlib { } void yosys_setup(); + +#ifdef WITH_PYTHON +bool yosys_already_setup(); +#endif + void yosys_shutdown(); #ifdef YOSYS_ENABLE_TCL -- cgit v1.2.3 From 6d18837d62436b297b34c20d5a005ef0b6a75da2 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 15:11:06 +0200 Subject: Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path --- kernel/yosys.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 8380fe75d..e36c68752 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -495,10 +495,7 @@ void yosys_setup() PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); Py_Initialize(); PyRun_SimpleString("import sys"); - PyRun_SimpleString("sys.path.append(\"./\")"); - //PyRun_SimpleString("import libyosys"); - //PyRun_SimpleString("sys.path.append(\"./plugins\")"); - //PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); + PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); #endif Pass::init_register(); -- cgit v1.2.3 From d41c68ee5ad908db1dd75552816789e493d011bf Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 15:27:50 +0200 Subject: The share directory cannot be searched when used as a Python library, only in shell mode --- kernel/driver.cc | 8 ++++++++ kernel/yosys.cc | 1 - 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 178641101..255fe45c4 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -110,6 +110,10 @@ int main(int argc, char **argv) log_error_stderr = true; yosys_banner(); yosys_setup(); +#ifdef WITH_PYTHON + PyRun_SimpleString(("sys.path.append(\""+proc_self_dirname()+"\")").c_str()); + PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); +#endif if (argc == 2) { @@ -462,6 +466,10 @@ int main(int argc, char **argv) #endif yosys_setup(); +#ifdef WITH_PYTHON + PyRun_SimpleString(("sys.path.append(\""+proc_self_dirname()+"\")").c_str()); + PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); +#endif log_error_atexit = yosys_atexit; for (auto &fn : plugin_filenames) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index e36c68752..a6d09c077 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -495,7 +495,6 @@ void yosys_setup() PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); Py_Initialize(); PyRun_SimpleString("import sys"); - PyRun_SimpleString(("sys.path.append(\""+proc_share_dirname()+"plugins\")").c_str()); #endif Pass::init_register(); -- cgit v1.2.3 From 95d65971f3f114adb8b62a9d29bc0829467e3d81 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 16:04:43 +0200 Subject: added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile --- kernel/python_wrappers.cc | 6 +++--- kernel/rtlil.cc | 6 ++---- kernel/rtlil.h | 1 + kernel/yosys.h | 2 ++ 4 files changed, 8 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index af1f80929..2c27ea47f 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -2783,13 +2783,13 @@ namespace YOSYS_PYTHON { struct Initializer { Initializer() { - if(!Yosys::yosys_already_setup()) - { + if(!Yosys::yosys_already_setup()) + { Yosys::log_streams.push_back(&std::cout); Yosys::log_error_stderr = true; Yosys::yosys_setup(); Yosys::yosys_banner(); - } + } } Initializer(Initializer const &) {} diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index bcda931d2..93b138071 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3925,14 +3925,12 @@ RTLIL::Process *RTLIL::Process::clone() const return new_proc; } + +#ifdef WITH_PYTHON RTLIL::Memory::~Memory() { -#ifdef WITH_PYTHON RTLIL::Memory::get_all_memorys()->erase(hashidx_); -#endif } - -#ifdef WITH_PYTHON static std::map *all_memorys = new std::map(); std::map *RTLIL::Memory::get_all_memorys(void) { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 89413a166..0e5159be2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1175,6 +1175,7 @@ struct RTLIL::Memory : public RTLIL::AttrObject unsigned int hash() const { return hashidx_; } Memory(); + ~Memory(); RTLIL::IdString name; int width, start_offset, size; diff --git a/kernel/yosys.h b/kernel/yosys.h index 6ed0f8b20..9f5f056a5 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -66,7 +66,9 @@ #include #include +#ifdef WITH_PYTHON #include +#endif #ifndef _YOSYS_ # error It looks like you are trying to build Yosys without the config defines set. \ -- cgit v1.2.3 From 29efc9d0b1b003113e1faf1e76ce32cffb0ff95a Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 11:07:59 +0200 Subject: Deleted duplicate Destructor --- kernel/rtlil.h | 1 - 1 file changed, 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0e5159be2..89413a166 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1175,7 +1175,6 @@ struct RTLIL::Memory : public RTLIL::AttrObject unsigned int hash() const { return hashidx_; } Memory(); - ~Memory(); RTLIL::IdString name; int width, start_offset, size; -- cgit v1.2.3 From 334bfce4c4df994a8a0bdbf0f50b29df996e3cb0 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 13:15:08 +0200 Subject: Added previousely missed functions --- kernel/python_wrappers.cc | 446 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 445 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 2c27ea47f..5e964dcac 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -36,7 +36,7 @@ namespace YOSYS_PYTHON { void log(std::string text) { - Yosys::log(text.c_str()); + Yosys::log("%s",text.c_str()); } struct IdString @@ -74,11 +74,23 @@ namespace YOSYS_PYTHON { //WRAPPED static inline void put_reference(int idx) static inline void put_reference(int idx); + //WRAPPED std::string str() const { + std::string str(); + + //WRAPPED bool empty() const { + bool empty(); + + //WRAPPED void clear() { + void clear(); + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } bool in_IdString(IdString *rhs); //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } bool in_std_string(std::string rhs); + + //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } + bool in_pool_IdString(boost::python::list *rhs); }; std::ostream &operator<<(std::ostream &ostr, const IdString &ref) @@ -110,12 +122,36 @@ namespace YOSYS_PYTHON { return ref_obj; } + //WRAPPED bool as_bool() const; + bool as_bool(); + //WRAPPED int as_int(bool is_signed = false) const; int as_int(bool is_signed = false); + //WRAPPED std::string as_string() const; + std::string as_string(); + //WRAPPED static Const from_string(std::string str); static Const from_string(std::string str); + //WRAPPED std::string decode_string() const; + std::string decode_string(); + + //WRAPPED inline int size() const { return bits.size(); } + inline int size(); + + //WRAPPED bool is_fully_zero() const; + bool is_fully_zero(); + + //WRAPPED bool is_fully_ones() const; + bool is_fully_ones(); + + //WRAPPED bool is_fully_def() const; + bool is_fully_def(); + + //WRAPPED bool is_fully_undef() const; + bool is_fully_undef(); + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { inline Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); }; @@ -148,6 +184,9 @@ namespace YOSYS_PYTHON { { return ref_obj; } + + //WRAPPED RTLIL::CaseRule *clone() const; + CaseRule clone(); }; std::ostream &operator<<(std::ostream &ostr, const CaseRule &ref) @@ -178,6 +217,9 @@ namespace YOSYS_PYTHON { { return ref_obj; } + + //WRAPPED RTLIL::SwitchRule *clone() const; + SwitchRule clone(); }; std::ostream &operator<<(std::ostream &ostr, const SwitchRule &ref) @@ -208,6 +250,9 @@ namespace YOSYS_PYTHON { { return ref_obj; } + + //WRAPPED RTLIL::SyncRule *clone() const; + SyncRule clone(); }; std::ostream &operator<<(std::ostream &ostr, const SyncRule &ref) @@ -238,6 +283,9 @@ namespace YOSYS_PYTHON { { return ref_obj; } + + //WRAPPED RTLIL::Process *clone() const; + Process clone(); }; std::ostream &operator<<(std::ostream &ostr, const Process &ref) @@ -332,6 +380,12 @@ namespace YOSYS_PYTHON { return ref_obj; } + //WRAPPED inline int size() const { return width_; } + inline int size(); + + //WRAPPED inline bool empty() const { return width_ == 0; } + inline bool empty(); + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); void replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with); @@ -383,9 +437,57 @@ namespace YOSYS_PYTHON { //WRAPPED RTLIL::SigSpec repeat(int num) const; SigSpec repeat(int num); + //WRAPPED bool is_wire() const; + bool is_wire(); + + //WRAPPED bool is_chunk() const; + bool is_chunk(); + + //WRAPPED inline bool is_bit() const { return width_ == 1; } + inline bool is_bit(); + + //WRAPPED bool is_fully_const() const; + bool is_fully_const(); + + //WRAPPED bool is_fully_zero() const; + bool is_fully_zero(); + + //WRAPPED bool is_fully_ones() const; + bool is_fully_ones(); + + //WRAPPED bool is_fully_def() const; + bool is_fully_def(); + + //WRAPPED bool is_fully_undef() const; + bool is_fully_undef(); + + //WRAPPED bool has_const() const; + bool has_const(); + + //WRAPPED bool has_marked_bits() const; + bool has_marked_bits(); + + //WRAPPED bool as_bool() const; + bool as_bool(); + //WRAPPED int as_int(bool is_signed = false) const; int as_int(bool is_signed = false); + //WRAPPED std::string as_string() const; + std::string as_string(); + + //WRAPPED RTLIL::Const as_const() const; + Const as_const(); + + //WRAPPED RTLIL::Wire *as_wire() const; + Wire as_wire(); + + //WRAPPED RTLIL::SigChunk as_chunk() const; + SigChunk as_chunk(); + + //WRAPPED RTLIL::SigBit as_bit() const; + SigBit as_bit(); + //WRAPPED bool match(std::string pattern) const; bool match(std::string pattern); @@ -397,6 +499,9 @@ namespace YOSYS_PYTHON { //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str); + + //WRAPPED void check() const; + void check(); }; std::ostream &operator<<(std::ostream &ostr, const SigSpec &ref) @@ -432,6 +537,9 @@ namespace YOSYS_PYTHON { //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); void setPort(IdString *portname, SigSpec *signal); + //WRAPPED bool known() const; + bool known(); + //WRAPPED bool input(RTLIL::IdString portname) const; bool input(IdString *portname); @@ -449,6 +557,9 @@ namespace YOSYS_PYTHON { //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + + //WRAPPED bool has_keep_attr() const { + bool has_keep_attr(); }; std::ostream &operator<<(std::ostream &ostr, const Cell &ref) @@ -578,6 +689,24 @@ namespace YOSYS_PYTHON { //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; void cloneInto(Module *new_mod); + //WRAPPED bool has_memories() const; + bool has_memories(); + + //WRAPPED bool has_processes() const; + bool has_processes(); + + //WRAPPED bool has_memories_warn() const; + bool has_memories_warn(); + + //WRAPPED bool has_processes_warn() const; + bool has_processes_warn(); + + //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } + Wire wire(IdString *id); + + //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } + Cell cell(IdString *id); + //WRAPPED void remove(const pool &wires); void remove_pool_Wire(boost::python::list *wires); @@ -1104,6 +1233,9 @@ namespace YOSYS_PYTHON { //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; bool selected_whole_module_Module(Module *mod); + + //WRAPPED bool full_selection() const { + bool full_selection(); }; std::ostream &operator<<(std::ostream &ostr, const Design &ref) @@ -1557,6 +1689,24 @@ namespace YOSYS_PYTHON { Yosys::RTLIL::IdString::put_reference(idx); } + //WRAPPED std::string str() const { + std::string IdString::str() + { + return this->get_cpp_obj()->str(); + } + + //WRAPPED bool empty() const { + bool IdString::empty() + { + return this->get_cpp_obj()->empty(); + } + + //WRAPPED void clear() { + void IdString::clear() + { + this->get_cpp_obj()->clear(); + } + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } bool IdString::in_IdString(IdString *rhs) { @@ -1569,30 +1719,124 @@ namespace YOSYS_PYTHON { return this->get_cpp_obj()->in(rhs); } + //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } + bool IdString::in_pool_IdString(boost::python::list *rhs) + { + pool rhs_; + for(int i = 0; i < len(*rhs); ++i) + { + } + return this->get_cpp_obj()->in(rhs_); + } + + //WRAPPED bool as_bool() const; + bool Const::as_bool() + { + return this->get_cpp_obj()->as_bool(); + } + //WRAPPED int as_int(bool is_signed = false) const; int Const::as_int(bool is_signed) { return this->get_cpp_obj()->as_int(is_signed); } + //WRAPPED std::string as_string() const; + std::string Const::as_string() + { + return this->get_cpp_obj()->as_string(); + } + //WRAPPED static Const from_string(std::string str); Const Const::from_string(std::string str) { return Const(Yosys::RTLIL::Const::from_string(str)); } + //WRAPPED std::string decode_string() const; + std::string Const::decode_string() + { + return this->get_cpp_obj()->decode_string(); + } + + //WRAPPED inline int size() const { return bits.size(); } + inline int Const::size() + { + return this->get_cpp_obj()->size(); + } + + //WRAPPED bool is_fully_zero() const; + bool Const::is_fully_zero() + { + return this->get_cpp_obj()->is_fully_zero(); + } + + //WRAPPED bool is_fully_ones() const; + bool Const::is_fully_ones() + { + return this->get_cpp_obj()->is_fully_ones(); + } + + //WRAPPED bool is_fully_def() const; + bool Const::is_fully_def() + { + return this->get_cpp_obj()->is_fully_def(); + } + + //WRAPPED bool is_fully_undef() const; + bool Const::is_fully_undef() + { + return this->get_cpp_obj()->is_fully_undef(); + } + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { inline Const Const::extract(int offset, int len, State padding) { return Const(this->get_cpp_obj()->extract(offset, len, padding)); } + //WRAPPED RTLIL::CaseRule *clone() const; + CaseRule CaseRule::clone() + { + return CaseRule(this->get_cpp_obj()->clone()); + } + + //WRAPPED RTLIL::SwitchRule *clone() const; + SwitchRule SwitchRule::clone() + { + return SwitchRule(this->get_cpp_obj()->clone()); + } + + //WRAPPED RTLIL::SyncRule *clone() const; + SyncRule SyncRule::clone() + { + return SyncRule(this->get_cpp_obj()->clone()); + } + + //WRAPPED RTLIL::Process *clone() const; + Process Process::clone() + { + return Process(this->get_cpp_obj()->clone()); + } + //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; SigChunk SigChunk::extract(int offset, int length) { return SigChunk(this->get_cpp_obj()->extract(offset, length)); } + //WRAPPED inline int size() const { return width_; } + inline int SigSpec::size() + { + return this->get_cpp_obj()->size(); + } + + //WRAPPED inline bool empty() const { return width_ == 0; } + inline bool SigSpec::empty() + { + return this->get_cpp_obj()->empty(); + } + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with) { @@ -1711,12 +1955,108 @@ namespace YOSYS_PYTHON { return SigSpec(this->get_cpp_obj()->repeat(num)); } + //WRAPPED bool is_wire() const; + bool SigSpec::is_wire() + { + return this->get_cpp_obj()->is_wire(); + } + + //WRAPPED bool is_chunk() const; + bool SigSpec::is_chunk() + { + return this->get_cpp_obj()->is_chunk(); + } + + //WRAPPED inline bool is_bit() const { return width_ == 1; } + inline bool SigSpec::is_bit() + { + return this->get_cpp_obj()->is_bit(); + } + + //WRAPPED bool is_fully_const() const; + bool SigSpec::is_fully_const() + { + return this->get_cpp_obj()->is_fully_const(); + } + + //WRAPPED bool is_fully_zero() const; + bool SigSpec::is_fully_zero() + { + return this->get_cpp_obj()->is_fully_zero(); + } + + //WRAPPED bool is_fully_ones() const; + bool SigSpec::is_fully_ones() + { + return this->get_cpp_obj()->is_fully_ones(); + } + + //WRAPPED bool is_fully_def() const; + bool SigSpec::is_fully_def() + { + return this->get_cpp_obj()->is_fully_def(); + } + + //WRAPPED bool is_fully_undef() const; + bool SigSpec::is_fully_undef() + { + return this->get_cpp_obj()->is_fully_undef(); + } + + //WRAPPED bool has_const() const; + bool SigSpec::has_const() + { + return this->get_cpp_obj()->has_const(); + } + + //WRAPPED bool has_marked_bits() const; + bool SigSpec::has_marked_bits() + { + return this->get_cpp_obj()->has_marked_bits(); + } + + //WRAPPED bool as_bool() const; + bool SigSpec::as_bool() + { + return this->get_cpp_obj()->as_bool(); + } + //WRAPPED int as_int(bool is_signed = false) const; int SigSpec::as_int(bool is_signed) { return this->get_cpp_obj()->as_int(is_signed); } + //WRAPPED std::string as_string() const; + std::string SigSpec::as_string() + { + return this->get_cpp_obj()->as_string(); + } + + //WRAPPED RTLIL::Const as_const() const; + Const SigSpec::as_const() + { + return Const(this->get_cpp_obj()->as_const()); + } + + //WRAPPED RTLIL::Wire *as_wire() const; + Wire SigSpec::as_wire() + { + return Wire(this->get_cpp_obj()->as_wire()); + } + + //WRAPPED RTLIL::SigChunk as_chunk() const; + SigChunk SigSpec::as_chunk() + { + return SigChunk(this->get_cpp_obj()->as_chunk()); + } + + //WRAPPED RTLIL::SigBit as_bit() const; + SigBit SigSpec::as_bit() + { + return SigBit(this->get_cpp_obj()->as_bit()); + } + //WRAPPED bool match(std::string pattern) const; bool SigSpec::match(std::string pattern) { @@ -1741,6 +2081,12 @@ namespace YOSYS_PYTHON { return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); } + //WRAPPED void check() const; + void SigSpec::check() + { + this->get_cpp_obj()->check(); + } + //WRAPPED bool hasPort(RTLIL::IdString portname) const; bool Cell::hasPort(IdString *portname) { @@ -1759,6 +2105,12 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj()); } + //WRAPPED bool known() const; + bool Cell::known() + { + return this->get_cpp_obj()->known(); + } + //WRAPPED bool input(RTLIL::IdString portname) const; bool Cell::input(IdString *portname) { @@ -1795,6 +2147,12 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed); } + //WRAPPED bool has_keep_attr() const { + bool Cell::has_keep_attr() + { + return this->get_cpp_obj()->has_keep_attr(); + } + //WRAPPED void connect(const RTLIL::SigSig &conn); void Module::connect_SigSig(PyObject* conn) { @@ -1828,6 +2186,42 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj()); } + //WRAPPED bool has_memories() const; + bool Module::has_memories() + { + return this->get_cpp_obj()->has_memories(); + } + + //WRAPPED bool has_processes() const; + bool Module::has_processes() + { + return this->get_cpp_obj()->has_processes(); + } + + //WRAPPED bool has_memories_warn() const; + bool Module::has_memories_warn() + { + return this->get_cpp_obj()->has_memories_warn(); + } + + //WRAPPED bool has_processes_warn() const; + bool Module::has_processes_warn() + { + return this->get_cpp_obj()->has_processes_warn(); + } + + //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } + Wire Module::wire(IdString *id) + { + return Wire(this->get_cpp_obj()->wire(*id->get_cpp_obj())); + } + + //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } + Cell Module::cell(IdString *id) + { + return Cell(this->get_cpp_obj()->cell(*id->get_cpp_obj())); + } + //WRAPPED void remove(const pool &wires); void Module::remove_pool_Wire(boost::python::list *wires) { @@ -2780,6 +3174,12 @@ namespace YOSYS_PYTHON { return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj()); } + //WRAPPED bool full_selection() const { + bool Design::full_selection() + { + return this->get_cpp_obj()->full_selection(); + } + struct Initializer { Initializer() { @@ -2853,36 +3253,52 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("get_reference", &IdString::get_reference) .def("put_reference", &IdString::put_reference) + .def("str", &IdString::str) + .def("empty", &IdString::empty) + .def("clear", &IdString::clear) .def("in_IdString", &IdString::in_IdString) .def("in_std_string", &IdString::in_std_string) + .def("in_pool_IdString", &IdString::in_pool_IdString) ; class_("Const") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("as_bool", &Const::as_bool) .def("as_int", &Const::as_int) + .def("as_string", &Const::as_string) .def("from_string", &Const::from_string) + .def("decode_string", &Const::decode_string) + .def("size", &Const::size) + .def("is_fully_zero", &Const::is_fully_zero) + .def("is_fully_ones", &Const::is_fully_ones) + .def("is_fully_def", &Const::is_fully_def) + .def("is_fully_undef", &Const::is_fully_undef) .def("extract", &Const::extract) ; class_("CaseRule") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("clone", &CaseRule::clone) ; class_("SwitchRule") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("clone", &SwitchRule::clone) ; class_("SyncRule") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("clone", &SyncRule::clone) ; class_("Process") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("clone", &Process::clone) ; class_("SigChunk") @@ -2899,6 +3315,8 @@ namespace YOSYS_PYTHON { class_("SigSpec") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("size", &SigSpec::size) + .def("empty", &SigSpec::empty) .def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec) .def("replace_SigSpec_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec_SigSpec) .def("replace_int_SigSpec", &SigSpec::replace_int_SigSpec) @@ -2916,11 +3334,28 @@ namespace YOSYS_PYTHON { .def("append_bit", &SigSpec::append_bit) .def("extend_u0", &SigSpec::extend_u0) .def("repeat", &SigSpec::repeat) + .def("is_wire", &SigSpec::is_wire) + .def("is_chunk", &SigSpec::is_chunk) + .def("is_bit", &SigSpec::is_bit) + .def("is_fully_const", &SigSpec::is_fully_const) + .def("is_fully_zero", &SigSpec::is_fully_zero) + .def("is_fully_ones", &SigSpec::is_fully_ones) + .def("is_fully_def", &SigSpec::is_fully_def) + .def("is_fully_undef", &SigSpec::is_fully_undef) + .def("has_const", &SigSpec::has_const) + .def("has_marked_bits", &SigSpec::has_marked_bits) + .def("as_bool", &SigSpec::as_bool) .def("as_int", &SigSpec::as_int) + .def("as_string", &SigSpec::as_string) + .def("as_const", &SigSpec::as_const) + .def("as_wire", &SigSpec::as_wire) + .def("as_chunk", &SigSpec::as_chunk) + .def("as_bit", &SigSpec::as_bit) .def("match", &SigSpec::match) .def("parse", &SigSpec::parse) .def("parse_sel", &SigSpec::parse_sel) .def("parse_rhs", &SigSpec::parse_rhs) + .def("check", &SigSpec::check) ; class_("Cell", no_init) @@ -2929,12 +3364,14 @@ namespace YOSYS_PYTHON { .def("hasPort", &Cell::hasPort) .def("unsetPort", &Cell::unsetPort) .def("setPort", &Cell::setPort) + .def("known", &Cell::known) .def("input", &Cell::input) .def("output", &Cell::output) .def("hasParam", &Cell::hasParam) .def("unsetParam", &Cell::unsetParam) .def("setParam", &Cell::setParam) .def("fixup_parameters", &Cell::fixup_parameters) + .def("has_keep_attr", &Cell::has_keep_attr) ; class_("Wire", no_init) @@ -2957,6 +3394,12 @@ namespace YOSYS_PYTHON { .def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec) .def("new_connections", &Module::new_connections) .def("cloneInto", &Module::cloneInto) + .def("has_memories", &Module::has_memories) + .def("has_processes", &Module::has_processes) + .def("has_memories_warn", &Module::has_memories_warn) + .def("has_processes_warn", &Module::has_processes_warn) + .def("wire", &Module::wire) + .def("cell", &Module::cell) .def("remove_pool_Wire", &Module::remove_pool_Wire) .def("remove_Cell", &Module::remove_Cell) .def("rename_Wire_IdString", &Module::rename_Wire_IdString) @@ -3123,6 +3566,7 @@ namespace YOSYS_PYTHON { .def("selected_member", &Design::selected_member) .def("selected_module_Module", &Design::selected_module_Module) .def("selected_whole_module_Module", &Design::selected_whole_module_Module) + .def("full_selection", &Design::full_selection) ; def("escape_id", escape_id); -- cgit v1.2.3 From 4acb29db0c5b9c8374865640772592a49f51ec5e Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 14:49:35 +0200 Subject: added operators <, == and != --- kernel/python_wrappers.cc | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 5e964dcac..015a303f8 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -91,6 +91,12 @@ namespace YOSYS_PYTHON { //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } bool in_pool_IdString(boost::python::list *rhs); + + bool operator<(IdString rhs) { return get_cpp_obj() ("Const") @@ -3275,6 +3308,9 @@ namespace YOSYS_PYTHON { .def("is_fully_def", &Const::is_fully_def) .def("is_fully_undef", &Const::is_fully_undef) .def("extract", &Const::extract) + .def(self < self) + .def(self == self) + .def(self != self) ; class_("CaseRule") @@ -3305,11 +3341,17 @@ namespace YOSYS_PYTHON { .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) .def("extract", &SigChunk::extract) + .def(self < self) + .def(self == self) + .def(self != self) ; class_("SigBit") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def(self < self) + .def(self == self) + .def(self != self) ; class_("SigSpec") @@ -3356,6 +3398,9 @@ namespace YOSYS_PYTHON { .def("parse_sel", &SigSpec::parse_sel) .def("parse_rhs", &SigSpec::parse_rhs) .def("check", &SigSpec::check) + .def(self < self) + .def(self == self) + .def(self != self) ; class_("Cell", no_init) -- cgit v1.2.3 From 038caab4e0de7e8c3b0dde8c77a716fbdb86cf1f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 15:25:43 +0200 Subject: Wrapped functions that use unsigned int or type_t as types --- kernel/python_wrappers.cc | 134 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 127 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 015a303f8..3d9094313 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -69,20 +69,29 @@ namespace YOSYS_PYTHON { } //WRAPPED static inline int get_reference(int idx) - static inline int get_reference(int idx); + static int get_reference(int idx); //WRAPPED static inline void put_reference(int idx) - static inline void put_reference(int idx); + static void put_reference(int idx); //WRAPPED std::string str() const { std::string str(); + //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { + std::string substr(size_t pos = 0, size_t len = std::string::npos); + + //WRAPPED size_t size() const { + size_t size(); + //WRAPPED bool empty() const { bool empty(); //WRAPPED void clear() { void clear(); + //WRAPPED unsigned int hash() const { + unsigned int hash(); + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } bool in_IdString(IdString *rhs); @@ -144,7 +153,7 @@ namespace YOSYS_PYTHON { std::string decode_string(); //WRAPPED inline int size() const { return bits.size(); } - inline int size(); + int size(); //WRAPPED bool is_fully_zero() const; bool is_fully_zero(); @@ -159,7 +168,10 @@ namespace YOSYS_PYTHON { bool is_fully_undef(); //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { - inline Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); + Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); + + //WRAPPED inline unsigned int hash() const { + unsigned int hash(); bool operator<(Const rhs) { return get_cpp_obj() get_cpp_obj()->str(); } + //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { + std::string IdString::substr(size_t pos, size_t len) + { + return this->get_cpp_obj()->substr(pos, len); + } + + //WRAPPED size_t size() const { + size_t IdString::size() + { + return this->get_cpp_obj()->size(); + } + //WRAPPED bool empty() const { bool IdString::empty() { @@ -1737,6 +1785,12 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->clear(); } + //WRAPPED unsigned int hash() const { + unsigned int IdString::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } bool IdString::in_IdString(IdString *rhs) { @@ -1825,6 +1879,12 @@ namespace YOSYS_PYTHON { return Const(this->get_cpp_obj()->extract(offset, len, padding)); } + //WRAPPED inline unsigned int hash() const { + inline unsigned int Const::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED RTLIL::CaseRule *clone() const; CaseRule CaseRule::clone() { @@ -1855,6 +1915,18 @@ namespace YOSYS_PYTHON { return SigChunk(this->get_cpp_obj()->extract(offset, length)); } + //WRAPPED unsigned int hash() const; + unsigned int SigBit::hash() + { + return this->get_cpp_obj()->hash(); + } + + //WRAPPED size_t get_hash() const { + size_t SigSpec::get_hash() + { + return this->get_cpp_obj()->get_hash(); + } + //WRAPPED inline int size() const { return width_; } inline int SigSpec::size() { @@ -2111,12 +2183,24 @@ namespace YOSYS_PYTHON { return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); } + //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; + unsigned int SigSpec::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED void check() const; void SigSpec::check() { this->get_cpp_obj()->check(); } + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Cell::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED bool hasPort(RTLIL::IdString portname) const; bool Cell::hasPort(IdString *portname) { @@ -2183,6 +2267,24 @@ namespace YOSYS_PYTHON { return this->get_cpp_obj()->has_keep_attr(); } + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Wire::hash() + { + return this->get_cpp_obj()->hash(); + } + + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Memory::hash() + { + return this->get_cpp_obj()->hash(); + } + + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Module::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED void connect(const RTLIL::SigSig &conn); void Module::connect_SigSig(PyObject* conn) { @@ -3096,6 +3198,12 @@ namespace YOSYS_PYTHON { return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src)); } + //WRAPPED unsigned int hash() const { return hashidx_; } + unsigned int Design::hash() + { + return this->get_cpp_obj()->hash(); + } + //WRAPPED RTLIL::Module *module(RTLIL::IdString name); Module Design::module(IdString *name) { @@ -3284,8 +3392,11 @@ namespace YOSYS_PYTHON { .def("get_reference", &IdString::get_reference) .def("put_reference", &IdString::put_reference) .def("str", &IdString::str) + .def("substr", &IdString::substr) + .def("size", &IdString::size) .def("empty", &IdString::empty) .def("clear", &IdString::clear) + .def("hash", &IdString::hash) .def("in_IdString", &IdString::in_IdString) .def("in_std_string", &IdString::in_std_string) .def("in_pool_IdString", &IdString::in_pool_IdString) @@ -3308,6 +3419,7 @@ namespace YOSYS_PYTHON { .def("is_fully_def", &Const::is_fully_def) .def("is_fully_undef", &Const::is_fully_undef) .def("extract", &Const::extract) + .def("hash", &Const::hash) .def(self < self) .def(self == self) .def(self != self) @@ -3349,6 +3461,7 @@ namespace YOSYS_PYTHON { class_("SigBit") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hash", &SigBit::hash) .def(self < self) .def(self == self) .def(self != self) @@ -3357,6 +3470,7 @@ namespace YOSYS_PYTHON { class_("SigSpec") .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("get_hash", &SigSpec::get_hash) .def("size", &SigSpec::size) .def("empty", &SigSpec::empty) .def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec) @@ -3397,6 +3511,7 @@ namespace YOSYS_PYTHON { .def("parse", &SigSpec::parse) .def("parse_sel", &SigSpec::parse_sel) .def("parse_rhs", &SigSpec::parse_rhs) + .def("hash", &SigSpec::hash) .def("check", &SigSpec::check) .def(self < self) .def(self == self) @@ -3406,6 +3521,7 @@ namespace YOSYS_PYTHON { class_("Cell", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hash", &Cell::hash) .def("hasPort", &Cell::hasPort) .def("unsetPort", &Cell::unsetPort) .def("setPort", &Cell::setPort) @@ -3422,11 +3538,13 @@ namespace YOSYS_PYTHON { class_("Wire", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hash", &Wire::hash) ; class_("Memory", no_init) .def(boost::python::self_ns::str(boost::python::self_ns::self)) .def(boost::python::self_ns::repr(boost::python::self_ns::self)) + .def("hash", &Memory::hash) ; class_("Module") @@ -3435,6 +3553,7 @@ namespace YOSYS_PYTHON { .def("get_cells", &Module::get_cells) .def("get_wires", &Module::get_wires) .def("register_monitor", &Module::register_monitor) + .def("hash", &Module::hash) .def("connect_SigSig", &Module::connect_SigSig) .def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec) .def("new_connections", &Module::new_connections) @@ -3593,6 +3712,7 @@ namespace YOSYS_PYTHON { .def("get_modules", &Design::get_modules) .def("run", &Design::run) .def("register_monitor", &Design::register_monitor) + .def("hash", &Design::hash) .def("module", &Design::module) .def("has", &Design::has) .def("add", &Design::add) -- cgit v1.2.3 From 60608a86bbeddbb8e2fe736adb931d757ed92bda Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 22 Aug 2018 11:59:22 +0200 Subject: Fixed Identation --- kernel/python_wrappers.cc | 377 +++++++++++++++++++++++----------------------- 1 file changed, 188 insertions(+), 189 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 3d9094313..5ca4e6e6a 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -1541,148 +1541,148 @@ namespace YOSYS_PYTHON { return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - struct Monitor : public Yosys::RTLIL::Monitor - { - - virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_add(new Module(module)); - } - - virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_del(new Module(module)); - } - - virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE - { - Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); - Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); - py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig)); - delete tmp_port; - delete tmp_old_sig; - } - - virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE - { - Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); - Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); - py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second))); - delete first; - delete second; - } - - virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE - { - boost::python::list sigsig_list; - for(auto sigsig : sigsig_vec) - sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second))); - py_notify_connect_list(new Module(module), sigsig_list); - } - - virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_blackout(new Module(module)); - } - - virtual void py_notify_module_add(Module*){}; - virtual void py_notify_module_del(Module*){}; - virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){}; - virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; - virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; - virtual void py_notify_blackout(Module*){}; - }; - - struct MonitorWrap : Monitor, boost::python::wrapper - { - void py_notify_module_add(Module* m) - { - if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) - py_notify_module_add(m); - else - Monitor::py_notify_module_add(m); - } - - void default_py_notify_module_add(Module* m) - { - this->Monitor::py_notify_module_add(m); - } - - void py_notify_module_del(Module* m) - { - if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) - py_notify_module_del(m); - else - Monitor::py_notify_module_del(m); - } - - void default_py_notify_module_del(Module* m) - { - this->Monitor::py_notify_module_del(m); - } - - void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) - { - if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) - py_notify_connect_cell(cell, port, old_sig, sig); - else - Monitor::py_notify_connect_cell(cell, port, old_sig, sig); - } - - void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) - { - this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); - } - - void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) - { - if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) - py_notify_connect_tuple(module, sigsig); - else - Monitor::py_notify_connect_tuple(module, sigsig); - } - - void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) - { - this->Monitor::py_notify_connect_tuple(module, sigsig); - } - - void py_notify_connect_list(Module* module, boost::python::list sigsig_list) - { - if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) - py_notify_connect_list(module, sigsig_list); - else - Monitor::py_notify_connect_list(module, sigsig_list); - } - - void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list) - { - this->Monitor::py_notify_connect_list(module, sigsig_list); - } - - void py_notify_blackout(Module* m) - { - if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) - py_notify_blackout(m); - else - Monitor::py_notify_blackout(m); - } - - void default_py_notify_blackout(Module* m) - { - this->Monitor::py_notify_blackout(m); - } - }; - - struct PyPass : public Yosys::Pass - { + struct Monitor : public Yosys::RTLIL::Monitor + { + + virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_add(new Module(module)); + } + + virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_module_del(new Module(module)); + } + + virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE + { + Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); + Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); + py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig)); + delete tmp_port; + delete tmp_old_sig; + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE + { + Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); + Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); + py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second))); + delete first; + delete second; + } + + virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + { + boost::python::list sigsig_list; + for(auto sigsig : sigsig_vec) + sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second))); + py_notify_connect_list(new Module(module), sigsig_list); + } + + virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE + { + py_notify_blackout(new Module(module)); + } + + virtual void py_notify_module_add(Module*){}; + virtual void py_notify_module_del(Module*){}; + virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){}; + virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; + virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; + virtual void py_notify_blackout(Module*){}; + }; + + struct MonitorWrap : Monitor, boost::python::wrapper + { + void py_notify_module_add(Module* m) + { + if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) + py_notify_module_add(m); + else + Monitor::py_notify_module_add(m); + } + + void default_py_notify_module_add(Module* m) + { + this->Monitor::py_notify_module_add(m); + } + + void py_notify_module_del(Module* m) + { + if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) + py_notify_module_del(m); + else + Monitor::py_notify_module_del(m); + } + + void default_py_notify_module_del(Module* m) + { + this->Monitor::py_notify_module_del(m); + } + + void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + { + if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) + py_notify_connect_cell(cell, port, old_sig, sig); + else + Monitor::py_notify_connect_cell(cell, port, old_sig, sig); + } + + void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + { + this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); + } + + void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + { + if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) + py_notify_connect_tuple(module, sigsig); + else + Monitor::py_notify_connect_tuple(module, sigsig); + } + + void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + { + this->Monitor::py_notify_connect_tuple(module, sigsig); + } + + void py_notify_connect_list(Module* module, boost::python::list sigsig_list) + { + if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) + py_notify_connect_list(module, sigsig_list); + else + Monitor::py_notify_connect_list(module, sigsig_list); + } + + void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list) + { + this->Monitor::py_notify_connect_list(module, sigsig_list); + } + + void py_notify_blackout(Module* m) + { + if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) + py_notify_blackout(m); + else + Monitor::py_notify_blackout(m); + } + + void default_py_notify_blackout(Module* m) + { + this->Monitor::py_notify_blackout(m); + } + }; + + struct PyPass : public Yosys::Pass + { PyPass(std::string name, std::string short_help) : Yosys::Pass(name, short_help) { } virtual void execute(vector args, Yosys::RTLIL::Design* d) YS_OVERRIDE { boost::python::list py_args; - for(auto arg : args) - py_args.append(arg); + for(auto arg : args) + py_args.append(arg); py_execute(py_args, new Design(d)); } @@ -1693,19 +1693,19 @@ namespace YOSYS_PYTHON { virtual void py_execute(boost::python::list args, Design* d){} virtual void py_help(){} - }; + }; - struct PassWrap : PyPass, boost::python::wrapper - { + struct PassWrap : PyPass, boost::python::wrapper + { PassWrap(std::string name, std::string short_help) : PyPass(name, short_help) { } void py_execute(boost::python::list args, Design* d) { - if(boost::python::override py_execute = this->get_override("py_execute")) - py_execute(args, d); - else - PyPass::py_execute(args, d); + if(boost::python::override py_execute = this->get_override("py_execute")) + py_execute(args, d); + else + PyPass::py_execute(args, d); } void default_py_execute(boost::python::list args, Design* d) @@ -1715,17 +1715,17 @@ namespace YOSYS_PYTHON { void py_help() { - if(boost::python::override py_help = this->get_override("py_help")) - py_help(); - else - PyPass::py_help(); + if(boost::python::override py_help = this->get_override("py_help")) + py_help(); + else + PyPass::py_help(); } void default_py_help() { this->PyPass::py_help(); } - }; + }; void Module::register_monitor(Monitor* const m) { @@ -3321,13 +3321,13 @@ namespace YOSYS_PYTHON { struct Initializer { Initializer() { - if(!Yosys::yosys_already_setup()) - { + if(!Yosys::yosys_already_setup()) + { Yosys::log_streams.push_back(&std::cout); Yosys::log_error_stderr = true; Yosys::yosys_setup(); Yosys::yosys_banner(); - } + } } Initializer(Initializer const &) {} @@ -3341,46 +3341,46 @@ namespace YOSYS_PYTHON { { using namespace boost::python; - enum_("State") - .value("S0",Yosys::RTLIL::S0) - .value("S1",Yosys::RTLIL::S1) - .value("Sx",Yosys::RTLIL::Sx) - .value("Sz",Yosys::RTLIL::Sz) - .value("Sa",Yosys::RTLIL::Sa) - .value("Sm",Yosys::RTLIL::Sm) - ; - - enum_("SyncType") - .value("ST0",Yosys::RTLIL::ST0) - .value("ST1",Yosys::RTLIL::ST1) - .value("STp",Yosys::RTLIL::STp) - .value("STn",Yosys::RTLIL::STn) - .value("STe",Yosys::RTLIL::STe) - .value("STa",Yosys::RTLIL::STa) - .value("STg",Yosys::RTLIL::STg) - .value("STi",Yosys::RTLIL::STi) - ; - - enum_("ConstFlags") - .value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE) - .value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING) - .value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED) - .value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL) - ; + enum_("State") + .value("S0",Yosys::RTLIL::S0) + .value("S1",Yosys::RTLIL::S1) + .value("Sx",Yosys::RTLIL::Sx) + .value("Sz",Yosys::RTLIL::Sz) + .value("Sa",Yosys::RTLIL::Sa) + .value("Sm",Yosys::RTLIL::Sm) + ; + + enum_("SyncType") + .value("ST0",Yosys::RTLIL::ST0) + .value("ST1",Yosys::RTLIL::ST1) + .value("STp",Yosys::RTLIL::STp) + .value("STn",Yosys::RTLIL::STn) + .value("STe",Yosys::RTLIL::STe) + .value("STa",Yosys::RTLIL::STa) + .value("STg",Yosys::RTLIL::STg) + .value("STi",Yosys::RTLIL::STi) + ; + + enum_("ConstFlags") + .value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE) + .value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING) + .value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED) + .value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL) + ; class_("Monitor") - .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) - .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) - .def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell) - .def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple) - .def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list) - .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) - ; + .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) + .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) + .def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell) + .def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple) + .def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list) + .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) + ; class_("Pass", init()) - .def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute) - .def("py_help", &PyPass::py_help, &PassWrap::default_py_help) - ; + .def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute) + .def("py_help", &PyPass::py_help, &PassWrap::default_py_help) + ; class_("Initializer"); scope().attr("_hidden") = new Initializer(); @@ -3772,7 +3772,6 @@ namespace YOSYS_PYTHON { def("const_pow", const_pow); def("const_pos", const_pos); def("const_neg", const_neg); - def("run",run); def("log",log); -- cgit v1.2.3 From 0ecfffa69c753b3d86d4d0e63311ed5b5cf2ab61 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 22 Aug 2018 14:42:42 +0200 Subject: Do not pass heap object to Python. This way they should be completely managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function --- kernel/python_wrappers.cc | 660 +++++++++++++++++++++++----------------------- 1 file changed, 337 insertions(+), 323 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index 5ca4e6e6a..d50c83a57 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -39,6 +39,7 @@ namespace YOSYS_PYTHON { Yosys::log("%s",text.c_str()); } + //WRAPPED from kernel/rtlil struct IdString { Yosys::RTLIL::IdString* ref_obj; @@ -113,6 +114,7 @@ namespace YOSYS_PYTHON { ostr << ref.ref_obj->str(); return ostr; } + //WRAPPED from kernel/rtlil struct Const { Yosys::RTLIL::Const* ref_obj; @@ -185,6 +187,7 @@ namespace YOSYS_PYTHON { ostr << ref.ref_obj->as_string(); return ostr; } + //WRAPPED from kernel/rtlil struct CaseRule { Yosys::RTLIL::CaseRule* ref_obj; @@ -218,6 +221,7 @@ namespace YOSYS_PYTHON { ostr << "CaseRule object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct SwitchRule { Yosys::RTLIL::SwitchRule* ref_obj; @@ -251,6 +255,7 @@ namespace YOSYS_PYTHON { ostr << "SwitchRule object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct SyncRule { Yosys::RTLIL::SyncRule* ref_obj; @@ -284,6 +289,7 @@ namespace YOSYS_PYTHON { ostr << "SyncRule object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct Process { Yosys::RTLIL::Process* ref_obj; @@ -317,6 +323,7 @@ namespace YOSYS_PYTHON { ostr << "Process with name " << ref.ref_obj->name.c_str(); return ostr; } + //WRAPPED from kernel/rtlil struct SigChunk { Yosys::RTLIL::SigChunk* ref_obj; @@ -356,6 +363,7 @@ namespace YOSYS_PYTHON { ostr << "SigChunk object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct SigBit { Yosys::RTLIL::SigBit* ref_obj; @@ -395,6 +403,7 @@ namespace YOSYS_PYTHON { ostr << "SigBit object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct SigSpec { Yosys::RTLIL::SigSpec* ref_obj; @@ -560,6 +569,7 @@ namespace YOSYS_PYTHON { ostr << "SigSpec object at " << ref.ref_obj; return ostr; } + //WRAPPED from kernel/rtlil struct Cell { unsigned int hashidx_; @@ -624,6 +634,7 @@ namespace YOSYS_PYTHON { ostr << "deleted Cell"; return ostr; } + //WRAPPED from kernel/rtlil struct Wire { unsigned int hashidx_; @@ -655,6 +666,7 @@ namespace YOSYS_PYTHON { ostr << "deleted Wire"; return ostr; } + //WRAPPED from kernel/rtlil struct Memory { unsigned int hashidx_; @@ -686,6 +698,7 @@ namespace YOSYS_PYTHON { ostr << "deleted Memory"; return ostr; } + //WRAPPED from kernel/rtlil struct Module { unsigned int hashidx_; @@ -715,7 +728,7 @@ namespace YOSYS_PYTHON { } for(auto &mod_it : cpp_obj->cells_) { - result.append(new Cell(mod_it.second)); + result.append(Cell(mod_it.second)); } return result; } @@ -730,7 +743,7 @@ namespace YOSYS_PYTHON { } for(auto &mod_it : cpp_obj->wires_) { - result.append(new Wire(mod_it.second)); + result.append(Wire(mod_it.second)); } return result; } @@ -1199,6 +1212,7 @@ namespace YOSYS_PYTHON { ostr << "deleted Module"; return ostr; } + //WRAPPED from kernel/rtlil struct Design { unsigned int hashidx_; @@ -1228,7 +1242,7 @@ namespace YOSYS_PYTHON { } for(auto &mod_it : cpp_obj->modules_) { - result.append(new Module(mod_it.second)); + result.append(Module(mod_it.second)); } return result; } @@ -1313,229 +1327,229 @@ namespace YOSYS_PYTHON { return ostr; } - //WRAPPED static inline std::string escape_id(std::string str) { + //WRAPPED static inline std::string escape_id(std::string str) { FROM FILE kernel/rtlil.h inline std::string escape_id(std::string str) { return Yosys::RTLIL::escape_id(str); } - //WRAPPED static inline std::string unescape_id(std::string str) { + //WRAPPED static inline std::string unescape_id(std::string str) { FROM FILE kernel/rtlil.h inline std::string unescape_id_std_string(std::string str) { return Yosys::RTLIL::unescape_id(str); } - //WRAPPED static inline std::string unescape_id(RTLIL::IdString str) { + //WRAPPED static inline std::string unescape_id(RTLIL::IdString str) { FROM FILE kernel/rtlil.h inline std::string unescape_id_IdString(IdString *str) { return Yosys::RTLIL::unescape_id(*str->get_cpp_obj()); } - //WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_reduce_bool(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_reduce_bool(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_logic_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_logic_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_logic_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_logic_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_logic_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_logic_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_shl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_shl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_shr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_shr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_sshl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_sshl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_sshr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_sshr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_shift(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_shift(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_shiftx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_shiftx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_lt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_lt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_le(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_le(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_eq(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_eq(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_ne(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_ne(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_eqx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_eqx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_nex(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_nex(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_ge(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_ge(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_gt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_gt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_add(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_add(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_sub(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_sub(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_mul(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_mul(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_div(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_div(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_mod(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_mod(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_pow(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_pow(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_pos(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_pos(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); } - //WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + //WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h Const const_neg(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) { return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); @@ -1546,19 +1560,19 @@ namespace YOSYS_PYTHON { virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE { - py_notify_module_add(new Module(module)); + py_notify_module_add(Module(module)); } virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE { - py_notify_module_del(new Module(module)); + py_notify_module_del(Module(module)); } virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE { Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); - py_notify_connect_cell(new Cell(cell), new IdString(tmp_port), new SigSpec(tmp_old_sig), new SigSpec(&sig)); + py_notify_connect_cell(Cell(cell), IdString(tmp_port), SigSpec(tmp_old_sig), SigSpec(&sig)); delete tmp_port; delete tmp_old_sig; } @@ -1567,7 +1581,7 @@ namespace YOSYS_PYTHON { { Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); - py_notify_connect_tuple(new Module(module), boost::python::make_tuple(new SigSpec(first), new SigSpec(second))); + py_notify_connect_tuple(Module(module), boost::python::make_tuple(SigSpec(first), SigSpec(second))); delete first; delete second; } @@ -1576,26 +1590,26 @@ namespace YOSYS_PYTHON { { boost::python::list sigsig_list; for(auto sigsig : sigsig_vec) - sigsig_list.append(boost::python::make_tuple(new SigSpec(&sigsig.first), new SigSpec(&sigsig.second))); - py_notify_connect_list(new Module(module), sigsig_list); + sigsig_list.append(boost::python::make_tuple(SigSpec(&sigsig.first), SigSpec(&sigsig.second))); + py_notify_connect_list(Module(module), sigsig_list); } virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE { - py_notify_blackout(new Module(module)); + py_notify_blackout(Module(module)); } - virtual void py_notify_module_add(Module*){}; - virtual void py_notify_module_del(Module*){}; - virtual void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig){}; - virtual void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig){}; - virtual void py_notify_connect_list(Module* module, boost::python::list sigsig_list){}; - virtual void py_notify_blackout(Module*){}; + virtual void py_notify_module_add(Module){}; + virtual void py_notify_module_del(Module){}; + virtual void py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig){}; + virtual void py_notify_connect_tuple(Module module, boost::python::tuple sigsig){}; + virtual void py_notify_connect_list(Module module, boost::python::list sigsig_list){}; + virtual void py_notify_blackout(Module){}; }; struct MonitorWrap : Monitor, boost::python::wrapper { - void py_notify_module_add(Module* m) + void py_notify_module_add(Module m) { if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) py_notify_module_add(m); @@ -1603,12 +1617,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_module_add(m); } - void default_py_notify_module_add(Module* m) + void default_py_notify_module_add(Module m) { this->Monitor::py_notify_module_add(m); } - void py_notify_module_del(Module* m) + void py_notify_module_del(Module m) { if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) py_notify_module_del(m); @@ -1616,12 +1630,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_module_del(m); } - void default_py_notify_module_del(Module* m) + void default_py_notify_module_del(Module m) { this->Monitor::py_notify_module_del(m); } - void py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + void py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig) { if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) py_notify_connect_cell(cell, port, old_sig, sig); @@ -1629,12 +1643,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_connect_cell(cell, port, old_sig, sig); } - void default_py_notify_connect_cell(Cell *cell, IdString *port, SigSpec *old_sig, SigSpec *sig) + void default_py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig) { this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); } - void py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + void py_notify_connect_tuple(Module module, boost::python::tuple sigsig) { if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) py_notify_connect_tuple(module, sigsig); @@ -1642,12 +1656,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_connect_tuple(module, sigsig); } - void default_py_notify_connect_tuple(Module *module, boost::python::tuple sigsig) + void default_py_notify_connect_tuple(Module module, boost::python::tuple sigsig) { this->Monitor::py_notify_connect_tuple(module, sigsig); } - void py_notify_connect_list(Module* module, boost::python::list sigsig_list) + void py_notify_connect_list(Module module, boost::python::list sigsig_list) { if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) py_notify_connect_list(module, sigsig_list); @@ -1655,12 +1669,12 @@ namespace YOSYS_PYTHON { Monitor::py_notify_connect_list(module, sigsig_list); } - void default_py_notify_connect_list(Module* module, boost::python::list sigsig_list) + void default_py_notify_connect_list(Module module, boost::python::list sigsig_list) { this->Monitor::py_notify_connect_list(module, sigsig_list); } - void py_notify_blackout(Module* m) + void py_notify_blackout(Module m) { if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) py_notify_blackout(m); @@ -1668,7 +1682,7 @@ namespace YOSYS_PYTHON { Monitor::py_notify_blackout(m); } - void default_py_notify_blackout(Module* m) + void default_py_notify_blackout(Module m) { this->Monitor::py_notify_blackout(m); } @@ -1743,67 +1757,67 @@ namespace YOSYS_PYTHON { cpp_design->monitors.insert(m); } - //WRAPPED static inline int get_reference(int idx) + //WRAPPED static inline int get_reference(int idx) FROM FILE kernel/rtlil.h inline int IdString::get_reference(int idx) { return Yosys::RTLIL::IdString::get_reference(idx); } - //WRAPPED static inline void put_reference(int idx) + //WRAPPED static inline void put_reference(int idx) FROM FILE kernel/rtlil.h inline void IdString::put_reference(int idx) { Yosys::RTLIL::IdString::put_reference(idx); } - //WRAPPED std::string str() const { + //WRAPPED std::string str() const { FROM FILE kernel/rtlil.h std::string IdString::str() { return this->get_cpp_obj()->str(); } - //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { + //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { FROM FILE kernel/rtlil.h std::string IdString::substr(size_t pos, size_t len) { return this->get_cpp_obj()->substr(pos, len); } - //WRAPPED size_t size() const { + //WRAPPED size_t size() const { FROM FILE kernel/rtlil.h size_t IdString::size() { return this->get_cpp_obj()->size(); } - //WRAPPED bool empty() const { + //WRAPPED bool empty() const { FROM FILE kernel/rtlil.h bool IdString::empty() { return this->get_cpp_obj()->empty(); } - //WRAPPED void clear() { + //WRAPPED void clear() { FROM FILE kernel/rtlil.h void IdString::clear() { this->get_cpp_obj()->clear(); } - //WRAPPED unsigned int hash() const { + //WRAPPED unsigned int hash() const { FROM FILE kernel/rtlil.h unsigned int IdString::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED bool in(IdString rhs) const { return *this == rhs; } + //WRAPPED bool in(IdString rhs) const { return *this == rhs; } FROM FILE kernel/rtlil.h bool IdString::in_IdString(IdString *rhs) { return this->get_cpp_obj()->in(*rhs->get_cpp_obj()); } - //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } + //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } FROM FILE kernel/rtlil.h bool IdString::in_std_string(std::string rhs) { return this->get_cpp_obj()->in(rhs); } - //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } + //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } FROM FILE kernel/rtlil.h bool IdString::in_pool_IdString(boost::python::list *rhs) { pool rhs_; @@ -1813,169 +1827,169 @@ namespace YOSYS_PYTHON { return this->get_cpp_obj()->in(rhs_); } - //WRAPPED bool as_bool() const; + //WRAPPED bool as_bool() const; FROM FILE kernel/rtlil.h bool Const::as_bool() { return this->get_cpp_obj()->as_bool(); } - //WRAPPED int as_int(bool is_signed = false) const; + //WRAPPED int as_int(bool is_signed = false) const; FROM FILE kernel/rtlil.h int Const::as_int(bool is_signed) { return this->get_cpp_obj()->as_int(is_signed); } - //WRAPPED std::string as_string() const; + //WRAPPED std::string as_string() const; FROM FILE kernel/rtlil.h std::string Const::as_string() { return this->get_cpp_obj()->as_string(); } - //WRAPPED static Const from_string(std::string str); + //WRAPPED static Const from_string(std::string str); FROM FILE kernel/rtlil.h Const Const::from_string(std::string str) { return Const(Yosys::RTLIL::Const::from_string(str)); } - //WRAPPED std::string decode_string() const; + //WRAPPED std::string decode_string() const; FROM FILE kernel/rtlil.h std::string Const::decode_string() { return this->get_cpp_obj()->decode_string(); } - //WRAPPED inline int size() const { return bits.size(); } + //WRAPPED inline int size() const { return bits.size(); } FROM FILE kernel/rtlil.h inline int Const::size() { return this->get_cpp_obj()->size(); } - //WRAPPED bool is_fully_zero() const; + //WRAPPED bool is_fully_zero() const; FROM FILE kernel/rtlil.h bool Const::is_fully_zero() { return this->get_cpp_obj()->is_fully_zero(); } - //WRAPPED bool is_fully_ones() const; + //WRAPPED bool is_fully_ones() const; FROM FILE kernel/rtlil.h bool Const::is_fully_ones() { return this->get_cpp_obj()->is_fully_ones(); } - //WRAPPED bool is_fully_def() const; + //WRAPPED bool is_fully_def() const; FROM FILE kernel/rtlil.h bool Const::is_fully_def() { return this->get_cpp_obj()->is_fully_def(); } - //WRAPPED bool is_fully_undef() const; + //WRAPPED bool is_fully_undef() const; FROM FILE kernel/rtlil.h bool Const::is_fully_undef() { return this->get_cpp_obj()->is_fully_undef(); } - //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { + //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { FROM FILE kernel/rtlil.h inline Const Const::extract(int offset, int len, State padding) { return Const(this->get_cpp_obj()->extract(offset, len, padding)); } - //WRAPPED inline unsigned int hash() const { + //WRAPPED inline unsigned int hash() const { FROM FILE kernel/rtlil.h inline unsigned int Const::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED RTLIL::CaseRule *clone() const; + //WRAPPED RTLIL::CaseRule *clone() const; FROM FILE kernel/rtlil.h CaseRule CaseRule::clone() { return CaseRule(this->get_cpp_obj()->clone()); } - //WRAPPED RTLIL::SwitchRule *clone() const; + //WRAPPED RTLIL::SwitchRule *clone() const; FROM FILE kernel/rtlil.h SwitchRule SwitchRule::clone() { return SwitchRule(this->get_cpp_obj()->clone()); } - //WRAPPED RTLIL::SyncRule *clone() const; + //WRAPPED RTLIL::SyncRule *clone() const; FROM FILE kernel/rtlil.h SyncRule SyncRule::clone() { return SyncRule(this->get_cpp_obj()->clone()); } - //WRAPPED RTLIL::Process *clone() const; + //WRAPPED RTLIL::Process *clone() const; FROM FILE kernel/rtlil.h Process Process::clone() { return Process(this->get_cpp_obj()->clone()); } - //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; + //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; FROM FILE kernel/rtlil.h SigChunk SigChunk::extract(int offset, int length) { return SigChunk(this->get_cpp_obj()->extract(offset, length)); } - //WRAPPED unsigned int hash() const; + //WRAPPED unsigned int hash() const; FROM FILE kernel/rtlil.h unsigned int SigBit::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED size_t get_hash() const { + //WRAPPED size_t get_hash() const { FROM FILE kernel/rtlil.h size_t SigSpec::get_hash() { return this->get_cpp_obj()->get_hash(); } - //WRAPPED inline int size() const { return width_; } + //WRAPPED inline int size() const { return width_; } FROM FILE kernel/rtlil.h inline int SigSpec::size() { return this->get_cpp_obj()->size(); } - //WRAPPED inline bool empty() const { return width_ == 0; } + //WRAPPED inline bool empty() const { return width_ == 0; } FROM FILE kernel/rtlil.h inline bool SigSpec::empty() { return this->get_cpp_obj()->empty(); } - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); FROM FILE kernel/rtlil.h void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with) { this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj()); } - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; + //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h void SigSpec::replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other) { this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj(), other->get_cpp_obj()); } - //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); + //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); FROM FILE kernel/rtlil.h void SigSpec::replace_int_SigSpec(int offset, SigSpec *with) { this->get_cpp_obj()->replace(offset, *with->get_cpp_obj()); } - //WRAPPED void remove(const RTLIL::SigSpec &pattern); + //WRAPPED void remove(const RTLIL::SigSpec &pattern); FROM FILE kernel/rtlil.h void SigSpec::remove_SigSpec(SigSpec *pattern) { this->get_cpp_obj()->remove(*pattern->get_cpp_obj()); } - //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; + //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h void SigSpec::remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) { this->get_cpp_obj()->remove(*pattern->get_cpp_obj(), other->get_cpp_obj()); } - //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); + //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h void SigSpec::remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) { this->get_cpp_obj()->remove2(*pattern->get_cpp_obj(), other->get_cpp_obj()); } - //WRAPPED void remove(const pool &pattern); + //WRAPPED void remove(const pool &pattern); FROM FILE kernel/rtlil.h void SigSpec::remove_pool_SigBit(boost::python::list *pattern) { pool pattern_; @@ -1985,7 +1999,7 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->remove(pattern_); } - //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; + //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) { pool pattern_; @@ -1995,7 +2009,7 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj()); } - //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); + //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) { pool pattern_; @@ -2005,19 +2019,19 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj()); } - //WRAPPED void remove(int offset, int length = 1); + //WRAPPED void remove(int offset, int length = 1); FROM FILE kernel/rtlil.h void SigSpec::remove_int_int(int offset, int length) { this->get_cpp_obj()->remove(offset, length); } - //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; + //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h SigSpec SigSpec::extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) { return SigSpec(this->get_cpp_obj()->extract(*pattern->get_cpp_obj(), other->get_cpp_obj())); } - //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; + //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) { pool pattern_; @@ -2027,265 +2041,265 @@ namespace YOSYS_PYTHON { return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj())); } - //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; + //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; FROM FILE kernel/rtlil.h SigSpec SigSpec::extract_int_int(int offset, int length) { return SigSpec(this->get_cpp_obj()->extract(offset, length)); } - //WRAPPED void append(const RTLIL::SigSpec &signal); + //WRAPPED void append(const RTLIL::SigSpec &signal); FROM FILE kernel/rtlil.h void SigSpec::append(SigSpec *signal) { this->get_cpp_obj()->append(*signal->get_cpp_obj()); } - //WRAPPED void append_bit(const RTLIL::SigBit &bit); + //WRAPPED void append_bit(const RTLIL::SigBit &bit); FROM FILE kernel/rtlil.h void SigSpec::append_bit(SigBit *bit) { this->get_cpp_obj()->append_bit(*bit->get_cpp_obj()); } - //WRAPPED void extend_u0(int width, bool is_signed = false); + //WRAPPED void extend_u0(int width, bool is_signed = false); FROM FILE kernel/rtlil.h void SigSpec::extend_u0(int width, bool is_signed) { this->get_cpp_obj()->extend_u0(width, is_signed); } - //WRAPPED RTLIL::SigSpec repeat(int num) const; + //WRAPPED RTLIL::SigSpec repeat(int num) const; FROM FILE kernel/rtlil.h SigSpec SigSpec::repeat(int num) { return SigSpec(this->get_cpp_obj()->repeat(num)); } - //WRAPPED bool is_wire() const; + //WRAPPED bool is_wire() const; FROM FILE kernel/rtlil.h bool SigSpec::is_wire() { return this->get_cpp_obj()->is_wire(); } - //WRAPPED bool is_chunk() const; + //WRAPPED bool is_chunk() const; FROM FILE kernel/rtlil.h bool SigSpec::is_chunk() { return this->get_cpp_obj()->is_chunk(); } - //WRAPPED inline bool is_bit() const { return width_ == 1; } + //WRAPPED inline bool is_bit() const { return width_ == 1; } FROM FILE kernel/rtlil.h inline bool SigSpec::is_bit() { return this->get_cpp_obj()->is_bit(); } - //WRAPPED bool is_fully_const() const; + //WRAPPED bool is_fully_const() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_const() { return this->get_cpp_obj()->is_fully_const(); } - //WRAPPED bool is_fully_zero() const; + //WRAPPED bool is_fully_zero() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_zero() { return this->get_cpp_obj()->is_fully_zero(); } - //WRAPPED bool is_fully_ones() const; + //WRAPPED bool is_fully_ones() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_ones() { return this->get_cpp_obj()->is_fully_ones(); } - //WRAPPED bool is_fully_def() const; + //WRAPPED bool is_fully_def() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_def() { return this->get_cpp_obj()->is_fully_def(); } - //WRAPPED bool is_fully_undef() const; + //WRAPPED bool is_fully_undef() const; FROM FILE kernel/rtlil.h bool SigSpec::is_fully_undef() { return this->get_cpp_obj()->is_fully_undef(); } - //WRAPPED bool has_const() const; + //WRAPPED bool has_const() const; FROM FILE kernel/rtlil.h bool SigSpec::has_const() { return this->get_cpp_obj()->has_const(); } - //WRAPPED bool has_marked_bits() const; + //WRAPPED bool has_marked_bits() const; FROM FILE kernel/rtlil.h bool SigSpec::has_marked_bits() { return this->get_cpp_obj()->has_marked_bits(); } - //WRAPPED bool as_bool() const; + //WRAPPED bool as_bool() const; FROM FILE kernel/rtlil.h bool SigSpec::as_bool() { return this->get_cpp_obj()->as_bool(); } - //WRAPPED int as_int(bool is_signed = false) const; + //WRAPPED int as_int(bool is_signed = false) const; FROM FILE kernel/rtlil.h int SigSpec::as_int(bool is_signed) { return this->get_cpp_obj()->as_int(is_signed); } - //WRAPPED std::string as_string() const; + //WRAPPED std::string as_string() const; FROM FILE kernel/rtlil.h std::string SigSpec::as_string() { return this->get_cpp_obj()->as_string(); } - //WRAPPED RTLIL::Const as_const() const; + //WRAPPED RTLIL::Const as_const() const; FROM FILE kernel/rtlil.h Const SigSpec::as_const() { return Const(this->get_cpp_obj()->as_const()); } - //WRAPPED RTLIL::Wire *as_wire() const; + //WRAPPED RTLIL::Wire *as_wire() const; FROM FILE kernel/rtlil.h Wire SigSpec::as_wire() { return Wire(this->get_cpp_obj()->as_wire()); } - //WRAPPED RTLIL::SigChunk as_chunk() const; + //WRAPPED RTLIL::SigChunk as_chunk() const; FROM FILE kernel/rtlil.h SigChunk SigSpec::as_chunk() { return SigChunk(this->get_cpp_obj()->as_chunk()); } - //WRAPPED RTLIL::SigBit as_bit() const; + //WRAPPED RTLIL::SigBit as_bit() const; FROM FILE kernel/rtlil.h SigBit SigSpec::as_bit() { return SigBit(this->get_cpp_obj()->as_bit()); } - //WRAPPED bool match(std::string pattern) const; + //WRAPPED bool match(std::string pattern) const; FROM FILE kernel/rtlil.h bool SigSpec::match(std::string pattern) { return this->get_cpp_obj()->match(pattern); } - //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h bool SigSpec::parse(SigSpec *sig, Module *module, std::string str) { return Yosys::RTLIL::SigSpec::parse(*sig->get_cpp_obj(), module->get_cpp_obj(), str); } - //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); + //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h bool SigSpec::parse_sel(SigSpec *sig, Design *design, Module *module, std::string str) { return Yosys::RTLIL::SigSpec::parse_sel(*sig->get_cpp_obj(), design->get_cpp_obj(), module->get_cpp_obj(), str); } - //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); + //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h bool SigSpec::parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str) { return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); } - //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; + //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; FROM FILE kernel/rtlil.h unsigned int SigSpec::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED void check() const; + //WRAPPED void check() const; FROM FILE kernel/rtlil.h void SigSpec::check() { this->get_cpp_obj()->check(); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Cell::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED bool hasPort(RTLIL::IdString portname) const; + //WRAPPED bool hasPort(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h bool Cell::hasPort(IdString *portname) { return this->get_cpp_obj()->hasPort(*portname->get_cpp_obj()); } - //WRAPPED void unsetPort(RTLIL::IdString portname); + //WRAPPED void unsetPort(RTLIL::IdString portname); FROM FILE kernel/rtlil.h void Cell::unsetPort(IdString *portname) { this->get_cpp_obj()->unsetPort(*portname->get_cpp_obj()); } - //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); + //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); FROM FILE kernel/rtlil.h void Cell::setPort(IdString *portname, SigSpec *signal) { this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj()); } - //WRAPPED bool known() const; + //WRAPPED bool known() const; FROM FILE kernel/rtlil.h bool Cell::known() { return this->get_cpp_obj()->known(); } - //WRAPPED bool input(RTLIL::IdString portname) const; + //WRAPPED bool input(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h bool Cell::input(IdString *portname) { return this->get_cpp_obj()->input(*portname->get_cpp_obj()); } - //WRAPPED bool output(RTLIL::IdString portname) const; + //WRAPPED bool output(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h bool Cell::output(IdString *portname) { return this->get_cpp_obj()->output(*portname->get_cpp_obj()); } - //WRAPPED bool hasParam(RTLIL::IdString paramname) const; + //WRAPPED bool hasParam(RTLIL::IdString paramname) const; FROM FILE kernel/rtlil.h bool Cell::hasParam(IdString *paramname) { return this->get_cpp_obj()->hasParam(*paramname->get_cpp_obj()); } - //WRAPPED void unsetParam(RTLIL::IdString paramname); + //WRAPPED void unsetParam(RTLIL::IdString paramname); FROM FILE kernel/rtlil.h void Cell::unsetParam(IdString *paramname) { this->get_cpp_obj()->unsetParam(*paramname->get_cpp_obj()); } - //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); + //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); FROM FILE kernel/rtlil.h void Cell::setParam(IdString *paramname, Const *value) { this->get_cpp_obj()->setParam(*paramname->get_cpp_obj(), *value->get_cpp_obj()); } - //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); + //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); FROM FILE kernel/rtlil.h void Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed); } - //WRAPPED bool has_keep_attr() const { + //WRAPPED bool has_keep_attr() const { FROM FILE kernel/rtlil.h bool Cell::has_keep_attr() { return this->get_cpp_obj()->has_keep_attr(); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Wire::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Memory::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Module::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED void connect(const RTLIL::SigSig &conn); + //WRAPPED void connect(const RTLIL::SigSig &conn); FROM FILE kernel/rtlil.h void Module::connect_SigSig(PyObject* conn) { if(!PyTuple_Check(conn) or PyTuple_Size(conn) != 2) @@ -2296,13 +2310,13 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->connect(conn_); } - //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); + //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); FROM FILE kernel/rtlil.h void Module::connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs) { this->get_cpp_obj()->connect(*lhs->get_cpp_obj(), *rhs->get_cpp_obj()); } - //WRAPPED void new_connections(const std::vector &new_conn); + //WRAPPED void new_connections(const std::vector &new_conn); FROM FILE kernel/rtlil.h void Module::new_connections(boost::python::list *new_conn) { std::vector new_conn_; @@ -2312,49 +2326,49 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->new_connections(new_conn_); } - //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; + //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; FROM FILE kernel/rtlil.h void Module::cloneInto(Module *new_mod) { this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj()); } - //WRAPPED bool has_memories() const; + //WRAPPED bool has_memories() const; FROM FILE kernel/rtlil.h bool Module::has_memories() { return this->get_cpp_obj()->has_memories(); } - //WRAPPED bool has_processes() const; + //WRAPPED bool has_processes() const; FROM FILE kernel/rtlil.h bool Module::has_processes() { return this->get_cpp_obj()->has_processes(); } - //WRAPPED bool has_memories_warn() const; + //WRAPPED bool has_memories_warn() const; FROM FILE kernel/rtlil.h bool Module::has_memories_warn() { return this->get_cpp_obj()->has_memories_warn(); } - //WRAPPED bool has_processes_warn() const; + //WRAPPED bool has_processes_warn() const; FROM FILE kernel/rtlil.h bool Module::has_processes_warn() { return this->get_cpp_obj()->has_processes_warn(); } - //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } + //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } FROM FILE kernel/rtlil.h Wire Module::wire(IdString *id) { return Wire(this->get_cpp_obj()->wire(*id->get_cpp_obj())); } - //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } + //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } FROM FILE kernel/rtlil.h Cell Module::cell(IdString *id) { return Cell(this->get_cpp_obj()->cell(*id->get_cpp_obj())); } - //WRAPPED void remove(const pool &wires); + //WRAPPED void remove(const pool &wires); FROM FILE kernel/rtlil.h void Module::remove_pool_Wire(boost::python::list *wires) { pool wires_; @@ -2364,955 +2378,955 @@ namespace YOSYS_PYTHON { this->get_cpp_obj()->remove(wires_); } - //WRAPPED void remove(RTLIL::Cell *cell); + //WRAPPED void remove(RTLIL::Cell *cell); FROM FILE kernel/rtlil.h void Module::remove_Cell(Cell *cell) { this->get_cpp_obj()->remove(cell->get_cpp_obj()); } - //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); + //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h void Module::rename_Wire_IdString(Wire *wire, IdString *new_name) { this->get_cpp_obj()->rename(wire->get_cpp_obj(), *new_name->get_cpp_obj()); } - //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); + //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h void Module::rename_Cell_IdString(Cell *cell, IdString *new_name) { this->get_cpp_obj()->rename(cell->get_cpp_obj(), *new_name->get_cpp_obj()); } - //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); + //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h void Module::rename_IdString_IdString(IdString *old_name, IdString *new_name) { this->get_cpp_obj()->rename(*old_name->get_cpp_obj(), *new_name->get_cpp_obj()); } - //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); + //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); FROM FILE kernel/rtlil.h void Module::swap_names_Wire_Wire(Wire *w1, Wire *w2) { this->get_cpp_obj()->swap_names(w1->get_cpp_obj(), w2->get_cpp_obj()); } - //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); + //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); FROM FILE kernel/rtlil.h void Module::swap_names_Cell_Cell(Cell *c1, Cell *c2) { this->get_cpp_obj()->swap_names(c1->get_cpp_obj(), c2->get_cpp_obj()); } - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); FROM FILE kernel/rtlil.h IdString Module::uniquify_IdString(IdString *name) { return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj())); } - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); + //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); FROM FILE kernel/rtlil.h IdString Module::uniquify_IdString_int(IdString *name, int index) { return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj(), index)); } - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); FROM FILE kernel/rtlil.h Wire Module::addWire_IdString_int(IdString *name, int width) { return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), width)); } - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); FROM FILE kernel/rtlil.h Wire Module::addWire_IdString_Wire(IdString *name, Wire *other) { return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), other->get_cpp_obj())); } - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); FROM FILE kernel/rtlil.h Cell Module::addCell_IdString_IdString(IdString *name, IdString *type) { return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), *type->get_cpp_obj())); } - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); FROM FILE kernel/rtlil.h Cell Module::addCell_IdString_Cell(IdString *name, Cell *other) { return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), other->get_cpp_obj())); } - //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addPos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addNeg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addShl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addShr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addSshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addSshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addShift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addShiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addEq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addNe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addEqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addNex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addGe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addGt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addAdd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addSub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addMul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addDiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addMod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed, bool b_signed, std::string src) { return Cell(this->get_cpp_obj()->addPow(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), a_signed, b_signed, src)); } - //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) { return Cell(this->get_cpp_obj()->addLogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addMux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addPmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src) { return Cell(this->get_cpp_obj()->addSlice(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *offset->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addConcat(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src) { return Cell(this->get_cpp_obj()->addLut(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *lut->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addTribuf(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addAssert(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addAssume(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addLive(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addFair(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) { return Cell(this->get_cpp_obj()->addCover(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addEquiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity, bool clr_polarity, std::string src) { return Cell(this->get_cpp_obj()->addSr(*name->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_q->get_cpp_obj(), set_polarity, clr_polarity, src)); } - //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) { return Cell(this->get_cpp_obj()->addFf(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); } - //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); } - //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); } - //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addBufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addNotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addAndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addNandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addOrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addNorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addXorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addXnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addAndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addOrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addMuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addAoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addOai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addAoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) { return Cell(this->get_cpp_obj()->addOai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) { return Cell(this->get_cpp_obj()->addFfGate(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); } - //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); } - //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); } - //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); } - //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Not(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Pos(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Pos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Neg(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Neg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->And(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Or(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Xor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Xnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->ReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Shl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Shr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Sshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Sshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Shift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Shiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Lt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Le(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Eq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Ne(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Eqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Nex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Ge(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Gt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Add(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Sub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Mul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Div(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->Mod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::LogicNot(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->LogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->LogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) { return SigSpec(this->get_cpp_obj()->LogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); } - //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) { return SigSpec(this->get_cpp_obj()->Mux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) { return SigSpec(this->get_cpp_obj()->Pmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::BufGate(IdString *name, SigBit *sig_a, std::string src) { return SigBit(this->get_cpp_obj()->BufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); + //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::NotGate(IdString *name, SigBit *sig_a, std::string src) { return SigBit(this->get_cpp_obj()->NotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->AndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->NandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->OrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->NorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->XorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->XnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->AndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); + //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) { return SigBit(this->get_cpp_obj()->OrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); + //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src) { return SigBit(this->get_cpp_obj()->MuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) { return SigBit(this->get_cpp_obj()->Aoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); + //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) { return SigBit(this->get_cpp_obj()->Oai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) { return SigBit(this->get_cpp_obj()->Aoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); + //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); FROM FILE kernel/rtlil.h SigBit Module::Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) { return SigBit(this->get_cpp_obj()->Oai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); } - //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Anyconst(IdString *name, int width, std::string src) { return SigSpec(this->get_cpp_obj()->Anyconst(*name->get_cpp_obj(), width, src)); } - //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Anyseq(IdString *name, int width, std::string src) { return SigSpec(this->get_cpp_obj()->Anyseq(*name->get_cpp_obj(), width, src)); } - //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Allconst(IdString *name, int width, std::string src) { return SigSpec(this->get_cpp_obj()->Allconst(*name->get_cpp_obj(), width, src)); } - //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Allseq(IdString *name, int width, std::string src) { return SigSpec(this->get_cpp_obj()->Allseq(*name->get_cpp_obj(), width, src)); } - //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); + //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Initstate(IdString *name, std::string src) { return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src)); } - //WRAPPED unsigned int hash() const { return hashidx_; } + //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h unsigned int Design::hash() { return this->get_cpp_obj()->hash(); } - //WRAPPED RTLIL::Module *module(RTLIL::IdString name); + //WRAPPED RTLIL::Module *module(RTLIL::IdString name); FROM FILE kernel/rtlil.h Module Design::module(IdString *name) { return Module(this->get_cpp_obj()->module(*name->get_cpp_obj())); } - //WRAPPED bool has(RTLIL::IdString id) const { + //WRAPPED bool has(RTLIL::IdString id) const { FROM FILE kernel/rtlil.h bool Design::has(IdString *id) { return this->get_cpp_obj()->has(*id->get_cpp_obj()); } - //WRAPPED void add(RTLIL::Module *module); + //WRAPPED void add(RTLIL::Module *module); FROM FILE kernel/rtlil.h void Design::add(Module *module) { this->get_cpp_obj()->add(module->get_cpp_obj()); } - //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); + //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); FROM FILE kernel/rtlil.h Module Design::addModule(IdString *name) { return Module(this->get_cpp_obj()->addModule(*name->get_cpp_obj())); } - //WRAPPED void remove(RTLIL::Module *module); + //WRAPPED void remove(RTLIL::Module *module); FROM FILE kernel/rtlil.h void Design::remove(Module *module) { this->get_cpp_obj()->remove(module->get_cpp_obj()); } - //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); + //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h void Design::rename(Module *module, IdString *new_name) { this->get_cpp_obj()->rename(module->get_cpp_obj(), *new_name->get_cpp_obj()); } - //WRAPPED void scratchpad_unset(std::string varname); + //WRAPPED void scratchpad_unset(std::string varname); FROM FILE kernel/rtlil.h void Design::scratchpad_unset(std::string varname) { this->get_cpp_obj()->scratchpad_unset(varname); } - //WRAPPED void scratchpad_set_int(std::string varname, int value); + //WRAPPED void scratchpad_set_int(std::string varname, int value); FROM FILE kernel/rtlil.h void Design::scratchpad_set_int(std::string varname, int value) { this->get_cpp_obj()->scratchpad_set_int(varname, value); } - //WRAPPED void scratchpad_set_bool(std::string varname, bool value); + //WRAPPED void scratchpad_set_bool(std::string varname, bool value); FROM FILE kernel/rtlil.h void Design::scratchpad_set_bool(std::string varname, bool value) { this->get_cpp_obj()->scratchpad_set_bool(varname, value); } - //WRAPPED void scratchpad_set_string(std::string varname, std::string value); + //WRAPPED void scratchpad_set_string(std::string varname, std::string value); FROM FILE kernel/rtlil.h void Design::scratchpad_set_string(std::string varname, std::string value) { this->get_cpp_obj()->scratchpad_set_string(varname, value); } - //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; + //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; FROM FILE kernel/rtlil.h int Design::scratchpad_get_int(std::string varname, int default_value) { return this->get_cpp_obj()->scratchpad_get_int(varname, default_value); } - //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; + //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; FROM FILE kernel/rtlil.h bool Design::scratchpad_get_bool(std::string varname, bool default_value) { return this->get_cpp_obj()->scratchpad_get_bool(varname, default_value); } - //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; + //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; FROM FILE kernel/rtlil.h std::string Design::scratchpad_get_string(std::string varname, std::string default_value) { return this->get_cpp_obj()->scratchpad_get_string(varname, default_value); } - //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; + //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; FROM FILE kernel/rtlil.h bool Design::selected_module_IdString(IdString *mod_name) { return this->get_cpp_obj()->selected_module(*mod_name->get_cpp_obj()); } - //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; + //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; FROM FILE kernel/rtlil.h bool Design::selected_whole_module_IdString(IdString *mod_name) { return this->get_cpp_obj()->selected_whole_module(*mod_name->get_cpp_obj()); } - //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; + //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; FROM FILE kernel/rtlil.h bool Design::selected_member(IdString *mod_name, IdString *memb_name) { return this->get_cpp_obj()->selected_member(*mod_name->get_cpp_obj(), *memb_name->get_cpp_obj()); } - //WRAPPED bool selected_module(RTLIL::Module *mod) const; + //WRAPPED bool selected_module(RTLIL::Module *mod) const; FROM FILE kernel/rtlil.h bool Design::selected_module_Module(Module *mod) { return this->get_cpp_obj()->selected_module(mod->get_cpp_obj()); } - //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; + //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; FROM FILE kernel/rtlil.h bool Design::selected_whole_module_Module(Module *mod) { return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj()); } - //WRAPPED bool full_selection() const { + //WRAPPED bool full_selection() const { FROM FILE kernel/rtlil.h bool Design::full_selection() { return this->get_cpp_obj()->full_selection(); -- cgit v1.2.3 From ba18e0f81aa8beeb3f6c82b5584d4c3e227c612b Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 23 Aug 2018 13:57:37 +0200 Subject: Fixed segfault / multiple free issue with lists --- kernel/python_wrappers.cc | 64 ++++++++++++++++++++++++++++------------------- 1 file changed, 38 insertions(+), 26 deletions(-) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index d50c83a57..be95ef23d 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -100,7 +100,7 @@ namespace YOSYS_PYTHON { bool in_std_string(std::string rhs); //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } - bool in_pool_IdString(boost::python::list *rhs); + bool in_pool_IdString(boost::python::list rhs); bool operator<(IdString rhs) { return get_cpp_obj() &pattern); - void remove_pool_SigBit(boost::python::list *pattern); + void remove_pool_SigBit(boost::python::list pattern); //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; - void remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + void remove_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); - void remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + void remove2_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); //WRAPPED void remove(int offset, int length = 1); void remove_int_int(int offset, int length = 1); @@ -471,7 +471,7 @@ namespace YOSYS_PYTHON { SigSpec extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; - SigSpec extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other); + SigSpec extract_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; SigSpec extract_int_int(int offset, int length = 1); @@ -760,7 +760,7 @@ namespace YOSYS_PYTHON { void connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs); //WRAPPED void new_connections(const std::vector &new_conn); - void new_connections(boost::python::list *new_conn); + void new_connections(boost::python::list new_conn); //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; void cloneInto(Module *new_mod); @@ -784,7 +784,7 @@ namespace YOSYS_PYTHON { Cell cell(IdString *id); //WRAPPED void remove(const pool &wires); - void remove_pool_Wire(boost::python::list *wires); + void remove_pool_Wire(boost::python::list wires); //WRAPPED void remove(RTLIL::Cell *cell); void remove_Cell(Cell *cell); @@ -1573,8 +1573,6 @@ namespace YOSYS_PYTHON { Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); py_notify_connect_cell(Cell(cell), IdString(tmp_port), SigSpec(tmp_old_sig), SigSpec(&sig)); - delete tmp_port; - delete tmp_old_sig; } virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE @@ -1582,15 +1580,13 @@ namespace YOSYS_PYTHON { Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); py_notify_connect_tuple(Module(module), boost::python::make_tuple(SigSpec(first), SigSpec(second))); - delete first; - delete second; } virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE { boost::python::list sigsig_list; for(auto sigsig : sigsig_vec) - sigsig_list.append(boost::python::make_tuple(SigSpec(&sigsig.first), SigSpec(&sigsig.second))); + sigsig_list.append(boost::python::make_tuple(*(new SigSpec(&sigsig.first)), *(new SigSpec(&sigsig.second)))); py_notify_connect_list(Module(module), sigsig_list); } @@ -1818,11 +1814,13 @@ namespace YOSYS_PYTHON { } //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } FROM FILE kernel/rtlil.h - bool IdString::in_pool_IdString(boost::python::list *rhs) + bool IdString::in_pool_IdString(boost::python::list rhs) { pool rhs_; - for(int i = 0; i < len(*rhs); ++i) + while(len(rhs) > 0) { + IdString tmp = boost::python::extract(rhs.pop()); + rhs_.insert(*tmp.get_cpp_obj()); } return this->get_cpp_obj()->in(rhs_); } @@ -1990,31 +1988,37 @@ namespace YOSYS_PYTHON { } //WRAPPED void remove(const pool &pattern); FROM FILE kernel/rtlil.h - void SigSpec::remove_pool_SigBit(boost::python::list *pattern) + void SigSpec::remove_pool_SigBit(boost::python::list pattern) { pool pattern_; - for(int i = 0; i < len(*pattern); ++i) + while(len(pattern) > 0) { + SigBit tmp = boost::python::extract(pattern.pop()); + pattern_.insert(*tmp.get_cpp_obj()); } this->get_cpp_obj()->remove(pattern_); } //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h - void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) { pool pattern_; - for(int i = 0; i < len(*pattern); ++i) + while(len(pattern) > 0) { + SigBit tmp = boost::python::extract(pattern.pop()); + pattern_.insert(*tmp.get_cpp_obj()); } this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj()); } //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h - void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) { pool pattern_; - for(int i = 0; i < len(*pattern); ++i) + while(len(pattern) > 0) { + SigBit tmp = boost::python::extract(pattern.pop()); + pattern_.insert(*tmp.get_cpp_obj()); } this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj()); } @@ -2032,11 +2036,13 @@ namespace YOSYS_PYTHON { } //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list *pattern, SigSpec *other) + SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) { pool pattern_; - for(int i = 0; i < len(*pattern); ++i) + while(len(pattern) > 0) { + SigBit tmp = boost::python::extract(pattern.pop()); + pattern_.insert(*tmp.get_cpp_obj()); } return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj())); } @@ -2317,11 +2323,15 @@ namespace YOSYS_PYTHON { } //WRAPPED void new_connections(const std::vector &new_conn); FROM FILE kernel/rtlil.h - void Module::new_connections(boost::python::list *new_conn) + void Module::new_connections(boost::python::list new_conn) { std::vector new_conn_; - for(int i = 0; i < len(*new_conn); ++i) + while(len(new_conn) > 0) { + boost::python::tuple tmp1 = boost::python::extract(new_conn.pop()); + SigSpec tmp2 = boost::python::extract(tmp1[0]); + SigSpec tmp3 = boost::python::extract(tmp1[1]); + new_conn_.push_back(Yosys::RTLIL::SigSig(*tmp2.get_cpp_obj(), *tmp3.get_cpp_obj())); } this->get_cpp_obj()->new_connections(new_conn_); } @@ -2369,11 +2379,13 @@ namespace YOSYS_PYTHON { } //WRAPPED void remove(const pool &wires); FROM FILE kernel/rtlil.h - void Module::remove_pool_Wire(boost::python::list *wires) + void Module::remove_pool_Wire(boost::python::list wires) { pool wires_; - for(int i = 0; i < len(*wires); ++i) + while(len(wires) > 0) { + Wire tmp = boost::python::extract(wires.pop()); + wires_.insert(tmp.get_cpp_obj()); } this->get_cpp_obj()->remove(wires_); } -- cgit v1.2.3 From 586d7df7e266b439c81f01266f8daf24be532b55 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 23 Aug 2018 14:39:44 +0200 Subject: added default yosys license text --- kernel/python_wrappers.cc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index be95ef23d..da438e4c6 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -1,3 +1,22 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + #ifdef WITH_PYTHON #include "yosys.h" -- cgit v1.2.3 From 604734b484f17b87f434506acc0d627cee39c0c2 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Thu, 23 Aug 2018 14:48:20 +0200 Subject: added functions whose definitions are split over multiple lines --- kernel/python_wrappers.cc | 60 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'kernel') diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc index da438e4c6..7e4525a9a 100644 --- a/kernel/python_wrappers.cc +++ b/kernel/python_wrappers.cc @@ -994,9 +994,18 @@ namespace YOSYS_PYTHON { //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); Cell addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addDffsr(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); + Cell addAdff(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, Const *arst_value, bool clk_polarity = true, bool arst_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); Cell addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addDlatchsr(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); Cell addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); @@ -1051,9 +1060,18 @@ namespace YOSYS_PYTHON { //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); Cell addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addDffsrGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + + //WRAPPED RTLIL::Cell* addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); + Cell addAdffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); Cell addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); + //WRAPPED RTLIL::Cell* addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); + Cell addDlatchsrGate(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); SigSpec Not(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); @@ -2787,12 +2805,30 @@ namespace YOSYS_PYTHON { return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); } + //WRAPPED RTLIL::Cell* addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addDffsr(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffsr(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, set_polarity, clr_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addAdff(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, Const *arst_value, bool clk_polarity, bool arst_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addAdff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_arst->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), *arst_value->get_cpp_obj(), clk_polarity, arst_polarity, src)); + } + //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); } + //WRAPPED RTLIL::Cell* addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addDlatchsr(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDlatchsr(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, set_polarity, clr_polarity, src)); + } + //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) { @@ -2901,12 +2937,30 @@ namespace YOSYS_PYTHON { return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); } + //WRAPPED RTLIL::Cell* addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addDffsrGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDffsrGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, set_polarity, clr_polarity, src)); + } + + //WRAPPED RTLIL::Cell* addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addAdffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, bool arst_value, bool clk_polarity, bool arst_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addAdffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_arst->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), arst_value, clk_polarity, arst_polarity, src)); + } + //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) { return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); } + //WRAPPED RTLIL::Cell* addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h + Cell Module::addDlatchsrGate(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, std::string src) + { + return Cell(this->get_cpp_obj()->addDlatchsrGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, set_polarity, clr_polarity, src)); + } + //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) { @@ -3673,7 +3727,10 @@ namespace YOSYS_PYTHON { .def("addFf", &Module::addFf) .def("addDff", &Module::addDff) .def("addDffe", &Module::addDffe) + .def("addDffsr", &Module::addDffsr) + .def("addAdff", &Module::addAdff) .def("addDlatch", &Module::addDlatch) + .def("addDlatchsr", &Module::addDlatchsr) .def("addBufGate", &Module::addBufGate) .def("addNotGate", &Module::addNotGate) .def("addAndGate", &Module::addAndGate) @@ -3692,7 +3749,10 @@ namespace YOSYS_PYTHON { .def("addFfGate", &Module::addFfGate) .def("addDffGate", &Module::addDffGate) .def("addDffeGate", &Module::addDffeGate) + .def("addDffsrGate", &Module::addDffsrGate) + .def("addAdffGate", &Module::addAdffGate) .def("addDlatchGate", &Module::addDlatchGate) + .def("addDlatchsrGate", &Module::addDlatchsrGate) .def("Not", &Module::Not) .def("Pos", &Module::Pos) .def("Neg", &Module::Neg) -- cgit v1.2.3 From c5e9034834ce0bcc6f6c611bc3ad3d244a32732f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 19 Sep 2018 10:16:53 +0200 Subject: Fix Cygwin build and document needed packages --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 264b1f63d..ad032899c 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -166,7 +166,7 @@ std::string vstringf(const char *fmt, va_list ap) std::string string; char *str = NULL; -#ifdef _WIN32 +#if defined(_WIN32 )|| defined(__CYGWIN__) int sz = 64, rc; while (1) { va_list apc; -- cgit v1.2.3 From 6f8abc11435abae7d3632a891bfa216da4c27acc Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 19 Sep 2018 10:32:34 +0200 Subject: Exposed generator script to make-process --- kernel/cost.h | 4 +- kernel/python_wrappers.cc | 3886 --------------------------------------------- 2 files changed, 2 insertions(+), 3888 deletions(-) delete mode 100644 kernel/python_wrappers.cc (limited to 'kernel') diff --git a/kernel/cost.h b/kernel/cost.h index e795b571b..41a09eb63 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache = nullptr); -int get_cell_cost(RTLIL::IdString type, const dict ¶meters = dict(), +inline int get_cell_cost(RTLIL::IdString type, const dict ¶meters = dict(), RTLIL::Design *design = nullptr, dict *mod_cost_cache = nullptr) { static dict gate_cost = { @@ -76,7 +76,7 @@ int get_cell_cost(RTLIL::IdString type, const dict *mod_cost_cache) +inline int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache) { return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache); } diff --git a/kernel/python_wrappers.cc b/kernel/python_wrappers.cc deleted file mode 100644 index 7e4525a9a..000000000 --- a/kernel/python_wrappers.cc +++ /dev/null @@ -1,3886 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifdef WITH_PYTHON - -#include "yosys.h" -#include -#include -#include -#include -#include -#include - -using namespace Yosys; - -namespace YOSYS_PYTHON { - - struct IdString; - struct Const; - struct CaseRule; - struct SwitchRule; - struct SyncRule; - struct Process; - struct SigChunk; - struct SigBit; - struct SigSpec; - struct Cell; - struct Wire; - struct Memory; - struct Module; - struct Design; - struct Monitor; - typedef Yosys::RTLIL::State State; - - void run(std::string command) - { - Yosys::run_pass(command); - } - - void log(std::string text) - { - Yosys::log("%s",text.c_str()); - } - - //WRAPPED from kernel/rtlil - struct IdString - { - Yosys::RTLIL::IdString* ref_obj; - - IdString(Yosys::RTLIL::IdString* ref = new Yosys::RTLIL::IdString()) - { - this->ref_obj = new Yosys::RTLIL::IdString(*ref); - } - - ~IdString() - { - delete(this->ref_obj); - } - - IdString(Yosys::RTLIL::IdString ref) - { - this->ref_obj = new Yosys::RTLIL::IdString(ref); - } - - IdString(const std::string &str) - { - this->ref_obj = new Yosys::RTLIL::IdString(str); - } - - Yosys::RTLIL::IdString* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED static inline int get_reference(int idx) - static int get_reference(int idx); - - //WRAPPED static inline void put_reference(int idx) - static void put_reference(int idx); - - //WRAPPED std::string str() const { - std::string str(); - - //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { - std::string substr(size_t pos = 0, size_t len = std::string::npos); - - //WRAPPED size_t size() const { - size_t size(); - - //WRAPPED bool empty() const { - bool empty(); - - //WRAPPED void clear() { - void clear(); - - //WRAPPED unsigned int hash() const { - unsigned int hash(); - - //WRAPPED bool in(IdString rhs) const { return *this == rhs; } - bool in_IdString(IdString *rhs); - - //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } - bool in_std_string(std::string rhs); - - //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } - bool in_pool_IdString(boost::python::list rhs); - - bool operator<(IdString rhs) { return get_cpp_obj() str(); - return ostr; - } - //WRAPPED from kernel/rtlil - struct Const - { - Yosys::RTLIL::Const* ref_obj; - - Const(Yosys::RTLIL::Const* ref = new Yosys::RTLIL::Const()) - { - this->ref_obj = new Yosys::RTLIL::Const(*ref); - } - - ~Const() - { - delete(this->ref_obj); - } - - Const(Yosys::RTLIL::Const ref) - { - this->ref_obj = new Yosys::RTLIL::Const(ref); - } - - Yosys::RTLIL::Const* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED bool as_bool() const; - bool as_bool(); - - //WRAPPED int as_int(bool is_signed = false) const; - int as_int(bool is_signed = false); - - //WRAPPED std::string as_string() const; - std::string as_string(); - - //WRAPPED static Const from_string(std::string str); - static Const from_string(std::string str); - - //WRAPPED std::string decode_string() const; - std::string decode_string(); - - //WRAPPED inline int size() const { return bits.size(); } - int size(); - - //WRAPPED bool is_fully_zero() const; - bool is_fully_zero(); - - //WRAPPED bool is_fully_ones() const; - bool is_fully_ones(); - - //WRAPPED bool is_fully_def() const; - bool is_fully_def(); - - //WRAPPED bool is_fully_undef() const; - bool is_fully_undef(); - - //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { - Const extract(int offset, int len = 1, State padding = RTLIL::State::S0); - - //WRAPPED inline unsigned int hash() const { - unsigned int hash(); - - bool operator<(Const rhs) { return get_cpp_obj() as_string(); - return ostr; - } - //WRAPPED from kernel/rtlil - struct CaseRule - { - Yosys::RTLIL::CaseRule* ref_obj; - - CaseRule(Yosys::RTLIL::CaseRule* ref = new Yosys::RTLIL::CaseRule()) - { - this->ref_obj = ref->clone(); - } - - ~CaseRule() - { - delete(this->ref_obj); - } - - CaseRule(Yosys::RTLIL::CaseRule ref) - { - this->ref_obj = ref.clone(); - } - - Yosys::RTLIL::CaseRule* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::CaseRule *clone() const; - CaseRule clone(); - }; - - std::ostream &operator<<(std::ostream &ostr, const CaseRule &ref) - { - ostr << "CaseRule object at " << ref.ref_obj; - return ostr; - } - //WRAPPED from kernel/rtlil - struct SwitchRule - { - Yosys::RTLIL::SwitchRule* ref_obj; - - SwitchRule(Yosys::RTLIL::SwitchRule* ref = new Yosys::RTLIL::SwitchRule()) - { - this->ref_obj = ref->clone(); - } - - ~SwitchRule() - { - delete(this->ref_obj); - } - - SwitchRule(Yosys::RTLIL::SwitchRule ref) - { - this->ref_obj = ref.clone(); - } - - Yosys::RTLIL::SwitchRule* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::SwitchRule *clone() const; - SwitchRule clone(); - }; - - std::ostream &operator<<(std::ostream &ostr, const SwitchRule &ref) - { - ostr << "SwitchRule object at " << ref.ref_obj; - return ostr; - } - //WRAPPED from kernel/rtlil - struct SyncRule - { - Yosys::RTLIL::SyncRule* ref_obj; - - SyncRule(Yosys::RTLIL::SyncRule* ref = new Yosys::RTLIL::SyncRule()) - { - this->ref_obj = ref->clone(); - } - - ~SyncRule() - { - delete(this->ref_obj); - } - - SyncRule(Yosys::RTLIL::SyncRule ref) - { - this->ref_obj = ref.clone(); - } - - Yosys::RTLIL::SyncRule* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::SyncRule *clone() const; - SyncRule clone(); - }; - - std::ostream &operator<<(std::ostream &ostr, const SyncRule &ref) - { - ostr << "SyncRule object at " << ref.ref_obj; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Process - { - Yosys::RTLIL::Process* ref_obj; - - Process(Yosys::RTLIL::Process* ref = new Yosys::RTLIL::Process()) - { - this->ref_obj = ref->clone(); - } - - ~Process() - { - delete(this->ref_obj); - } - - Process(Yosys::RTLIL::Process ref) - { - this->ref_obj = ref.clone(); - } - - Yosys::RTLIL::Process* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::Process *clone() const; - Process clone(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Process &ref) - { - ostr << "Process with name " << ref.ref_obj->name.c_str(); - return ostr; - } - //WRAPPED from kernel/rtlil - struct SigChunk - { - Yosys::RTLIL::SigChunk* ref_obj; - - SigChunk(Yosys::RTLIL::SigChunk* ref = new Yosys::RTLIL::SigChunk()) - { - this->ref_obj = new Yosys::RTLIL::SigChunk(*ref); - } - - ~SigChunk() - { - delete(this->ref_obj); - } - - SigChunk(Yosys::RTLIL::SigChunk ref) - { - this->ref_obj = new Yosys::RTLIL::SigChunk(ref); - } - - Yosys::RTLIL::SigChunk* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; - SigChunk extract(int offset, int length); - - bool operator<(SigChunk rhs) { return get_cpp_obj() ref_obj = new Yosys::RTLIL::SigBit(*ref); - } - - ~SigBit() - { - delete(this->ref_obj); - } - - SigBit(Yosys::RTLIL::SigBit ref) - { - this->ref_obj = new Yosys::RTLIL::SigBit(ref); - } - - Yosys::RTLIL::SigBit* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED unsigned int hash() const; - unsigned int hash(); - - bool operator<(SigBit rhs) { return get_cpp_obj() ref_obj = new Yosys::RTLIL::SigSpec(*ref); - } - - ~SigSpec() - { - delete(this->ref_obj); - } - - SigSpec(Yosys::RTLIL::SigSpec ref) - { - this->ref_obj = new Yosys::RTLIL::SigSpec(ref); - } - - Yosys::RTLIL::SigSpec* get_cpp_obj() const - { - return ref_obj; - } - - //WRAPPED size_t get_hash() const { - size_t get_hash(); - - //WRAPPED inline int size() const { return width_; } - int size(); - - //WRAPPED inline bool empty() const { return width_ == 0; } - bool empty(); - - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); - void replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with); - - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; - void replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other); - - //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); - void replace_int_SigSpec(int offset, SigSpec *with); - - //WRAPPED void remove(const RTLIL::SigSpec &pattern); - void remove_SigSpec(SigSpec *pattern); - - //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; - void remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); - - //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); - void remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); - - //WRAPPED void remove(const pool &pattern); - void remove_pool_SigBit(boost::python::list pattern); - - //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; - void remove_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); - - //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); - void remove2_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); - - //WRAPPED void remove(int offset, int length = 1); - void remove_int_int(int offset, int length = 1); - - //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; - SigSpec extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other); - - //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; - SigSpec extract_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other); - - //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; - SigSpec extract_int_int(int offset, int length = 1); - - //WRAPPED void append(const RTLIL::SigSpec &signal); - void append(SigSpec *signal); - - //WRAPPED void append_bit(const RTLIL::SigBit &bit); - void append_bit(SigBit *bit); - - //WRAPPED void extend_u0(int width, bool is_signed = false); - void extend_u0(int width, bool is_signed = false); - - //WRAPPED RTLIL::SigSpec repeat(int num) const; - SigSpec repeat(int num); - - //WRAPPED bool is_wire() const; - bool is_wire(); - - //WRAPPED bool is_chunk() const; - bool is_chunk(); - - //WRAPPED inline bool is_bit() const { return width_ == 1; } - bool is_bit(); - - //WRAPPED bool is_fully_const() const; - bool is_fully_const(); - - //WRAPPED bool is_fully_zero() const; - bool is_fully_zero(); - - //WRAPPED bool is_fully_ones() const; - bool is_fully_ones(); - - //WRAPPED bool is_fully_def() const; - bool is_fully_def(); - - //WRAPPED bool is_fully_undef() const; - bool is_fully_undef(); - - //WRAPPED bool has_const() const; - bool has_const(); - - //WRAPPED bool has_marked_bits() const; - bool has_marked_bits(); - - //WRAPPED bool as_bool() const; - bool as_bool(); - - //WRAPPED int as_int(bool is_signed = false) const; - int as_int(bool is_signed = false); - - //WRAPPED std::string as_string() const; - std::string as_string(); - - //WRAPPED RTLIL::Const as_const() const; - Const as_const(); - - //WRAPPED RTLIL::Wire *as_wire() const; - Wire as_wire(); - - //WRAPPED RTLIL::SigChunk as_chunk() const; - SigChunk as_chunk(); - - //WRAPPED RTLIL::SigBit as_bit() const; - SigBit as_bit(); - - //WRAPPED bool match(std::string pattern) const; - bool match(std::string pattern); - - //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); - static bool parse(SigSpec *sig, Module *module, std::string str); - - //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); - static bool parse_sel(SigSpec *sig, Design *design, Module *module, std::string str); - - //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); - static bool parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str); - - //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; - unsigned int hash(); - - //WRAPPED void check() const; - void check(); - - bool operator<(SigSpec rhs) { return get_cpp_obj() hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Cell* get_cpp_obj() const - { - Yosys::RTLIL::Cell* ret = Yosys::RTLIL::Cell::get_all_cells()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - - //WRAPPED bool hasPort(RTLIL::IdString portname) const; - bool hasPort(IdString *portname); - - //WRAPPED void unsetPort(RTLIL::IdString portname); - void unsetPort(IdString *portname); - - //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); - void setPort(IdString *portname, SigSpec *signal); - - //WRAPPED bool known() const; - bool known(); - - //WRAPPED bool input(RTLIL::IdString portname) const; - bool input(IdString *portname); - - //WRAPPED bool output(RTLIL::IdString portname) const; - bool output(IdString *portname); - - //WRAPPED bool hasParam(RTLIL::IdString paramname) const; - bool hasParam(IdString *paramname); - - //WRAPPED void unsetParam(RTLIL::IdString paramname); - void unsetParam(IdString *paramname); - - //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); - void setParam(IdString *paramname, Const *value); - - //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); - void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); - - //WRAPPED bool has_keep_attr() const { - bool has_keep_attr(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Cell &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Cell with name " << ref.get_cpp_obj()->name.c_str(); - else - ostr << "deleted Cell"; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Wire - { - unsigned int hashidx_; - Yosys::RTLIL::Wire* ref_obj; - - Wire(Yosys::RTLIL::Wire* ref) - { - this->hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Wire* get_cpp_obj() const - { - Yosys::RTLIL::Wire* ret = Yosys::RTLIL::Wire::get_all_wires()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Wire &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Wire with name " << ref.get_cpp_obj()->name.c_str(); - else - ostr << "deleted Wire"; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Memory - { - unsigned int hashidx_; - Yosys::RTLIL::Memory* ref_obj; - - Memory(Yosys::RTLIL::Memory* ref) - { - this->hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Memory* get_cpp_obj() const - { - Yosys::RTLIL::Memory* ret = Yosys::RTLIL::Memory::get_all_memorys()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Memory &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Memory with name " << ref.get_cpp_obj()->name.c_str(); - else - ostr << "deleted Memory"; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Module - { - unsigned int hashidx_; - Yosys::RTLIL::Module* ref_obj; - - Module(Yosys::RTLIL::Module* ref = new Yosys::RTLIL::Module()) - { - this->hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Module* get_cpp_obj() const - { - Yosys::RTLIL::Module* ret = Yosys::RTLIL::Module::get_all_modules()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - boost::python::list get_cells() - { - Yosys::RTLIL::Module* cpp_obj = get_cpp_obj(); - boost::python::list result; - if(cpp_obj == NULL) - { - return result; - } - for(auto &mod_it : cpp_obj->cells_) - { - result.append(Cell(mod_it.second)); - } - return result; - } - - boost::python::list get_wires() - { - Yosys::RTLIL::Module* cpp_obj = get_cpp_obj(); - boost::python::list result; - if(cpp_obj == NULL) - { - return result; - } - for(auto &mod_it : cpp_obj->wires_) - { - result.append(Wire(mod_it.second)); - } - return result; - } - - void register_monitor(Monitor* const m); - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - - //WRAPPED void connect(const RTLIL::SigSig &conn); - void connect_SigSig(PyObject *conn); - - //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); - void connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs); - - //WRAPPED void new_connections(const std::vector &new_conn); - void new_connections(boost::python::list new_conn); - - //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; - void cloneInto(Module *new_mod); - - //WRAPPED bool has_memories() const; - bool has_memories(); - - //WRAPPED bool has_processes() const; - bool has_processes(); - - //WRAPPED bool has_memories_warn() const; - bool has_memories_warn(); - - //WRAPPED bool has_processes_warn() const; - bool has_processes_warn(); - - //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } - Wire wire(IdString *id); - - //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } - Cell cell(IdString *id); - - //WRAPPED void remove(const pool &wires); - void remove_pool_Wire(boost::python::list wires); - - //WRAPPED void remove(RTLIL::Cell *cell); - void remove_Cell(Cell *cell); - - //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); - void rename_Wire_IdString(Wire *wire, IdString *new_name); - - //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); - void rename_Cell_IdString(Cell *cell, IdString *new_name); - - //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); - void rename_IdString_IdString(IdString *old_name, IdString *new_name); - - //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); - void swap_names_Wire_Wire(Wire *w1, Wire *w2); - - //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); - void swap_names_Cell_Cell(Cell *c1, Cell *c2); - - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); - IdString uniquify_IdString(IdString *name); - - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); - IdString uniquify_IdString_int(IdString *name, int index); - - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); - Wire addWire_IdString_int(IdString *name, int width = 1); - - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); - Wire addWire_IdString_Wire(IdString *name, Wire *other); - - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); - Cell addCell_IdString_IdString(IdString *name, IdString *type); - - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); - Cell addCell_IdString_Cell(IdString *name, Cell *other); - - //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); - Cell addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed = false, bool b_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); - Cell addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); - Cell addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src = ""); - - //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); - Cell addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src = ""); - - //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); - Cell addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src = ""); - - //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); - Cell addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); - Cell addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); - Cell addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); - Cell addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addDffsr(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); - Cell addAdff(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, Const *arst_value, bool clk_polarity = true, bool arst_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); - Cell addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addDlatchsr(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); - Cell addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src = ""); - - //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); - Cell addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); - Cell addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); - Cell addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool en_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addDffsrGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); - Cell addAdffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); - Cell addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::Cell* addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); - Cell addDlatchsrGate(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec Not(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec Pos(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec Neg(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); - SigSpec LogicNot(IdString *name, SigSpec *sig_a, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); - SigSpec LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed = false, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); - SigSpec Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); - SigSpec Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src = ""); - - //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); - SigBit BufGate(IdString *name, SigBit *sig_a, std::string src = ""); - - //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); - SigBit NotGate(IdString *name, SigBit *sig_a, std::string src = ""); - - //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); - SigBit OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src = ""); - - //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); - SigBit MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src = ""); - - //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); - SigBit Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = ""); - - //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); - SigBit Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src = ""); - - //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); - SigBit Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = ""); - - //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); - SigBit Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); - SigSpec Anyconst(IdString *name, int width = 1, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); - SigSpec Anyseq(IdString *name, int width = 1, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); - SigSpec Allconst(IdString *name, int width = 1, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); - SigSpec Allseq(IdString *name, int width = 1, std::string src = ""); - - //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); - SigSpec Initstate(IdString *name, std::string src = ""); - }; - - std::ostream &operator<<(std::ostream &ostr, const Module &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Module with name " << ref.get_cpp_obj()->name.c_str(); - else - ostr << "deleted Module"; - return ostr; - } - //WRAPPED from kernel/rtlil - struct Design - { - unsigned int hashidx_; - Yosys::RTLIL::Design* ref_obj; - - Design(Yosys::RTLIL::Design* ref = new Yosys::RTLIL::Design()) - { - this->hashidx_ = ref->hashidx_; - this->ref_obj = ref; - } - - Yosys::RTLIL::Design* get_cpp_obj() const - { - Yosys::RTLIL::Design* ret = Yosys::RTLIL::Design::get_all_designs()->at(this->hashidx_); - if(ret != NULL && ret == this->ref_obj) - return ret; - return NULL; - } - - boost::python::list get_modules() - { - Yosys::RTLIL::Design* cpp_obj = get_cpp_obj(); - boost::python::list result; - if(cpp_obj == NULL) - { - return result; - } - for(auto &mod_it : cpp_obj->modules_) - { - result.append(Module(mod_it.second)); - } - return result; - } - - void run(std::string command) - { - Yosys::RTLIL::Design* cpp_design = get_cpp_obj(); - if(cpp_design != NULL) - Yosys::run_pass(command, cpp_design); - - } - - void register_monitor(Monitor* const m); - - //WRAPPED unsigned int hash() const { return hashidx_; } - unsigned int hash(); - - //WRAPPED RTLIL::Module *module(RTLIL::IdString name); - Module module(IdString *name); - - //WRAPPED bool has(RTLIL::IdString id) const { - bool has(IdString *id); - - //WRAPPED void add(RTLIL::Module *module); - void add(Module *module); - - //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); - Module addModule(IdString *name); - - //WRAPPED void remove(RTLIL::Module *module); - void remove(Module *module); - - //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); - void rename(Module *module, IdString *new_name); - - //WRAPPED void scratchpad_unset(std::string varname); - void scratchpad_unset(std::string varname); - - //WRAPPED void scratchpad_set_int(std::string varname, int value); - void scratchpad_set_int(std::string varname, int value); - - //WRAPPED void scratchpad_set_bool(std::string varname, bool value); - void scratchpad_set_bool(std::string varname, bool value); - - //WRAPPED void scratchpad_set_string(std::string varname, std::string value); - void scratchpad_set_string(std::string varname, std::string value); - - //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; - int scratchpad_get_int(std::string varname, int default_value = 0); - - //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; - bool scratchpad_get_bool(std::string varname, bool default_value = false); - - //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; - std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()); - - //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; - bool selected_module_IdString(IdString *mod_name); - - //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; - bool selected_whole_module_IdString(IdString *mod_name); - - //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; - bool selected_member(IdString *mod_name, IdString *memb_name); - - //WRAPPED bool selected_module(RTLIL::Module *mod) const; - bool selected_module_Module(Module *mod); - - //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; - bool selected_whole_module_Module(Module *mod); - - //WRAPPED bool full_selection() const { - bool full_selection(); - }; - - std::ostream &operator<<(std::ostream &ostr, const Design &ref) - { - if(ref.get_cpp_obj() != NULL) - ostr << "Design with identifier " << ref.hashidx_; - else - ostr << "deleted Design"; - return ostr; - } - - //WRAPPED static inline std::string escape_id(std::string str) { FROM FILE kernel/rtlil.h - inline std::string escape_id(std::string str) - { - return Yosys::RTLIL::escape_id(str); - } - - //WRAPPED static inline std::string unescape_id(std::string str) { FROM FILE kernel/rtlil.h - inline std::string unescape_id_std_string(std::string str) - { - return Yosys::RTLIL::unescape_id(str); - } - - //WRAPPED static inline std::string unescape_id(RTLIL::IdString str) { FROM FILE kernel/rtlil.h - inline std::string unescape_id_IdString(IdString *str) - { - return Yosys::RTLIL::unescape_id(*str->get_cpp_obj()); - } - - //WRAPPED RTLIL::Const const_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_xor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_xor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_xnor(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_xnor(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_reduce_bool(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_reduce_bool(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_logic_not(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_logic_not(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_logic_and(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_logic_and(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_logic_or(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_logic_or(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_shl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_shl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_shr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_shr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_sshl(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_sshl(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_sshr(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_sshr(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_shift(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_shift(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_shiftx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_shiftx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_lt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_lt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_le(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_le(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_eq(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_eq(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_ne(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_ne(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_eqx(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_eqx(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_nex(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_nex(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_ge(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_ge(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_gt(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_gt(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_add(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_add(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_sub(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_sub(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_mul(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_mul(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_div(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_div(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_mod(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_mod(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_pow(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_pow(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_pos(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_pos(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_pos(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - //WRAPPED RTLIL::Const const_neg(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); FROM FILE kernel/rtlil.h - Const const_neg(Const *arg1, Const *arg2, bool signed1, bool signed2, int result_len) - { - return Const(Yosys::RTLIL::const_neg(*arg1->get_cpp_obj(), *arg2->get_cpp_obj(), signed1, signed2, result_len)); - } - - struct Monitor : public Yosys::RTLIL::Monitor - { - - virtual void notify_module_add(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_add(Module(module)); - } - - virtual void notify_module_del(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_module_del(Module(module)); - } - - virtual void notify_connect(Yosys::RTLIL::Cell *cell, const Yosys::RTLIL::IdString &port, const Yosys::RTLIL::SigSpec &old_sig, Yosys::RTLIL::SigSpec &sig) YS_OVERRIDE - { - Yosys::RTLIL::IdString *tmp_port = new Yosys::RTLIL::IdString(port); - Yosys::RTLIL::SigSpec *tmp_old_sig = new Yosys::RTLIL::SigSpec(old_sig); - py_notify_connect_cell(Cell(cell), IdString(tmp_port), SigSpec(tmp_old_sig), SigSpec(&sig)); - } - - virtual void notify_connect(Yosys::RTLIL::Module *module, const Yosys::RTLIL::SigSig &sigsig) YS_OVERRIDE - { - Yosys::RTLIL::SigSpec *first = new Yosys::RTLIL::SigSpec(sigsig.first); - Yosys::RTLIL::SigSpec *second = new Yosys::RTLIL::SigSpec(sigsig.second); - py_notify_connect_tuple(Module(module), boost::python::make_tuple(SigSpec(first), SigSpec(second))); - } - - virtual void notify_connect(Yosys::RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE - { - boost::python::list sigsig_list; - for(auto sigsig : sigsig_vec) - sigsig_list.append(boost::python::make_tuple(*(new SigSpec(&sigsig.first)), *(new SigSpec(&sigsig.second)))); - py_notify_connect_list(Module(module), sigsig_list); - } - - virtual void notify_blackout(Yosys::RTLIL::Module *module) YS_OVERRIDE - { - py_notify_blackout(Module(module)); - } - - virtual void py_notify_module_add(Module){}; - virtual void py_notify_module_del(Module){}; - virtual void py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig){}; - virtual void py_notify_connect_tuple(Module module, boost::python::tuple sigsig){}; - virtual void py_notify_connect_list(Module module, boost::python::list sigsig_list){}; - virtual void py_notify_blackout(Module){}; - }; - - struct MonitorWrap : Monitor, boost::python::wrapper - { - void py_notify_module_add(Module m) - { - if(boost::python::override py_notify_module_add = this->get_override("py_notify_module_add")) - py_notify_module_add(m); - else - Monitor::py_notify_module_add(m); - } - - void default_py_notify_module_add(Module m) - { - this->Monitor::py_notify_module_add(m); - } - - void py_notify_module_del(Module m) - { - if(boost::python::override py_notify_module_del = this->get_override("py_notify_module_del")) - py_notify_module_del(m); - else - Monitor::py_notify_module_del(m); - } - - void default_py_notify_module_del(Module m) - { - this->Monitor::py_notify_module_del(m); - } - - void py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig) - { - if(boost::python::override py_notify_connect_cell = this->get_override("py_notify_connect_cell")) - py_notify_connect_cell(cell, port, old_sig, sig); - else - Monitor::py_notify_connect_cell(cell, port, old_sig, sig); - } - - void default_py_notify_connect_cell(Cell cell, IdString port, SigSpec old_sig, SigSpec sig) - { - this->Monitor::py_notify_connect_cell(cell, port, old_sig, sig); - } - - void py_notify_connect_tuple(Module module, boost::python::tuple sigsig) - { - if(boost::python::override py_notify_connect_tuple = this->get_override("py_notify_connect_tuple")) - py_notify_connect_tuple(module, sigsig); - else - Monitor::py_notify_connect_tuple(module, sigsig); - } - - void default_py_notify_connect_tuple(Module module, boost::python::tuple sigsig) - { - this->Monitor::py_notify_connect_tuple(module, sigsig); - } - - void py_notify_connect_list(Module module, boost::python::list sigsig_list) - { - if(boost::python::override py_notify_connect_list = this->get_override("py_notify_connect_list")) - py_notify_connect_list(module, sigsig_list); - else - Monitor::py_notify_connect_list(module, sigsig_list); - } - - void default_py_notify_connect_list(Module module, boost::python::list sigsig_list) - { - this->Monitor::py_notify_connect_list(module, sigsig_list); - } - - void py_notify_blackout(Module m) - { - if(boost::python::override py_notify_blackout = this->get_override("py_notify_blackout")) - py_notify_blackout(m); - else - Monitor::py_notify_blackout(m); - } - - void default_py_notify_blackout(Module m) - { - this->Monitor::py_notify_blackout(m); - } - }; - - struct PyPass : public Yosys::Pass - { - PyPass(std::string name, std::string short_help) : Yosys::Pass(name, short_help) { } - - virtual void execute(vector args, Yosys::RTLIL::Design* d) YS_OVERRIDE - { - boost::python::list py_args; - for(auto arg : args) - py_args.append(arg); - py_execute(py_args, new Design(d)); - } - - virtual void help() YS_OVERRIDE - { - py_help(); - } - - virtual void py_execute(boost::python::list args, Design* d){} - virtual void py_help(){} - }; - - struct PassWrap : PyPass, boost::python::wrapper - { - - PassWrap(std::string name, std::string short_help) : PyPass(name, short_help) { } - - void py_execute(boost::python::list args, Design* d) - { - if(boost::python::override py_execute = this->get_override("py_execute")) - py_execute(args, d); - else - PyPass::py_execute(args, d); - } - - void default_py_execute(boost::python::list args, Design* d) - { - this->PyPass::py_execute(args, d); - } - - void py_help() - { - if(boost::python::override py_help = this->get_override("py_help")) - py_help(); - else - PyPass::py_help(); - } - - void default_py_help() - { - this->PyPass::py_help(); - } - }; - - void Module::register_monitor(Monitor* const m) - { - Yosys::RTLIL::Module* cpp_module = this->get_cpp_obj(); - if(cpp_module == NULL) - return; - cpp_module->monitors.insert(m); - } - - void Design::register_monitor(Monitor* const m) - { - Yosys::RTLIL::Design* cpp_design = this->get_cpp_obj(); - if(cpp_design == NULL) - return; - cpp_design->monitors.insert(m); - } - - //WRAPPED static inline int get_reference(int idx) FROM FILE kernel/rtlil.h - inline int IdString::get_reference(int idx) - { - return Yosys::RTLIL::IdString::get_reference(idx); - } - - //WRAPPED static inline void put_reference(int idx) FROM FILE kernel/rtlil.h - inline void IdString::put_reference(int idx) - { - Yosys::RTLIL::IdString::put_reference(idx); - } - - //WRAPPED std::string str() const { FROM FILE kernel/rtlil.h - std::string IdString::str() - { - return this->get_cpp_obj()->str(); - } - - //WRAPPED std::string substr(size_t pos = 0, size_t len = std::string::npos) const { FROM FILE kernel/rtlil.h - std::string IdString::substr(size_t pos, size_t len) - { - return this->get_cpp_obj()->substr(pos, len); - } - - //WRAPPED size_t size() const { FROM FILE kernel/rtlil.h - size_t IdString::size() - { - return this->get_cpp_obj()->size(); - } - - //WRAPPED bool empty() const { FROM FILE kernel/rtlil.h - bool IdString::empty() - { - return this->get_cpp_obj()->empty(); - } - - //WRAPPED void clear() { FROM FILE kernel/rtlil.h - void IdString::clear() - { - this->get_cpp_obj()->clear(); - } - - //WRAPPED unsigned int hash() const { FROM FILE kernel/rtlil.h - unsigned int IdString::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED bool in(IdString rhs) const { return *this == rhs; } FROM FILE kernel/rtlil.h - bool IdString::in_IdString(IdString *rhs) - { - return this->get_cpp_obj()->in(*rhs->get_cpp_obj()); - } - - //WRAPPED bool in(const std::string &rhs) const { return *this == rhs; } FROM FILE kernel/rtlil.h - bool IdString::in_std_string(std::string rhs) - { - return this->get_cpp_obj()->in(rhs); - } - - //WRAPPED bool in(const pool &rhs) const { return rhs.count(*this) != 0; } FROM FILE kernel/rtlil.h - bool IdString::in_pool_IdString(boost::python::list rhs) - { - pool rhs_; - while(len(rhs) > 0) - { - IdString tmp = boost::python::extract(rhs.pop()); - rhs_.insert(*tmp.get_cpp_obj()); - } - return this->get_cpp_obj()->in(rhs_); - } - - //WRAPPED bool as_bool() const; FROM FILE kernel/rtlil.h - bool Const::as_bool() - { - return this->get_cpp_obj()->as_bool(); - } - - //WRAPPED int as_int(bool is_signed = false) const; FROM FILE kernel/rtlil.h - int Const::as_int(bool is_signed) - { - return this->get_cpp_obj()->as_int(is_signed); - } - - //WRAPPED std::string as_string() const; FROM FILE kernel/rtlil.h - std::string Const::as_string() - { - return this->get_cpp_obj()->as_string(); - } - - //WRAPPED static Const from_string(std::string str); FROM FILE kernel/rtlil.h - Const Const::from_string(std::string str) - { - return Const(Yosys::RTLIL::Const::from_string(str)); - } - - //WRAPPED std::string decode_string() const; FROM FILE kernel/rtlil.h - std::string Const::decode_string() - { - return this->get_cpp_obj()->decode_string(); - } - - //WRAPPED inline int size() const { return bits.size(); } FROM FILE kernel/rtlil.h - inline int Const::size() - { - return this->get_cpp_obj()->size(); - } - - //WRAPPED bool is_fully_zero() const; FROM FILE kernel/rtlil.h - bool Const::is_fully_zero() - { - return this->get_cpp_obj()->is_fully_zero(); - } - - //WRAPPED bool is_fully_ones() const; FROM FILE kernel/rtlil.h - bool Const::is_fully_ones() - { - return this->get_cpp_obj()->is_fully_ones(); - } - - //WRAPPED bool is_fully_def() const; FROM FILE kernel/rtlil.h - bool Const::is_fully_def() - { - return this->get_cpp_obj()->is_fully_def(); - } - - //WRAPPED bool is_fully_undef() const; FROM FILE kernel/rtlil.h - bool Const::is_fully_undef() - { - return this->get_cpp_obj()->is_fully_undef(); - } - - //WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { FROM FILE kernel/rtlil.h - inline Const Const::extract(int offset, int len, State padding) - { - return Const(this->get_cpp_obj()->extract(offset, len, padding)); - } - - //WRAPPED inline unsigned int hash() const { FROM FILE kernel/rtlil.h - inline unsigned int Const::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED RTLIL::CaseRule *clone() const; FROM FILE kernel/rtlil.h - CaseRule CaseRule::clone() - { - return CaseRule(this->get_cpp_obj()->clone()); - } - - //WRAPPED RTLIL::SwitchRule *clone() const; FROM FILE kernel/rtlil.h - SwitchRule SwitchRule::clone() - { - return SwitchRule(this->get_cpp_obj()->clone()); - } - - //WRAPPED RTLIL::SyncRule *clone() const; FROM FILE kernel/rtlil.h - SyncRule SyncRule::clone() - { - return SyncRule(this->get_cpp_obj()->clone()); - } - - //WRAPPED RTLIL::Process *clone() const; FROM FILE kernel/rtlil.h - Process Process::clone() - { - return Process(this->get_cpp_obj()->clone()); - } - - //WRAPPED RTLIL::SigChunk extract(int offset, int length) const; FROM FILE kernel/rtlil.h - SigChunk SigChunk::extract(int offset, int length) - { - return SigChunk(this->get_cpp_obj()->extract(offset, length)); - } - - //WRAPPED unsigned int hash() const; FROM FILE kernel/rtlil.h - unsigned int SigBit::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED size_t get_hash() const { FROM FILE kernel/rtlil.h - size_t SigSpec::get_hash() - { - return this->get_cpp_obj()->get_hash(); - } - - //WRAPPED inline int size() const { return width_; } FROM FILE kernel/rtlil.h - inline int SigSpec::size() - { - return this->get_cpp_obj()->size(); - } - - //WRAPPED inline bool empty() const { return width_ == 0; } FROM FILE kernel/rtlil.h - inline bool SigSpec::empty() - { - return this->get_cpp_obj()->empty(); - } - - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with); FROM FILE kernel/rtlil.h - void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with) - { - this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj()); - } - - //WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h - void SigSpec::replace_SigSpec_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with, SigSpec *other) - { - this->get_cpp_obj()->replace(*pattern->get_cpp_obj(), *with->get_cpp_obj(), other->get_cpp_obj()); - } - - //WRAPPED void replace(int offset, const RTLIL::SigSpec &with); FROM FILE kernel/rtlil.h - void SigSpec::replace_int_SigSpec(int offset, SigSpec *with) - { - this->get_cpp_obj()->replace(offset, *with->get_cpp_obj()); - } - - //WRAPPED void remove(const RTLIL::SigSpec &pattern); FROM FILE kernel/rtlil.h - void SigSpec::remove_SigSpec(SigSpec *pattern) - { - this->get_cpp_obj()->remove(*pattern->get_cpp_obj()); - } - - //WRAPPED void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h - void SigSpec::remove_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) - { - this->get_cpp_obj()->remove(*pattern->get_cpp_obj(), other->get_cpp_obj()); - } - - //WRAPPED void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h - void SigSpec::remove2_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) - { - this->get_cpp_obj()->remove2(*pattern->get_cpp_obj(), other->get_cpp_obj()); - } - - //WRAPPED void remove(const pool &pattern); FROM FILE kernel/rtlil.h - void SigSpec::remove_pool_SigBit(boost::python::list pattern) - { - pool pattern_; - while(len(pattern) > 0) - { - SigBit tmp = boost::python::extract(pattern.pop()); - pattern_.insert(*tmp.get_cpp_obj()); - } - this->get_cpp_obj()->remove(pattern_); - } - - //WRAPPED void remove(const pool &pattern, RTLIL::SigSpec *other) const; FROM FILE kernel/rtlil.h - void SigSpec::remove_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) - { - pool pattern_; - while(len(pattern) > 0) - { - SigBit tmp = boost::python::extract(pattern.pop()); - pattern_.insert(*tmp.get_cpp_obj()); - } - this->get_cpp_obj()->remove(pattern_, other->get_cpp_obj()); - } - - //WRAPPED void remove2(const pool &pattern, RTLIL::SigSpec *other); FROM FILE kernel/rtlil.h - void SigSpec::remove2_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) - { - pool pattern_; - while(len(pattern) > 0) - { - SigBit tmp = boost::python::extract(pattern.pop()); - pattern_.insert(*tmp.get_cpp_obj()); - } - this->get_cpp_obj()->remove2(pattern_, other->get_cpp_obj()); - } - - //WRAPPED void remove(int offset, int length = 1); FROM FILE kernel/rtlil.h - void SigSpec::remove_int_int(int offset, int length) - { - this->get_cpp_obj()->remove(offset, length); - } - - //WRAPPED RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::extract_SigSpec_SigSpec(SigSpec *pattern, SigSpec *other) - { - return SigSpec(this->get_cpp_obj()->extract(*pattern->get_cpp_obj(), other->get_cpp_obj())); - } - - //WRAPPED RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::extract_pool_SigBit_SigSpec(boost::python::list pattern, SigSpec *other) - { - pool pattern_; - while(len(pattern) > 0) - { - SigBit tmp = boost::python::extract(pattern.pop()); - pattern_.insert(*tmp.get_cpp_obj()); - } - return SigSpec(this->get_cpp_obj()->extract(pattern_, other->get_cpp_obj())); - } - - //WRAPPED RTLIL::SigSpec extract(int offset, int length = 1) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::extract_int_int(int offset, int length) - { - return SigSpec(this->get_cpp_obj()->extract(offset, length)); - } - - //WRAPPED void append(const RTLIL::SigSpec &signal); FROM FILE kernel/rtlil.h - void SigSpec::append(SigSpec *signal) - { - this->get_cpp_obj()->append(*signal->get_cpp_obj()); - } - - //WRAPPED void append_bit(const RTLIL::SigBit &bit); FROM FILE kernel/rtlil.h - void SigSpec::append_bit(SigBit *bit) - { - this->get_cpp_obj()->append_bit(*bit->get_cpp_obj()); - } - - //WRAPPED void extend_u0(int width, bool is_signed = false); FROM FILE kernel/rtlil.h - void SigSpec::extend_u0(int width, bool is_signed) - { - this->get_cpp_obj()->extend_u0(width, is_signed); - } - - //WRAPPED RTLIL::SigSpec repeat(int num) const; FROM FILE kernel/rtlil.h - SigSpec SigSpec::repeat(int num) - { - return SigSpec(this->get_cpp_obj()->repeat(num)); - } - - //WRAPPED bool is_wire() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_wire() - { - return this->get_cpp_obj()->is_wire(); - } - - //WRAPPED bool is_chunk() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_chunk() - { - return this->get_cpp_obj()->is_chunk(); - } - - //WRAPPED inline bool is_bit() const { return width_ == 1; } FROM FILE kernel/rtlil.h - inline bool SigSpec::is_bit() - { - return this->get_cpp_obj()->is_bit(); - } - - //WRAPPED bool is_fully_const() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_const() - { - return this->get_cpp_obj()->is_fully_const(); - } - - //WRAPPED bool is_fully_zero() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_zero() - { - return this->get_cpp_obj()->is_fully_zero(); - } - - //WRAPPED bool is_fully_ones() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_ones() - { - return this->get_cpp_obj()->is_fully_ones(); - } - - //WRAPPED bool is_fully_def() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_def() - { - return this->get_cpp_obj()->is_fully_def(); - } - - //WRAPPED bool is_fully_undef() const; FROM FILE kernel/rtlil.h - bool SigSpec::is_fully_undef() - { - return this->get_cpp_obj()->is_fully_undef(); - } - - //WRAPPED bool has_const() const; FROM FILE kernel/rtlil.h - bool SigSpec::has_const() - { - return this->get_cpp_obj()->has_const(); - } - - //WRAPPED bool has_marked_bits() const; FROM FILE kernel/rtlil.h - bool SigSpec::has_marked_bits() - { - return this->get_cpp_obj()->has_marked_bits(); - } - - //WRAPPED bool as_bool() const; FROM FILE kernel/rtlil.h - bool SigSpec::as_bool() - { - return this->get_cpp_obj()->as_bool(); - } - - //WRAPPED int as_int(bool is_signed = false) const; FROM FILE kernel/rtlil.h - int SigSpec::as_int(bool is_signed) - { - return this->get_cpp_obj()->as_int(is_signed); - } - - //WRAPPED std::string as_string() const; FROM FILE kernel/rtlil.h - std::string SigSpec::as_string() - { - return this->get_cpp_obj()->as_string(); - } - - //WRAPPED RTLIL::Const as_const() const; FROM FILE kernel/rtlil.h - Const SigSpec::as_const() - { - return Const(this->get_cpp_obj()->as_const()); - } - - //WRAPPED RTLIL::Wire *as_wire() const; FROM FILE kernel/rtlil.h - Wire SigSpec::as_wire() - { - return Wire(this->get_cpp_obj()->as_wire()); - } - - //WRAPPED RTLIL::SigChunk as_chunk() const; FROM FILE kernel/rtlil.h - SigChunk SigSpec::as_chunk() - { - return SigChunk(this->get_cpp_obj()->as_chunk()); - } - - //WRAPPED RTLIL::SigBit as_bit() const; FROM FILE kernel/rtlil.h - SigBit SigSpec::as_bit() - { - return SigBit(this->get_cpp_obj()->as_bit()); - } - - //WRAPPED bool match(std::string pattern) const; FROM FILE kernel/rtlil.h - bool SigSpec::match(std::string pattern) - { - return this->get_cpp_obj()->match(pattern); - } - - //WRAPPED static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h - bool SigSpec::parse(SigSpec *sig, Module *module, std::string str) - { - return Yosys::RTLIL::SigSpec::parse(*sig->get_cpp_obj(), module->get_cpp_obj(), str); - } - - //WRAPPED static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h - bool SigSpec::parse_sel(SigSpec *sig, Design *design, Module *module, std::string str) - { - return Yosys::RTLIL::SigSpec::parse_sel(*sig->get_cpp_obj(), design->get_cpp_obj(), module->get_cpp_obj(), str); - } - - //WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); FROM FILE kernel/rtlil.h - bool SigSpec::parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str) - { - return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str); - } - - //WRAPPED unsigned int hash() const { if(!hash_) updhash(); return hash_; }; FROM FILE kernel/rtlil.h - unsigned int SigSpec::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED void check() const; FROM FILE kernel/rtlil.h - void SigSpec::check() - { - this->get_cpp_obj()->check(); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Cell::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED bool hasPort(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h - bool Cell::hasPort(IdString *portname) - { - return this->get_cpp_obj()->hasPort(*portname->get_cpp_obj()); - } - - //WRAPPED void unsetPort(RTLIL::IdString portname); FROM FILE kernel/rtlil.h - void Cell::unsetPort(IdString *portname) - { - this->get_cpp_obj()->unsetPort(*portname->get_cpp_obj()); - } - - //WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal); FROM FILE kernel/rtlil.h - void Cell::setPort(IdString *portname, SigSpec *signal) - { - this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj()); - } - - //WRAPPED bool known() const; FROM FILE kernel/rtlil.h - bool Cell::known() - { - return this->get_cpp_obj()->known(); - } - - //WRAPPED bool input(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h - bool Cell::input(IdString *portname) - { - return this->get_cpp_obj()->input(*portname->get_cpp_obj()); - } - - //WRAPPED bool output(RTLIL::IdString portname) const; FROM FILE kernel/rtlil.h - bool Cell::output(IdString *portname) - { - return this->get_cpp_obj()->output(*portname->get_cpp_obj()); - } - - //WRAPPED bool hasParam(RTLIL::IdString paramname) const; FROM FILE kernel/rtlil.h - bool Cell::hasParam(IdString *paramname) - { - return this->get_cpp_obj()->hasParam(*paramname->get_cpp_obj()); - } - - //WRAPPED void unsetParam(RTLIL::IdString paramname); FROM FILE kernel/rtlil.h - void Cell::unsetParam(IdString *paramname) - { - this->get_cpp_obj()->unsetParam(*paramname->get_cpp_obj()); - } - - //WRAPPED void setParam(RTLIL::IdString paramname, RTLIL::Const value); FROM FILE kernel/rtlil.h - void Cell::setParam(IdString *paramname, Const *value) - { - this->get_cpp_obj()->setParam(*paramname->get_cpp_obj(), *value->get_cpp_obj()); - } - - //WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); FROM FILE kernel/rtlil.h - void Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) - { - this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed); - } - - //WRAPPED bool has_keep_attr() const { FROM FILE kernel/rtlil.h - bool Cell::has_keep_attr() - { - return this->get_cpp_obj()->has_keep_attr(); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Wire::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Memory::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Module::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED void connect(const RTLIL::SigSig &conn); FROM FILE kernel/rtlil.h - void Module::connect_SigSig(PyObject* conn) - { - if(!PyTuple_Check(conn) or PyTuple_Size(conn) != 2) - throw std::logic_error("Tuple of two SigSpecs required"); - SigSpec conn_sp0 = boost::python::extract(PyTuple_GetItem(conn, 0)); - SigSpec conn_sp1 = boost::python::extract(PyTuple_GetItem(conn, 1)); - Yosys::RTLIL::SigSig conn_(conn_sp0.get_cpp_obj(), conn_sp1.get_cpp_obj()); - this->get_cpp_obj()->connect(conn_); - } - - //WRAPPED void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); FROM FILE kernel/rtlil.h - void Module::connect_SigSpec_SigSpec(SigSpec *lhs, SigSpec *rhs) - { - this->get_cpp_obj()->connect(*lhs->get_cpp_obj(), *rhs->get_cpp_obj()); - } - - //WRAPPED void new_connections(const std::vector &new_conn); FROM FILE kernel/rtlil.h - void Module::new_connections(boost::python::list new_conn) - { - std::vector new_conn_; - while(len(new_conn) > 0) - { - boost::python::tuple tmp1 = boost::python::extract(new_conn.pop()); - SigSpec tmp2 = boost::python::extract(tmp1[0]); - SigSpec tmp3 = boost::python::extract(tmp1[1]); - new_conn_.push_back(Yosys::RTLIL::SigSig(*tmp2.get_cpp_obj(), *tmp3.get_cpp_obj())); - } - this->get_cpp_obj()->new_connections(new_conn_); - } - - //WRAPPED void cloneInto(RTLIL::Module *new_mod) const; FROM FILE kernel/rtlil.h - void Module::cloneInto(Module *new_mod) - { - this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj()); - } - - //WRAPPED bool has_memories() const; FROM FILE kernel/rtlil.h - bool Module::has_memories() - { - return this->get_cpp_obj()->has_memories(); - } - - //WRAPPED bool has_processes() const; FROM FILE kernel/rtlil.h - bool Module::has_processes() - { - return this->get_cpp_obj()->has_processes(); - } - - //WRAPPED bool has_memories_warn() const; FROM FILE kernel/rtlil.h - bool Module::has_memories_warn() - { - return this->get_cpp_obj()->has_memories_warn(); - } - - //WRAPPED bool has_processes_warn() const; FROM FILE kernel/rtlil.h - bool Module::has_processes_warn() - { - return this->get_cpp_obj()->has_processes_warn(); - } - - //WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; } FROM FILE kernel/rtlil.h - Wire Module::wire(IdString *id) - { - return Wire(this->get_cpp_obj()->wire(*id->get_cpp_obj())); - } - - //WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; } FROM FILE kernel/rtlil.h - Cell Module::cell(IdString *id) - { - return Cell(this->get_cpp_obj()->cell(*id->get_cpp_obj())); - } - - //WRAPPED void remove(const pool &wires); FROM FILE kernel/rtlil.h - void Module::remove_pool_Wire(boost::python::list wires) - { - pool wires_; - while(len(wires) > 0) - { - Wire tmp = boost::python::extract(wires.pop()); - wires_.insert(tmp.get_cpp_obj()); - } - this->get_cpp_obj()->remove(wires_); - } - - //WRAPPED void remove(RTLIL::Cell *cell); FROM FILE kernel/rtlil.h - void Module::remove_Cell(Cell *cell) - { - this->get_cpp_obj()->remove(cell->get_cpp_obj()); - } - - //WRAPPED void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h - void Module::rename_Wire_IdString(Wire *wire, IdString *new_name) - { - this->get_cpp_obj()->rename(wire->get_cpp_obj(), *new_name->get_cpp_obj()); - } - - //WRAPPED void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h - void Module::rename_Cell_IdString(Cell *cell, IdString *new_name) - { - this->get_cpp_obj()->rename(cell->get_cpp_obj(), *new_name->get_cpp_obj()); - } - - //WRAPPED void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h - void Module::rename_IdString_IdString(IdString *old_name, IdString *new_name) - { - this->get_cpp_obj()->rename(*old_name->get_cpp_obj(), *new_name->get_cpp_obj()); - } - - //WRAPPED void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2); FROM FILE kernel/rtlil.h - void Module::swap_names_Wire_Wire(Wire *w1, Wire *w2) - { - this->get_cpp_obj()->swap_names(w1->get_cpp_obj(), w2->get_cpp_obj()); - } - - //WRAPPED void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2); FROM FILE kernel/rtlil.h - void Module::swap_names_Cell_Cell(Cell *c1, Cell *c2) - { - this->get_cpp_obj()->swap_names(c1->get_cpp_obj(), c2->get_cpp_obj()); - } - - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name); FROM FILE kernel/rtlil.h - IdString Module::uniquify_IdString(IdString *name) - { - return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj())); - } - - //WRAPPED RTLIL::IdString uniquify(RTLIL::IdString name, int &index); FROM FILE kernel/rtlil.h - IdString Module::uniquify_IdString_int(IdString *name, int index) - { - return IdString(this->get_cpp_obj()->uniquify(*name->get_cpp_obj(), index)); - } - - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); FROM FILE kernel/rtlil.h - Wire Module::addWire_IdString_int(IdString *name, int width) - { - return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), width)); - } - - //WRAPPED RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); FROM FILE kernel/rtlil.h - Wire Module::addWire_IdString_Wire(IdString *name, Wire *other) - { - return Wire(this->get_cpp_obj()->addWire(*name->get_cpp_obj(), other->get_cpp_obj())); - } - - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); FROM FILE kernel/rtlil.h - Cell Module::addCell_IdString_IdString(IdString *name, IdString *type) - { - return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), *type->get_cpp_obj())); - } - - //WRAPPED RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); FROM FILE kernel/rtlil.h - Cell Module::addCell_IdString_Cell(IdString *name, Cell *other) - { - return Cell(this->get_cpp_obj()->addCell(*name->get_cpp_obj(), other->get_cpp_obj())); - } - - //WRAPPED RTLIL::Cell* addNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addPos(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addPos(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addPos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addNeg(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNeg(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addNeg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addXor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceOr(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceXor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceXnor(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addReduceBool(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addShl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addShl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addShl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addShr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addShr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addShr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addSshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addSshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addSshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addSshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addShift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addShift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addShift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addShiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addShiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addShiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addEq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addEq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addEq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addNe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addNe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addEqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addEqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addEqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addNex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addNex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addGe(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addGe(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addGe(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addGt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addGt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addGt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addAdd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAdd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addAdd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addSub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addSub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addMul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addMul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addMul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addDiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addDiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addMod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addMod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addMod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addPow(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool a_signed, bool b_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addPow(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), a_signed, b_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLogicNot(IdString *name, SigSpec *sig_a, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addLogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, bool is_signed, std::string src) - { - return Cell(this->get_cpp_obj()->addLogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::Cell* addMux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addMux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addMux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addPmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addPmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addPmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSlice(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *offset, std::string src) - { - return Cell(this->get_cpp_obj()->addSlice(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *offset->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addConcat(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addConcat(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLut(IdString *name, SigSpec *sig_a, SigSpec *sig_y, Const *lut, std::string src) - { - return Cell(this->get_cpp_obj()->addLut(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), *lut->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addTribuf(IdString *name, SigSpec *sig_a, SigSpec *sig_en, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addTribuf(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAssert(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addAssert(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAssume(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addAssume(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addLive(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addLive(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addFair(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addFair(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addCover(IdString *name, SigSpec *sig_a, SigSpec *sig_en, std::string src) - { - return Cell(this->get_cpp_obj()->addCover(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_en->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addEquiv(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addEquiv(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addSr(IdString *name, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_q, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addSr(*name->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_q->get_cpp_obj(), set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addFf(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) - { - return Cell(this->get_cpp_obj()->addFf(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDff(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffe(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffe(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffsr(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffsr(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAdff(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, Const *arst_value, bool clk_polarity, bool arst_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addAdff(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_arst->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), *arst_value->get_cpp_obj(), clk_polarity, arst_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDlatch(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDlatch(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDlatchsr(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDlatchsr(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addBufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addBufGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addBufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addNotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNotGate(IdString *name, SigBit *sig_a, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addNotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addAndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addNandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addNandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addOrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addOrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addNorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addNorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addNorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addXorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addXorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addXorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addXnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addXnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addXnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addAndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addOrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addOrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addMuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addMuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addMuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addAoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addOai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addOai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addAoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addAoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addOai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addOai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, SigBit *sig_y, std::string src) - { - return Cell(this->get_cpp_obj()->addOai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_y->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addFfGate(IdString *name, SigSpec *sig_d, SigSpec *sig_q, std::string src) - { - return Cell(this->get_cpp_obj()->addFfGate(*name->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::Cell* addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffeGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool en_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffeGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, en_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDffsrGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDffsrGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), clk_polarity, set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addAdffGate(IdString *name, SigSpec *sig_clk, SigSpec *sig_arst, SigSpec *sig_d, SigSpec *sig_q, bool arst_value, bool clk_polarity, bool arst_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addAdffGate(*name->get_cpp_obj(), *sig_clk->get_cpp_obj(), *sig_arst->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), arst_value, clk_polarity, arst_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDlatchGate(IdString *name, SigSpec *sig_en, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDlatchGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, src)); - } - - //WRAPPED RTLIL::Cell* addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = ""); FROM FILE kernel/rtlil.h - Cell Module::addDlatchsrGate(IdString *name, SigSpec *sig_en, SigSpec *sig_set, SigSpec *sig_clr, SigSpec *sig_d, SigSpec *sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, std::string src) - { - return Cell(this->get_cpp_obj()->addDlatchsrGate(*name->get_cpp_obj(), *sig_en->get_cpp_obj(), *sig_set->get_cpp_obj(), *sig_clr->get_cpp_obj(), *sig_d->get_cpp_obj(), *sig_q->get_cpp_obj(), en_polarity, set_polarity, clr_polarity, src)); - } - - //WRAPPED RTLIL::SigSpec Not(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Not(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Not(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Pos(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Pos(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Pos(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Neg(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Neg(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Neg(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec And(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::And(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->And(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Or(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Or(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Or(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Xor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Xor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Xor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Xnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Xnor(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Xnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceAnd(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceOr(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceXor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceXor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceXor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceXnor(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceXnor(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceXnor(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec ReduceBool(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::ReduceBool(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->ReduceBool(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Shl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Shl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Shl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Shr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Shr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Shr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Sshl(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Sshl(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Sshl(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Sshr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Sshr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Sshr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Shift(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Shift(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Shift(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Shiftx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Shiftx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Shiftx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Lt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Lt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Lt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Le(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Le(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Le(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Eq(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Eq(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Eq(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Ne(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Ne(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Ne(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Eqx(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Eqx(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Eqx(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Nex(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Nex(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Nex(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Ge(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Ge(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Ge(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Gt(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Gt(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Gt(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Add(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Add(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Add(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Sub(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Sub(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Sub(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Mul(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Mul(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Mul(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Div(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Div(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Div(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Mod(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Mod(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->Mod(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec LogicNot(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::LogicNot(IdString *name, SigSpec *sig_a, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->LogicNot(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec LogicAnd(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::LogicAnd(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->LogicAnd(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec LogicOr(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed = false, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::LogicOr(IdString *name, SigSpec *sig_a, SigSpec *sig_b, bool is_signed, std::string src) - { - return SigSpec(this->get_cpp_obj()->LogicOr(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), is_signed, src)); - } - - //WRAPPED RTLIL::SigSpec Mux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Mux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) - { - return SigSpec(this->get_cpp_obj()->Mux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigSpec Pmux(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Pmux(IdString *name, SigSpec *sig_a, SigSpec *sig_b, SigSpec *sig_s, std::string src) - { - return SigSpec(this->get_cpp_obj()->Pmux(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit BufGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::BufGate(IdString *name, SigBit *sig_a, std::string src) - { - return SigBit(this->get_cpp_obj()->BufGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit NotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::NotGate(IdString *name, SigBit *sig_a, std::string src) - { - return SigBit(this->get_cpp_obj()->NotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit AndGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::AndGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->AndGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit NandGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::NandGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->NandGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit OrGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::OrGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->OrGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit NorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::NorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->NorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit XorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::XorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->XorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit XnorGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::XnorGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->XnorGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit AndnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::AndnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->AndnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit OrnotGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::OrnotGate(IdString *name, SigBit *sig_a, SigBit *sig_b, std::string src) - { - return SigBit(this->get_cpp_obj()->OrnotGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit MuxGate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::MuxGate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_s, std::string src) - { - return SigBit(this->get_cpp_obj()->MuxGate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_s->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit Aoi3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::Aoi3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) - { - return SigBit(this->get_cpp_obj()->Aoi3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit Oai3Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::Oai3Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, std::string src) - { - return SigBit(this->get_cpp_obj()->Oai3Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit Aoi4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::Aoi4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) - { - return SigBit(this->get_cpp_obj()->Aoi4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigBit Oai4Gate(RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigBit Module::Oai4Gate(IdString *name, SigBit *sig_a, SigBit *sig_b, SigBit *sig_c, SigBit *sig_d, std::string src) - { - return SigBit(this->get_cpp_obj()->Oai4Gate(*name->get_cpp_obj(), *sig_a->get_cpp_obj(), *sig_b->get_cpp_obj(), *sig_c->get_cpp_obj(), *sig_d->get_cpp_obj(), src)); - } - - //WRAPPED RTLIL::SigSpec Anyconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Anyconst(IdString *name, int width, std::string src) - { - return SigSpec(this->get_cpp_obj()->Anyconst(*name->get_cpp_obj(), width, src)); - } - - //WRAPPED RTLIL::SigSpec Anyseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Anyseq(IdString *name, int width, std::string src) - { - return SigSpec(this->get_cpp_obj()->Anyseq(*name->get_cpp_obj(), width, src)); - } - - //WRAPPED RTLIL::SigSpec Allconst(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Allconst(IdString *name, int width, std::string src) - { - return SigSpec(this->get_cpp_obj()->Allconst(*name->get_cpp_obj(), width, src)); - } - - //WRAPPED RTLIL::SigSpec Allseq(RTLIL::IdString name, int width = 1, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Allseq(IdString *name, int width, std::string src) - { - return SigSpec(this->get_cpp_obj()->Allseq(*name->get_cpp_obj(), width, src)); - } - - //WRAPPED RTLIL::SigSpec Initstate(RTLIL::IdString name, const std::string &src = ""); FROM FILE kernel/rtlil.h - SigSpec Module::Initstate(IdString *name, std::string src) - { - return SigSpec(this->get_cpp_obj()->Initstate(*name->get_cpp_obj(), src)); - } - - //WRAPPED unsigned int hash() const { return hashidx_; } FROM FILE kernel/rtlil.h - unsigned int Design::hash() - { - return this->get_cpp_obj()->hash(); - } - - //WRAPPED RTLIL::Module *module(RTLIL::IdString name); FROM FILE kernel/rtlil.h - Module Design::module(IdString *name) - { - return Module(this->get_cpp_obj()->module(*name->get_cpp_obj())); - } - - //WRAPPED bool has(RTLIL::IdString id) const { FROM FILE kernel/rtlil.h - bool Design::has(IdString *id) - { - return this->get_cpp_obj()->has(*id->get_cpp_obj()); - } - - //WRAPPED void add(RTLIL::Module *module); FROM FILE kernel/rtlil.h - void Design::add(Module *module) - { - this->get_cpp_obj()->add(module->get_cpp_obj()); - } - - //WRAPPED RTLIL::Module *addModule(RTLIL::IdString name); FROM FILE kernel/rtlil.h - Module Design::addModule(IdString *name) - { - return Module(this->get_cpp_obj()->addModule(*name->get_cpp_obj())); - } - - //WRAPPED void remove(RTLIL::Module *module); FROM FILE kernel/rtlil.h - void Design::remove(Module *module) - { - this->get_cpp_obj()->remove(module->get_cpp_obj()); - } - - //WRAPPED void rename(RTLIL::Module *module, RTLIL::IdString new_name); FROM FILE kernel/rtlil.h - void Design::rename(Module *module, IdString *new_name) - { - this->get_cpp_obj()->rename(module->get_cpp_obj(), *new_name->get_cpp_obj()); - } - - //WRAPPED void scratchpad_unset(std::string varname); FROM FILE kernel/rtlil.h - void Design::scratchpad_unset(std::string varname) - { - this->get_cpp_obj()->scratchpad_unset(varname); - } - - //WRAPPED void scratchpad_set_int(std::string varname, int value); FROM FILE kernel/rtlil.h - void Design::scratchpad_set_int(std::string varname, int value) - { - this->get_cpp_obj()->scratchpad_set_int(varname, value); - } - - //WRAPPED void scratchpad_set_bool(std::string varname, bool value); FROM FILE kernel/rtlil.h - void Design::scratchpad_set_bool(std::string varname, bool value) - { - this->get_cpp_obj()->scratchpad_set_bool(varname, value); - } - - //WRAPPED void scratchpad_set_string(std::string varname, std::string value); FROM FILE kernel/rtlil.h - void Design::scratchpad_set_string(std::string varname, std::string value) - { - this->get_cpp_obj()->scratchpad_set_string(varname, value); - } - - //WRAPPED int scratchpad_get_int(std::string varname, int default_value = 0) const; FROM FILE kernel/rtlil.h - int Design::scratchpad_get_int(std::string varname, int default_value) - { - return this->get_cpp_obj()->scratchpad_get_int(varname, default_value); - } - - //WRAPPED bool scratchpad_get_bool(std::string varname, bool default_value = false) const; FROM FILE kernel/rtlil.h - bool Design::scratchpad_get_bool(std::string varname, bool default_value) - { - return this->get_cpp_obj()->scratchpad_get_bool(varname, default_value); - } - - //WRAPPED std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const; FROM FILE kernel/rtlil.h - std::string Design::scratchpad_get_string(std::string varname, std::string default_value) - { - return this->get_cpp_obj()->scratchpad_get_string(varname, default_value); - } - - //WRAPPED bool selected_module(RTLIL::IdString mod_name) const; FROM FILE kernel/rtlil.h - bool Design::selected_module_IdString(IdString *mod_name) - { - return this->get_cpp_obj()->selected_module(*mod_name->get_cpp_obj()); - } - - //WRAPPED bool selected_whole_module(RTLIL::IdString mod_name) const; FROM FILE kernel/rtlil.h - bool Design::selected_whole_module_IdString(IdString *mod_name) - { - return this->get_cpp_obj()->selected_whole_module(*mod_name->get_cpp_obj()); - } - - //WRAPPED bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; FROM FILE kernel/rtlil.h - bool Design::selected_member(IdString *mod_name, IdString *memb_name) - { - return this->get_cpp_obj()->selected_member(*mod_name->get_cpp_obj(), *memb_name->get_cpp_obj()); - } - - //WRAPPED bool selected_module(RTLIL::Module *mod) const; FROM FILE kernel/rtlil.h - bool Design::selected_module_Module(Module *mod) - { - return this->get_cpp_obj()->selected_module(mod->get_cpp_obj()); - } - - //WRAPPED bool selected_whole_module(RTLIL::Module *mod) const; FROM FILE kernel/rtlil.h - bool Design::selected_whole_module_Module(Module *mod) - { - return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj()); - } - - //WRAPPED bool full_selection() const { FROM FILE kernel/rtlil.h - bool Design::full_selection() - { - return this->get_cpp_obj()->full_selection(); - } - - struct Initializer - { - Initializer() { - if(!Yosys::yosys_already_setup()) - { - Yosys::log_streams.push_back(&std::cout); - Yosys::log_error_stderr = true; - Yosys::yosys_setup(); - Yosys::yosys_banner(); - } - } - - Initializer(Initializer const &) {} - - ~Initializer() { - Yosys::yosys_shutdown(); - } - }; - - BOOST_PYTHON_MODULE(libyosys) - { - using namespace boost::python; - - enum_("State") - .value("S0",Yosys::RTLIL::S0) - .value("S1",Yosys::RTLIL::S1) - .value("Sx",Yosys::RTLIL::Sx) - .value("Sz",Yosys::RTLIL::Sz) - .value("Sa",Yosys::RTLIL::Sa) - .value("Sm",Yosys::RTLIL::Sm) - ; - - enum_("SyncType") - .value("ST0",Yosys::RTLIL::ST0) - .value("ST1",Yosys::RTLIL::ST1) - .value("STp",Yosys::RTLIL::STp) - .value("STn",Yosys::RTLIL::STn) - .value("STe",Yosys::RTLIL::STe) - .value("STa",Yosys::RTLIL::STa) - .value("STg",Yosys::RTLIL::STg) - .value("STi",Yosys::RTLIL::STi) - ; - - enum_("ConstFlags") - .value("CONST_FLAG_NONE",Yosys::RTLIL::CONST_FLAG_NONE) - .value("CONST_FLAG_STRING",Yosys::RTLIL::CONST_FLAG_STRING) - .value("CONST_FLAG_SIGNED",Yosys::RTLIL::CONST_FLAG_SIGNED) - .value("CONST_FLAG_REAL",Yosys::RTLIL::CONST_FLAG_REAL) - ; - - class_("Monitor") - .def("py_notify_module_add", &Monitor::py_notify_module_add, &MonitorWrap::default_py_notify_module_add) - .def("py_notify_module_del", &Monitor::py_notify_module_del, &MonitorWrap::default_py_notify_module_del) - .def("py_notify_connect_cell", &Monitor::py_notify_connect_cell, &MonitorWrap::default_py_notify_connect_cell) - .def("py_notify_connect_tuple", &Monitor::py_notify_connect_tuple, &MonitorWrap::default_py_notify_connect_tuple) - .def("py_notify_connect_list", &Monitor::py_notify_connect_list, &MonitorWrap::default_py_notify_connect_list) - .def("py_notify_blackout", &Monitor::py_notify_blackout, &MonitorWrap::default_py_notify_blackout) - ; - - class_("Pass", init()) - .def("py_execute", &PyPass::py_execute, &PassWrap::default_py_execute) - .def("py_help", &PyPass::py_help, &PassWrap::default_py_help) - ; - - class_("Initializer"); - scope().attr("_hidden") = new Initializer(); - - class_("IdString") - .def(init()) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_reference", &IdString::get_reference) - .def("put_reference", &IdString::put_reference) - .def("str", &IdString::str) - .def("substr", &IdString::substr) - .def("size", &IdString::size) - .def("empty", &IdString::empty) - .def("clear", &IdString::clear) - .def("hash", &IdString::hash) - .def("in_IdString", &IdString::in_IdString) - .def("in_std_string", &IdString::in_std_string) - .def("in_pool_IdString", &IdString::in_pool_IdString) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("Const") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("as_bool", &Const::as_bool) - .def("as_int", &Const::as_int) - .def("as_string", &Const::as_string) - .def("from_string", &Const::from_string) - .def("decode_string", &Const::decode_string) - .def("size", &Const::size) - .def("is_fully_zero", &Const::is_fully_zero) - .def("is_fully_ones", &Const::is_fully_ones) - .def("is_fully_def", &Const::is_fully_def) - .def("is_fully_undef", &Const::is_fully_undef) - .def("extract", &Const::extract) - .def("hash", &Const::hash) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("CaseRule") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("clone", &CaseRule::clone) - ; - - class_("SwitchRule") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("clone", &SwitchRule::clone) - ; - - class_("SyncRule") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("clone", &SyncRule::clone) - ; - - class_("Process") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("clone", &Process::clone) - ; - - class_("SigChunk") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("extract", &SigChunk::extract) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("SigBit") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("hash", &SigBit::hash) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("SigSpec") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_hash", &SigSpec::get_hash) - .def("size", &SigSpec::size) - .def("empty", &SigSpec::empty) - .def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec) - .def("replace_SigSpec_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec_SigSpec) - .def("replace_int_SigSpec", &SigSpec::replace_int_SigSpec) - .def("remove_SigSpec", &SigSpec::remove_SigSpec) - .def("remove_SigSpec_SigSpec", &SigSpec::remove_SigSpec_SigSpec) - .def("remove2_SigSpec_SigSpec", &SigSpec::remove2_SigSpec_SigSpec) - .def("remove_pool_SigBit", &SigSpec::remove_pool_SigBit) - .def("remove_pool_SigBit_SigSpec", &SigSpec::remove_pool_SigBit_SigSpec) - .def("remove2_pool_SigBit_SigSpec", &SigSpec::remove2_pool_SigBit_SigSpec) - .def("remove_int_int", &SigSpec::remove_int_int) - .def("extract_SigSpec_SigSpec", &SigSpec::extract_SigSpec_SigSpec) - .def("extract_pool_SigBit_SigSpec", &SigSpec::extract_pool_SigBit_SigSpec) - .def("extract_int_int", &SigSpec::extract_int_int) - .def("append", &SigSpec::append) - .def("append_bit", &SigSpec::append_bit) - .def("extend_u0", &SigSpec::extend_u0) - .def("repeat", &SigSpec::repeat) - .def("is_wire", &SigSpec::is_wire) - .def("is_chunk", &SigSpec::is_chunk) - .def("is_bit", &SigSpec::is_bit) - .def("is_fully_const", &SigSpec::is_fully_const) - .def("is_fully_zero", &SigSpec::is_fully_zero) - .def("is_fully_ones", &SigSpec::is_fully_ones) - .def("is_fully_def", &SigSpec::is_fully_def) - .def("is_fully_undef", &SigSpec::is_fully_undef) - .def("has_const", &SigSpec::has_const) - .def("has_marked_bits", &SigSpec::has_marked_bits) - .def("as_bool", &SigSpec::as_bool) - .def("as_int", &SigSpec::as_int) - .def("as_string", &SigSpec::as_string) - .def("as_const", &SigSpec::as_const) - .def("as_wire", &SigSpec::as_wire) - .def("as_chunk", &SigSpec::as_chunk) - .def("as_bit", &SigSpec::as_bit) - .def("match", &SigSpec::match) - .def("parse", &SigSpec::parse) - .def("parse_sel", &SigSpec::parse_sel) - .def("parse_rhs", &SigSpec::parse_rhs) - .def("hash", &SigSpec::hash) - .def("check", &SigSpec::check) - .def(self < self) - .def(self == self) - .def(self != self) - ; - - class_("Cell", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("hash", &Cell::hash) - .def("hasPort", &Cell::hasPort) - .def("unsetPort", &Cell::unsetPort) - .def("setPort", &Cell::setPort) - .def("known", &Cell::known) - .def("input", &Cell::input) - .def("output", &Cell::output) - .def("hasParam", &Cell::hasParam) - .def("unsetParam", &Cell::unsetParam) - .def("setParam", &Cell::setParam) - .def("fixup_parameters", &Cell::fixup_parameters) - .def("has_keep_attr", &Cell::has_keep_attr) - ; - - class_("Wire", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("hash", &Wire::hash) - ; - - class_("Memory", no_init) - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("hash", &Memory::hash) - ; - - class_("Module") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_cells", &Module::get_cells) - .def("get_wires", &Module::get_wires) - .def("register_monitor", &Module::register_monitor) - .def("hash", &Module::hash) - .def("connect_SigSig", &Module::connect_SigSig) - .def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec) - .def("new_connections", &Module::new_connections) - .def("cloneInto", &Module::cloneInto) - .def("has_memories", &Module::has_memories) - .def("has_processes", &Module::has_processes) - .def("has_memories_warn", &Module::has_memories_warn) - .def("has_processes_warn", &Module::has_processes_warn) - .def("wire", &Module::wire) - .def("cell", &Module::cell) - .def("remove_pool_Wire", &Module::remove_pool_Wire) - .def("remove_Cell", &Module::remove_Cell) - .def("rename_Wire_IdString", &Module::rename_Wire_IdString) - .def("rename_Cell_IdString", &Module::rename_Cell_IdString) - .def("rename_IdString_IdString", &Module::rename_IdString_IdString) - .def("swap_names_Wire_Wire", &Module::swap_names_Wire_Wire) - .def("swap_names_Cell_Cell", &Module::swap_names_Cell_Cell) - .def("uniquify_IdString", &Module::uniquify_IdString) - .def("uniquify_IdString_int", &Module::uniquify_IdString_int) - .def("addWire_IdString_int", &Module::addWire_IdString_int) - .def("addWire_IdString_Wire", &Module::addWire_IdString_Wire) - .def("addCell_IdString_IdString", &Module::addCell_IdString_IdString) - .def("addCell_IdString_Cell", &Module::addCell_IdString_Cell) - .def("addNot", &Module::addNot) - .def("addPos", &Module::addPos) - .def("addNeg", &Module::addNeg) - .def("addAnd", &Module::addAnd) - .def("addOr", &Module::addOr) - .def("addXor", &Module::addXor) - .def("addXnor", &Module::addXnor) - .def("addReduceAnd", &Module::addReduceAnd) - .def("addReduceOr", &Module::addReduceOr) - .def("addReduceXor", &Module::addReduceXor) - .def("addReduceXnor", &Module::addReduceXnor) - .def("addReduceBool", &Module::addReduceBool) - .def("addShl", &Module::addShl) - .def("addShr", &Module::addShr) - .def("addSshl", &Module::addSshl) - .def("addSshr", &Module::addSshr) - .def("addShift", &Module::addShift) - .def("addShiftx", &Module::addShiftx) - .def("addLt", &Module::addLt) - .def("addLe", &Module::addLe) - .def("addEq", &Module::addEq) - .def("addNe", &Module::addNe) - .def("addEqx", &Module::addEqx) - .def("addNex", &Module::addNex) - .def("addGe", &Module::addGe) - .def("addGt", &Module::addGt) - .def("addAdd", &Module::addAdd) - .def("addSub", &Module::addSub) - .def("addMul", &Module::addMul) - .def("addDiv", &Module::addDiv) - .def("addMod", &Module::addMod) - .def("addPow", &Module::addPow) - .def("addLogicNot", &Module::addLogicNot) - .def("addLogicAnd", &Module::addLogicAnd) - .def("addLogicOr", &Module::addLogicOr) - .def("addMux", &Module::addMux) - .def("addPmux", &Module::addPmux) - .def("addSlice", &Module::addSlice) - .def("addConcat", &Module::addConcat) - .def("addLut", &Module::addLut) - .def("addTribuf", &Module::addTribuf) - .def("addAssert", &Module::addAssert) - .def("addAssume", &Module::addAssume) - .def("addLive", &Module::addLive) - .def("addFair", &Module::addFair) - .def("addCover", &Module::addCover) - .def("addEquiv", &Module::addEquiv) - .def("addSr", &Module::addSr) - .def("addFf", &Module::addFf) - .def("addDff", &Module::addDff) - .def("addDffe", &Module::addDffe) - .def("addDffsr", &Module::addDffsr) - .def("addAdff", &Module::addAdff) - .def("addDlatch", &Module::addDlatch) - .def("addDlatchsr", &Module::addDlatchsr) - .def("addBufGate", &Module::addBufGate) - .def("addNotGate", &Module::addNotGate) - .def("addAndGate", &Module::addAndGate) - .def("addNandGate", &Module::addNandGate) - .def("addOrGate", &Module::addOrGate) - .def("addNorGate", &Module::addNorGate) - .def("addXorGate", &Module::addXorGate) - .def("addXnorGate", &Module::addXnorGate) - .def("addAndnotGate", &Module::addAndnotGate) - .def("addOrnotGate", &Module::addOrnotGate) - .def("addMuxGate", &Module::addMuxGate) - .def("addAoi3Gate", &Module::addAoi3Gate) - .def("addOai3Gate", &Module::addOai3Gate) - .def("addAoi4Gate", &Module::addAoi4Gate) - .def("addOai4Gate", &Module::addOai4Gate) - .def("addFfGate", &Module::addFfGate) - .def("addDffGate", &Module::addDffGate) - .def("addDffeGate", &Module::addDffeGate) - .def("addDffsrGate", &Module::addDffsrGate) - .def("addAdffGate", &Module::addAdffGate) - .def("addDlatchGate", &Module::addDlatchGate) - .def("addDlatchsrGate", &Module::addDlatchsrGate) - .def("Not", &Module::Not) - .def("Pos", &Module::Pos) - .def("Neg", &Module::Neg) - .def("And", &Module::And) - .def("Or", &Module::Or) - .def("Xor", &Module::Xor) - .def("Xnor", &Module::Xnor) - .def("ReduceAnd", &Module::ReduceAnd) - .def("ReduceOr", &Module::ReduceOr) - .def("ReduceXor", &Module::ReduceXor) - .def("ReduceXnor", &Module::ReduceXnor) - .def("ReduceBool", &Module::ReduceBool) - .def("Shl", &Module::Shl) - .def("Shr", &Module::Shr) - .def("Sshl", &Module::Sshl) - .def("Sshr", &Module::Sshr) - .def("Shift", &Module::Shift) - .def("Shiftx", &Module::Shiftx) - .def("Lt", &Module::Lt) - .def("Le", &Module::Le) - .def("Eq", &Module::Eq) - .def("Ne", &Module::Ne) - .def("Eqx", &Module::Eqx) - .def("Nex", &Module::Nex) - .def("Ge", &Module::Ge) - .def("Gt", &Module::Gt) - .def("Add", &Module::Add) - .def("Sub", &Module::Sub) - .def("Mul", &Module::Mul) - .def("Div", &Module::Div) - .def("Mod", &Module::Mod) - .def("LogicNot", &Module::LogicNot) - .def("LogicAnd", &Module::LogicAnd) - .def("LogicOr", &Module::LogicOr) - .def("Mux", &Module::Mux) - .def("Pmux", &Module::Pmux) - .def("BufGate", &Module::BufGate) - .def("NotGate", &Module::NotGate) - .def("AndGate", &Module::AndGate) - .def("NandGate", &Module::NandGate) - .def("OrGate", &Module::OrGate) - .def("NorGate", &Module::NorGate) - .def("XorGate", &Module::XorGate) - .def("XnorGate", &Module::XnorGate) - .def("AndnotGate", &Module::AndnotGate) - .def("OrnotGate", &Module::OrnotGate) - .def("MuxGate", &Module::MuxGate) - .def("Aoi3Gate", &Module::Aoi3Gate) - .def("Oai3Gate", &Module::Oai3Gate) - .def("Aoi4Gate", &Module::Aoi4Gate) - .def("Oai4Gate", &Module::Oai4Gate) - .def("Anyconst", &Module::Anyconst) - .def("Anyseq", &Module::Anyseq) - .def("Allconst", &Module::Allconst) - .def("Allseq", &Module::Allseq) - .def("Initstate", &Module::Initstate) - ; - - class_("Design") - .def(boost::python::self_ns::str(boost::python::self_ns::self)) - .def(boost::python::self_ns::repr(boost::python::self_ns::self)) - .def("get_modules", &Design::get_modules) - .def("run", &Design::run) - .def("register_monitor", &Design::register_monitor) - .def("hash", &Design::hash) - .def("module", &Design::module) - .def("has", &Design::has) - .def("add", &Design::add) - .def("addModule", &Design::addModule) - .def("remove", &Design::remove) - .def("rename", &Design::rename) - .def("scratchpad_unset", &Design::scratchpad_unset) - .def("scratchpad_set_int", &Design::scratchpad_set_int) - .def("scratchpad_set_bool", &Design::scratchpad_set_bool) - .def("scratchpad_set_string", &Design::scratchpad_set_string) - .def("scratchpad_get_int", &Design::scratchpad_get_int) - .def("scratchpad_get_bool", &Design::scratchpad_get_bool) - .def("scratchpad_get_string", &Design::scratchpad_get_string) - .def("selected_module_IdString", &Design::selected_module_IdString) - .def("selected_whole_module_IdString", &Design::selected_whole_module_IdString) - .def("selected_member", &Design::selected_member) - .def("selected_module_Module", &Design::selected_module_Module) - .def("selected_whole_module_Module", &Design::selected_whole_module_Module) - .def("full_selection", &Design::full_selection) - ; - - def("escape_id", escape_id); - def("unescape_id_std_string", unescape_id_std_string); - def("unescape_id_IdString", unescape_id_IdString); - def("const_not", const_not); - def("const_and", const_and); - def("const_or", const_or); - def("const_xor", const_xor); - def("const_xnor", const_xnor); - def("const_reduce_and", const_reduce_and); - def("const_reduce_or", const_reduce_or); - def("const_reduce_xor", const_reduce_xor); - def("const_reduce_xnor", const_reduce_xnor); - def("const_reduce_bool", const_reduce_bool); - def("const_logic_not", const_logic_not); - def("const_logic_and", const_logic_and); - def("const_logic_or", const_logic_or); - def("const_shl", const_shl); - def("const_shr", const_shr); - def("const_sshl", const_sshl); - def("const_sshr", const_sshr); - def("const_shift", const_shift); - def("const_shiftx", const_shiftx); - def("const_lt", const_lt); - def("const_le", const_le); - def("const_eq", const_eq); - def("const_ne", const_ne); - def("const_eqx", const_eqx); - def("const_nex", const_nex); - def("const_ge", const_ge); - def("const_gt", const_gt); - def("const_add", const_add); - def("const_sub", const_sub); - def("const_mul", const_mul); - def("const_div", const_div); - def("const_mod", const_mod); - def("const_pow", const_pow); - def("const_pos", const_pos); - def("const_neg", const_neg); - def("run",run); - def("log",log); - - } - -} -#endif -- cgit v1.2.3 From 1355492c8966596f3694b781d6cdf12b17681bc1 Mon Sep 17 00:00:00 2001 From: Adrian Wheeldon Date: Thu, 4 Oct 2018 15:36:26 +0100 Subject: Fix IdString M in setup_stdcells() --- kernel/celltypes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index fcc4fcc4b..6041168bb 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -157,7 +157,7 @@ struct CellTypes IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D"; IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H"; IdString I = "\\I", J = "\\J", K = "\\K", L = "\\L"; - IdString M = "\\I", N = "\\N", O = "\\O", P = "\\P"; + IdString M = "\\M", N = "\\N", O = "\\O", P = "\\P"; IdString S = "\\S", T = "\\T", U = "\\U", V = "\\V"; IdString Y = "\\Y"; -- cgit v1.2.3 From 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Thu, 11 Oct 2018 23:33:31 +0200 Subject: Synthesis support for SystemVerilog interfaces This time doing the changes mostly in AST before RTLIL generation --- kernel/rtlil.cc | 15 +++++++++++++++ kernel/rtlil.h | 2 ++ 2 files changed, 17 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a4fa2cf04..fadac0872 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -639,6 +639,13 @@ RTLIL::Module::~Module() delete it->second; } +void RTLIL::Module::reprocess_module(RTLIL::Design *design, dict local_interfaces) +{ + log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name)); + (void)local_interfaces; // To remove build warning + (void)design; // To remove build warning +} + RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, bool mayfail) { if (mayfail) @@ -646,6 +653,14 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, dict , bool mayfail) +{ + if (mayfail) + return RTLIL::IdString(); + log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); +} + size_t RTLIL::Module::count_id(RTLIL::IdString id) { return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 027faf416..8a2b0a4f3 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -907,7 +907,9 @@ public: Module(); virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail = false); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, dict interfaces, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); + virtual void reprocess_module(RTLIL::Design *design, dict local_interfaces); virtual void sort(); virtual void check(); -- cgit v1.2.3 From 458a94059e6738d93a87ddb9af282d0e1d28791d Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Fri, 12 Oct 2018 20:58:37 +0200 Subject: Support for 'modports' for System Verilog interfaces --- kernel/rtlil.cc | 2 +- kernel/rtlil.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index fadac0872..07dd4bfa0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -654,7 +654,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, dict , bool mayfail) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, dict, dict, bool mayfail) { if (mayfail) return RTLIL::IdString(); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8a2b0a4f3..276540aa1 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -907,7 +907,7 @@ public: Module(); virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail = false); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, dict interfaces, bool mayfail = false); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, dict interfaces, dict modports, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); virtual void reprocess_module(RTLIL::Design *design, dict local_interfaces); -- cgit v1.2.3 From c50afc4246d552db079aec303b0d79ae92107a67 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Sat, 13 Oct 2018 20:34:44 +0200 Subject: Documentation improvements etc. - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) --- kernel/rtlil.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 07dd4bfa0..14259f8ed 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -639,11 +639,9 @@ RTLIL::Module::~Module() delete it->second; } -void RTLIL::Module::reprocess_module(RTLIL::Design *design, dict local_interfaces) +void RTLIL::Module::reprocess_module(RTLIL::Design *, dict) { log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name)); - (void)local_interfaces; // To remove build warning - (void)design; // To remove build warning } RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, bool mayfail) -- cgit v1.2.3 From 9ed77f5ba853a316cf88221fa142e188f84765f0 Mon Sep 17 00:00:00 2001 From: whentze Date: Mon, 22 Oct 2018 19:40:22 +0200 Subject: fix unhandled std::out_of_range when calling yosys with 3-character argument --- kernel/yosys.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index ad032899c..21eeadaaf 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -821,7 +821,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen command = "verilog"; else if (filename.size() > 2 && filename.substr(filename.size()-3) == ".sv") command = "verilog -sv"; - else if (filename.size() > 2 && filename.substr(filename.size()-4) == ".vhd") + else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".vhd") command = "vhdl"; else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif") command = "blif"; @@ -833,7 +833,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen command = "ilang"; else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".ys") command = "script"; - else if (filename.size() > 2 && filename.substr(filename.size()-4) == ".tcl") + else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".tcl") command = "tcl"; else if (filename == "-") command = "script"; -- cgit v1.2.3 From 6732e566321b828c83b563d24a10ac31c6d03e28 Mon Sep 17 00:00:00 2001 From: Jon Burgess Date: Sun, 28 Oct 2018 14:49:09 +0000 Subject: Avoid assert when label is an empty string Calling back() on an empty string is not allowed and triggers an assert with recent gcc: $ cd manual/PRESENTATION_Intro $ ../../yosys counter.ys ... /usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits; _Alloc = std::allocator; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed. 802 if (label.back() == ':' && GetSize(label) > 1) (gdb) p label $1 = "" --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 21eeadaaf..f002955ad 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -799,7 +799,7 @@ static void handle_label(std::string &command, bool &from_to_active, const std:: while (pos < GetSize(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n') label += command[pos++]; - if (label.back() == ':' && GetSize(label) > 1) + if (GetSize(label) > 1 && label.back() == ':') { label = label.substr(0, GetSize(label)-1); command = command.substr(pos); -- cgit v1.2.3 From e90195b737912f6cffcc1b8720c7d72e746d8854 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 29 Nov 2018 05:07:40 +0100 Subject: Improve ConstEval error handling for non-eval cell types Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 19 ++++++++++++------- kernel/consteval.h | 9 +++++++-- 2 files changed, 19 insertions(+), 9 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 6041168bb..8b8a56111 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -257,7 +257,7 @@ struct CellTypes return v; } - static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) + static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr) { if (type == "$sshr" && !signed1) type = "$shr"; @@ -329,10 +329,15 @@ struct CellTypes if (type == "$_ORNOT_") return const_or(arg1, eval_not(arg2), false, false, 1); + if (errp != nullptr) { + *errp = true; + return State::Sm; + } + log_abort(); } - static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2) + static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr) { if (cell->type == "$slice") { RTLIL::Const ret; @@ -415,10 +420,10 @@ struct CellTypes bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool(); int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1; - return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len); + return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp); } - static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3) + static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr) { if (cell->type.in("$mux", "$pmux", "$_MUX_")) { RTLIL::Const ret = arg1; @@ -436,10 +441,10 @@ struct CellTypes return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1)); log_assert(arg3.bits.size() == 0); - return eval(cell, arg1, arg2); + return eval(cell, arg1, arg2, errp); } - static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4) + static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr) { if (cell->type == "$_AOI4_") return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); @@ -447,7 +452,7 @@ struct CellTypes return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); log_assert(arg4.bits.size() == 0); - return eval(cell, arg1, arg2, arg3); + return eval(cell, arg1, arg2, arg3, errp); } }; diff --git a/kernel/consteval.h b/kernel/consteval.h index 0229f5045..154373a8d 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -321,8 +321,13 @@ struct ConstEval if (sig_d.size() > 0 && !eval(sig_d, undef, cell)) return false; - set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), - sig_c.as_const(), sig_d.as_const())); + bool eval_err = false; + RTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err); + + if (eval_err) + return false; + + set(sig_y, eval_ret); } return true; -- cgit v1.2.3 From 2ca237e08665e4307da5bf40b7f3e17ca3e640db Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 20 Dec 2018 07:29:46 +0000 Subject: tcl: add support for passing arguments to scripts. --- kernel/yosys.cc | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index f002955ad..6884305d9 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -166,7 +166,7 @@ std::string vstringf(const char *fmt, va_list ap) std::string string; char *str = NULL; -#if defined(_WIN32 )|| defined(__CYGWIN__) +#if defined(_WIN32 )|| defined(__CYGWIN__) int sz = 64, rc; while (1) { va_list apc; @@ -637,8 +637,9 @@ extern Tcl_Interp *yosys_get_tcl_interp() struct TclPass : public Pass { TclPass() : Pass("tcl", "execute a TCL script file") { } void help() YS_OVERRIDE { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" tcl \n"); + log(" tcl [args]\n"); log("\n"); log("This command executes the tcl commands in the specified file.\n"); log("Use 'yosys cmd' to run the yosys command 'cmd' from tcl.\n"); @@ -648,14 +649,24 @@ struct TclPass : public Pass { log("'proc' and 'rename' are wrapped to tcl commands 'procs' and 'renames'\n"); log("in order to avoid a name collision with the built in commands.\n"); log("\n"); + log("If any arguments are specified, these arguments are provided to the script via\n"); + log("the standard $argc and $argv variables.\n"); + log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + void execute(std::vector args, RTLIL::Design *) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing script file.\n"); - if (args.size() > 2) - extra_args(args, 1, design, false); - if (Tcl_EvalFile(yosys_get_tcl_interp(), args[1].c_str()) != TCL_OK) - log_cmd_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp())); + + std::vector script_args; + for (auto it = args.begin() + 2; it != args.end(); ++it) + script_args.push_back(Tcl_NewStringObj((*it).c_str(), (*it).size())); + + Tcl_Interp *interp = yosys_get_tcl_interp(); + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argc", 4), NULL, Tcl_NewIntObj(script_args.size()), 0); + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv", 4), NULL, Tcl_NewListObj(script_args.size(), script_args.data()), 0); + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv0", 5), NULL, Tcl_NewStringObj(args[1].c_str(), args[1].size()), 0); + if (Tcl_EvalFile(interp, args[1].c_str()) != TCL_OK) + log_cmd_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(interp)); } } TclPass; #endif -- cgit v1.2.3 From 18291c20d2b17689729d9c36b08967e928e4e32a Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 23 Dec 2018 09:04:23 +0000 Subject: proc_clean: remove any empty cases if all cases use all-def compare. --- kernel/rtlil.cc | 10 ++++++++++ kernel/rtlil.h | 4 ++++ 2 files changed, 14 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 14259f8ed..8404db5e9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3793,6 +3793,11 @@ RTLIL::CaseRule::~CaseRule() delete *it; } +bool RTLIL::CaseRule::empty() const +{ + return actions.empty() && switches.empty(); +} + RTLIL::CaseRule *RTLIL::CaseRule::clone() const { RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule; @@ -3809,6 +3814,11 @@ RTLIL::SwitchRule::~SwitchRule() delete *it; } +bool RTLIL::SwitchRule::empty() const +{ + return cases.empty(); +} + RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const { RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 276540aa1..f877622aa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1227,6 +1227,8 @@ struct RTLIL::CaseRule ~CaseRule(); void optimize(); + bool empty() const; + template void rewrite_sigspecs(T &functor); RTLIL::CaseRule *clone() const; }; @@ -1238,6 +1240,8 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject ~SwitchRule(); + bool empty() const; + template void rewrite_sigspecs(T &functor); RTLIL::SwitchRule *clone() const; }; -- cgit v1.2.3 From efa278e232d20ea080743801bd91d55ec62955cf Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 7 Dec 2018 19:14:07 +0000 Subject: Fix typographical and grammatical errors and inconsistencies. The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. --- kernel/log.h | 2 +- kernel/yosys.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index 0b4905c3a..e1f54a197 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -195,7 +195,7 @@ struct PerformanceTimer t += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL; return t; # else -# error Dont know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?). +# error "Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?)." # endif } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 6884305d9..2ed0f4db4 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -744,7 +744,7 @@ std::string proc_self_dirname() return "/"; } #else - #error Dont know how to determine process executable base path! + #error "Don't know how to determine process executable base path!" #endif #ifdef EMSCRIPTEN -- cgit v1.2.3 From e70ebe557cd02f52f32a297fa63008dba25e4f6a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 13 Jan 2019 17:00:58 +0100 Subject: Add optional nullstr argument to log_id() Signed-off-by: Clifford Wolf --- kernel/log.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index e1f54a197..759939025 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -94,7 +94,9 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); const char *log_const(const RTLIL::Const &value, bool autoint = true); const char *log_id(RTLIL::IdString id); -template static inline const char *log_id(T *obj) { +template static inline const char *log_id(T *obj, const char *nullstr = nullptr) { + if (nullstr && obj == nullptr) + return nullstr; return log_id(obj->name); } -- cgit v1.2.3 From edf7267019ec2e9a69be2fc5d5022a738acbe7b2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 8 Feb 2019 13:58:20 -0800 Subject: Refactor kernel/cost.h definition into cost.cc --- kernel/cost.cc | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/cost.h | 51 ++------------------------------------- 2 files changed, 77 insertions(+), 49 deletions(-) create mode 100644 kernel/cost.cc (limited to 'kernel') diff --git a/kernel/cost.cc b/kernel/cost.cc new file mode 100644 index 000000000..175f01e64 --- /dev/null +++ b/kernel/cost.cc @@ -0,0 +1,75 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/cost.h" + +YOSYS_NAMESPACE_BEGIN + +int get_cell_cost(RTLIL::IdString type, const dict ¶meters, + RTLIL::Design *design, dict *mod_cost_cache) +{ + static dict gate_cost = { + { "$_BUF_", 1 }, + { "$_NOT_", 2 }, + { "$_AND_", 4 }, + { "$_NAND_", 4 }, + { "$_OR_", 4 }, + { "$_NOR_", 4 }, + { "$_ANDNOT_", 4 }, + { "$_ORNOT_", 4 }, + { "$_XOR_", 8 }, + { "$_XNOR_", 8 }, + { "$_AOI3_", 6 }, + { "$_OAI3_", 6 }, + { "$_AOI4_", 8 }, + { "$_OAI4_", 8 }, + { "$_MUX_", 4 } + }; + + if (gate_cost.count(type)) + return gate_cost.at(type); + + if (parameters.empty() && design && design->module(type)) + { + RTLIL::Module *mod = design->module(type); + + if (mod->attributes.count("\\cost")) + return mod->attributes.at("\\cost").as_int(); + + dict local_mod_cost_cache; + if (mod_cost_cache == nullptr) + mod_cost_cache = &local_mod_cost_cache; + + if (mod_cost_cache->count(mod->name)) + return mod_cost_cache->at(mod->name); + + int module_cost = 1; + for (auto c : mod->cells()) + module_cost += get_cell_cost(c, mod_cost_cache); + + (*mod_cost_cache)[mod->name] = module_cost; + return module_cost; + } + + log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters)); + return 1; +} + +YOSYS_NAMESPACE_END diff --git a/kernel/cost.h b/kernel/cost.h index e795b571b..7d7822fa0 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -27,56 +27,9 @@ YOSYS_NAMESPACE_BEGIN int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache = nullptr); int get_cell_cost(RTLIL::IdString type, const dict ¶meters = dict(), - RTLIL::Design *design = nullptr, dict *mod_cost_cache = nullptr) -{ - static dict gate_cost = { - { "$_BUF_", 1 }, - { "$_NOT_", 2 }, - { "$_AND_", 4 }, - { "$_NAND_", 4 }, - { "$_OR_", 4 }, - { "$_NOR_", 4 }, - { "$_ANDNOT_", 4 }, - { "$_ORNOT_", 4 }, - { "$_XOR_", 8 }, - { "$_XNOR_", 8 }, - { "$_AOI3_", 6 }, - { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, - { "$_MUX_", 4 } - }; - - if (gate_cost.count(type)) - return gate_cost.at(type); - - if (parameters.empty() && design && design->module(type)) - { - RTLIL::Module *mod = design->module(type); - - if (mod->attributes.count("\\cost")) - return mod->attributes.at("\\cost").as_int(); - - dict local_mod_cost_cache; - if (mod_cost_cache == nullptr) - mod_cost_cache = &local_mod_cost_cache; - - if (mod_cost_cache->count(mod->name)) - return mod_cost_cache->at(mod->name); - - int module_cost = 1; - for (auto c : mod->cells()) - module_cost += get_cell_cost(c, mod_cost_cache); - - (*mod_cost_cache)[mod->name] = module_cost; - return module_cost; - } - - log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters)); - return 1; -} + RTLIL::Design *design = nullptr, dict *mod_cost_cache = nullptr); -int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache) +inline int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache) { return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache); } -- cgit v1.2.3 From 246391200e3e0d47ee571d4d77dd0744dba0e164 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 20 Feb 2019 16:36:42 +0100 Subject: Add FF support to wreduce Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8404db5e9..d4aebcda9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2410,6 +2410,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) if (connections_.count("\\Y")) parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]); + if (connections_.count("\\Q")) + parameters["\\WIDTH"] = GetSize(connections_["\\Q"]); + check(); } -- cgit v1.2.3 From 953e0bf88d363180619452dd0049268ee9cfbb67 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Feb 2019 14:27:46 +0100 Subject: Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior Signed-off-by: Clifford Wolf --- kernel/driver.cc | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 178641101..ca8f6a7b5 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -179,6 +179,7 @@ int main(int argc, char **argv) { std::string frontend_command = "auto"; std::string backend_command = "auto"; + std::vector vlog_defines; std::vector passes_commands; std::vector plugin_filenames; std::string output_filename = ""; @@ -268,7 +269,10 @@ int main(int argc, char **argv) printf(" -A\n"); printf(" will call abort() at the end of the script. for debugging\n"); printf("\n"); - printf(" -D [:]\n"); + printf(" -D [=]\n"); + printf(" set the specified Verilog define (via \"read -define\")\n"); + printf("\n"); + printf(" -U [:]\n"); printf(" dump the design when printing the specified log header to a file.\n"); printf(" yosys_dump_.il is used as filename if none is specified.\n"); printf(" Use 'ALL' as to dump at every header.\n"); @@ -307,7 +311,7 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:E:")) != -1) + while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:U:E:")) != -1) { switch (opt) { @@ -408,6 +412,9 @@ int main(int argc, char **argv) std::regex_constants::egrep)); break; case 'D': + vlog_defines.push_back(optarg); + break; + case 'U': { auto args = split_tokens(optarg, ":"); if (!args.empty() && args[0] == "ALL") { @@ -473,6 +480,13 @@ int main(int argc, char **argv) shell(yosys_design); } + if (!vlog_defines.empty()) { + std::string vdef_cmd = "read -define"; + for (auto vdef : vlog_defines) + vdef_cmd += " " + vdef; + run_pass(vdef_cmd); + } + while (optind < argc) run_frontend(argv[optind++], frontend_command, output_filename == "-" ? &backend_command : NULL); -- cgit v1.2.3 From 0a6588569bb859d74876bf50956cb5f02cf3a31d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Feb 2019 15:51:59 +0100 Subject: Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine" Signed-off-by: Clifford Wolf --- kernel/driver.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index ca8f6a7b5..a0bb7e60a 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -272,7 +272,7 @@ int main(int argc, char **argv) printf(" -D [=]\n"); printf(" set the specified Verilog define (via \"read -define\")\n"); printf("\n"); - printf(" -U [:]\n"); + printf(" -P [:]\n"); printf(" dump the design when printing the specified log header to a file.\n"); printf(" yosys_dump_.il is used as filename if none is specified.\n"); printf(" Use 'ALL' as to dump at every header.\n"); @@ -311,7 +311,7 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:U:E:")) != -1) + while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:P:E:")) != -1) { switch (opt) { @@ -414,7 +414,7 @@ int main(int argc, char **argv) case 'D': vlog_defines.push_back(optarg); break; - case 'U': + case 'P': { auto args = split_tokens(optarg, ":"); if (!args.empty() && args[0] == "ALL") { -- cgit v1.2.3 From 3ea0161ae7f6111cb435c839eff694476a6527ab Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 26 Feb 2019 12:04:16 -0800 Subject: Add IdString::ends_with() --- kernel/rtlil.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f877622aa..eb71fec7b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -222,6 +222,12 @@ namespace RTLIL return std::string(c_str() + pos, len); } + bool ends_with(const char* suffix) const { + size_t len = strlen(suffix); + if (size() < len) return false; + return substr(size()-len) == suffix; + } + size_t size() const { return str().size(); } -- cgit v1.2.3 From d9bb5f3637634ea214194b612aee4bb0c62d7a5c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 11 Mar 2019 01:08:36 -0700 Subject: Add ENABLE_GLOB Makefile switch Signed-off-by: Clifford Wolf --- kernel/yosys.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 2ed0f4db4..6fd53f85e 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -33,7 +33,7 @@ # include #endif -#ifdef _WIN32 +#if defined(_WIN32) # include # include #elif defined(__APPLE__) @@ -41,13 +41,15 @@ # include # include # include -# include #else # include # include # include # include # include +#endif + +#if !defined(_WIN32) && defined(YOSYS_ENABLE_GLOB) # include #endif @@ -564,7 +566,7 @@ std::vector glob_filename(const std::string &filename_pattern) { std::vector results; -#ifdef _WIN32 +#if defined(_WIN32) || !defined(YOSYS_ENABLE_GLOB) results.push_back(filename_pattern); #else glob_t globbuf; -- cgit v1.2.3 From 20c6a8c9b0abb384517c4cc6f58cd29a90bda6ff Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 11 Mar 2019 20:12:28 +0100 Subject: Improve determinism of IdString DB for similar scripts Signed-off-by: Clifford Wolf --- kernel/log.cc | 4 ++++ kernel/register.cc | 2 ++ kernel/rtlil.cc | 2 ++ kernel/rtlil.h | 64 +++++++++++++++++++++++++++++++++++++++++++++++++----- 4 files changed, 67 insertions(+), 5 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 0ee2170a0..400a549dd 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -196,7 +196,11 @@ void logv_header(RTLIL::Design *design, const char *format, va_list ap) if (log_hdump.count(header_id) && design != nullptr) for (auto &filename : log_hdump.at(header_id)) { log("Dumping current design to '%s'.\n", filename.c_str()); + if (yosys_xtrace) + IdString::xtrace_db_dump(); Pass::call(design, {"dump", "-o", filename}); + if (yosys_xtrace) + log("#X# -- end of dump --\n"); } if (pop_errfile) diff --git a/kernel/register.cc b/kernel/register.cc index 402a5b3ea..64956401f 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -86,6 +86,8 @@ Pass::pre_post_exec_state_t Pass::pre_execute() void Pass::post_execute(Pass::pre_post_exec_state_t state) { + IdString::checkpoint(); + int64_t time_ns = PerformanceTimer::query() - state.begin_ns; runtime_ns += time_ns; current_pass = state.parent_pass; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d4aebcda9..7f1816190 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -33,6 +33,8 @@ std::vector RTLIL::IdString::global_refcount_storage_; std::vector RTLIL::IdString::global_id_storage_; dict RTLIL::IdString::global_id_index_; std::vector RTLIL::IdString::global_free_idx_list_; +int RTLIL::IdString::last_created_idx_[8]; +int RTLIL::IdString::last_created_idx_ptr_; RTLIL::Const::Const() { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f877622aa..01323d112 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -76,6 +76,9 @@ namespace RTLIL struct IdString { + #undef YOSYS_XTRACE_GET_PUT + #undef YOSYS_SORT_ID_FREE_LIST + // the global id string cache static struct destruct_guard_t { @@ -89,9 +92,43 @@ namespace RTLIL static dict global_id_index_; static std::vector global_free_idx_list_; + static int last_created_idx_ptr_; + static int last_created_idx_[8]; + + static inline void xtrace_db_dump() + { + #ifdef YOSYS_XTRACE_GET_PUT + for (int idx = 0; idx < GetSize(global_id_storage_); idx++) + { + if (global_id_storage_.at(idx) == nullptr) + log("#X# DB-DUMP index %d: FREE\n", idx); + else + log("#X# DB-DUMP index %d: '%s' (ref %d)\n", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx)); + } + #endif + } + + static inline void checkpoint() + { + last_created_idx_ptr_ = 0; + for (int i = 0; i < 8; i++) { + if (last_created_idx_[i]) + put_reference(last_created_idx_[i]); + last_created_idx_[i] = 0; + } + #ifdef YOSYS_SORT_ID_FREE_LIST + std::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater()); + #endif + } + static inline int get_reference(int idx) { global_refcount_storage_.at(idx)++; + #ifdef YOSYS_XTRACE_GET_PUT + if (yosys_xtrace) { + log("#X# GET-BY-INDEX '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); + } + #endif return idx; } @@ -107,6 +144,11 @@ namespace RTLIL auto it = global_id_index_.find((char*)p); if (it != global_id_index_.end()) { global_refcount_storage_.at(it->second)++; + #ifdef YOSYS_XTRACE_GET_PUT + if (yosys_xtrace) { + log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second)); + } + #endif return it->second; } @@ -124,16 +166,22 @@ namespace RTLIL global_refcount_storage_.at(idx)++; // Avoid Create->Delete->Create pattern - static IdString last_created_id; - put_reference(last_created_id.index_); - last_created_id.index_ = idx; - get_reference(last_created_id.index_); + if (last_created_idx_[last_created_idx_ptr_]) + put_reference(last_created_idx_[last_created_idx_ptr_]); + last_created_idx_[last_created_idx_ptr_] = idx; + get_reference(last_created_idx_[last_created_idx_ptr_]); + last_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7; if (yosys_xtrace) { log("#X# New IdString '%s' with index %d.\n", p, idx); log_backtrace("-X- ", yosys_xtrace-1); } + #ifdef YOSYS_XTRACE_GET_PUT + if (yosys_xtrace) { + log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); + } + #endif return idx; } @@ -144,6 +192,12 @@ namespace RTLIL if (!destruct_guard.ok) return; + #ifdef YOSYS_XTRACE_GET_PUT + if (yosys_xtrace) { + log("#X# PUT '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); + } + #endif + log_assert(global_refcount_storage_.at(idx) > 0); if (--global_refcount_storage_.at(idx) != 0) @@ -1282,7 +1336,7 @@ inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const { return wire ? (offset < other.offset) : (data < other.data); if (wire != nullptr && other.wire != nullptr) return wire->name < other.wire->name; - return wire < other.wire; + return (wire != nullptr) < (other.wire != nullptr); } inline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const { -- cgit v1.2.3 From 1cd04a68389671c91dddb56cc3d2f9032f9b44e3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Mar 2019 21:14:50 +0100 Subject: Fix a bug in handling quotes in multi-cmd lines in Yosys scripts Signed-off-by: Clifford Wolf --- kernel/yosys.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 6fd53f85e..450e4e4cf 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -218,12 +218,18 @@ std::string next_token(std::string &text, const char *sep, bool long_strings) if (long_strings && pos_begin != text.size() && text[pos_begin] == '"') { string sep_string = sep; - for (size_t i = pos_begin+1; i < text.size(); i++) + for (size_t i = pos_begin+1; i < text.size(); i++) { if (text[i] == '"' && (i+1 == text.size() || sep_string.find(text[i+1]) != std::string::npos)) { std::string token = text.substr(pos_begin, i-pos_begin+1); text = text.substr(i+1); return token; } + if (i+1 < text.size() && text[i] == '"' && text[i+1] == ';' && (i+2 == text.size() || sep_string.find(text[i+2]) != std::string::npos)) { + std::string token = text.substr(pos_begin, i-pos_begin+1); + text = text.substr(i+2); + return token + ";"; + } + } } size_t pos_end = text.find_first_of(sep, pos_begin); -- cgit v1.2.3 From 76c9c350e7d0dfc11b609d98bdcd1ea0d845cb06 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Mar 2019 17:36:06 +0100 Subject: Add hashlib "::element(int n)" methods Signed-off-by: Clifford Wolf --- kernel/hashlib.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'kernel') diff --git a/kernel/hashlib.h b/kernel/hashlib.h index df534ec1b..e7cb312ed 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -557,9 +557,11 @@ public: void clear() { hashtable.clear(); entries.clear(); } iterator begin() { return iterator(this, int(entries.size())-1); } + iterator element(int n) { return iterator(this, int(entries.size())-1-n); } iterator end() { return iterator(nullptr, -1); } const_iterator begin() const { return const_iterator(this, int(entries.size())-1); } + const_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); } const_iterator end() const { return const_iterator(nullptr, -1); } }; @@ -881,9 +883,11 @@ public: void clear() { hashtable.clear(); entries.clear(); } iterator begin() { return iterator(this, int(entries.size())-1); } + iterator element(int n) { return iterator(this, int(entries.size())-1-n); } iterator end() { return iterator(nullptr, -1); } const_iterator begin() const { return const_iterator(this, int(entries.size())-1); } + const_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); } const_iterator end() const { return const_iterator(nullptr, -1); } }; @@ -952,6 +956,7 @@ public: void clear() { database.clear(); } const_iterator begin() const { return database.begin(); } + const_iterator element(int n) const { return database.element(n); } const_iterator end() const { return database.end(); } }; @@ -1051,6 +1056,7 @@ public: void clear() { database.clear(); parents.clear(); } const_iterator begin() const { return database.begin(); } + const_iterator element(int n) const { return database.element(n); } const_iterator end() const { return database.end(); } }; -- cgit v1.2.3 From 370db33a4c347049cb8f66c181d39fd2f2ce5e3a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Mar 2019 20:18:38 +0100 Subject: Add fmcombine pass Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 45 ++++++++++++++++++++++++++++++--------------- kernel/rtlil.cc | 4 ++-- 2 files changed, 32 insertions(+), 17 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 8b8a56111..ae88f4aaf 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -81,6 +81,27 @@ struct CellTypes } void setup_internals() + { + setup_internals_eval(); + + IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y"; + + setup_type("$tribuf", {A, EN}, {Y}, true); + + setup_type("$assert", {A, EN}, pool(), true); + setup_type("$assume", {A, EN}, pool(), true); + setup_type("$live", {A, EN}, pool(), true); + setup_type("$fair", {A, EN}, pool(), true); + setup_type("$cover", {A, EN}, pool(), true); + setup_type("$initstate", pool(), {Y}, true); + setup_type("$anyconst", pool(), {Y}, true); + setup_type("$anyseq", pool(), {Y}, true); + setup_type("$allconst", pool(), {Y}, true); + setup_type("$allseq", pool(), {Y}, true); + setup_type("$equiv", {A, B}, {Y}, true); + } + + void setup_internals_eval() { std::vector unary_ops = { "$not", "$pos", "$neg", @@ -111,20 +132,6 @@ struct CellTypes setup_type("$lcu", {P, G, CI}, {CO}, true); setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true); setup_type("$fa", {A, B, C}, {X, Y}, true); - - setup_type("$tribuf", {A, EN}, {Y}, true); - - setup_type("$assert", {A, EN}, pool(), true); - setup_type("$assume", {A, EN}, pool(), true); - setup_type("$live", {A, EN}, pool(), true); - setup_type("$fair", {A, EN}, pool(), true); - setup_type("$cover", {A, EN}, pool(), true); - setup_type("$initstate", pool(), {Y}, true); - setup_type("$anyconst", pool(), {Y}, true); - setup_type("$anyseq", pool(), {Y}, true); - setup_type("$allconst", pool(), {Y}, true); - setup_type("$allseq", pool(), {Y}, true); - setup_type("$equiv", {A, B}, {Y}, true); } void setup_internals_mem() @@ -153,6 +160,15 @@ struct CellTypes } void setup_stdcells() + { + setup_stdcells_eval(); + + IdString A = "\\A", E = "\\E", Y = "\\Y"; + + setup_type("$_TBUF_", {A, E}, {Y}, true); + } + + void setup_stdcells_eval() { IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D"; IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H"; @@ -179,7 +195,6 @@ struct CellTypes setup_type("$_OAI3_", {A, B, C}, {Y}, true); setup_type("$_AOI4_", {A, B, C, D}, {Y}, true); setup_type("$_OAI4_", {A, B, C, D}, {Y}, true); - setup_type("$_TBUF_", {A, E}, {Y}, true); } void setup_stdcells_mem() diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7f1816190..d0fa88890 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -760,7 +760,7 @@ namespace { void check() { - if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || + if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" || cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") return; @@ -2360,7 +2360,7 @@ void RTLIL::Cell::check() void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { - if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || + if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" || type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") return; -- cgit v1.2.3 From 3b796c033cc40a753e24f21b25b2701a30f022f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Mar 2019 14:38:48 +0100 Subject: Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 2 +- kernel/rtlil.h | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d0fa88890..b3214579d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3237,7 +3237,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) remove(width, width_ - width); if (width_ < width) { - RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; + RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; if (!is_signed) padding = RTLIL::State::S0; while (width_ < width) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 01323d112..52496e702 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -546,6 +546,14 @@ struct RTLIL::Const return ret; } + void extu(int width) { + bits.resize(width, RTLIL::State::S0); + } + + void exts(int width) { + bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back()); + } + inline unsigned int hash() const { unsigned int h = mkhash_init; for (auto b : bits) -- cgit v1.2.3 From 072c9393805d59b988f93b184356c54731237a5a Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 1 Apr 2019 13:36:01 +0200 Subject: Fixed identation --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index ceb1d1d39..a12355f1d 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -63,7 +63,7 @@ extern "C" PyObject* INIT_MODULE(); #else # define INIT_MODULE initlibyosys - extern "C" void INIT_MODULE(); + extern "C" void INIT_MODULE(); #endif #endif -- cgit v1.2.3 From 0774a500d4a03104787e6514c69ff4995633a65f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 12:21:21 +0200 Subject: Added support for changing Yosys namespace --- kernel/yosys.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index a630798bb..2cf6188b4 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -119,6 +119,7 @@ extern const char *Tcl_GetStringResult(Tcl_Interp *interp); # define PATH_MAX 4096 #endif +#define YOSYS_NAMESPACE Yosys #define PRIVATE_NAMESPACE_BEGIN namespace { #define PRIVATE_NAMESPACE_END } #define YOSYS_NAMESPACE_BEGIN namespace Yosys { -- cgit v1.2.3 From 827a96d3a38afe025c9efbd182069a9c9adee267 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 3 Apr 2019 14:27:39 +0200 Subject: Global lists in rtlil.cc are now static objects --- kernel/rtlil.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index efe2c3559..bb870f66f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -387,10 +387,10 @@ RTLIL::Design::~Design() } #ifdef WITH_PYTHON -static std::map *all_designs = new std::map(); +static std::map all_designs; std::map *RTLIL::Design::get_all_designs(void) { - return all_designs; + return &all_designs; } #endif @@ -671,10 +671,10 @@ RTLIL::Module::~Module() } #ifdef WITH_PYTHON -static std::map *all_modules = new std::map(); +static std::map all_modules; std::map *RTLIL::Module::get_all_modules(void) { - return all_modules; + return &all_modules; } #endif @@ -2253,10 +2253,10 @@ RTLIL::Wire::~Wire() } #ifdef WITH_PYTHON -static std::map *all_wires = new std::map(); +static std::map all_wires; std::map *RTLIL::Wire::get_all_wires(void) { - return all_wires; + return &all_wires; } #endif @@ -2296,10 +2296,10 @@ RTLIL::Cell::~Cell() } #ifdef WITH_PYTHON -static std::map *all_cells = new std::map(); +static std::map all_cells; std::map *RTLIL::Cell::get_all_cells(void) { - return all_cells; + return &all_cells; } #endif @@ -3959,10 +3959,10 @@ RTLIL::Memory::~Memory() { RTLIL::Memory::get_all_memorys()->erase(hashidx_); } -static std::map *all_memorys = new std::map(); +static std::map all_memorys; std::map *RTLIL::Memory::get_all_memorys(void) { - return all_memorys; + return &all_memorys; } #endif YOSYS_NAMESPACE_END -- cgit v1.2.3 From dfb242c905ff10bb4038f080aeb74a820e8fbd00 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 5 Apr 2019 17:31:49 +0200 Subject: Add "read_ilang -lib" Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 24 ++++++++++++++++++++++++ kernel/rtlil.h | 1 + 2 files changed, 25 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b3214579d..9ae20a317 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -641,6 +641,30 @@ RTLIL::Module::~Module() delete it->second; } +void RTLIL::Module::makeblackbox() +{ + pool delwires; + + for (auto it = wires_.begin(); it != wires_.end(); ++it) + if (!it->second->port_input && !it->second->port_output) + delwires.insert(it->second); + + for (auto it = memories.begin(); it != memories.end(); ++it) + delete it->second; + memories.clear(); + + for (auto it = cells_.begin(); it != cells_.end(); ++it) + delete it->second; + cells_.clear(); + + for (auto it = processes.begin(); it != processes.end(); ++it) + delete it->second; + processes.clear(); + + remove(delwires); + set_bool_attribute("\\blackbox"); +} + void RTLIL::Module::reprocess_module(RTLIL::Design *, dict) { log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name)); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 52496e702..fb045bc72 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -976,6 +976,7 @@ public: virtual void sort(); virtual void check(); virtual void optimize(); + virtual void makeblackbox(); void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); -- cgit v1.2.3 From f4abc21d8ad79621cc24852bd76abf40a9d9f702 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 18 Apr 2019 17:42:12 +0200 Subject: Add "whitebox" attribute, add "read_verilog -wb" Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 6 +++--- kernel/rtlil.h | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9ae20a317..2f8715755 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -589,7 +589,7 @@ std::vector RTLIL::Design::selected_modules() const std::vector result; result.reserve(modules_.size()); for (auto &it : modules_) - if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox")) + if (selected_module(it.first) && !it.second->get_blackbox_attribute()) result.push_back(it.second); return result; } @@ -599,7 +599,7 @@ std::vector RTLIL::Design::selected_whole_modules() const std::vector result; result.reserve(modules_.size()); for (auto &it : modules_) - if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox")) + if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute()) result.push_back(it.second); return result; } @@ -609,7 +609,7 @@ std::vector RTLIL::Design::selected_whole_modules_warn() const std::vector result; result.reserve(modules_.size()); for (auto &it : modules_) - if (it.second->get_bool_attribute("\\blackbox")) + if (it.second->get_blackbox_attribute()) continue; else if (selected_whole_module(it.first)) result.push_back(it.second); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fb045bc72..176dc3fc2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -569,6 +569,10 @@ struct RTLIL::AttrObject void set_bool_attribute(RTLIL::IdString id); bool get_bool_attribute(RTLIL::IdString id) const; + bool get_blackbox_attribute() const { + return get_bool_attribute("\\blackbox") || get_bool_attribute("\\whitebox"); + } + void set_strpool_attribute(RTLIL::IdString id, const pool &data); void add_strpool_attribute(RTLIL::IdString id, const pool &data); pool get_strpool_attribute(RTLIL::IdString id) const; -- cgit v1.2.3 From c997a77014b5d8dbfb24e77bb8157454619ea366 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Apr 2019 10:19:45 -0700 Subject: Ignore 'whitebox' attr in flatten with "-wb" option --- kernel/rtlil.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c11c020c1..db0a8f762 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -575,8 +575,8 @@ struct RTLIL::AttrObject void set_bool_attribute(RTLIL::IdString id); bool get_bool_attribute(RTLIL::IdString id) const; - bool get_blackbox_attribute() const { - return get_bool_attribute("\\blackbox") || get_bool_attribute("\\whitebox"); + bool get_blackbox_attribute(bool ignore_wb=false) const { + return get_bool_attribute("\\blackbox") || (!ignore_wb && get_bool_attribute("\\whitebox")); } void set_strpool_attribute(RTLIL::IdString id, const pool &data); -- cgit v1.2.3 From 290a798cec4dae02886877a342b00c1ba7d5b22d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Apr 2019 10:19:45 -0700 Subject: Ignore 'whitebox' attr in flatten with "-wb" option --- kernel/rtlil.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 176dc3fc2..9e396d6f6 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -569,8 +569,8 @@ struct RTLIL::AttrObject void set_bool_attribute(RTLIL::IdString id); bool get_bool_attribute(RTLIL::IdString id) const; - bool get_blackbox_attribute() const { - return get_bool_attribute("\\blackbox") || get_bool_attribute("\\whitebox"); + bool get_blackbox_attribute(bool ignore_wb=false) const { + return get_bool_attribute("\\blackbox") || (!ignore_wb && get_bool_attribute("\\whitebox")); } void set_strpool_attribute(RTLIL::IdString id, const pool &data); -- cgit v1.2.3 From 5b915f01539c993466e83593ee8ae69b45360b81 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 20 Apr 2019 11:04:46 +0200 Subject: Add "wbflip" command Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 7 +++++-- kernel/rtlil.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2f8715755..f6f08bb9e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -207,9 +207,12 @@ bool RTLIL::Const::is_fully_undef() const return true; } -void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id) +void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value) { - attributes[id] = RTLIL::Const(1); + if (value) + attributes[id] = RTLIL::Const(1); + else if (attributes.count(id)) + attributes.erase(id); } bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9e396d6f6..330a81c3b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -566,7 +566,7 @@ struct RTLIL::AttrObject { dict attributes; - void set_bool_attribute(RTLIL::IdString id); + void set_bool_attribute(RTLIL::IdString id, bool value=true); bool get_bool_attribute(RTLIL::IdString id) const; bool get_blackbox_attribute(bool ignore_wb=false) const { -- cgit v1.2.3 From e158ea20979165c1bac4c5c4027cf53255e57baa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 17:25:52 +0200 Subject: Add log_debug() framework Signed-off-by: Clifford Wolf --- kernel/driver.cc | 8 +++++++- kernel/log.cc | 7 +++++++ kernel/log.h | 43 +++++++++++++++++++++++++++++++++++++++++++ kernel/register.cc | 1 + 4 files changed, 58 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index c539ba569..1bc7a5935 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -295,6 +295,9 @@ int main(int argc, char **argv) printf(" -E \n"); printf(" write a Makefile dependencies file with in- and output file names\n"); printf("\n"); + printf(" -g\n"); + printf(" globally enable debug log messages\n"); + printf("\n"); printf(" -V\n"); printf(" print version information and exit\n"); printf("\n"); @@ -315,7 +318,7 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:P:E:")) != -1) + while ((opt = getopt(argc, argv, "MXAQTVSgm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:P:E:")) != -1) { switch (opt) { @@ -340,6 +343,9 @@ int main(int argc, char **argv) case 'S': passes_commands.push_back("synth"); break; + case 'g': + log_force_debug++; + break; case 'm': plugin_filenames.push_back(optarg); break; diff --git a/kernel/log.cc b/kernel/log.cc index 400a549dd..9a9104e26 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -56,6 +56,10 @@ int log_verbose_level; string log_last_error; void (*log_error_atexit)() = NULL; +int log_make_debug = 0; +int log_force_debug = 0; +int log_debug_suppressed = 0; + vector header_count; pool log_id_cache; vector string_buf; @@ -92,6 +96,9 @@ void logv(const char *format, va_list ap) format++; } + if (log_make_debug && !ys_debug(1)) + return; + std::string str = vstringf(format, ap); if (str.empty()) diff --git a/kernel/log.h b/kernel/log.h index 759939025..e6afae716 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -64,6 +64,10 @@ extern int log_verbose_level; extern string log_last_error; extern void (*log_error_atexit)(); +extern int log_make_debug; +extern int log_force_debug; +extern int log_debug_suppressed; + void logv(const char *format, va_list ap); void logv_header(RTLIL::Design *design, const char *format, va_list ap); void logv_warning(const char *format, va_list ap); @@ -82,6 +86,45 @@ YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4), noreturn); YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); +#ifndef NDEBUG +static inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; } +# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0) +#else +static inline bool ys_debug(int n = 0) { return false; } +# define log_debug(_fmt, ...) do { } while (0) +#endif + +static inline void log_suppressed() { + if (log_debug_suppressed && !log_make_debug) { + log("\n", log_debug_suppressed); + log_debug_suppressed = 0; + } +} + +struct LogMakeDebugHdl { + bool status = false; + LogMakeDebugHdl(bool start_on = false) { + if (start_on) + on(); + } + ~LogMakeDebugHdl() { + off(); + } + void on() { + if (status) return; + status=true; + log_make_debug++; + } + void off_silent() { + if (!status) return; + status=false; + log_make_debug--; + } + void off() { + off_silent(); + } +}; + void log_spacer(); void log_push(); void log_pop(); diff --git a/kernel/register.cc b/kernel/register.cc index 64956401f..71eb6b187 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -87,6 +87,7 @@ Pass::pre_post_exec_state_t Pass::pre_execute() void Pass::post_execute(Pass::pre_post_exec_state_t state) { IdString::checkpoint(); + log_suppressed(); int64_t time_ns = PerformanceTimer::query() - state.begin_ns; runtime_ns += time_ns; -- cgit v1.2.3 From 2c6358ea25d595bf014a564860e3ffde7eddb2cb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 11:21:17 -0700 Subject: Remove kernel/cost.cc since master has refactored it --- kernel/cost.cc | 75 ---------------------------------------------------------- 1 file changed, 75 deletions(-) delete mode 100644 kernel/cost.cc (limited to 'kernel') diff --git a/kernel/cost.cc b/kernel/cost.cc deleted file mode 100644 index 175f01e64..000000000 --- a/kernel/cost.cc +++ /dev/null @@ -1,75 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/cost.h" - -YOSYS_NAMESPACE_BEGIN - -int get_cell_cost(RTLIL::IdString type, const dict ¶meters, - RTLIL::Design *design, dict *mod_cost_cache) -{ - static dict gate_cost = { - { "$_BUF_", 1 }, - { "$_NOT_", 2 }, - { "$_AND_", 4 }, - { "$_NAND_", 4 }, - { "$_OR_", 4 }, - { "$_NOR_", 4 }, - { "$_ANDNOT_", 4 }, - { "$_ORNOT_", 4 }, - { "$_XOR_", 8 }, - { "$_XNOR_", 8 }, - { "$_AOI3_", 6 }, - { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, - { "$_MUX_", 4 } - }; - - if (gate_cost.count(type)) - return gate_cost.at(type); - - if (parameters.empty() && design && design->module(type)) - { - RTLIL::Module *mod = design->module(type); - - if (mod->attributes.count("\\cost")) - return mod->attributes.at("\\cost").as_int(); - - dict local_mod_cost_cache; - if (mod_cost_cache == nullptr) - mod_cost_cache = &local_mod_cost_cache; - - if (mod_cost_cache->count(mod->name)) - return mod_cost_cache->at(mod->name); - - int module_cost = 1; - for (auto c : mod->cells()) - module_cost += get_cell_cost(c, mod_cost_cache); - - (*mod_cost_cache)[mod->name] = module_cost; - return module_cost; - } - - log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters)); - return 1; -} - -YOSYS_NAMESPACE_END -- cgit v1.2.3 From 742c2f245dbe9db1cb89257b296b71b1cb9ac771 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 23 Apr 2019 17:54:00 +0100 Subject: Fixes for OAI4 cell implementation Fixes #955 and the underlying issue in #954 Signed-off-by: David Shah --- kernel/cellaigs.cc | 2 +- kernel/celltypes.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 5fd76afe5..26c625f89 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -453,7 +453,7 @@ Aig::Aig(Cell *cell) int B = mk.inport("\\B"); int C = mk.inport("\\C"); int D = mk.inport("\\D"); - int Y = mk.nand_gate(mk.nor_gate(A, B), mk.nor_gate(C, D)); + int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); mk.outport(Y, "\\Y"); goto optimize; } diff --git a/kernel/celltypes.h b/kernel/celltypes.h index ae88f4aaf..0da78c313 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -464,7 +464,7 @@ struct CellTypes if (cell->type == "$_AOI4_") return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); if (cell->type == "$_OAI4_") - return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); + return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1)); log_assert(arg4.bits.size() == 0); return eval(cell, arg1, arg2, arg3, errp); -- cgit v1.2.3 From 3cc95fb4be27a3e130563db102ed268876027288 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Apr 2019 21:58:57 +0200 Subject: Add specify parser Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7e1159cac..7d5334eb1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1194,6 +1194,16 @@ namespace { return; } + if (cell->type == "$specify2") { + // FIXME + return; + } + + if (cell->type == "$specify3") { + // FIXME + return; + } + if (cell->type == "$_BUF_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } -- cgit v1.2.3 From e1d73e03d38e9408cc7bce685645bb170ca5a6b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:26:20 +0200 Subject: Add InternalCellChecker support for $specify2 and $specify3 Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d5334eb1..9e06b8323 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1194,13 +1194,27 @@ namespace { return; } - if (cell->type == "$specify2") { - // FIXME - return; - } - - if (cell->type == "$specify3") { - // FIXME + if (cell->type.in("$specify2", "$specify3")) { + param_bool("\\FULL"); + param_bool("\\SRC_DST_PEN"); + param_bool("\\SRC_DST_POL"); + param("\\T_RISE_MIN"); + param("\\T_RISE_AVG"); + param("\\T_RISE_MAX"); + param("\\T_FALL_MIN"); + param("\\T_FALL_AVG"); + param("\\T_FALL_MAX"); + port("\\EN", 1); + port("\\SRC", param("\\SRC_WIDTH")); + port("\\DST", param("\\DST_WIDTH")); + if (cell->type == "$specify3") { + param_bool("\\EDGE_EN"); + param_bool("\\EDGE_POL"); + param_bool("\\DAT_DST_PEN"); + param_bool("\\DAT_DST_POL"); + port("\\DAT", param("\\DST_WIDTH")); + } + check_expected(); return; } -- cgit v1.2.3 From aec2475a9d7a2a903d5015840a3320ce2cedf5cd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:29:59 +0200 Subject: Add CellTypes support for $specify2 and $specify3 Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 0da78c313..f8c73ed83 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -85,6 +85,7 @@ struct CellTypes setup_internals_eval(); IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y"; + IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT"; setup_type("$tribuf", {A, EN}, {Y}, true); @@ -99,6 +100,8 @@ struct CellTypes setup_type("$allconst", pool(), {Y}, true); setup_type("$allseq", pool(), {Y}, true); setup_type("$equiv", {A, B}, {Y}, true); + setup_type("$specify2", {EN, SRC, DST}, pool(), true); + setup_type("$specify3", {EN, SRC, DST, DAT}, pool(), true); } void setup_internals_eval() -- cgit v1.2.3 From e807e88b607834170692f56a5538b89fd4175a36 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:52:47 +0200 Subject: Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9e06b8323..4522b0a08 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1199,10 +1199,10 @@ namespace { param_bool("\\SRC_DST_PEN"); param_bool("\\SRC_DST_POL"); param("\\T_RISE_MIN"); - param("\\T_RISE_AVG"); + param("\\T_RISE_TYP"); param("\\T_RISE_MAX"); param("\\T_FALL_MIN"); - param("\\T_FALL_AVG"); + param("\\T_FALL_TYP"); param("\\T_FALL_MAX"); port("\\EN", 1); port("\\SRC", param("\\SRC_WIDTH")); -- cgit v1.2.3 From 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 15:46:40 +0200 Subject: Add $specrule cells for $setup/$hold/$skew specify rules Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 2 ++ kernel/rtlil.cc | 15 +++++++++++++++ 2 files changed, 17 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index f8c73ed83..4e91eddda 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -86,6 +86,7 @@ struct CellTypes IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y"; IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT"; + IdString EN_SRC = "\\EN_SRC", EN_DST = "\\EN_DST"; setup_type("$tribuf", {A, EN}, {Y}, true); @@ -102,6 +103,7 @@ struct CellTypes setup_type("$equiv", {A, B}, {Y}, true); setup_type("$specify2", {EN, SRC, DST}, pool(), true); setup_type("$specify3", {EN, SRC, DST, DAT}, pool(), true); + setup_type("$specrule", {EN_SRC, EN_DST, SRC, DST}, pool(), true); } void setup_internals_eval() diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 4522b0a08..dae3698a9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1218,6 +1218,21 @@ namespace { return; } + if (cell->type == "$specrule") { + param_bool("\\SRC_PEN"); + param_bool("\\SRC_POL"); + param_bool("\\DST_PEN"); + param_bool("\\DST_POL"); + param_bool("\\LIMIT_GT"); + param("\\T_LIMIT"); + port("\\SRC_EN", 1); + port("\\DST_EN", 1); + port("\\SRC", param("\\SRC_WIDTH")); + port("\\DST", param("\\DST_WIDTH")); + check_expected(); + return; + } + if (cell->type == "$_BUF_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } -- cgit v1.2.3 From 4575e4ad86494e99dd05200f7242dfa632053c78 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 22:18:04 +0200 Subject: Improve $specrule interface Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index dae3698a9..3dd18c296 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1223,7 +1223,8 @@ namespace { param_bool("\\SRC_POL"); param_bool("\\DST_PEN"); param_bool("\\DST_POL"); - param_bool("\\LIMIT_GT"); + param_bool("\\SKEW"); + param_bool("\\HOLD"); param("\\T_LIMIT"); port("\\SRC_EN", 1); port("\\DST_EN", 1); -- cgit v1.2.3 From 64925b4e8f7890f5447d9655b2c69dd59a93f7cd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 22:57:10 +0200 Subject: Improve $specrule interface Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3dd18c296..040644c47 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1219,13 +1219,13 @@ namespace { } if (cell->type == "$specrule") { + param("\\TYPE"); param_bool("\\SRC_PEN"); param_bool("\\SRC_POL"); param_bool("\\DST_PEN"); param_bool("\\DST_POL"); - param_bool("\\SKEW"); - param_bool("\\HOLD"); param("\\T_LIMIT"); + param("\\T_LIMIT2"); port("\\SRC_EN", 1); port("\\DST_EN", 1); port("\\SRC", param("\\SRC_WIDTH")); -- cgit v1.2.3 From e531fb203aedeb3863ebf8add0bbd8251183d27a Mon Sep 17 00:00:00 2001 From: Oleg Endo Date: Mon, 29 Apr 2019 16:13:34 +0900 Subject: escape spaces with backslash when writing dep file filenames are sparated by spaces in the dep file. if a filename in the dep file contains spaces they must be escaped, otherwise the tool that reads the dep file will see multiple wrong filenames. --- kernel/driver.cc | 4 ++-- kernel/yosys.cc | 14 ++++++++++++++ kernel/yosys.h | 1 + 3 files changed, 17 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 1bc7a5935..8c56d059b 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -529,13 +529,13 @@ int main(int argc, char **argv) log_error("Can't open dependencies file for writing: %s\n", strerror(errno)); bool first = true; for (auto fn : yosys_output_files) { - fprintf(f, "%s%s", first ? "" : " ", fn.c_str()); + fprintf(f, "%s%s", first ? "" : " ", escape_filename_spaces (fn).c_str()); first = false; } fprintf(f, ":"); for (auto fn : yosys_input_files) { if (yosys_output_files.count(fn) == 0) - fprintf(f, " %s", fn.c_str()); + fprintf(f, " %s", escape_filename_spaces (fn).c_str()); } fprintf(f, "\n"); } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index a12355f1d..267a7d01c 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -482,6 +482,20 @@ void remove_directory(std::string dirname) #endif } +std::string escape_filename_spaces (const std::string& filename) +{ + std::string out; + out.reserve (filename.size ()); + for (auto c : filename) + { + if (c == ' ') + out += "\\ "; + else + out.push_back (c); + } + return out; +} + int GetSize(RTLIL::Wire *wire) { return wire->width; diff --git a/kernel/yosys.h b/kernel/yosys.h index 2cf6188b4..d64904151 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -257,6 +257,7 @@ std::string make_temp_dir(std::string template_str = "/tmp/yosys_XXXXXX"); bool check_file_exists(std::string filename, bool is_exec = false); bool is_absolute_path(std::string filename); void remove_directory(std::string dirname); +std::string escape_filename_spaces (const std::string& filename); template int GetSize(const T &obj) { return obj.size(); } int GetSize(RTLIL::Wire *wire); -- cgit v1.2.3 From 4f15e7f00fa2b073d6df39d4af7171f2a3f07bc9 Mon Sep 17 00:00:00 2001 From: Oleg Endo Date: Mon, 29 Apr 2019 19:20:33 +0900 Subject: fix codestyle formatting --- kernel/driver.cc | 4 ++-- kernel/yosys.cc | 22 +++++++++++----------- kernel/yosys.h | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index 8c56d059b..f273057dd 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -529,13 +529,13 @@ int main(int argc, char **argv) log_error("Can't open dependencies file for writing: %s\n", strerror(errno)); bool first = true; for (auto fn : yosys_output_files) { - fprintf(f, "%s%s", first ? "" : " ", escape_filename_spaces (fn).c_str()); + fprintf(f, "%s%s", first ? "" : " ", escape_filename_spaces(fn).c_str()); first = false; } fprintf(f, ":"); for (auto fn : yosys_input_files) { if (yosys_output_files.count(fn) == 0) - fprintf(f, " %s", escape_filename_spaces (fn).c_str()); + fprintf(f, " %s", escape_filename_spaces(fn).c_str()); } fprintf(f, "\n"); } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 267a7d01c..20d972150 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -482,18 +482,18 @@ void remove_directory(std::string dirname) #endif } -std::string escape_filename_spaces (const std::string& filename) +std::string escape_filename_spaces(const std::string& filename) { - std::string out; - out.reserve (filename.size ()); - for (auto c : filename) - { - if (c == ' ') - out += "\\ "; - else - out.push_back (c); - } - return out; + std::string out; + out.reserve(filename.size()); + for (auto c : filename) + { + if (c == ' ') + out += "\\ "; + else + out.push_back(c); + } + return out; } int GetSize(RTLIL::Wire *wire) diff --git a/kernel/yosys.h b/kernel/yosys.h index d64904151..82eb069ab 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -257,7 +257,7 @@ std::string make_temp_dir(std::string template_str = "/tmp/yosys_XXXXXX"); bool check_file_exists(std::string filename, bool is_exec = false); bool is_absolute_path(std::string filename); void remove_directory(std::string dirname); -std::string escape_filename_spaces (const std::string& filename); +std::string escape_filename_spaces(const std::string& filename); template int GetSize(const T &obj) { return obj.size(); } int GetSize(RTLIL::Wire *wire); -- cgit v1.2.3 From 9268cd16135db87920ee49a54a16dab62fc1f4a8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Apr 2019 15:19:04 +0200 Subject: Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7e1159cac..dd6817873 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3456,7 +3456,7 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const pack(); other.pack(); - if (chunks_.size() != chunks_.size()) + if (chunks_.size() != other.chunks_.size()) return false; updhash(); -- cgit v1.2.3 From ac10e7d96da4965751fd60a8dd42a8998c011c39 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Fri, 3 May 2019 03:10:43 +0300 Subject: Initial implementation of elaboration system tasks (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. --- kernel/log.cc | 11 +++++++++++ kernel/log.h | 1 + 2 files changed, 12 insertions(+) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 9a9104e26..d2a661bb0 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -278,6 +278,17 @@ void log_file_warning(const std::string &filename, int lineno, va_end(ap); } +void log_file_info(const std::string &filename, int lineno, + const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string prefix = stringf("%s:%d: Info: ", + filename.c_str(), lineno); + logv_warning_with_prefix(prefix.c_str(), format, ap); + va_end(ap); +} + YS_ATTRIBUTE(noreturn) static void logv_error_with_prefix(const char *prefix, const char *format, va_list ap) diff --git a/kernel/log.h b/kernel/log.h index e6afae716..3e1facae8 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -80,6 +80,7 @@ void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); // Log with filename to report a problem in a source file. void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); +void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); -- cgit v1.2.3 From 87426f5a06b0cf9d1fe44efda65e3c048d89d322 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 May 2019 08:46:24 +0200 Subject: Improve write_verilog specify support Signed-off-by: Clifford Wolf --- kernel/rtlil.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index db5c33c73..0c3fa6f76 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -50,7 +50,7 @@ namespace RTLIL CONST_FLAG_NONE = 0, CONST_FLAG_STRING = 1, CONST_FLAG_SIGNED = 2, // only used for parameters - CONST_FLAG_REAL = 4 // unused -- to be used for parameters + CONST_FLAG_REAL = 4 // only used for parameters }; struct Const; -- cgit v1.2.3 From bafbb9ee905f042056d723ecde4a62d58b6d8f4c Mon Sep 17 00:00:00 2001 From: Matthew Daiter Date: Mon, 6 May 2019 18:33:56 -0500 Subject: Optimize ceil_log2 function --- kernel/yosys.cc | 6 ++++-- kernel/yosys.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 20d972150..377572fc2 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -151,14 +151,16 @@ void yosys_banner() int ceil_log2(int x) { +#if defined(__GNUC__) + return x > 1 ? (8*sizeof(int)) - __builtin_clz(x-1) : 0; +#else if (x <= 0) return 0; - for (int i = 0; i < 32; i++) if (((x-1) >> i) == 0) return i; - log_abort(); +#endif } std::string stringf(const char *fmt, ...) diff --git a/kernel/yosys.h b/kernel/yosys.h index 82eb069ab..c7b671724 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -244,7 +244,7 @@ extern bool memhasher_active; inline void memhasher() { if (memhasher_active) memhasher_do(); } void yosys_banner(); -int ceil_log2(int x); +int ceil_log2(int x) YS_ATTRIBUTE(const); std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2)); std::string vstringf(const char *fmt, va_list ap); int readsome(std::istream &f, char *s, int n); -- cgit v1.2.3 From 6e629d289515e2792fa644fca105998bd9e366de Mon Sep 17 00:00:00 2001 From: Matthew Daiter Date: Tue, 7 May 2019 22:04:28 -0500 Subject: Minor optimization to get_attribute_bool --- kernel/rtlil.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 147d378e5..79ff4a6a6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -218,15 +218,19 @@ void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value) { if (value) attributes[id] = RTLIL::Const(1); - else if (attributes.count(id)) - attributes.erase(id); + else { + const auto it = attributes.find(id); + if (it != attributes.end()) + attributes.erase(it); + } } bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const { - if (attributes.count(id) == 0) + const auto it = attributes.find(id); + if (it == attributes.end()) return false; - return attributes.at(id).as_bool(); + return it->second.as_bool(); } void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool &data) -- cgit v1.2.3 From 30c762d3a148afa9e27a93c1fa098b7c478511a4 Mon Sep 17 00:00:00 2001 From: Kristoffer Ellersgaard Koch Date: Sun, 5 May 2019 10:00:27 +0200 Subject: Fix all warnings that occurred when compiling with gcc9 --- kernel/rtlil.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index db5c33c73..54c8ee3bd 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -518,6 +518,7 @@ struct RTLIL::Const Const(const std::vector &bits) : bits(bits) { flags = CONST_FLAG_NONE; } Const(const std::vector &bits); Const(const RTLIL::Const &c); + RTLIL::Const &operator =(const RTLIL::Const &other) = default; bool operator <(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const; @@ -597,6 +598,7 @@ struct RTLIL::SigChunk SigChunk(RTLIL::State bit, int width = 1); SigChunk(RTLIL::SigBit bit); SigChunk(const RTLIL::SigChunk &sigchunk); + RTLIL::SigChunk &operator =(const RTLIL::SigChunk &other) = default; RTLIL::SigChunk extract(int offset, int length) const; @@ -622,6 +624,7 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigChunk &chunk, int index); SigBit(const RTLIL::SigSpec &sig); SigBit(const RTLIL::SigBit &sigbit); + RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default; bool operator <(const RTLIL::SigBit &other) const; bool operator ==(const RTLIL::SigBit &other) const; -- cgit v1.2.3 From 287de4b848bdd33a9ba52018fc9b9779a10e60c7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 15 May 2019 16:01:00 +0200 Subject: Add rewrite_sigspecs2, Improve remove() wires Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 29 +++++++++++++++++++++------- kernel/rtlil.h | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 79ff4a6a6..790ba52a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1514,7 +1514,10 @@ void RTLIL::Module::add(RTLIL::Cell *cell) cell->module = this; } -namespace { +void RTLIL::Module::remove(const pool &wires) +{ + log_assert(refcount_wires_ == 0); + struct DeleteWireWorker { RTLIL::Module *module; @@ -1529,17 +1532,29 @@ namespace { } sig = chunks; } - }; -} -void RTLIL::Module::remove(const pool &wires) -{ - log_assert(refcount_wires_ == 0); + void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) { + log_assert(GetSize(lhs) == GetSize(rhs)); + RTLIL::SigSpec new_lhs, new_rhs; + for (int i = 0; i < GetSize(lhs); i++) { + RTLIL::SigBit lhs_bit = lhs[i]; + if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) + continue; + RTLIL::SigBit rhs_bit = rhs[i]; + if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire)) + continue; + new_lhs.append(lhs_bit); + new_rhs.append(rhs_bit); + } + lhs = new_lhs; + rhs = new_rhs; + } + }; DeleteWireWorker delete_wire_worker; delete_wire_worker.module = this; delete_wire_worker.wires_p = &wires; - rewrite_sigspecs(delete_wire_worker); + rewrite_sigspecs2(delete_wire_worker); for (auto &it : wires) { log_assert(wires_.count(it->name) != 0); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a0270bd1c..81ca93dce 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1001,6 +1001,7 @@ public: void fixup_ports(); template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; @@ -1306,6 +1307,7 @@ public: } template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); #ifdef WITH_PYTHON static std::map *get_all_cells(void); @@ -1324,6 +1326,7 @@ struct RTLIL::CaseRule bool empty() const; template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); RTLIL::CaseRule *clone() const; }; @@ -1337,6 +1340,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject bool empty() const; template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); RTLIL::SwitchRule *clone() const; }; @@ -1347,6 +1351,7 @@ struct RTLIL::SyncRule std::vector actions; template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); RTLIL::SyncRule *clone() const; }; @@ -1359,6 +1364,7 @@ struct RTLIL::Process : public RTLIL::AttrObject ~Process(); template void rewrite_sigspecs(T &functor); + template void rewrite_sigspecs2(T &functor); RTLIL::Process *clone() const; }; @@ -1420,12 +1426,30 @@ void RTLIL::Module::rewrite_sigspecs(T &functor) } } +template +void RTLIL::Module::rewrite_sigspecs2(T &functor) +{ + for (auto &it : cells_) + it.second->rewrite_sigspecs2(functor); + for (auto &it : processes) + it.second->rewrite_sigspecs2(functor); + for (auto &it : connections_) { + functor(it.first, it.second); + } +} + template void RTLIL::Cell::rewrite_sigspecs(T &functor) { for (auto &it : connections_) functor(it.second); } +template +void RTLIL::Cell::rewrite_sigspecs2(T &functor) { + for (auto &it : connections_) + functor(it.second); +} + template void RTLIL::CaseRule::rewrite_sigspecs(T &functor) { for (auto &it : compare) @@ -1438,6 +1462,17 @@ void RTLIL::CaseRule::rewrite_sigspecs(T &functor) { it->rewrite_sigspecs(functor); } +template +void RTLIL::CaseRule::rewrite_sigspecs2(T &functor) { + for (auto &it : compare) + functor(it); + for (auto &it : actions) { + functor(it.first, it.second); + } + for (auto it : switches) + it->rewrite_sigspecs2(functor); +} + template void RTLIL::SwitchRule::rewrite_sigspecs(T &functor) { @@ -1446,6 +1481,14 @@ void RTLIL::SwitchRule::rewrite_sigspecs(T &functor) it->rewrite_sigspecs(functor); } +template +void RTLIL::SwitchRule::rewrite_sigspecs2(T &functor) +{ + functor(signal); + for (auto it : cases) + it->rewrite_sigspecs2(functor); +} + template void RTLIL::SyncRule::rewrite_sigspecs(T &functor) { @@ -1456,6 +1499,15 @@ void RTLIL::SyncRule::rewrite_sigspecs(T &functor) } } +template +void RTLIL::SyncRule::rewrite_sigspecs2(T &functor) +{ + functor(signal); + for (auto &it : actions) { + functor(it.first, it.second); + } +} + template void RTLIL::Process::rewrite_sigspecs(T &functor) { @@ -1464,6 +1516,14 @@ void RTLIL::Process::rewrite_sigspecs(T &functor) it->rewrite_sigspecs(functor); } +template +void RTLIL::Process::rewrite_sigspecs2(T &functor) +{ + root_case.rewrite_sigspecs2(functor); + for (auto it : syncs) + it->rewrite_sigspecs2(functor); +} + YOSYS_NAMESPACE_END #endif -- cgit v1.2.3 From 0971f772d7975a3e6e3772838ce8e333a2a088c4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 22 May 2019 13:46:38 +0200 Subject: Fix handling of warning and error messages within log_make_debug-blocks Signed-off-by: Clifford Wolf --- kernel/log.cc | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 9a9104e26..fa74a6a3c 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -230,6 +230,9 @@ static void logv_warning_with_prefix(const char *prefix, } else { + int bak_log_make_debug = log_make_debug; + log_make_debug = 0; + for (auto &re : log_werror_regexes) if (std::regex_search(message, re)) log_error("%s", message.c_str()); @@ -254,6 +257,7 @@ static void logv_warning_with_prefix(const char *prefix, } log_warnings_count++; + log_make_debug = bak_log_make_debug; } } @@ -285,6 +289,9 @@ static void logv_error_with_prefix(const char *prefix, #ifdef EMSCRIPTEN auto backup_log_files = log_files; #endif + int bak_log_make_debug = log_make_debug; + log_make_debug = 0; + log_suppressed(); if (log_errfile != NULL) log_files.push_back(log_errfile); @@ -298,6 +305,8 @@ static void logv_error_with_prefix(const char *prefix, log("%s%s", prefix, log_last_error.c_str()); log_flush(); + log_make_debug = bak_log_make_debug; + if (log_error_atexit) log_error_atexit(); -- cgit v1.2.3 From ba2185ead89fdb6afeec6043ab18f2e045d80247 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 28 May 2019 16:43:25 +0200 Subject: Refactor hierarchy wand/wor handling Signed-off-by: Clifford Wolf --- kernel/rtlil.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 81ca93dce..8509670ff 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -601,6 +601,7 @@ struct RTLIL::SigChunk RTLIL::SigChunk &operator =(const RTLIL::SigChunk &other) = default; RTLIL::SigChunk extract(int offset, int length) const; + inline int size() const { return width; } bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; -- cgit v1.2.3 From 211d85cfcc1ae701bb9392347bcbb9750e3045b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Jun 2019 12:41:09 +0200 Subject: Fixes and cleanups in AST_TECALL handling Signed-off-by: Clifford Wolf --- kernel/log.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 9ce952cae..a7820950c 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -277,7 +277,7 @@ void log_file_warning(const std::string &filename, int lineno, va_list ap; va_start(ap, format); std::string prefix = stringf("%s:%d: Warning: ", - filename.c_str(), lineno); + filename.c_str(), lineno); logv_warning_with_prefix(prefix.c_str(), format, ap); va_end(ap); } @@ -287,9 +287,9 @@ void log_file_info(const std::string &filename, int lineno, { va_list ap; va_start(ap, format); - std::string prefix = stringf("%s:%d: Info: ", - filename.c_str(), lineno); - logv_warning_with_prefix(prefix.c_str(), format, ap); + std::string fmt = stringf("%s:%d: Info: %s", + filename.c_str(), lineno, format); + logv(fmt.c_str(), ap); va_end(ap); } -- cgit v1.2.3 From d097f423d1b30a3936388bb93a0a88fd3527ad49 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Mon, 10 Jun 2019 21:42:35 +0200 Subject: Refactor driver map generation - Implement iterators over the driver map that enumerate signals and cells within the cones of the signal --- kernel/satgen_algo.h | 158 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 kernel/satgen_algo.h (limited to 'kernel') diff --git a/kernel/satgen_algo.h b/kernel/satgen_algo.h new file mode 100644 index 000000000..483dfad5c --- /dev/null +++ b/kernel/satgen_algo.h @@ -0,0 +1,158 @@ +/* -*- c++ -*- + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef SATGEN_ALGO_H +#define SATGEN_ALGO_H + +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" +#include + +YOSYS_NAMESPACE_BEGIN + +struct DriverMap : public std::map>> { + RTLIL::Module *module; + SigMap sigmap; + + using map_t = std::map>>; + + struct DriverMapConeWireIterator : public std::iterator { + using set_iter_t = std::set::iterator; + + DriverMap *drvmap; + const RTLIL::SigBit *sig; + std::stack> dfs; + + DriverMapConeWireIterator(DriverMap *drvmap) : DriverMapConeWireIterator(drvmap, NULL) {} + + DriverMapConeWireIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {} + + inline const RTLIL::SigBit &operator*() const { return *sig; }; + inline bool operator!=(const DriverMapConeWireIterator &other) const { return sig != other.sig; } + inline bool operator==(const DriverMapConeWireIterator &other) const { return sig == other.sig; } + inline void operator++() + { + if (drvmap->count(*sig)) { + std::pair> &drv = drvmap->at(*sig); + dfs.push(std::make_pair(drv.second.begin(), drv.second.end())); + sig = &(*dfs.top().first); + } else { + while (1) { + auto &inputs_iter = dfs.top(); + + inputs_iter.first++; + if (inputs_iter.first != inputs_iter.second) { + sig = &(*inputs_iter.first); + return; + } else { + dfs.pop(); + if (dfs.empty()) { + sig = NULL; + return; + } + } + } + } + } + }; + + struct DriverMapConeWireIterable { + DriverMap *drvmap; + const RTLIL::SigBit *sig; + + DriverMapConeWireIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {} + + inline DriverMapConeWireIterator begin() { return DriverMapConeWireIterator(drvmap, sig); } + inline DriverMapConeWireIterator end() { return DriverMapConeWireIterator(drvmap); } + }; + + struct DriverMapConeCellIterator : public std::iterator { + DriverMap *drvmap; + const RTLIL::SigBit *sig; + + DriverMapConeWireIterator sig_iter; + + DriverMapConeCellIterator(DriverMap *drvmap) : DriverMapConeCellIterator(drvmap, NULL) {} + + DriverMapConeCellIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig), sig_iter(drvmap, sig) + { + if ((sig != NULL) && (!drvmap->count(*sig_iter))) { + ++(*this); + } + } + + inline RTLIL::Cell *operator*() const + { + std::pair> &drv = drvmap->at(*sig); + return drv.first; + }; + inline bool operator!=(const DriverMapConeCellIterator &other) const { return sig_iter != other.sig_iter; } + inline bool operator==(const DriverMapConeCellIterator &other) const { return sig_iter == other.sig_iter; } + inline void operator++() + { + do { + ++sig_iter; + if (sig_iter.sig == NULL) { + return; + } + } while (!drvmap->count(*sig_iter)); + } + }; + + struct DriverMapConeCellIterable { + DriverMap *drvmap; + const RTLIL::SigBit *sig; + + DriverMapConeCellIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {} + + inline DriverMapConeCellIterator begin() { return DriverMapConeCellIterator(drvmap, sig); } + inline DriverMapConeCellIterator end() { return DriverMapConeCellIterator(drvmap); } + }; + + DriverMap(RTLIL::Module *module) : module(module), sigmap(module) + { + CellTypes ct; + ct.setup_internals(); + ct.setup_stdcells(); + + for (auto &it : module->cells_) { + if (ct.cell_known(it.second->type)) { + std::set inputs, outputs; + for (auto &port : it.second->connections()) { + std::vector bits = sigmap(port.second).to_sigbit_vector(); + if (ct.cell_output(it.second->type, port.first)) + outputs.insert(bits.begin(), bits.end()); + else + inputs.insert(bits.begin(), bits.end()); + } + std::pair> drv(it.second, inputs); + for (auto &bit : outputs) + (*this)[bit] = drv; + } + } + } + + DriverMapConeWireIterable cone(const RTLIL::SigBit &sig) { return DriverMapConeWireIterable(this, &sig); } + DriverMapConeCellIterable cell_cone(const RTLIL::SigBit &sig) { return DriverMapConeCellIterable(this, &sig); } +}; + +YOSYS_NAMESPACE_END + +#endif -- cgit v1.2.3 From 9892df17efadd0eafe5217e812fb4cec2bfdf6e5 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Tue, 11 Jun 2019 11:47:13 +0200 Subject: Generate satgen instance instead of calling sat pass --- kernel/satgen_algo.h | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/satgen_algo.h b/kernel/satgen_algo.h index 483dfad5c..d475d7d64 100644 --- a/kernel/satgen_algo.h +++ b/kernel/satgen_algo.h @@ -100,7 +100,7 @@ struct DriverMap : public std::map> &drv = drvmap->at(*sig); + std::pair> &drv = drvmap->at(*sig_iter); return drv.first; }; inline bool operator!=(const DriverMapConeCellIterator &other) const { return sig_iter != other.sig_iter; } @@ -126,6 +126,48 @@ struct DriverMap : public std::map { + DriverMap *drvmap; + const RTLIL::SigBit *sig; + + DriverMapConeWireIterator sig_iter; + + DriverMapConeInputsIterator(DriverMap *drvmap) : DriverMapConeInputsIterator(drvmap, NULL) {} + + DriverMapConeInputsIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig), sig_iter(drvmap, sig) + { + if ((sig != NULL) && (drvmap->count(*sig_iter))) { + ++(*this); + } + } + + inline const RTLIL::SigBit& operator*() const + { + return *sig_iter; + }; + inline bool operator!=(const DriverMapConeInputsIterator &other) const { return sig_iter != other.sig_iter; } + inline bool operator==(const DriverMapConeInputsIterator &other) const { return sig_iter == other.sig_iter; } + inline void operator++() + { + do { + ++sig_iter; + if (sig_iter.sig == NULL) { + return; + } + } while (drvmap->count(*sig_iter)); + } + }; + + struct DriverMapConeInputsIterable { + DriverMap *drvmap; + const RTLIL::SigBit *sig; + + DriverMapConeInputsIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {} + + inline DriverMapConeInputsIterator begin() { return DriverMapConeInputsIterator(drvmap, sig); } + inline DriverMapConeInputsIterator end() { return DriverMapConeInputsIterator(drvmap); } + }; + DriverMap(RTLIL::Module *module) : module(module), sigmap(module) { CellTypes ct; @@ -150,6 +192,7 @@ struct DriverMap : public std::map Date: Wed, 12 Jun 2019 19:35:05 +0200 Subject: Rename satgen_algo.h -> algo.h, code cleanup and refactoring --- kernel/algo.h | 239 +++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/celltypes.h | 9 +- kernel/satgen_algo.h | 201 ------------------------------------------- 3 files changed, 243 insertions(+), 206 deletions(-) create mode 100644 kernel/algo.h delete mode 100644 kernel/satgen_algo.h (limited to 'kernel') diff --git a/kernel/algo.h b/kernel/algo.h new file mode 100644 index 000000000..6ab96a875 --- /dev/null +++ b/kernel/algo.h @@ -0,0 +1,239 @@ +/* -*- c++ -*- + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef SATGEN_ALGO_H +#define SATGEN_ALGO_H + +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" +#include + +YOSYS_NAMESPACE_BEGIN + +CellTypes comb_cells_filt() +{ + CellTypes ct; + + ct.setup_internals(); + ct.setup_stdcells(); + + return ct; +} + +struct Netlist { + RTLIL::Module *module; + SigMap sigmap; + dict sigbit_driver_map; + dict> cell_inputs_map; + + Netlist(RTLIL::Module *module) : module(module), sigmap(module) + { + CellTypes ct(module->design); + setup_netlist(module, ct); + } + + Netlist(RTLIL::Module *module, const CellTypes &ct) : module(module), sigmap(module) { setup_netlist(module, ct); } + + void setup_netlist(RTLIL::Module *module, const CellTypes &ct) + { + for (auto cell : module->cells()) { + if (ct.cell_known(cell->type)) { + std::set inputs, outputs; + for (auto &port : cell->connections()) { + std::vector bits = sigmap(port.second).to_sigbit_vector(); + if (ct.cell_output(cell->type, port.first)) + outputs.insert(bits.begin(), bits.end()); + else + inputs.insert(bits.begin(), bits.end()); + } + cell_inputs_map[cell] = inputs; + for (auto &bit : outputs) { + sigbit_driver_map[bit] = cell; + }; + } + } + } +}; + +namespace detail +{ +struct NetlistConeWireIter : public std::iterator { + using set_iter_t = std::set::iterator; + + const Netlist &net; + const RTLIL::SigBit *p_sig; + std::stack> dfs_path_stack; + std::set cells_visited; + + NetlistConeWireIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig) {} + + const RTLIL::SigBit &operator*() const { return *p_sig; }; + bool operator!=(const NetlistConeWireIter &other) const { return p_sig != other.p_sig; } + bool operator==(const NetlistConeWireIter &other) const { return p_sig == other.p_sig; } + + void next_sig_in_dag() + { + while (1) { + if (dfs_path_stack.empty()) { + p_sig = NULL; + return; + } + + auto &cell_inputs_iter = dfs_path_stack.top().first; + auto &cell_inputs_iter_guard = dfs_path_stack.top().second; + + cell_inputs_iter++; + if (cell_inputs_iter != cell_inputs_iter_guard) { + p_sig = &(*cell_inputs_iter); + return; + } else { + dfs_path_stack.pop(); + } + } + } + + NetlistConeWireIter &operator++() + { + if (net.sigbit_driver_map.count(*p_sig)) { + auto drv = net.sigbit_driver_map.at(*p_sig); + + if (!cells_visited.count(drv)) { + auto &inputs = net.cell_inputs_map.at(drv); + dfs_path_stack.push(std::make_pair(inputs.begin(), inputs.end())); + cells_visited.insert(drv); + p_sig = &(*dfs_path_stack.top().first); + } else { + next_sig_in_dag(); + } + } else { + next_sig_in_dag(); + } + return *this; + } +}; + +struct NetlistConeWireIterable { + const Netlist &net; + const RTLIL::SigBit *p_sig; + + NetlistConeWireIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {} + + NetlistConeWireIter begin() { return NetlistConeWireIter(net, p_sig); } + NetlistConeWireIter end() { return NetlistConeWireIter(net); } +}; + +struct NetlistConeCellIter : public std::iterator { + const Netlist &net; + const RTLIL::SigBit *p_sig; + + NetlistConeWireIter sig_iter; + + NetlistConeCellIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig) + { + if ((p_sig != NULL) && (!has_driver_cell(*sig_iter))) { + ++(*this); + } + } + + bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); } + + RTLIL::Cell *operator*() const { return net.sigbit_driver_map.at(*sig_iter); }; + + bool operator!=(const NetlistConeCellIter &other) const { return sig_iter != other.sig_iter; } + bool operator==(const NetlistConeCellIter &other) const { return sig_iter == other.sig_iter; } + NetlistConeCellIter &operator++() + { + while (true) { + ++sig_iter; + if (sig_iter.p_sig == NULL) { + return *this; + } + + if (has_driver_cell(*sig_iter)) { + auto cell = net.sigbit_driver_map.at(*sig_iter); + + if (!sig_iter.cells_visited.count(cell)) { + return *this; + } + } + }; + } +}; + +struct NetlistConeCellIterable { + const Netlist &net; + const RTLIL::SigBit *p_sig; + + NetlistConeCellIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {} + + NetlistConeCellIter begin() { return NetlistConeCellIter(net, p_sig); } + NetlistConeCellIter end() { return NetlistConeCellIter(net); } +}; + +struct NetlistConeInputsIter : public std::iterator { + const Netlist &net; + const RTLIL::SigBit *p_sig; + + NetlistConeWireIter sig_iter; + + bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); } + + NetlistConeInputsIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig) + { + if ((p_sig != NULL) && (has_driver_cell(*sig_iter))) { + ++(*this); + } + } + + const RTLIL::SigBit &operator*() const { return *sig_iter; }; + bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; } + bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; } + NetlistConeInputsIter &operator++() + { + do { + ++sig_iter; + if (sig_iter.p_sig == NULL) { + return *this; + } + } while (has_driver_cell(*sig_iter)); + + return *this; + } +}; + +struct NetlistConeInputsIterable { + const Netlist &net; + const RTLIL::SigBit *p_sig; + + NetlistConeInputsIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {} + + NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, p_sig); } + NetlistConeInputsIter end() { return NetlistConeInputsIter(net); } +}; +} // namespace detail + +detail::NetlistConeWireIterable cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeWireIterable(net, &sig); } + +// detail::NetlistConeInputsIterable cone_inputs(const RTLIL::SigBit &sig) { return NetlistConeInputsIterable(this, &sig); } +detail::NetlistConeCellIterable cell_cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeCellIterable(net, &sig); } + +YOSYS_NAMESPACE_END + +#endif diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 4e91eddda..758661c02 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -246,24 +246,24 @@ struct CellTypes cell_types.clear(); } - bool cell_known(RTLIL::IdString type) + bool cell_known(RTLIL::IdString type) const { return cell_types.count(type) != 0; } - bool cell_output(RTLIL::IdString type, RTLIL::IdString port) + bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.outputs.count(port) != 0; } - bool cell_input(RTLIL::IdString type, RTLIL::IdString port) + bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.inputs.count(port) != 0; } - bool cell_evaluable(RTLIL::IdString type) + bool cell_evaluable(RTLIL::IdString type) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.is_evaluable; @@ -482,4 +482,3 @@ extern CellTypes yosys_celltypes; YOSYS_NAMESPACE_END #endif - diff --git a/kernel/satgen_algo.h b/kernel/satgen_algo.h deleted file mode 100644 index d475d7d64..000000000 --- a/kernel/satgen_algo.h +++ /dev/null @@ -1,201 +0,0 @@ -/* -*- c++ -*- - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifndef SATGEN_ALGO_H -#define SATGEN_ALGO_H - -#include "kernel/celltypes.h" -#include "kernel/rtlil.h" -#include "kernel/sigtools.h" -#include - -YOSYS_NAMESPACE_BEGIN - -struct DriverMap : public std::map>> { - RTLIL::Module *module; - SigMap sigmap; - - using map_t = std::map>>; - - struct DriverMapConeWireIterator : public std::iterator { - using set_iter_t = std::set::iterator; - - DriverMap *drvmap; - const RTLIL::SigBit *sig; - std::stack> dfs; - - DriverMapConeWireIterator(DriverMap *drvmap) : DriverMapConeWireIterator(drvmap, NULL) {} - - DriverMapConeWireIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {} - - inline const RTLIL::SigBit &operator*() const { return *sig; }; - inline bool operator!=(const DriverMapConeWireIterator &other) const { return sig != other.sig; } - inline bool operator==(const DriverMapConeWireIterator &other) const { return sig == other.sig; } - inline void operator++() - { - if (drvmap->count(*sig)) { - std::pair> &drv = drvmap->at(*sig); - dfs.push(std::make_pair(drv.second.begin(), drv.second.end())); - sig = &(*dfs.top().first); - } else { - while (1) { - auto &inputs_iter = dfs.top(); - - inputs_iter.first++; - if (inputs_iter.first != inputs_iter.second) { - sig = &(*inputs_iter.first); - return; - } else { - dfs.pop(); - if (dfs.empty()) { - sig = NULL; - return; - } - } - } - } - } - }; - - struct DriverMapConeWireIterable { - DriverMap *drvmap; - const RTLIL::SigBit *sig; - - DriverMapConeWireIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {} - - inline DriverMapConeWireIterator begin() { return DriverMapConeWireIterator(drvmap, sig); } - inline DriverMapConeWireIterator end() { return DriverMapConeWireIterator(drvmap); } - }; - - struct DriverMapConeCellIterator : public std::iterator { - DriverMap *drvmap; - const RTLIL::SigBit *sig; - - DriverMapConeWireIterator sig_iter; - - DriverMapConeCellIterator(DriverMap *drvmap) : DriverMapConeCellIterator(drvmap, NULL) {} - - DriverMapConeCellIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig), sig_iter(drvmap, sig) - { - if ((sig != NULL) && (!drvmap->count(*sig_iter))) { - ++(*this); - } - } - - inline RTLIL::Cell *operator*() const - { - std::pair> &drv = drvmap->at(*sig_iter); - return drv.first; - }; - inline bool operator!=(const DriverMapConeCellIterator &other) const { return sig_iter != other.sig_iter; } - inline bool operator==(const DriverMapConeCellIterator &other) const { return sig_iter == other.sig_iter; } - inline void operator++() - { - do { - ++sig_iter; - if (sig_iter.sig == NULL) { - return; - } - } while (!drvmap->count(*sig_iter)); - } - }; - - struct DriverMapConeCellIterable { - DriverMap *drvmap; - const RTLIL::SigBit *sig; - - DriverMapConeCellIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {} - - inline DriverMapConeCellIterator begin() { return DriverMapConeCellIterator(drvmap, sig); } - inline DriverMapConeCellIterator end() { return DriverMapConeCellIterator(drvmap); } - }; - - struct DriverMapConeInputsIterator : public std::iterator { - DriverMap *drvmap; - const RTLIL::SigBit *sig; - - DriverMapConeWireIterator sig_iter; - - DriverMapConeInputsIterator(DriverMap *drvmap) : DriverMapConeInputsIterator(drvmap, NULL) {} - - DriverMapConeInputsIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig), sig_iter(drvmap, sig) - { - if ((sig != NULL) && (drvmap->count(*sig_iter))) { - ++(*this); - } - } - - inline const RTLIL::SigBit& operator*() const - { - return *sig_iter; - }; - inline bool operator!=(const DriverMapConeInputsIterator &other) const { return sig_iter != other.sig_iter; } - inline bool operator==(const DriverMapConeInputsIterator &other) const { return sig_iter == other.sig_iter; } - inline void operator++() - { - do { - ++sig_iter; - if (sig_iter.sig == NULL) { - return; - } - } while (drvmap->count(*sig_iter)); - } - }; - - struct DriverMapConeInputsIterable { - DriverMap *drvmap; - const RTLIL::SigBit *sig; - - DriverMapConeInputsIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {} - - inline DriverMapConeInputsIterator begin() { return DriverMapConeInputsIterator(drvmap, sig); } - inline DriverMapConeInputsIterator end() { return DriverMapConeInputsIterator(drvmap); } - }; - - DriverMap(RTLIL::Module *module) : module(module), sigmap(module) - { - CellTypes ct; - ct.setup_internals(); - ct.setup_stdcells(); - - for (auto &it : module->cells_) { - if (ct.cell_known(it.second->type)) { - std::set inputs, outputs; - for (auto &port : it.second->connections()) { - std::vector bits = sigmap(port.second).to_sigbit_vector(); - if (ct.cell_output(it.second->type, port.first)) - outputs.insert(bits.begin(), bits.end()); - else - inputs.insert(bits.begin(), bits.end()); - } - std::pair> drv(it.second, inputs); - for (auto &bit : outputs) - (*this)[bit] = drv; - } - } - } - - DriverMapConeWireIterable cone(const RTLIL::SigBit &sig) { return DriverMapConeWireIterable(this, &sig); } - DriverMapConeInputsIterable cone_inputs(const RTLIL::SigBit &sig) { return DriverMapConeInputsIterable(this, &sig); } - DriverMapConeCellIterable cell_cone(const RTLIL::SigBit &sig) { return DriverMapConeCellIterable(this, &sig); } -}; - -YOSYS_NAMESPACE_END - -#endif -- cgit v1.2.3 From 4912567cbff3c24e9cddea0b59287ec53321af7a Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Thu, 13 Jun 2019 15:42:45 +0200 Subject: Pass SigBit by value to Netlist algorithms --- kernel/algo.h | 149 +++++++++++++++++++++++++++++++++------------------------- 1 file changed, 84 insertions(+), 65 deletions(-) (limited to 'kernel') diff --git a/kernel/algo.h b/kernel/algo.h index 6ab96a875..05467c60a 100644 --- a/kernel/algo.h +++ b/kernel/algo.h @@ -74,25 +74,43 @@ struct Netlist { namespace detail { -struct NetlistConeWireIter : public std::iterator { +struct NetlistConeWireIter : public std::iterator { using set_iter_t = std::set::iterator; const Netlist &net; - const RTLIL::SigBit *p_sig; + RTLIL::SigBit sig; + bool sentinel; + std::stack> dfs_path_stack; std::set cells_visited; - NetlistConeWireIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig) {} + NetlistConeWireIter(const Netlist &net) : net(net), sentinel(true) {} + + NetlistConeWireIter(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig), sentinel(false) {} - const RTLIL::SigBit &operator*() const { return *p_sig; }; - bool operator!=(const NetlistConeWireIter &other) const { return p_sig != other.p_sig; } - bool operator==(const NetlistConeWireIter &other) const { return p_sig == other.p_sig; } + const RTLIL::SigBit &operator*() const { return sig; }; + bool operator!=(const NetlistConeWireIter &other) const + { + if (sentinel || other.sentinel) { + return sentinel != other.sentinel; + } else { + return sig != other.sig; + } + } + + bool operator==(const NetlistConeWireIter &other) const { + if (sentinel || other.sentinel) { + return sentinel == other.sentinel; + } else { + return sig == other.sig; + } + } void next_sig_in_dag() { while (1) { if (dfs_path_stack.empty()) { - p_sig = NULL; + sentinel = true; return; } @@ -101,7 +119,7 @@ struct NetlistConeWireIter : public std::iterator { +struct NetlistConeCellIter : public std::iterator { const Netlist &net; - const RTLIL::SigBit *p_sig; NetlistConeWireIter sig_iter; - NetlistConeCellIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig) + NetlistConeCellIter(const Netlist &net) : net(net), sig_iter(net) {} + + NetlistConeCellIter(const Netlist &net, RTLIL::SigBit sig) : net(net), sig_iter(net, sig) { - if ((p_sig != NULL) && (!has_driver_cell(*sig_iter))) { + if ((!sig_iter.sentinel) && (!has_driver_cell(*sig_iter))) { ++(*this); } } @@ -162,7 +181,7 @@ struct NetlistConeCellIter : public std::iterator { - const Netlist &net; - const RTLIL::SigBit *p_sig; - - NetlistConeWireIter sig_iter; - - bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); } - - NetlistConeInputsIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig) - { - if ((p_sig != NULL) && (has_driver_cell(*sig_iter))) { - ++(*this); - } - } - - const RTLIL::SigBit &operator*() const { return *sig_iter; }; - bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; } - bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; } - NetlistConeInputsIter &operator++() - { - do { - ++sig_iter; - if (sig_iter.p_sig == NULL) { - return *this; - } - } while (has_driver_cell(*sig_iter)); - - return *this; - } -}; - -struct NetlistConeInputsIterable { - const Netlist &net; - const RTLIL::SigBit *p_sig; - - NetlistConeInputsIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {} - - NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, p_sig); } - NetlistConeInputsIter end() { return NetlistConeInputsIter(net); } -}; +// struct NetlistConeInputsIter : public std::iterator { +// const Netlist &net; +// RTLIL::SigBit sig; + +// NetlistConeWireIter sig_iter; + +// bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); } + +// NetlistConeInputsIter(const Netlist &net, RTLIL::SigBit sig = NULL) : net(net), sig(sig), sig_iter(net, sig) +// { +// if ((sig != NULL) && (has_driver_cell(sig_iter))) { +// ++(*this); +// } +// } + +// const RTLIL::SigBit &operator*() const { return sig_iter; }; +// bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; } +// bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; } +// NetlistConeInputsIter &operator++() +// { +// do { +// ++sig_iter; +// if (sig_iter->empty()) { +// return *this; +// } +// } while (has_driver_cell(sig_iter)); + +// return *this; +// } +// }; + +// struct NetlistConeInputsIterable { +// const Netlist &net; +// RTLIL::SigBit sig; + +// NetlistConeInputsIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {} + +// NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, sig); } +// NetlistConeInputsIter end() { return NetlistConeInputsIter(net); } +// }; } // namespace detail -detail::NetlistConeWireIterable cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeWireIterable(net, &sig); } +detail::NetlistConeWireIterable cone(const Netlist &net, RTLIL::SigBit sig) { return detail::NetlistConeWireIterable(net, net.sigmap(sig)); } -// detail::NetlistConeInputsIterable cone_inputs(const RTLIL::SigBit &sig) { return NetlistConeInputsIterable(this, &sig); } -detail::NetlistConeCellIterable cell_cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeCellIterable(net, &sig); } +// detail::NetlistConeInputsIterable cone_inputs(RTLIL::SigBit sig) { return NetlistConeInputsIterable(this, &sig); } +detail::NetlistConeCellIterable cell_cone(const Netlist &net, RTLIL::SigBit sig) { return detail::NetlistConeCellIterable(net, net.sigmap(sig)); } YOSYS_NAMESPACE_END -- cgit v1.2.3 From 8665f48879526f8f3ed79629f28a8686ed78a8ad Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Thu, 13 Jun 2019 19:35:37 +0200 Subject: Implement disconnection of constant register bits --- kernel/algo.h | 117 ++++++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 85 insertions(+), 32 deletions(-) (limited to 'kernel') diff --git a/kernel/algo.h b/kernel/algo.h index 05467c60a..9626c780e 100644 --- a/kernel/algo.h +++ b/kernel/algo.h @@ -40,16 +40,39 @@ CellTypes comb_cells_filt() struct Netlist { RTLIL::Module *module; SigMap sigmap; + CellTypes ct; dict sigbit_driver_map; dict> cell_inputs_map; - Netlist(RTLIL::Module *module) : module(module), sigmap(module) + Netlist(RTLIL::Module *module) : module(module), sigmap(module), ct(module->design) { setup_netlist(module, ct); } + + Netlist(RTLIL::Module *module, const CellTypes &ct) : module(module), sigmap(module), ct(ct) { setup_netlist(module, ct); } + + RTLIL::Cell *driver_cell(RTLIL::SigBit sig) const { - CellTypes ct(module->design); - setup_netlist(module, ct); + sig = sigmap(sig); + if (!sigbit_driver_map.count(sig)) { + return NULL; + } + + return sigbit_driver_map.at(sig); } - Netlist(RTLIL::Module *module, const CellTypes &ct) : module(module), sigmap(module) { setup_netlist(module, ct); } + RTLIL::SigBit& driver_port(RTLIL::SigBit sig) + { + RTLIL::Cell *cell = driver_cell(sig); + + for (auto &port : cell->connections_) { + if (ct.cell_output(cell->type, port.first)) { + RTLIL::SigSpec port_sig = sigmap(port.second); + for (int i = 0; i < GetSize(port_sig); i++) { + if (port_sig[i] == sig) { + return port.second[i]; + } + } + } + } + } void setup_netlist(RTLIL::Module *module, const CellTypes &ct) { @@ -80,13 +103,17 @@ struct NetlistConeWireIter : public std::iterator> dfs_path_stack; std::set cells_visited; - NetlistConeWireIter(const Netlist &net) : net(net), sentinel(true) {} + NetlistConeWireIter(const Netlist &net) : net(net), sentinel(true), cell_filter(NULL) {} - NetlistConeWireIter(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig), sentinel(false) {} + NetlistConeWireIter(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) + : net(net), sig(sig), sentinel(false), cell_filter(cell_filter) + { + } const RTLIL::SigBit &operator*() const { return sig; }; bool operator!=(const NetlistConeWireIter &other) const @@ -98,7 +125,8 @@ struct NetlistConeWireIter : public std::iteratorcell_known(cell->type))) { + next_sig_in_dag(); + return *this; + } + + auto &inputs = net.cell_inputs_map.at(cell); + dfs_path_stack.push(std::make_pair(inputs.begin(), inputs.end())); + cells_visited.insert(cell); + sig = (*dfs_path_stack.top().first); return *this; } }; @@ -150,10 +185,13 @@ struct NetlistConeWireIter : public std::iteratorcell_known(cell->type))) { + continue; + } + + if (!sig_iter.cells_visited.count(cell)) { + return *this; + } + } } }; struct NetlistConeCellIterable { const Netlist &net; RTLIL::SigBit sig; + CellTypes *cell_filter; - NetlistConeCellIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {} + NetlistConeCellIterable(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) : net(net), sig(sig), cell_filter(cell_filter) + { + } - NetlistConeCellIter begin() { return NetlistConeCellIter(net, sig); } + NetlistConeCellIter begin() { return NetlistConeCellIter(net, sig, cell_filter); } NetlistConeCellIter end() { return NetlistConeCellIter(net); } }; @@ -248,10 +295,16 @@ struct NetlistConeCellIterable { // }; } // namespace detail -detail::NetlistConeWireIterable cone(const Netlist &net, RTLIL::SigBit sig) { return detail::NetlistConeWireIterable(net, net.sigmap(sig)); } +detail::NetlistConeWireIterable cone(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) +{ + return detail::NetlistConeWireIterable(net, net.sigmap(sig), cell_filter = cell_filter); +} // detail::NetlistConeInputsIterable cone_inputs(RTLIL::SigBit sig) { return NetlistConeInputsIterable(this, &sig); } -detail::NetlistConeCellIterable cell_cone(const Netlist &net, RTLIL::SigBit sig) { return detail::NetlistConeCellIterable(net, net.sigmap(sig)); } +detail::NetlistConeCellIterable cell_cone(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) +{ + return detail::NetlistConeCellIterable(net, net.sigmap(sig), cell_filter); +} YOSYS_NAMESPACE_END -- cgit v1.2.3 From d39a5a77a9ec58ea97af91c961b02b5a55deaaa7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Jun 2019 13:13:48 -0700 Subject: Add ConstEvalAig specialised for AIGs --- kernel/consteval.h | 157 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 154373a8d..59e3ef20f 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -390,6 +390,163 @@ struct ConstEval } }; +struct ConstEvalAig +{ + RTLIL::Module *module; + //SigMap assign_map; + SigMap values_map; + //SigPool stop_signals; + SigSet sig2driver; + std::set busy; + std::vector stack; + //RTLIL::State defaultval; + + ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/ + { + CellTypes ct; + ct.setup_internals(); + ct.setup_stdcells(); + + for (auto &it : module->cells_) { + if (!ct.cell_known(it.second->type)) + continue; + for (auto &it2 : it.second->connections()) + if (ct.cell_output(it.second->type, it2.first)) + sig2driver.insert(/*assign_map*/(it2.second), it.second); + } + } + + void clear() + { + values_map.clear(); + //stop_signals.clear(); + } + + void push() + { + stack.push_back(values_map); + } + + void pop() + { + values_map.swap(stack.back()); + stack.pop_back(); + } + + void set(RTLIL::SigSpec sig, RTLIL::Const value) + { + //assign_map.apply(sig); +#ifndef NDEBUG + RTLIL::SigSpec current_val = values_map(sig); + for (int i = 0; i < GetSize(current_val); i++) + log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]); +#endif + values_map.add(sig, RTLIL::SigSpec(value)); + } + + //void stop(RTLIL::SigSpec sig) + //{ + // assign_map.apply(sig); + // stop_signals.add(sig); + //} + + bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef) + { + RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y"))); + if (sig_y.is_fully_const()) + return true; + + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) + return false; + + RTLIL::Const eval_ret; + if (cell->type == "$_NOT_") { + if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1; + else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0; + } + else if (cell->type == "$_AND_") { + if (sig_a == RTLIL::S0) { + eval_ret = RTLIL::S0; + goto eval_end; + } + + { + RTLIL::SigSpec sig_b = cell->getPort("\\B"); + if (sig_b.size() > 0 && !eval(sig_b, undef, cell)) + return false; + if (sig_b == RTLIL::S0) { + eval_ret = RTLIL::S0; + goto eval_end; + } + + if (sig_a != RTLIL::State::S1 || sig_b != RTLIL::State::S1) { + eval_ret = RTLIL::State::Sx; + goto eval_end; + } + + eval_ret = RTLIL::State::S1; + } + } + else log_abort(); + + +eval_end: + set(sig_y, eval_ret); + return true; + } + + bool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL) + { + //assign_map.apply(sig); + values_map.apply(sig); + + if (sig.is_fully_const()) + return true; + + //if (stop_signals.check_any(sig)) { + // undef = stop_signals.extract(sig); + // return false; + //} + + if (busy_cell) { + if (busy.count(busy_cell) > 0) { + undef = sig; + return false; + } + busy.insert(busy_cell); + } + + std::set driver_cells; + sig2driver.find(sig, driver_cells); + for (auto cell : driver_cells) { + if (!eval(cell, undef)) { + if (busy_cell) + busy.erase(busy_cell); + return false; + } + } + + if (busy_cell) + busy.erase(busy_cell); + + values_map.apply(sig); + if (sig.is_fully_const()) + return true; + + for (auto &c : sig.chunks()) + if (c.wire != NULL) + undef.append(c); + return false; + } + + bool eval(RTLIL::SigSpec &sig) + { + RTLIL::SigSpec undef; + return eval(sig, undef); + } +}; + YOSYS_NAMESPACE_END #endif -- cgit v1.2.3 From 63e2f83632a760d64e64f8e03529de941301125e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Jun 2019 13:29:03 -0700 Subject: More slimming --- kernel/consteval.h | 70 +++++++++++++++++++++++++++--------------------------- 1 file changed, 35 insertions(+), 35 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 59e3ef20f..e0131b233 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -397,8 +397,8 @@ struct ConstEvalAig SigMap values_map; //SigPool stop_signals; SigSet sig2driver; - std::set busy; - std::vector stack; + //std::set busy; + //std::vector stack; //RTLIL::State defaultval; ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/ @@ -422,16 +422,16 @@ struct ConstEvalAig //stop_signals.clear(); } - void push() - { - stack.push_back(values_map); - } + //void push() + //{ + // stack.push_back(values_map); + //} - void pop() - { - values_map.swap(stack.back()); - stack.pop_back(); - } + //void pop() + //{ + // values_map.swap(stack.back()); + // stack.pop_back(); + //} void set(RTLIL::SigSpec sig, RTLIL::Const value) { @@ -450,14 +450,14 @@ struct ConstEvalAig // stop_signals.add(sig); //} - bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef) + bool eval(RTLIL::Cell *cell /*, RTLIL::SigSpec &undef*/) { RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y"))); if (sig_y.is_fully_const()) return true; RTLIL::SigSpec sig_a = cell->getPort("\\A"); - if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) + if (sig_a.size() > 0 && !eval(sig_a /*, undef, cell*/)) return false; RTLIL::Const eval_ret; @@ -473,7 +473,7 @@ struct ConstEvalAig { RTLIL::SigSpec sig_b = cell->getPort("\\B"); - if (sig_b.size() > 0 && !eval(sig_b, undef, cell)) + if (sig_b.size() > 0 && !eval(sig_b /*, undef, cell*/)) return false; if (sig_b == RTLIL::S0) { eval_ret = RTLIL::S0; @@ -496,7 +496,7 @@ eval_end: return true; } - bool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL) + bool eval(RTLIL::SigSpec &sig /*, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL*/) { //assign_map.apply(sig); values_map.apply(sig); @@ -509,42 +509,42 @@ eval_end: // return false; //} - if (busy_cell) { - if (busy.count(busy_cell) > 0) { - undef = sig; - return false; - } - busy.insert(busy_cell); - } + //if (busy_cell) { + // if (busy.count(busy_cell) > 0) { + // undef = sig; + // return false; + // } + // busy.insert(busy_cell); + //} std::set driver_cells; sig2driver.find(sig, driver_cells); for (auto cell : driver_cells) { - if (!eval(cell, undef)) { - if (busy_cell) - busy.erase(busy_cell); + if (!eval(cell /*, undef*/)) { + //if (busy_cell) + // busy.erase(busy_cell); return false; } } - if (busy_cell) - busy.erase(busy_cell); + //if (busy_cell) + // busy.erase(busy_cell); values_map.apply(sig); if (sig.is_fully_const()) return true; - for (auto &c : sig.chunks()) - if (c.wire != NULL) - undef.append(c); + //for (auto &c : sig.chunks()) + // if (c.wire != NULL) + // undef.append(c); return false; } - bool eval(RTLIL::SigSpec &sig) - { - RTLIL::SigSpec undef; - return eval(sig, undef); - } + //bool eval(RTLIL::SigSpec &sig) + //{ + // RTLIL::SigSpec undef; + // return eval(sig, undef); + //} }; YOSYS_NAMESPACE_END -- cgit v1.2.3 From d09d4e0706e806d53b3b83986f49c1d59435d2ed Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Jun 2019 16:28:11 -0700 Subject: Move ConstEvalAig to aigerparse.cc --- kernel/consteval.h | 157 ----------------------------------------------------- 1 file changed, 157 deletions(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index e0131b233..154373a8d 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -390,163 +390,6 @@ struct ConstEval } }; -struct ConstEvalAig -{ - RTLIL::Module *module; - //SigMap assign_map; - SigMap values_map; - //SigPool stop_signals; - SigSet sig2driver; - //std::set busy; - //std::vector stack; - //RTLIL::State defaultval; - - ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/ - { - CellTypes ct; - ct.setup_internals(); - ct.setup_stdcells(); - - for (auto &it : module->cells_) { - if (!ct.cell_known(it.second->type)) - continue; - for (auto &it2 : it.second->connections()) - if (ct.cell_output(it.second->type, it2.first)) - sig2driver.insert(/*assign_map*/(it2.second), it.second); - } - } - - void clear() - { - values_map.clear(); - //stop_signals.clear(); - } - - //void push() - //{ - // stack.push_back(values_map); - //} - - //void pop() - //{ - // values_map.swap(stack.back()); - // stack.pop_back(); - //} - - void set(RTLIL::SigSpec sig, RTLIL::Const value) - { - //assign_map.apply(sig); -#ifndef NDEBUG - RTLIL::SigSpec current_val = values_map(sig); - for (int i = 0; i < GetSize(current_val); i++) - log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]); -#endif - values_map.add(sig, RTLIL::SigSpec(value)); - } - - //void stop(RTLIL::SigSpec sig) - //{ - // assign_map.apply(sig); - // stop_signals.add(sig); - //} - - bool eval(RTLIL::Cell *cell /*, RTLIL::SigSpec &undef*/) - { - RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y"))); - if (sig_y.is_fully_const()) - return true; - - RTLIL::SigSpec sig_a = cell->getPort("\\A"); - if (sig_a.size() > 0 && !eval(sig_a /*, undef, cell*/)) - return false; - - RTLIL::Const eval_ret; - if (cell->type == "$_NOT_") { - if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1; - else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0; - } - else if (cell->type == "$_AND_") { - if (sig_a == RTLIL::S0) { - eval_ret = RTLIL::S0; - goto eval_end; - } - - { - RTLIL::SigSpec sig_b = cell->getPort("\\B"); - if (sig_b.size() > 0 && !eval(sig_b /*, undef, cell*/)) - return false; - if (sig_b == RTLIL::S0) { - eval_ret = RTLIL::S0; - goto eval_end; - } - - if (sig_a != RTLIL::State::S1 || sig_b != RTLIL::State::S1) { - eval_ret = RTLIL::State::Sx; - goto eval_end; - } - - eval_ret = RTLIL::State::S1; - } - } - else log_abort(); - - -eval_end: - set(sig_y, eval_ret); - return true; - } - - bool eval(RTLIL::SigSpec &sig /*, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL*/) - { - //assign_map.apply(sig); - values_map.apply(sig); - - if (sig.is_fully_const()) - return true; - - //if (stop_signals.check_any(sig)) { - // undef = stop_signals.extract(sig); - // return false; - //} - - //if (busy_cell) { - // if (busy.count(busy_cell) > 0) { - // undef = sig; - // return false; - // } - // busy.insert(busy_cell); - //} - - std::set driver_cells; - sig2driver.find(sig, driver_cells); - for (auto cell : driver_cells) { - if (!eval(cell /*, undef*/)) { - //if (busy_cell) - // busy.erase(busy_cell); - return false; - } - } - - //if (busy_cell) - // busy.erase(busy_cell); - - values_map.apply(sig); - if (sig.is_fully_const()) - return true; - - //for (auto &c : sig.chunks()) - // if (c.wire != NULL) - // undef.append(c); - return false; - } - - //bool eval(RTLIL::SigSpec &sig) - //{ - // RTLIL::SigSpec undef; - // return eval(sig, undef); - //} -}; - YOSYS_NAMESPACE_END #endif -- cgit v1.2.3 From 53695e6729e8ae603be7e7cd9bc8b29758d61a11 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Fri, 14 Jun 2019 11:39:24 +0200 Subject: Prepare for situation when port of the signal cannot be found --- kernel/algo.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/algo.h b/kernel/algo.h index 9626c780e..f029ad6ab 100644 --- a/kernel/algo.h +++ b/kernel/algo.h @@ -58,10 +58,14 @@ struct Netlist { return sigbit_driver_map.at(sig); } - RTLIL::SigBit& driver_port(RTLIL::SigBit sig) + RTLIL::SigSpec driver_port(RTLIL::SigBit sig) { RTLIL::Cell *cell = driver_cell(sig); + if (!cell) { + return RTLIL::SigSpec(); + } + for (auto &port : cell->connections_) { if (ct.cell_output(cell->type, port.first)) { RTLIL::SigSpec port_sig = sigmap(port.second); @@ -72,6 +76,8 @@ struct Netlist { } } } + + return RTLIL::SigSpec(); } void setup_netlist(RTLIL::Module *module, const CellTypes &ct) -- cgit v1.2.3 From 8451cbea896d2b441b5c78eb2813790616d10b84 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Fri, 14 Jun 2019 12:14:02 +0200 Subject: Move netlist helper module to passes/opt for the time being --- kernel/algo.h | 317 ---------------------------------------------------------- 1 file changed, 317 deletions(-) delete mode 100644 kernel/algo.h (limited to 'kernel') diff --git a/kernel/algo.h b/kernel/algo.h deleted file mode 100644 index f029ad6ab..000000000 --- a/kernel/algo.h +++ /dev/null @@ -1,317 +0,0 @@ -/* -*- c++ -*- - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifndef SATGEN_ALGO_H -#define SATGEN_ALGO_H - -#include "kernel/celltypes.h" -#include "kernel/rtlil.h" -#include "kernel/sigtools.h" -#include - -YOSYS_NAMESPACE_BEGIN - -CellTypes comb_cells_filt() -{ - CellTypes ct; - - ct.setup_internals(); - ct.setup_stdcells(); - - return ct; -} - -struct Netlist { - RTLIL::Module *module; - SigMap sigmap; - CellTypes ct; - dict sigbit_driver_map; - dict> cell_inputs_map; - - Netlist(RTLIL::Module *module) : module(module), sigmap(module), ct(module->design) { setup_netlist(module, ct); } - - Netlist(RTLIL::Module *module, const CellTypes &ct) : module(module), sigmap(module), ct(ct) { setup_netlist(module, ct); } - - RTLIL::Cell *driver_cell(RTLIL::SigBit sig) const - { - sig = sigmap(sig); - if (!sigbit_driver_map.count(sig)) { - return NULL; - } - - return sigbit_driver_map.at(sig); - } - - RTLIL::SigSpec driver_port(RTLIL::SigBit sig) - { - RTLIL::Cell *cell = driver_cell(sig); - - if (!cell) { - return RTLIL::SigSpec(); - } - - for (auto &port : cell->connections_) { - if (ct.cell_output(cell->type, port.first)) { - RTLIL::SigSpec port_sig = sigmap(port.second); - for (int i = 0; i < GetSize(port_sig); i++) { - if (port_sig[i] == sig) { - return port.second[i]; - } - } - } - } - - return RTLIL::SigSpec(); - } - - void setup_netlist(RTLIL::Module *module, const CellTypes &ct) - { - for (auto cell : module->cells()) { - if (ct.cell_known(cell->type)) { - std::set inputs, outputs; - for (auto &port : cell->connections()) { - std::vector bits = sigmap(port.second).to_sigbit_vector(); - if (ct.cell_output(cell->type, port.first)) - outputs.insert(bits.begin(), bits.end()); - else - inputs.insert(bits.begin(), bits.end()); - } - cell_inputs_map[cell] = inputs; - for (auto &bit : outputs) { - sigbit_driver_map[bit] = cell; - }; - } - } - } -}; - -namespace detail -{ -struct NetlistConeWireIter : public std::iterator { - using set_iter_t = std::set::iterator; - - const Netlist &net; - RTLIL::SigBit sig; - bool sentinel; - CellTypes *cell_filter; - - std::stack> dfs_path_stack; - std::set cells_visited; - - NetlistConeWireIter(const Netlist &net) : net(net), sentinel(true), cell_filter(NULL) {} - - NetlistConeWireIter(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) - : net(net), sig(sig), sentinel(false), cell_filter(cell_filter) - { - } - - const RTLIL::SigBit &operator*() const { return sig; }; - bool operator!=(const NetlistConeWireIter &other) const - { - if (sentinel || other.sentinel) { - return sentinel != other.sentinel; - } else { - return sig != other.sig; - } - } - - bool operator==(const NetlistConeWireIter &other) const - { - if (sentinel || other.sentinel) { - return sentinel == other.sentinel; - } else { - return sig == other.sig; - } - } - - void next_sig_in_dag() - { - while (1) { - if (dfs_path_stack.empty()) { - sentinel = true; - return; - } - - auto &cell_inputs_iter = dfs_path_stack.top().first; - auto &cell_inputs_iter_guard = dfs_path_stack.top().second; - - cell_inputs_iter++; - if (cell_inputs_iter != cell_inputs_iter_guard) { - sig = *cell_inputs_iter; - return; - } else { - dfs_path_stack.pop(); - } - } - } - - NetlistConeWireIter &operator++() - { - RTLIL::Cell *cell = net.driver_cell(sig); - - if (!cell) { - next_sig_in_dag(); - return *this; - } - - if (cells_visited.count(cell)) { - next_sig_in_dag(); - return *this; - } - - if ((cell_filter) && (!cell_filter->cell_known(cell->type))) { - next_sig_in_dag(); - return *this; - } - - auto &inputs = net.cell_inputs_map.at(cell); - dfs_path_stack.push(std::make_pair(inputs.begin(), inputs.end())); - cells_visited.insert(cell); - sig = (*dfs_path_stack.top().first); - return *this; - } -}; - -struct NetlistConeWireIterable { - const Netlist &net; - RTLIL::SigBit sig; - CellTypes *cell_filter; - - NetlistConeWireIterable(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) : net(net), sig(sig), cell_filter(cell_filter) - { - } - - NetlistConeWireIter begin() { return NetlistConeWireIter(net, sig, cell_filter); } - NetlistConeWireIter end() { return NetlistConeWireIter(net); } -}; - -struct NetlistConeCellIter : public std::iterator { - const Netlist &net; - - NetlistConeWireIter sig_iter; - - NetlistConeCellIter(const Netlist &net) : net(net), sig_iter(net) {} - - NetlistConeCellIter(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) : net(net), sig_iter(net, sig, cell_filter) - { - if ((!sig_iter.sentinel) && (!has_driver_cell(*sig_iter))) { - ++(*this); - } - } - - bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); } - - RTLIL::Cell *operator*() const { return net.sigbit_driver_map.at(*sig_iter); }; - - bool operator!=(const NetlistConeCellIter &other) const { return sig_iter != other.sig_iter; } - bool operator==(const NetlistConeCellIter &other) const { return sig_iter == other.sig_iter; } - NetlistConeCellIter &operator++() - { - while (true) { - ++sig_iter; - if (sig_iter.sentinel) { - return *this; - } - - RTLIL::Cell* cell = net.driver_cell(*sig_iter); - - if (!cell) { - continue; - } - - if ((sig_iter.cell_filter) && (!sig_iter.cell_filter->cell_known(cell->type))) { - continue; - } - - if (!sig_iter.cells_visited.count(cell)) { - return *this; - } - } - } -}; - -struct NetlistConeCellIterable { - const Netlist &net; - RTLIL::SigBit sig; - CellTypes *cell_filter; - - NetlistConeCellIterable(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) : net(net), sig(sig), cell_filter(cell_filter) - { - } - - NetlistConeCellIter begin() { return NetlistConeCellIter(net, sig, cell_filter); } - NetlistConeCellIter end() { return NetlistConeCellIter(net); } -}; - -// struct NetlistConeInputsIter : public std::iterator { -// const Netlist &net; -// RTLIL::SigBit sig; - -// NetlistConeWireIter sig_iter; - -// bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); } - -// NetlistConeInputsIter(const Netlist &net, RTLIL::SigBit sig = NULL) : net(net), sig(sig), sig_iter(net, sig) -// { -// if ((sig != NULL) && (has_driver_cell(sig_iter))) { -// ++(*this); -// } -// } - -// const RTLIL::SigBit &operator*() const { return sig_iter; }; -// bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; } -// bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; } -// NetlistConeInputsIter &operator++() -// { -// do { -// ++sig_iter; -// if (sig_iter->empty()) { -// return *this; -// } -// } while (has_driver_cell(sig_iter)); - -// return *this; -// } -// }; - -// struct NetlistConeInputsIterable { -// const Netlist &net; -// RTLIL::SigBit sig; - -// NetlistConeInputsIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {} - -// NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, sig); } -// NetlistConeInputsIter end() { return NetlistConeInputsIter(net); } -// }; -} // namespace detail - -detail::NetlistConeWireIterable cone(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) -{ - return detail::NetlistConeWireIterable(net, net.sigmap(sig), cell_filter = cell_filter); -} - -// detail::NetlistConeInputsIterable cone_inputs(RTLIL::SigBit sig) { return NetlistConeInputsIterable(this, &sig); } -detail::NetlistConeCellIterable cell_cone(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) -{ - return detail::NetlistConeCellIterable(net, net.sigmap(sig), cell_filter); -} - -YOSYS_NAMESPACE_END - -#endif -- cgit v1.2.3 From a48b5bfaa5c55bfe4e5ff859b453ee00a1dd68c6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 14 Jun 2019 12:25:06 -0700 Subject: Further cleanup based on @daveshah1 --- kernel/rtlil.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index d3ad57d72..f4fcf5dcf 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -276,6 +276,12 @@ namespace RTLIL return std::string(c_str() + pos, len); } + bool begins_with(const char* prefix) const { + size_t len = strlen(prefix); + if (size() < len) return false; + return substr(0, len) == prefix; + } + bool ends_with(const char* suffix) const { size_t len = strlen(suffix); if (size() < len) return false; -- cgit v1.2.3 From b45d06d7a334c4b18e44793b33aaffcaf1f04b21 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 17 Jun 2019 12:54:24 -0700 Subject: Fix leak removing cells during ABC integration; also preserve attr --- kernel/rtlil.cc | 12 ++++++++++-- kernel/rtlil.h | 1 + 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 790ba52a3..f732b56b0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1565,13 +1565,21 @@ void RTLIL::Module::remove(const pool &wires) void RTLIL::Module::remove(RTLIL::Cell *cell) { + auto it = cells_.find(cell->name); + log_assert(it != cells_.end()); + remove(it); +} + +dict::iterator RTLIL::Module::remove(dict::iterator it) +{ + RTLIL::Cell *cell = it->second; while (!cell->connections_.empty()) cell->unsetPort(cell->connections_.begin()->first); - log_assert(cells_.count(cell->name) != 0); log_assert(refcount_cells_ == 0); - cells_.erase(cell->name); + it = cells_.erase(it); delete cell; + return it; } void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f4fcf5dcf..4a0f8b4f8 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1040,6 +1040,7 @@ public: // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const pool &wires); void remove(RTLIL::Cell *cell); + dict::iterator remove(dict::iterator it); void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); -- cgit v1.2.3 From 468c41d997477aa6c67a8b97bc4d9dcff185b815 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Mon, 17 Jun 2019 14:45:11 -0700 Subject: Support ~ for home directory This is tested on Linux only v2: Wrap functioanlity in ifndef _WIN32 (eddiehung) Find '~/' instead of '~' (cliffordwolf) Signed-off-by: Ben Widawsky --- kernel/yosys.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 377572fc2..94d6d675f 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -651,6 +651,10 @@ void rewrite_filename(std::string &filename) filename = filename.substr(1, GetSize(filename)-2); if (filename.substr(0, 2) == "+/") filename = proc_share_dirname() + filename.substr(2); +#ifndef _WIN32 + if (filename.substr(0, 2) == "~/") + filename = filename.replace(0, 1, getenv("HOME")); +#endif } #ifdef YOSYS_ENABLE_TCL -- cgit v1.2.3 From df6576edc83817b692d2096e806bd822f3fda430 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 19 Jun 2019 05:22:13 +0000 Subject: In RTLIL::Module::check(), check process invariants. --- kernel/rtlil.cc | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 790ba52a3..a09f4a0d1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1381,7 +1381,34 @@ void RTLIL::Module::check() for (auto &it : processes) { log_assert(it.first == it.second->name); log_assert(!it.first.empty()); - // FIXME: More checks here.. + log_assert(it.second->root_case.compare.empty()); + std::vector all_cases = {&it.second->root_case}; + for (size_t i = 0; i < all_cases.size(); i++) { + for (auto &switch_it : all_cases[i]->switches) { + for (auto &case_it : switch_it->cases) { + for (auto &compare_it : case_it->compare) { + log_assert(switch_it->signal.size() == compare_it.size()); + } + all_cases.push_back(case_it); + } + } + } + for (auto &sync_it : it.second->syncs) { + switch (sync_it->type) { + case SyncType::ST0: + case SyncType::ST1: + case SyncType::STp: + case SyncType::STn: + case SyncType::STe: + log_assert(!sync_it->signal.empty()); + break; + case SyncType::STa: + case SyncType::STg: + case SyncType::STi: + log_assert(sync_it->signal.empty()); + break; + } + } } for (auto &it : connections_) { -- cgit v1.2.3 From 8767ec3fbdc0986854107de9cf178953ef09f1db Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Thu, 20 Jun 2019 10:27:59 -0700 Subject: Add a few more filename rewrites This now allows a full pipeline to work, something such as: yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v" Otherwise, you will get something along the lines of: ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory Signed-off-by: Ben Widawsky --- kernel/register.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 71eb6b187..26da96b95 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -545,6 +545,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vectoropen(filename.c_str(), std::ofstream::trunc); yosys_output_files.insert(filename); -- cgit v1.2.3 From fb30fcb7c582406f627ebb15833791411091f738 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 27 Jun 2019 15:03:21 -0700 Subject: Undo iterator based Module::remove() for cells, as containers will not invalidate --- kernel/rtlil.cc | 12 ++---------- kernel/rtlil.h | 1 - 2 files changed, 2 insertions(+), 11 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 502b45cfd..a09f4a0d1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1592,21 +1592,13 @@ void RTLIL::Module::remove(const pool &wires) void RTLIL::Module::remove(RTLIL::Cell *cell) { - auto it = cells_.find(cell->name); - log_assert(it != cells_.end()); - remove(it); -} - -dict::iterator RTLIL::Module::remove(dict::iterator it) -{ - RTLIL::Cell *cell = it->second; while (!cell->connections_.empty()) cell->unsetPort(cell->connections_.begin()->first); + log_assert(cells_.count(cell->name) != 0); log_assert(refcount_cells_ == 0); - it = cells_.erase(it); + cells_.erase(cell->name); delete cell; - return it; } void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4a0f8b4f8..f4fcf5dcf 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1040,7 +1040,6 @@ public: // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const pool &wires); void remove(RTLIL::Cell *cell); - dict::iterator remove(dict::iterator it); void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); -- cgit v1.2.3 From 06971385fa5f47498c138f3f36a203b01c7cbb42 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 28 Jun 2019 13:36:33 -0700 Subject: Support ability for "script -select" to take commands from wires --- kernel/yosys.cc | 47 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 8 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 94d6d675f..7d4948881 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1254,24 +1254,55 @@ struct HistoryPass : public Pass { #endif struct ScriptCmdPass : public Pass { - ScriptCmdPass() : Pass("script", "execute commands from script file") { } + ScriptCmdPass() : Pass("script", "execute commands from file or wire") { } void help() YS_OVERRIDE { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" script [:]\n"); + log(" script -select [selection]\n"); log("\n"); - log("This command executes the yosys commands in the specified file.\n"); + log("This command executes the yosys commands in the specified file (default\n"); + log("behaviour), or commands embedded in the constant text value connected to the\n"); + log("selected wires.\n"); log("\n"); - log("The 2nd argument can be used to only execute the section of the\n"); - log("file between the specified labels. An empty from label is synonymous\n"); - log("for the beginning of the file and an empty to label is synonymous\n"); - log("for the end of the file.\n"); + log("In the default (file) case, the 2nd argument can be used to only execute the\n"); + log("section of the file between the specified labels. An empty from label is\n"); + log("synonymous with the beginning of the file and an empty to label is synonymous\n"); + log("with the end of the file.\n"); log("\n"); log("If only one label is specified (without ':') then only the block\n"); log("marked with that label (until the next label) is executed.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - if (args.size() < 2) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + bool select_mode = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-select") { + select_mode = true; + continue; + } + break; + } + if (select_mode) { + extra_args(args, argidx, design); + + for (auto mod : design->selected_modules()) + for (auto &c : mod->connections()) { + if (!c.first.is_wire()) + continue; + auto w = c.first.as_wire(); + if (!mod->selected(w)) + continue; + if (!c.second.is_fully_const()) + log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w)); + auto v = c.second.as_const(); + Pass::call(design, v.decode_string()); + } + } + else if (args.size() < 2) log_cmd_error("Missing script file.\n"); else if (args.size() == 2) run_frontend(args[1], "script", design); -- cgit v1.2.3 From 02ba85b13302f0d20f6b51cc7fdff2fb953421df Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:17:26 -0700 Subject: script -select -> script -scriptwire --- kernel/yosys.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7d4948881..456ad48a0 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1259,7 +1259,7 @@ struct ScriptCmdPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" script [:]\n"); - log(" script -select [selection]\n"); + log(" script -scriptwire [selection]\n"); log("\n"); log("This command executes the yosys commands in the specified file (default\n"); log("behaviour), or commands embedded in the constant text value connected to the\n"); @@ -1276,17 +1276,17 @@ struct ScriptCmdPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - bool select_mode = false; + bool scriptwire = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-select") { - select_mode = true; + if (args[argidx] == "-scriptwire") { + scriptwire = true; continue; } break; } - if (select_mode) { + if (scriptwire) { extra_args(args, argidx, design); for (auto mod : design->selected_modules()) -- cgit v1.2.3 From f1504696e56030ba5d1f2d7a4b7616695dd8020b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:20:37 -0700 Subject: Use Pass::call_on_module() as per @cliffordwolf comments --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 456ad48a0..f95c0127b 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1299,7 +1299,7 @@ struct ScriptCmdPass : public Pass { if (!c.second.is_fully_const()) log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w)); auto v = c.second.as_const(); - Pass::call(design, v.decode_string()); + Pass::call_on_module(design, mod, v.decode_string()); } } else if (args.size() < 2) -- cgit v1.2.3 From 93bc5affd3fc635dafec3a37bf4c5b94c252036f Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 8 Jul 2019 11:34:58 +0000 Subject: Allow attributes on individual switch cases in RTLIL. The parser changes are slightly awkward. Consider the following IL: process $0 switch \foo case 1'1 assign \bar \baz ... case end end Before this commit, attributes are valid in , and iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in and a part of case body, and in as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places. --- kernel/rtlil.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f4fcf5dcf..82cbfaf28 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1327,7 +1327,7 @@ public: #endif }; -struct RTLIL::CaseRule +struct RTLIL::CaseRule : public RTLIL::AttrObject { std::vector compare; std::vector actions; -- cgit v1.2.3 From 41d7d9d24b8ba7fd84dd72b27eb9aede10b8ef15 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 8 Jul 2019 19:21:21 -0700 Subject: Clarify script -scriptwire doc --- kernel/yosys.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index f95c0127b..a42a7c0b8 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1273,6 +1273,10 @@ struct ScriptCmdPass : public Pass { log("If only one label is specified (without ':') then only the block\n"); log("marked with that label (until the next label) is executed.\n"); log("\n"); + log("In \"-scriptwire\" mode, the commands on the selected wire(s) will be executed\n"); + log("in the scope of (and thus, relative to) the wires' owning module(s). This\n"); + log("'-module' mode can be exited by using the 'cd' command.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { -- cgit v1.2.3 From 0e6c83027f24cdf7082606a5631468ad28f41574 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 15 Jul 2019 12:12:21 +0200 Subject: Add log_checkpoint function and use it in opt_muxtree Signed-off-by: Clifford Wolf --- kernel/log.cc | 7 +++++++ kernel/log.h | 1 + 2 files changed, 8 insertions(+) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index a7820950c..1a2c89a9c 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -420,6 +420,13 @@ void log_pop() log_flush(); } +void log_checkpoint() +{ + log_id_cache.clear(); + IdString::checkpoint(); + log_flush(); +} + #if (defined(__linux__) || defined(__FreeBSD__)) && defined(YOSYS_ENABLE_PLUGINS) void log_backtrace(const char *prefix, int levels) { diff --git a/kernel/log.h b/kernel/log.h index 3e1facae8..3328018f3 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -130,6 +130,7 @@ void log_spacer(); void log_push(); void log_pop(); +void log_checkpoint(); void log_backtrace(const char *prefix, int levels); void log_reset_stack(); void log_flush(); -- cgit v1.2.3 From 44fd459c799e393d13d664102cf381264c80649f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 15 Jul 2019 17:10:42 +0200 Subject: Redesign log_id_cache so that it doesn't keep IdString instances referenced, fixes #1178 Signed-off-by: Clifford Wolf --- kernel/log.cc | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 1a2c89a9c..08ebe7af7 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -61,7 +61,7 @@ int log_force_debug = 0; int log_debug_suppressed = 0; vector header_count; -pool log_id_cache; +vector log_id_cache; vector string_buf; int string_buf_index = -1; @@ -69,6 +69,13 @@ static struct timeval initial_tv = { 0, 0 }; static bool next_print_log = false; static int log_newline_count = 0; +static void log_id_cache_clear() +{ + for (auto p : log_id_cache) + free(p); + log_id_cache.clear(); +} + #if defined(_WIN32) && !defined(__MINGW32__) // this will get time information and return it in timeval, simulating gettimeofday() int gettimeofday(struct timeval *tv, struct timezone *tz) @@ -414,7 +421,7 @@ void log_push() void log_pop() { header_count.pop_back(); - log_id_cache.clear(); + log_id_cache_clear(); string_buf.clear(); string_buf_index = -1; log_flush(); @@ -422,7 +429,7 @@ void log_pop() void log_checkpoint() { - log_id_cache.clear(); + log_id_cache_clear(); IdString::checkpoint(); log_flush(); } @@ -528,7 +535,7 @@ void log_reset_stack() { while (header_count.size() > 1) header_count.pop_back(); - log_id_cache.clear(); + log_id_cache_clear(); string_buf.clear(); string_buf_index = -1; log_flush(); @@ -587,8 +594,8 @@ const char *log_const(const RTLIL::Const &value, bool autoint) const char *log_id(RTLIL::IdString str) { - log_id_cache.insert(str); - const char *p = str.c_str(); + log_id_cache.push_back(strdup(str.c_str())); + const char *p = log_id_cache.back(); if (p[0] != '\\') return p; if (p[1] == '$' || p[1] == '\\' || p[1] == 0) -- cgit v1.2.3 From 06f94c92d49a82faad492026f2b0fe6cf0495fcf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 08:35:48 -0700 Subject: Revert "Add log_checkpoint function and use it in opt_muxtree" This reverts commit 0e6c83027f24cdf7082606a5631468ad28f41574. --- kernel/log.cc | 7 ------- kernel/log.h | 1 - 2 files changed, 8 deletions(-) (limited to 'kernel') diff --git a/kernel/log.cc b/kernel/log.cc index 08ebe7af7..e0a60ca12 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -427,13 +427,6 @@ void log_pop() log_flush(); } -void log_checkpoint() -{ - log_id_cache_clear(); - IdString::checkpoint(); - log_flush(); -} - #if (defined(__linux__) || defined(__FreeBSD__)) && defined(YOSYS_ENABLE_PLUGINS) void log_backtrace(const char *prefix, int levels) { diff --git a/kernel/log.h b/kernel/log.h index 3328018f3..3e1facae8 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -130,7 +130,6 @@ void log_spacer(); void log_push(); void log_pop(); -void log_checkpoint(); void log_backtrace(const char *prefix, int levels); void log_reset_stack(); void log_flush(); -- cgit v1.2.3 From 25ff27e37fcb12c6a298267eda2464431304d713 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 12:34:04 -0700 Subject: SigSpec::extract to take negative lengths --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a09f4a0d1..85b013bdc 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3353,7 +3353,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector(bits_.begin() + offset, bits_.begin() + offset + length); + return std::vector(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) -- cgit v1.2.3 From 54708dfbd786032e841f48f15af4875c1eabbbfe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 13:54:57 -0700 Subject: Add an SigSpec::at(offset, defval) convenience method --- kernel/rtlil.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 82cbfaf28..f9412e776 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -818,6 +818,7 @@ public: operator std::vector() const { return chunks(); } operator std::vector() const { return bits(); } + RTLIL::SigBit at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; } unsigned int hash() const { if (!hash_) updhash(); return hash_; }; -- cgit v1.2.3 From 25685a9a5b20c7c03b02d67f0a029702f0019e9d Mon Sep 17 00:00:00 2001 From: Jakob Wenzel Date: Wed, 24 Jul 2019 13:33:07 +0200 Subject: made ObjectIterator extend std::iterator this makes it possible to use std algorithms on them --- kernel/rtlil.h | 20 ++++++++++++++++++-- kernel/yosys.h | 1 + 2 files changed, 19 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 82cbfaf28..10225cff2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -420,7 +420,11 @@ namespace RTLIL // It maintains a reference counter that is used to make sure that the container is not modified while being iterated over. template - struct ObjIterator + struct ObjIterator : public std::iterator { typename dict::iterator it; dict *list_p; @@ -474,13 +478,25 @@ namespace RTLIL return it != other.it; } - inline void operator++() { + + inline bool operator==(const RTLIL::ObjIterator &other) const { + return !(*this != other); + } + + inline ObjIterator& operator++() { log_assert(list_p != nullptr); if (++it == list_p->end()) { (*refcount_p)--; list_p = nullptr; refcount_p = nullptr; } + return *this; + } + + inline const ObjIterator operator++(int) { + ObjIterator result(*this); + ++(*this); + return result; } }; diff --git a/kernel/yosys.h b/kernel/yosys.h index c7b671724..84c797b2d 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -52,6 +52,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 70882a807074a521515d1525d83ed7321f982d7e Mon Sep 17 00:00:00 2001 From: Jakob Wenzel Date: Thu, 25 Jul 2019 09:51:09 +0200 Subject: replaced std::iterator with using statements --- kernel/rtlil.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 10225cff2..712250b3e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -420,12 +420,12 @@ namespace RTLIL // It maintains a reference counter that is used to make sure that the container is not modified while being iterated over. template - struct ObjIterator : public std::iterator - { + struct ObjIterator { + using iterator_category = std::forward_iterator_tag; + using value_type = T; + using difference_type = ptrdiff_t; + using pointer = T*; + using reference = T&; typename dict::iterator it; dict *list_p; int *refcount_p; -- cgit v1.2.3 From 933db0410e096286c21772f5a2f44b03d2ed0b57 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 26 Jul 2019 10:23:58 +0100 Subject: Add support for reading gzip'd input files Signed-off-by: David Shah --- kernel/register.cc | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 26da96b95..4f1501330 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -25,6 +25,26 @@ #include #include +#ifdef YOSYS_ENABLE_ZLIB +#include + +PRIVATE_NAMESPACE_BEGIN +#define GZ_BUFFER_SIZE 8192 +void decompress_gzip(const std::string &filename, std::stringstream &out) +{ + char buffer[GZ_BUFFER_SIZE]; + int bytes_read; + gzFile gzf = gzopen(filename.c_str(), "rb"); + while(!gzeof(gzf)) { + bytes_read = gzread(gzf, reinterpret_cast(buffer), GZ_BUFFER_SIZE); + out.write(buffer, bytes_read); + } + gzclose(gzf); +} +PRIVATE_NAMESPACE_END + +#endif + YOSYS_NAMESPACE_BEGIN #define MAX_REG_COUNT 1000 @@ -436,6 +456,26 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector(magic), 3); + if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { +#ifdef YOSYS_ENABLE_ZLIB + log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); + if (magic[2] != 8) + log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n", + filename.c_str(), unsigned(magic[2])); + delete ff; + std::stringstream *df = new std::stringstream(); + decompress_gzip(filename, *df); + f = df; +#else + log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str()); +#endif + } else { + ff->clear(); + ff->seekg(0, std::ios::beg); + } } if (f == NULL) log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); -- cgit v1.2.3 From da6701c4cd26d559241c8a3de61b51ace1e03fe4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 26 Jul 2019 10:29:05 +0100 Subject: Fix frontend auto-detection for gzipped input Signed-off-by: David Shah --- kernel/yosys.cc | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index a42a7c0b8..191b6d5c7 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -894,23 +894,26 @@ void run_frontend(std::string filename, std::string command, std::string *backen design = yosys_design; if (command == "auto") { - if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") + std::string filename_trim = filename; + if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".gz") + filename_trim.erase(filename_trim.size()-3); + if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-2) == ".v") command = "verilog"; - else if (filename.size() > 2 && filename.substr(filename.size()-3) == ".sv") + else if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-3) == ".sv") command = "verilog -sv"; - else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".vhd") + else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".vhd") command = "vhdl"; - else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif") + else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".blif") command = "blif"; - else if (filename.size() > 5 && filename.substr(filename.size()-6) == ".eblif") + else if (filename_trim.size() > 5 && filename_trim.substr(filename_trim.size()-6) == ".eblif") command = "blif"; - else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".json") + else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".json") command = "json"; - else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") + else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".il") command = "ilang"; - else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".ys") + else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".ys") command = "script"; - else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".tcl") + else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".tcl") command = "tcl"; else if (filename == "-") command = "script"; -- cgit v1.2.3 From 3e4307c104f5caf0f3449421a75b19e7c90a71fe Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 29 Jul 2019 12:29:13 +0200 Subject: Fix case when file does not exist --- kernel/register.cc | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 4f1501330..4c6e3591f 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -456,25 +456,27 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector(magic), 3); - if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { -#ifdef YOSYS_ENABLE_ZLIB - log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); - if (magic[2] != 8) - log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n", - filename.c_str(), unsigned(magic[2])); - delete ff; - std::stringstream *df = new std::stringstream(); - decompress_gzip(filename, *df); - f = df; -#else - log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str()); -#endif - } else { - ff->clear(); - ff->seekg(0, std::ios::beg); + if (f != NULL) { + // Check for gzip magic + unsigned char magic[3]; + int n = readsome(*ff, reinterpret_cast(magic), 3); + if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { + #ifdef YOSYS_ENABLE_ZLIB + log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); + if (magic[2] != 8) + log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n", + filename.c_str(), unsigned(magic[2])); + delete ff; + std::stringstream *df = new std::stringstream(); + decompress_gzip(filename, *df); + f = df; + #else + log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str()); + #endif + } else { + ff->clear(); + ff->seekg(0, std::ios::beg); + } } } if (f == NULL) -- cgit v1.2.3 From f767179c759065d4b31eb64c81594c378d626704 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 31 Jul 2019 17:30:48 +0200 Subject: New mxe hacks needed to support 2ca237e --- kernel/yosys.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index 84c797b2d..09e8139bb 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -88,6 +88,10 @@ extern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName); extern void Tcl_Finalize(void); extern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr); extern const char *Tcl_GetStringResult(Tcl_Interp *interp); +extern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length); +extern Tcl_Obj *Tcl_NewIntObj(int intValue); +extern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]); +extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags); # endif #endif -- cgit v1.2.3 From 023086bd46bc828621ebb171b159efe1398aaecf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 6 Aug 2019 04:47:55 +0200 Subject: Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs Signed-off-by: Clifford Wolf --- kernel/cellaigs.cc | 2 ++ kernel/celltypes.h | 1 + kernel/consteval.h | 7 +++++-- kernel/cost.h | 34 +++++++++++++++++++++++++++++----- kernel/rtlil.cc | 2 ++ kernel/rtlil.h | 2 ++ kernel/satgen.h | 7 +++++-- 7 files changed, 46 insertions(+), 9 deletions(-) (limited to 'kernel') diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 26c625f89..fbc6d045e 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -325,6 +325,8 @@ Aig::Aig(Cell *cell) int A = mk.inport("\\A", i); int B = mk.inport("\\B", i); int Y = mk.mux_gate(A, B, S); + if (cell->type == "$_NMUX_") + Y = mk.not_gate(Y); mk.outport(Y, "\\Y", i); } goto optimize; diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 758661c02..d2594bc46 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -193,6 +193,7 @@ struct CellTypes setup_type("$_ANDNOT_", {A, B}, {Y}, true); setup_type("$_ORNOT_", {A, B}, {Y}, true); setup_type("$_MUX_", {A, B, S}, {Y}, true); + setup_type("$_NMUX_", {A, B, S}, {Y}, true); setup_type("$_MUX4_", {A, B, C, D, S, T}, {Y}, true); setup_type("$_MUX8_", {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true); setup_type("$_MUX16_", {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true); diff --git a/kernel/consteval.h b/kernel/consteval.h index 154373a8d..f70dfa0fb 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -145,7 +145,7 @@ struct ConstEval if (cell->hasPort("\\B")) sig_b = cell->getPort("\\B"); - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") + if (cell->type.in("$mux", "$pmux", "$_MUX_", "$_NMUX_")) { std::vector y_candidates; int count_maybe_set_s_bits = 0; @@ -175,7 +175,10 @@ struct ConstEval for (auto &yc : y_candidates) { if (!eval(yc, undef, cell)) return false; - y_values.push_back(yc.as_const()); + if (cell->type == "$_NMUX_") + y_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc))); + else + y_values.push_back(yc.as_const()); } if (y_values.size() > 1) diff --git a/kernel/cost.h b/kernel/cost.h index 41a09eb63..e8e077ff5 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -24,10 +24,10 @@ YOSYS_NAMESPACE_BEGIN -int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache = nullptr); +int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache = nullptr, bool cmos_cost = false); inline int get_cell_cost(RTLIL::IdString type, const dict ¶meters = dict(), - RTLIL::Design *design = nullptr, dict *mod_cost_cache = nullptr) + RTLIL::Design *design = nullptr, dict *mod_cost_cache = nullptr, bool cmos_cost = false) { static dict gate_cost = { { "$_BUF_", 1 }, @@ -44,9 +44,33 @@ inline int get_cell_cost(RTLIL::IdString type, const dict cmos_gate_cost = { + { "$_BUF_", 1 }, + { "$_NOT_", 2 }, + { "$_AND_", 6 }, + { "$_NAND_", 4 }, + { "$_OR_", 6 }, + { "$_NOR_", 4 }, + { "$_ANDNOT_", 6 }, + { "$_ORNOT_", 6 }, + { "$_XOR_", 12 }, + { "$_XNOR_", 12 }, + { "$_AOI3_", 6 }, + { "$_OAI3_", 6 }, + { "$_AOI4_", 8 }, + { "$_OAI4_", 8 }, + { "$_MUX_", 12 }, + { "$_NMUX_", 10 } + }; + + if (cmos_cost && cmos_gate_cost.count(type)) + return cmos_gate_cost.at(type); + if (gate_cost.count(type)) return gate_cost.at(type); @@ -76,9 +100,9 @@ inline int get_cell_cost(RTLIL::IdString type, const dict *mod_cost_cache) +inline int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache, bool cmos_cost) { - return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache); + return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache, cmos_cost); } YOSYS_NAMESPACE_END diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a09f4a0d1..ba8472ec1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1249,6 +1249,7 @@ namespace { if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; } if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; } if (cell->type == "$_MUX_") { check_gate("ABSY"); return; } + if (cell->type == "$_NMUX_") { check_gate("ABSY"); return; } if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; } if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; } if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; } @@ -1976,6 +1977,7 @@ DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y) DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y) DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y) DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y) +DEF_METHOD_4(NmuxGate, "$_NMUX_", A, B, S, Y) DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y) DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y) DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 712250b3e..1cfe71473 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1154,6 +1154,7 @@ public: RTLIL::Cell* addAndnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); RTLIL::Cell* addOrnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_y, const std::string &src = ""); RTLIL::Cell* addMuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); + RTLIL::Cell* addNmuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, RTLIL::SigBit sig_y, const std::string &src = ""); RTLIL::Cell* addAoi3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); RTLIL::Cell* addOai3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_y, const std::string &src = ""); RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, RTLIL::SigBit sig_y, const std::string &src = ""); @@ -1229,6 +1230,7 @@ public: RTLIL::SigBit AndnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); RTLIL::SigBit OrnotGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, const std::string &src = ""); RTLIL::SigBit MuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); + RTLIL::SigBit NmuxGate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_s, const std::string &src = ""); RTLIL::SigBit Aoi3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); RTLIL::SigBit Oai3Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, const std::string &src = ""); RTLIL::SigBit Aoi4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d, const std::string &src = ""); diff --git a/kernel/satgen.h b/kernel/satgen.h index 210cca3f3..e9f3ecd44 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -475,7 +475,7 @@ struct SatGen return true; } - if (cell->type == "$_MUX_" || cell->type == "$mux") + if (cell->type == "$_MUX_" || cell->type == "$mux" || cell->type == "$_NMUX_") { std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); @@ -483,7 +483,10 @@ struct SatGen std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy)); + if (cell->type == "$_NMUX_") + ez->assume(ez->vec_eq(ez->vec_not(ez->vec_ite(s.at(0), b, a)), yy)); + else + ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy)); if (model_undef) { -- cgit v1.2.3 From 27360ceda62691ab4f052f396a9174487076ce9a Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 29 Jul 2019 09:28:31 +0100 Subject: Add support for writing gzip-compressed files Signed-off-by: David Shah --- kernel/register.cc | 67 ++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 60 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 4c6e3591f..4f60338e9 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -41,6 +41,45 @@ void decompress_gzip(const std::string &filename, std::stringstream &out) } gzclose(gzf); } + +/* +An output stream that uses a stringbuf to buffer data internally, +using zlib to write gzip-compressed data every time the stream is flushed. +*/ +class gzip_ostream : public std::ostream { +public: + gzip_ostream() + { + rdbuf(&outbuf); + } + bool open(const std::string &filename) + { + return outbuf.open(filename); + } +private: + class gzip_streambuf : public std::stringbuf { + public: + gzip_streambuf() { }; + bool open(const std::string &filename) + { + gzf = gzopen(filename.c_str(), "wb"); + return gzf != nullptr; + } + virtual int sync() override + { + gzwrite(gzf, reinterpret_cast(str().c_str()), unsigned(str().size())); + str(""); + return 0; + } + ~gzip_streambuf() + { + sync(); + gzclose(gzf); + } + private: + gzFile gzf = nullptr; + } outbuf; +}; PRIVATE_NAMESPACE_END #endif @@ -588,14 +627,28 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vectoropen(filename.c_str(), std::ofstream::trunc); - yosys_output_files.insert(filename); - if (ff->fail()) { - delete ff; - log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + if (filename.size() > 3 && filename.substr(filename.size()-3) == ".gz") { +#ifdef YOSYS_ENABLE_ZLIB + gzip_ostream *gf = new gzip_ostream; + if (!gf->open(filename)) { + delete gf; + log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + } + yosys_output_files.insert(filename); + f = gf; +#else + log_cmd_error("Yosys is compiled without zlib support, unable to write gzip output.\n"); +#endif + } else { + std::ofstream *ff = new std::ofstream; + ff->open(filename.c_str(), std::ofstream::trunc); + yosys_output_files.insert(filename); + if (ff->fail()) { + delete ff; + log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + } + f = ff; } - f = ff; } if (called_with_fp) -- cgit v1.2.3 From 95a6582f342537d387063be10cba55c001ed19f5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 6 Aug 2019 19:21:37 +0200 Subject: Be less aggressive with running design->check() Signed-off-by: Clifford Wolf --- kernel/driver.cc | 6 ++++++ kernel/register.cc | 10 +++------- kernel/yosys.cc | 10 ++++++++-- 3 files changed, 17 insertions(+), 9 deletions(-) (limited to 'kernel') diff --git a/kernel/driver.cc b/kernel/driver.cc index f273057dd..70a97c4b9 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -522,6 +522,12 @@ int main(int argc, char **argv) if (!backend_command.empty()) run_backend(output_filename, backend_command); + yosys_design->check(); + for (auto it : saved_designs) + it.second->check(); + for (auto it : pushed_designs) + it->check(); + if (!depsfile.empty()) { FILE *f = fopen(depsfile.c_str(), "wt"); diff --git a/kernel/register.cc b/kernel/register.cc index 4c6e3591f..8f8f2c971 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -256,8 +256,6 @@ void Pass::call(RTLIL::Design *design, std::vector args) pass_register[args[0]]->post_execute(state); while (design->selection_stack.size() > orig_sel_stack_pos) design->selection_stack.pop_back(); - - design->check(); } void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command) @@ -339,8 +337,10 @@ void ScriptPass::run(std::string command, std::string info) log(" %s\n", command.c_str()); else log(" %s %s\n", command.c_str(), info.c_str()); - } else + } else { Pass::call(active_design, command); + active_design->check(); + } } void ScriptPass::run_script(RTLIL::Design *design, std::string run_from, std::string run_to) @@ -534,8 +534,6 @@ void Frontend::frontend_call(RTLIL::Design *design, std::istream *f, std::string args.push_back(filename); frontend_register[args[0]]->execute(args, design); } - - design->check(); } Backend::Backend(std::string name, std::string short_help) : @@ -645,8 +643,6 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f while (design->selection_stack.size() > orig_sel_stack_pos) design->selection_stack.pop_back(); - - design->check(); } static struct CellHelpMessages { diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 191b6d5c7..a4cc53f1a 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -964,14 +964,18 @@ void run_frontend(std::string filename, std::string command, std::string *backen command += next_line; } handle_label(command, from_to_active, run_from, run_to); - if (from_to_active) + if (from_to_active) { Pass::call(design, command); + design->check(); + } } if (!command.empty()) { handle_label(command, from_to_active, run_from, run_to); - if (from_to_active) + if (from_to_active) { Pass::call(design, command); + design->check(); + } } } catch (...) { @@ -1000,6 +1004,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen Pass::call(design, vector({command, filename})); else Frontend::frontend_call(design, NULL, filename, command); + design->check(); } void run_frontend(std::string filename, std::string command, RTLIL::Design *design) @@ -1183,6 +1188,7 @@ void shell(RTLIL::Design *design) design->selection_stack.pop_back(); log_reset_stack(); } + design->check(); } if (command == NULL) printf("exit\n"); -- cgit v1.2.3 From 0b56be8c5634f8b953cd3d087b4b6e2a11a2c173 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 15:24:55 -0700 Subject: Restore original SigSpec::extract() --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f2c81db72..ba8472ec1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3355,7 +3355,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); + return std::vector(bits_.begin() + offset, bits_.begin() + offset + length); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) -- cgit v1.2.3 From 84f52aee0d01378796792c9a2f068a22d955f586 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 15:25:11 -0700 Subject: Add SigSpec::extract_end() convenience function --- kernel/rtlil.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 633cb51d6..c07d39c65 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -788,6 +788,7 @@ public: RTLIL::SigSpec extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(const pool &pattern, const RTLIL::SigSpec *other = NULL) const; RTLIL::SigSpec extract(int offset, int length = 1) const; + RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); } void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); -- cgit v1.2.3 From 100c377451f18503fd85112d62d11ebdb6ac9d5a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 7 Aug 2019 01:12:14 +0200 Subject: Redesign of cell cost API Signed-off-by: Clifford Wolf --- kernel/cost.h | 148 ++++++++++++++++++++++++++++++---------------------------- 1 file changed, 77 insertions(+), 71 deletions(-) (limited to 'kernel') diff --git a/kernel/cost.h b/kernel/cost.h index e8e077ff5..7ff11eba2 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -24,86 +24,92 @@ YOSYS_NAMESPACE_BEGIN -int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache = nullptr, bool cmos_cost = false); - -inline int get_cell_cost(RTLIL::IdString type, const dict ¶meters = dict(), - RTLIL::Design *design = nullptr, dict *mod_cost_cache = nullptr, bool cmos_cost = false) +struct CellCosts { - static dict gate_cost = { - { "$_BUF_", 1 }, - { "$_NOT_", 2 }, - { "$_AND_", 4 }, - { "$_NAND_", 4 }, - { "$_OR_", 4 }, - { "$_NOR_", 4 }, - { "$_ANDNOT_", 4 }, - { "$_ORNOT_", 4 }, - { "$_XOR_", 8 }, - { "$_XNOR_", 8 }, - { "$_AOI3_", 6 }, - { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, - { "$_MUX_", 4 }, - { "$_NMUX_", 4 } - }; - - // match costs in "stat -tech cmos" - static dict cmos_gate_cost = { - { "$_BUF_", 1 }, - { "$_NOT_", 2 }, - { "$_AND_", 6 }, - { "$_NAND_", 4 }, - { "$_OR_", 6 }, - { "$_NOR_", 4 }, - { "$_ANDNOT_", 6 }, - { "$_ORNOT_", 6 }, - { "$_XOR_", 12 }, - { "$_XNOR_", 12 }, - { "$_AOI3_", 6 }, - { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, - { "$_MUX_", 12 }, - { "$_NMUX_", 10 } - }; - - if (cmos_cost && cmos_gate_cost.count(type)) - return cmos_gate_cost.at(type); - - if (gate_cost.count(type)) - return gate_cost.at(type); - - if (parameters.empty() && design && design->module(type)) + static const dict& default_gate_cost() { + static const dict db = { + { "$_BUF_", 1 }, + { "$_NOT_", 2 }, + { "$_AND_", 4 }, + { "$_NAND_", 4 }, + { "$_OR_", 4 }, + { "$_NOR_", 4 }, + { "$_ANDNOT_", 4 }, + { "$_ORNOT_", 4 }, + { "$_XOR_", 6 }, + { "$_XNOR_", 6 }, + { "$_AOI3_", 6 }, + { "$_OAI3_", 6 }, + { "$_AOI4_", 8 }, + { "$_OAI4_", 8 }, + { "$_MUX_", 4 }, + { "$_NMUX_", 4 } + }; + return db; + } + + static const dict& cmos_gate_cost() { + static const dict db = { + { "$_BUF_", 1 }, + { "$_NOT_", 2 }, + { "$_AND_", 6 }, + { "$_NAND_", 4 }, + { "$_OR_", 6 }, + { "$_NOR_", 4 }, + { "$_ANDNOT_", 6 }, + { "$_ORNOT_", 6 }, + { "$_XOR_", 12 }, + { "$_XNOR_", 12 }, + { "$_AOI3_", 6 }, + { "$_OAI3_", 6 }, + { "$_AOI4_", 8 }, + { "$_OAI4_", 8 }, + { "$_MUX_", 12 }, + { "$_NMUX_", 10 } + }; + return db; + } + + dict mod_cost_cache; + const dict *gate_cost = nullptr; + Design *design = nullptr; + + int get(RTLIL::IdString type) const { - RTLIL::Module *mod = design->module(type); + if (gate_cost && gate_cost->count(type)) + return gate_cost->at(type); - if (mod->attributes.count("\\cost")) - return mod->attributes.at("\\cost").as_int(); + log_warning("Can't determine cost of %s cell.\n", log_id(type)); + return 1; + } - dict local_mod_cost_cache; - if (mod_cost_cache == nullptr) - mod_cost_cache = &local_mod_cost_cache; + int get(RTLIL::Cell *cell) + { + if (gate_cost && gate_cost->count(cell->type)) + return gate_cost->at(cell->type); - if (mod_cost_cache->count(mod->name)) - return mod_cost_cache->at(mod->name); + if (design && design->module(cell->type) && cell->parameters.empty()) + { + RTLIL::Module *mod = design->module(cell->type); - int module_cost = 1; - for (auto c : mod->cells()) - module_cost += get_cell_cost(c, mod_cost_cache); + if (mod->attributes.count("\\cost")) + return mod->attributes.at("\\cost").as_int(); - (*mod_cost_cache)[mod->name] = module_cost; - return module_cost; - } + if (mod_cost_cache.count(mod->name)) + return mod_cost_cache.at(mod->name); - log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters)); - return 1; -} + int module_cost = 1; + for (auto c : mod->cells()) + module_cost += get(c); -inline int get_cell_cost(RTLIL::Cell *cell, dict *mod_cost_cache, bool cmos_cost) -{ - return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache, cmos_cost); -} + mod_cost_cache[mod->name] = module_cost; + return module_cost; + } + + log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters)); + return 1; + } +}; YOSYS_NAMESPACE_END -- cgit v1.2.3 From 3486235338faa1377bb4e1a8981a45b4ee6edfa9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 16:18:18 -0700 Subject: Make liberal use of IdString.in() --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ba8472ec1..42c65143d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -940,7 +940,7 @@ namespace { return; } - if (cell->type == "$logic_and" || cell->type == "$logic_or") { + if (cell->type.in("$logic_and", "$logic_or")) { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); port("\\A", param("\\A_WIDTH")); -- cgit v1.2.3 From e38f40af5b7cdd5c8b896ffba17069bd65f01f29 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 16:42:25 -0700 Subject: Use IdString::begins_with() --- kernel/rtlil.cc | 8 ++++---- kernel/rtlil.h | 10 +++++++--- 2 files changed, 11 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 42c65143d..e770d4b4b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -828,8 +828,8 @@ namespace { void check() { - if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" || - cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") + if (cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") || + cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:")) return; if (cell->type.in("$not", "$pos", "$neg")) { @@ -2553,8 +2553,8 @@ void RTLIL::Cell::check() void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { - if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" || - type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") + if (type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") || + type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:")) return; if (type == "$mux" || type == "$pmux") { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1cfe71473..d7e036431 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -276,20 +276,24 @@ namespace RTLIL return std::string(c_str() + pos, len); } + int compare(size_t pos, size_t len, const char* s) const { + return strncmp(c_str()+pos, s, len); + } + bool begins_with(const char* prefix) const { size_t len = strlen(prefix); if (size() < len) return false; - return substr(0, len) == prefix; + return compare(0, len, prefix); } bool ends_with(const char* suffix) const { size_t len = strlen(suffix); if (size() < len) return false; - return substr(size()-len) == suffix; + return compare(size()-len, len, suffix); } size_t size() const { - return str().size(); + return strlen(c_str()); } bool empty() const { -- cgit v1.2.3 From c11ad24fd7d961432cfdbca7497ba229d3b4f38d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 16:45:48 -0700 Subject: Use std::stoi instead of atoi(.c_str()) --- kernel/rtlil.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index e770d4b4b..0c7216520 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3921,14 +3921,14 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); if (index_tokens.size() == 1) { cover("kernel.rtlil.sigspec.parse.bit_sel"); - int a = atoi(index_tokens.at(0).c_str()); + int a = std::stoi(index_tokens.at(0)); if (a < 0 || a >= wire->width) return false; sig.append(RTLIL::SigSpec(wire, a)); } else { cover("kernel.rtlil.sigspec.parse.part_sel"); - int a = atoi(index_tokens.at(0).c_str()); - int b = atoi(index_tokens.at(1).c_str()); + int a = std::stoi(index_tokens.at(0)); + int b = std::stoi(index_tokens.at(1)); if (a > b) { int tmp = a; a = b, b = tmp; -- cgit v1.2.3 From 234fcf1724941b5c4fa77cc0359d339ddd36aeb3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 19:07:45 -0700 Subject: Fix typos --- kernel/rtlil.cc | 4 ++-- kernel/rtlil.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0c7216520..c8bfa8da6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -828,7 +828,7 @@ namespace { void check() { - if (cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") || + if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") || cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:")) return; @@ -2553,7 +2553,7 @@ void RTLIL::Cell::check() void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { - if (type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") || + if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") || type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:")) return; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index d7e036431..275b0b269 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -283,13 +283,13 @@ namespace RTLIL bool begins_with(const char* prefix) const { size_t len = strlen(prefix); if (size() < len) return false; - return compare(0, len, prefix); + return compare(0, len, prefix) == 0; } bool ends_with(const char* suffix) const { size_t len = strlen(suffix); if (size() < len) return false; - return compare(size()-len, len, suffix); + return compare(size()-len, len, suffix) == 0; } size_t size() const { -- cgit v1.2.3 From 338f6765ebeb6bd07197dbef8e22fa077bf2d043 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 7 Aug 2019 10:25:51 +0200 Subject: Tweak default gate costs, cleanup "stat -tech cmos" Signed-off-by: Clifford Wolf --- kernel/cost.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/cost.h b/kernel/cost.h index 7ff11eba2..10fa50fb3 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -36,12 +36,12 @@ struct CellCosts { "$_NOR_", 4 }, { "$_ANDNOT_", 4 }, { "$_ORNOT_", 4 }, - { "$_XOR_", 6 }, - { "$_XNOR_", 6 }, + { "$_XOR_", 5 }, + { "$_XNOR_", 5 }, { "$_AOI3_", 6 }, { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, + { "$_AOI4_", 7 }, + { "$_OAI4_", 7 }, { "$_MUX_", 4 }, { "$_NMUX_", 4 } }; -- cgit v1.2.3 From 9260e97aa28b245ee88d81d162bb6b83cbc5eab0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 7 Aug 2019 15:31:49 +0200 Subject: Automatically prune init attributes in verific front-end, fixes #1237 Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index d2594bc46..d1d9bf943 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -139,13 +139,10 @@ struct CellTypes setup_type("$fa", {A, B, C}, {X, Y}, true); } - void setup_internals_mem() + void setup_internals_ff() { IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN"; - IdString Q = "\\Q", D = "\\D", ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN"; - IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN"; - IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA"; - IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT"; + IdString Q = "\\Q", D = "\\D"; setup_type("$sr", {SET, CLR}, {Q}); setup_type("$ff", {D}, {Q}); @@ -156,6 +153,18 @@ struct CellTypes setup_type("$dlatch", {EN, D}, {Q}); setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q}); + } + + void setup_internals_mem() + { + setup_internals_ff(); + + IdString CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN"; + IdString ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN"; + IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN"; + IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA"; + IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT"; + setup_type("$memrd", {CLK, EN, ADDR}, {DATA}); setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool()); setup_type("$meminit", {ADDR, DATA}, pool()); -- cgit v1.2.3 From 48d0f994064557dc0832748e17133ee2eac88cbf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 11:09:17 -0700 Subject: stoi -> atoi --- kernel/rtlil.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c8bfa8da6..479a5794a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3921,14 +3921,14 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':'); if (index_tokens.size() == 1) { cover("kernel.rtlil.sigspec.parse.bit_sel"); - int a = std::stoi(index_tokens.at(0)); + int a = atoi(index_tokens.at(0).c_str()); if (a < 0 || a >= wire->width) return false; sig.append(RTLIL::SigSpec(wire, a)); } else { cover("kernel.rtlil.sigspec.parse.part_sel"); - int a = std::stoi(index_tokens.at(0)); - int b = std::stoi(index_tokens.at(1)); + int a = atoi(index_tokens.at(0).c_str()); + int b = atoi(index_tokens.at(1).c_str()); if (a > b) { int tmp = a; a = b, b = tmp; -- cgit v1.2.3 From 71649969213863b2695f1c51956886fc7879c3e6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 11:12:38 -0700 Subject: RTLIL::S{0,1} -> State::S{0,1} --- kernel/rtlil.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 479a5794a..fade0bc36 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -47,7 +47,7 @@ RTLIL::Const::Const(std::string str) for (int i = str.size()-1; i >= 0; i--) { unsigned char ch = str[i]; for (int j = 0; j < 8; j++) { - bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0); + bits.push_back((ch & 1) != 0 ? State::S1 : State::S0); ch = ch >> 1; } } @@ -57,7 +57,7 @@ RTLIL::Const::Const(int val, int width) { flags = RTLIL::CONST_FLAG_NONE; for (int i = 0; i < width; i++) { - bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0); + bits.push_back((val & 1) != 0 ? State::S1 : State::S0); val = val >> 1; } } @@ -73,7 +73,7 @@ RTLIL::Const::Const(const std::vector &bits) { flags = RTLIL::CONST_FLAG_NONE; for (auto b : bits) - this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0); + this->bits.push_back(b ? State::S1 : State::S0); } RTLIL::Const::Const(const RTLIL::Const &c) @@ -106,7 +106,7 @@ bool RTLIL::Const::operator !=(const RTLIL::Const &other) const bool RTLIL::Const::as_bool() const { for (size_t i = 0; i < bits.size(); i++) - if (bits[i] == RTLIL::S1) + if (bits[i] == State::S1) return true; return false; } @@ -115,9 +115,9 @@ int RTLIL::Const::as_int(bool is_signed) const { int32_t ret = 0; for (size_t i = 0; i < bits.size() && i < 32; i++) - if (bits[i] == RTLIL::S1) + if (bits[i] == State::S1) ret |= 1 << i; - if (is_signed && bits.back() == RTLIL::S1) + if (is_signed && bits.back() == State::S1) for (size_t i = bits.size(); i < 32; i++) ret |= 1 << i; return ret; -- cgit v1.2.3 From 71eff6f0deae3ffaf75cca22768b66a2dc918b3e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 11:14:03 -0700 Subject: RTLIL::S{0,1} -> State::S{0,1} for headers --- kernel/celltypes.h | 12 ++++++------ kernel/consteval.h | 22 +++++++++++----------- kernel/macc.h | 42 +++++++++++++++++++++--------------------- kernel/rtlil.h | 2 +- kernel/satgen.h | 2 +- 5 files changed, 40 insertions(+), 40 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index d2594bc46..7f1d35560 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -273,8 +273,8 @@ struct CellTypes static RTLIL::Const eval_not(RTLIL::Const v) { for (auto &bit : v.bits) - if (bit == RTLIL::S0) bit = RTLIL::S1; - else if (bit == RTLIL::S1) bit = RTLIL::S0; + if (bit == State::S0) bit = State::S1; + else if (bit == State::S1) bit = State::S0; return v; } @@ -380,15 +380,15 @@ struct CellTypes std::vector t = cell->parameters.at("\\LUT").bits; while (GetSize(t) < (1 << width)) - t.push_back(RTLIL::S0); + t.push_back(State::S0); t.resize(1 << width); for (int i = width-1; i >= 0; i--) { RTLIL::State sel = arg1.bits.at(i); std::vector new_t; - if (sel == RTLIL::S0) + if (sel == State::S0) new_t = std::vector(t.begin(), t.begin() + GetSize(t)/2); - else if (sel == RTLIL::S1) + else if (sel == State::S1) new_t = std::vector(t.begin() + GetSize(t)/2, t.end()); else for (int j = 0; j < GetSize(t)/2; j++) @@ -407,7 +407,7 @@ struct CellTypes std::vector t = cell->parameters.at("\\TABLE").bits; while (GetSize(t) < width*depth*2) - t.push_back(RTLIL::S0); + t.push_back(State::S0); RTLIL::State default_ret = State::S0; diff --git a/kernel/consteval.h b/kernel/consteval.h index f70dfa0fb..521ce96d4 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -114,8 +114,8 @@ struct ConstEval bool carry = sig_ci.as_bool(); for (int i = 0; i < GetSize(coval); i++) { - carry = (sig_g[i] == RTLIL::S1) || (sig_p[i] == RTLIL::S1 && carry); - coval.bits[i] = carry ? RTLIL::S1 : RTLIL::S0; + carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry); + coval.bits[i] = carry ? State::S1 : State::S0; } set(sig_co, coval); @@ -254,8 +254,8 @@ struct ConstEval sig_a.extend_u0(GetSize(sig_y), signed_a); sig_b.extend_u0(GetSize(sig_y), signed_b); - bool carry = sig_ci[0] == RTLIL::S1; - bool b_inv = sig_bi[0] == RTLIL::S1; + bool carry = sig_ci[0] == State::S1; + bool b_inv = sig_bi[0] == State::S1; for (int i = 0; i < GetSize(sig_y); i++) { @@ -264,22 +264,22 @@ struct ConstEval if (!x_inputs.is_fully_def()) { set(sig_x[i], RTLIL::Sx); } else { - bool bit_a = sig_a[i] == RTLIL::S1; - bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv; + bool bit_a = sig_a[i] == State::S1; + bool bit_b = (sig_b[i] == State::S1) != b_inv; bool bit_x = bit_a != bit_b; - set(sig_x[i], bit_x ? RTLIL::S1 : RTLIL::S0); + set(sig_x[i], bit_x ? State::S1 : State::S0); } if (any_input_undef) { set(sig_y[i], RTLIL::Sx); set(sig_co[i], RTLIL::Sx); } else { - bool bit_a = sig_a[i] == RTLIL::S1; - bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv; + bool bit_a = sig_a[i] == State::S1; + bool bit_b = (sig_b[i] == State::S1) != b_inv; bool bit_y = (bit_a != bit_b) != carry; carry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry); - set(sig_y[i], bit_y ? RTLIL::S1 : RTLIL::S0); - set(sig_co[i], carry ? RTLIL::S1 : RTLIL::S0); + set(sig_y[i], bit_y ? State::S1 : State::S0); + set(sig_co[i], carry ? State::S1 : State::S0); } } } diff --git a/kernel/macc.h b/kernel/macc.h index 286ce567f..c7595ebc1 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -70,9 +70,9 @@ struct Macc while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2]) port.in_b.remove(GetSize(port.in_b)-1); } else { - while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == RTLIL::S0) + while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0) port.in_a.remove(GetSize(port.in_a)-1); - while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == RTLIL::S0) + while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0) port.in_b.remove(GetSize(port.in_b)-1); } @@ -80,9 +80,9 @@ struct Macc } for (auto &bit : bit_ports) - if (bit == RTLIL::S1) + if (bit == State::S1) off = const_add(off, RTLIL::Const(1, width), false, false, width); - else if (bit != RTLIL::S0) + else if (bit != State::S0) new_bit_ports.append(bit); if (off.as_bool()) { @@ -113,10 +113,10 @@ struct Macc #endif int num_bits = 0; - if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 1; - if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 2; - if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 4; - if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 8; + if (config_bits[config_cursor++] == State::S1) num_bits |= 1; + if (config_bits[config_cursor++] == State::S1) num_bits |= 2; + if (config_bits[config_cursor++] == State::S1) num_bits |= 4; + if (config_bits[config_cursor++] == State::S1) num_bits |= 8; int port_a_cursor = 0; while (port_a_cursor < GetSize(port_a)) @@ -124,12 +124,12 @@ struct Macc log_assert(config_cursor + 2 + 2*num_bits <= config_width); port_t this_port; - this_port.is_signed = config_bits[config_cursor++] == RTLIL::S1; - this_port.do_subtract = config_bits[config_cursor++] == RTLIL::S1; + this_port.is_signed = config_bits[config_cursor++] == State::S1; + this_port.do_subtract = config_bits[config_cursor++] == State::S1; int size_a = 0; for (int i = 0; i < num_bits; i++) - if (config_bits[config_cursor++] == RTLIL::S1) + if (config_bits[config_cursor++] == State::S1) size_a |= 1 << i; this_port.in_a = port_a.extract(port_a_cursor, size_a); @@ -137,7 +137,7 @@ struct Macc int size_b = 0; for (int i = 0; i < num_bits; i++) - if (config_bits[config_cursor++] == RTLIL::S1) + if (config_bits[config_cursor++] == State::S1) size_b |= 1 << i; this_port.in_b = port_a.extract(port_a_cursor, size_b); @@ -166,26 +166,26 @@ struct Macc num_bits++, max_size /= 2; log_assert(num_bits < 16); - config_bits.push_back(num_bits & 1 ? RTLIL::S1 : RTLIL::S0); - config_bits.push_back(num_bits & 2 ? RTLIL::S1 : RTLIL::S0); - config_bits.push_back(num_bits & 4 ? RTLIL::S1 : RTLIL::S0); - config_bits.push_back(num_bits & 8 ? RTLIL::S1 : RTLIL::S0); + config_bits.push_back(num_bits & 1 ? State::S1 : State::S0); + config_bits.push_back(num_bits & 2 ? State::S1 : State::S0); + config_bits.push_back(num_bits & 4 ? State::S1 : State::S0); + config_bits.push_back(num_bits & 8 ? State::S1 : State::S0); for (auto &port : ports) { if (GetSize(port.in_a) == 0) continue; - config_bits.push_back(port.is_signed ? RTLIL::S1 : RTLIL::S0); - config_bits.push_back(port.do_subtract ? RTLIL::S1 : RTLIL::S0); + config_bits.push_back(port.is_signed ? State::S1 : State::S0); + config_bits.push_back(port.do_subtract ? State::S1 : State::S0); int size_a = GetSize(port.in_a); for (int i = 0; i < num_bits; i++) - config_bits.push_back(size_a & (1 << i) ? RTLIL::S1 : RTLIL::S0); + config_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0); int size_b = GetSize(port.in_b); for (int i = 0; i < num_bits; i++) - config_bits.push_back(size_b & (1 << i) ? RTLIL::S1 : RTLIL::S0); + config_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0); port_a.append(port.in_a); port_a.append(port.in_b); @@ -202,7 +202,7 @@ struct Macc bool eval(RTLIL::Const &result) const { for (auto &bit : result.bits) - bit = RTLIL::S0; + bit = State::S0; for (auto &port : ports) { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 99c683974..37b5f984c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1408,7 +1408,7 @@ struct RTLIL::Process : public RTLIL::AttrObject inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { } inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } -inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { } +inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { } inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } diff --git a/kernel/satgen.h b/kernel/satgen.h index e9f3ecd44..596f522ec 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -1023,7 +1023,7 @@ struct SatGen std::vector lut; for (auto bit : cell->getParam("\\LUT").bits) - lut.push_back(bit == RTLIL::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); + lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); while (GetSize(lut) < (1 << GetSize(a))) lut.push_back(ez->CONST_FALSE); lut.resize(1 << GetSize(a)); -- cgit v1.2.3 From 6d77236f3845cd8785e7bdd4da3c5ef966be6043 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 12:20:08 -0700 Subject: substr() -> compare() --- kernel/register.cc | 14 +++++++------- kernel/yosys.cc | 50 +++++++++++++++++++++++++------------------------- 2 files changed, 32 insertions(+), 32 deletions(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index e4237cac4..1fd1bad1d 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -200,7 +200,7 @@ void Pass::extra_args(std::vector args, size_t argidx, RTLIL::Desig { std::string arg = args[argidx]; - if (arg.substr(0, 1) == "-") + if (arg.compare(0, 1, "-") == 0) cmd_error(args, argidx, "Unknown option or option in arguments."); if (!select) @@ -449,7 +449,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector 3 && filename.substr(filename.size()-3) == ".gz") { + if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".gz") == 0) { #ifdef YOSYS_ENABLE_ZLIB gzip_ostream *gf = new gzip_ostream; if (!gf->open(filename)) { diff --git a/kernel/yosys.cc b/kernel/yosys.cc index a4cc53f1a..5a53f90fd 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -647,12 +647,12 @@ std::vector glob_filename(const std::string &filename_pattern) void rewrite_filename(std::string &filename) { - if (filename.substr(0, 1) == "\"" && filename.substr(GetSize(filename)-1) == "\"") + if (filename.compare(0, 1, "\"") == 0 && filename.compare(GetSize(filename)-1, std::string::npos, "\"") == 0) filename = filename.substr(1, GetSize(filename)-2); - if (filename.substr(0, 2) == "+/") + if (filename.compare(0, 2, "+/") == 0) filename = proc_share_dirname() + filename.substr(2); #ifndef _WIN32 - if (filename.substr(0, 2) == "~/") + if (filename.compare(0, 2, "~/") == 0) filename = filename.replace(0, 1, getenv("HOME")); #endif } @@ -895,25 +895,25 @@ void run_frontend(std::string filename, std::string command, std::string *backen if (command == "auto") { std::string filename_trim = filename; - if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".gz") + if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".gz") == 0) filename_trim.erase(filename_trim.size()-3); - if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-2) == ".v") + if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-2, std::string::npos, ".v") == 0) command = "verilog"; - else if (filename_trim.size() > 2 && filename_trim.substr(filename_trim.size()-3) == ".sv") + else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0) command = "verilog -sv"; - else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".vhd") + else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0) command = "vhdl"; - else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".blif") + else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0) command = "blif"; - else if (filename_trim.size() > 5 && filename_trim.substr(filename_trim.size()-6) == ".eblif") + else if (filename_trim.size() > 5 && filename_trim.compare(filename_trim.size()-6, std::string::npos, ".eblif") == 0) command = "blif"; - else if (filename_trim.size() > 4 && filename_trim.substr(filename_trim.size()-5) == ".json") + else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0) command = "json"; - else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".il") + else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0) command = "ilang"; - else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-3) == ".ys") + else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0) command = "script"; - else if (filename_trim.size() > 3 && filename_trim.substr(filename_trim.size()-4) == ".tcl") + else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0) command = "tcl"; else if (filename == "-") command = "script"; @@ -1028,17 +1028,17 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig design = yosys_design; if (command == "auto") { - if (filename.size() > 2 && filename.substr(filename.size()-2) == ".v") + if (filename.size() > 2 && filename.compare(filename.size()-2, std::string::npos, ".v") == 0) command = "verilog"; - else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") + else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0) command = "ilang"; - else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig") + else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0) command = "aiger"; - else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif") + else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".blif") == 0) command = "blif"; - else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif") + else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".edif") == 0) command = "edif"; - else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".json") + else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".json") == 0) command = "json"; else if (filename == "-") command = "ilang"; @@ -1072,7 +1072,7 @@ static char *readline_cmd_generator(const char *text, int state) } for (; it != pass_register.end(); it++) { - if (it->first.substr(0, len) == text) + if (it->first.compare(0, len, text) == 0) return strdup((it++)->first.c_str()); } return NULL; @@ -1094,7 +1094,7 @@ static char *readline_obj_generator(const char *text, int state) if (design->selected_active_module.empty()) { for (auto &it : design->modules_) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) + if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); } else @@ -1103,19 +1103,19 @@ static char *readline_obj_generator(const char *text, int state) RTLIL::Module *module = design->modules_.at(design->selected_active_module); for (auto &it : module->wires_) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) + if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); for (auto &it : module->memories) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) + if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); for (auto &it : module->cells_) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) + if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); for (auto &it : module->processes) - if (RTLIL::unescape_id(it.first).substr(0, len) == text) + if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); } -- cgit v1.2.3 From b5534b66c8fb0cfb4f3e62a6ee694d1f603dc7d8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 9 Aug 2019 18:54:03 +0200 Subject: Improve API of ID() macro Signed-off-by: Clifford Wolf --- kernel/yosys.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index 09e8139bb..49716ed52 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -305,8 +305,16 @@ RTLIL::IdString new_id(std::string file, int line, std::string func); #define NEW_ID \ YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__) -#define ID(_str) \ - ([]() { static YOSYS_NAMESPACE_PREFIX RTLIL::IdString _id(_str); return _id; })() +// Create a statically allocated IdString object, using for example ID(A) or ID($add). +// +// Recipe for Converting old code that is using conversion of strings like "\\A" and +// "$add" for creating IdStrings: Run below SED command on the .cc file and then use for +// example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary. +// +// sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' +// +#define ID(_id) ([]() { const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \ + static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })() RTLIL::Design *yosys_get_design(); std::string proc_self_dirname(); -- cgit v1.2.3 From 8222c5735e3b31fc2a7507abe607bb5aa9f863de Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 10 Aug 2019 11:41:09 +0200 Subject: More improvements and cleanups in IdString subsystem - better use of "inline" keyword - deprecate "sticky" IDs feature - improve handling of empty ID - add move constructor Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 2 ++ kernel/rtlil.h | 88 ++++++++++++++++++++++++++++++++++----------------------- kernel/yosys.cc | 7 ----- 3 files changed, 54 insertions(+), 43 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index fade0bc36..91b6a1d30 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -33,8 +33,10 @@ std::vector RTLIL::IdString::global_refcount_storage_; std::vector RTLIL::IdString::global_id_storage_; dict RTLIL::IdString::global_id_index_; std::vector RTLIL::IdString::global_free_idx_list_; +#ifdef YOSYS_USE_STICKY_IDS int RTLIL::IdString::last_created_idx_[8]; int RTLIL::IdString::last_created_idx_ptr_; +#endif RTLIL::Const::Const() { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 37b5f984c..e771655d7 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -78,6 +78,7 @@ namespace RTLIL { #undef YOSYS_XTRACE_GET_PUT #undef YOSYS_SORT_ID_FREE_LIST + #undef YOSYS_USE_STICKY_IDS // the global id string cache @@ -92,8 +93,10 @@ namespace RTLIL static dict global_id_index_; static std::vector global_free_idx_list_; + #ifdef YOSYS_USE_STICKY_IDS static int last_created_idx_ptr_; static int last_created_idx_[8]; + #endif static inline void xtrace_db_dump() { @@ -110,12 +113,14 @@ namespace RTLIL static inline void checkpoint() { + #ifdef YOSYS_USE_STICKY_IDS last_created_idx_ptr_ = 0; for (int i = 0; i < 8; i++) { if (last_created_idx_[i]) put_reference(last_created_idx_[i]); last_created_idx_[i] = 0; } + #endif #ifdef YOSYS_SORT_ID_FREE_LIST std::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater()); #endif @@ -123,36 +128,42 @@ namespace RTLIL static inline int get_reference(int idx) { - global_refcount_storage_.at(idx)++; + if (idx) { + global_refcount_storage_[idx]++; #ifdef YOSYS_XTRACE_GET_PUT - if (yosys_xtrace) { - log("#X# GET-BY-INDEX '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); - } + if (yosys_xtrace) + log("#X# GET-BY-INDEX '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); #endif + } return idx; } - static inline int get_reference(const char *p) + static int get_reference(const char *p) { log_assert(destruct_guard.ok); - if (p[0]) { - log_assert(p[1] != 0); - log_assert(p[0] == '$' || p[0] == '\\'); - } + if (!p[0]) + return 0; + + log_assert(p[0] == '$' || p[0] == '\\'); + log_assert(p[1] != 0); auto it = global_id_index_.find((char*)p); if (it != global_id_index_.end()) { global_refcount_storage_.at(it->second)++; #ifdef YOSYS_XTRACE_GET_PUT - if (yosys_xtrace) { + if (yosys_xtrace) log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second)); - } #endif return it->second; } if (global_free_idx_list_.empty()) { + if (global_id_storage_.empty()) { + global_refcount_storage_.push_back(0); + global_id_storage_.push_back((char*)""); + global_id_index_[global_id_storage_.back()] = 0; + } log_assert(global_id_storage_.size() < 0x40000000); global_free_idx_list_.push_back(global_id_storage_.size()); global_id_storage_.push_back(nullptr); @@ -165,23 +176,25 @@ namespace RTLIL global_id_index_[global_id_storage_.at(idx)] = idx; global_refcount_storage_.at(idx)++; - // Avoid Create->Delete->Create pattern - if (last_created_idx_[last_created_idx_ptr_]) - put_reference(last_created_idx_[last_created_idx_ptr_]); - last_created_idx_[last_created_idx_ptr_] = idx; - get_reference(last_created_idx_[last_created_idx_ptr_]); - last_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7; - if (yosys_xtrace) { log("#X# New IdString '%s' with index %d.\n", p, idx); log_backtrace("-X- ", yosys_xtrace-1); } #ifdef YOSYS_XTRACE_GET_PUT - if (yosys_xtrace) { + if (yosys_xtrace) log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); - } #endif + + #ifdef YOSYS_USE_STICKY_IDS + // Avoid Create->Delete->Create pattern + if (last_created_idx_[last_created_idx_ptr_]) + put_reference(last_created_idx_[last_created_idx_ptr_]); + last_created_idx_[last_created_idx_ptr_] = idx; + get_reference(last_created_idx_[last_created_idx_ptr_]); + last_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7; + #endif + return idx; } @@ -189,7 +202,7 @@ namespace RTLIL { // put_reference() may be called from destructors after the destructor of // global_refcount_storage_ has been run. in this case we simply do nothing. - if (!destruct_guard.ok) + if (!destruct_guard.ok || !idx) return; #ifdef YOSYS_XTRACE_GET_PUT @@ -198,11 +211,13 @@ namespace RTLIL } #endif - log_assert(global_refcount_storage_.at(idx) > 0); + int &refcount = global_refcount_storage_[idx]; - if (--global_refcount_storage_.at(idx) != 0) + if (--refcount > 0) return; + log_assert(refcount == 0); + if (yosys_xtrace) { log("#X# Removed IdString '%s' with index %d.\n", global_id_storage_.at(idx), idx); log_backtrace("-X- ", yosys_xtrace-1); @@ -218,41 +233,42 @@ namespace RTLIL int index_; - IdString() : index_(get_reference("")) { } - IdString(const char *str) : index_(get_reference(str)) { } - IdString(const IdString &str) : index_(get_reference(str.index_)) { } - IdString(const std::string &str) : index_(get_reference(str.c_str())) { } - ~IdString() { put_reference(index_); } + inline IdString() : index_(0) { } + inline IdString(const char *str) : index_(get_reference(str)) { } + inline IdString(const IdString &str) : index_(get_reference(str.index_)) { } + inline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; } + inline IdString(const std::string &str) : index_(get_reference(str.c_str())) { } + inline ~IdString() { put_reference(index_); } - void operator=(const IdString &rhs) { + inline void operator=(const IdString &rhs) { put_reference(index_); index_ = get_reference(rhs.index_); } - void operator=(const char *rhs) { + inline void operator=(const char *rhs) { IdString id(rhs); *this = id; } - void operator=(const std::string &rhs) { + inline void operator=(const std::string &rhs) { IdString id(rhs); *this = id; } - const char *c_str() const { + inline const char *c_str() const { return global_id_storage_.at(index_); } - std::string str() const { + inline std::string str() const { return std::string(global_id_storage_.at(index_)); } - bool operator<(const IdString &rhs) const { + inline bool operator<(const IdString &rhs) const { return index_ < rhs.index_; } - bool operator==(const IdString &rhs) const { return index_ == rhs.index_; } - bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; } + inline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; } + inline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; } // The methods below are just convenience functions for better compatibility with std::string. diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 5a53f90fd..fc9bd96fe 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -510,10 +510,6 @@ void yosys_setup() if(already_setup) return; already_setup = true; - // if there are already IdString objects then we have a global initialization order bug - IdString empty_id; - log_assert(empty_id.index_ == 0); - IdString::get_reference(empty_id.index_); #ifdef WITH_PYTHON PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); @@ -575,9 +571,6 @@ void yosys_shutdown() #ifdef WITH_PYTHON Py_Finalize(); #endif - - IdString empty_id; - IdString::put_reference(empty_id.index_); } RTLIL::IdString new_id(std::string file, int line, std::string func) -- cgit v1.2.3 From 390bf459fbd766d4b1f9d16c6e10d665b43369d5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 10 Aug 2019 12:24:16 +0200 Subject: Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) Signed-off-by: Clifford Wolf --- kernel/cellaigs.cc | 196 ++++----- kernel/celledges.cc | 42 +- kernel/celltypes.h | 244 +++++------ kernel/consteval.h | 66 +-- kernel/cost.h | 68 +-- kernel/macc.h | 20 +- kernel/rtlil.cc | 1163 ++++++++++++++++++++++++++------------------------- kernel/rtlil.h | 14 +- kernel/satgen.h | 522 +++++++++++------------ kernel/yosys.cc | 7 + 10 files changed, 1182 insertions(+), 1160 deletions(-) (limited to 'kernel') diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index fbc6d045e..6d496db45 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -268,9 +268,9 @@ Aig::Aig(Cell *cell) cell->parameters.sort(); for (auto p : cell->parameters) { - if (p.first == "\\A_WIDTH" && mkname_a_signed) { + if (p.first == ID(A_WIDTH) && mkname_a_signed) { name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); - } else if (p.first == "\\B_WIDTH" && mkname_b_signed) { + } else if (p.first == ID(B_WIDTH) && mkname_b_signed) { name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); } else { mkname_last = name; @@ -280,183 +280,183 @@ Aig::Aig(Cell *cell) mkname_a_signed = false; mkname_b_signed = false; mkname_is_signed = false; - if (p.first == "\\A_SIGNED") { + if (p.first == ID(A_SIGNED)) { mkname_a_signed = true; mkname_is_signed = p.second.as_bool(); } - if (p.first == "\\B_SIGNED") { + if (p.first == ID(B_SIGNED)) { mkname_b_signed = true; mkname_is_signed = p.second.as_bool(); } } - if (cell->type.in("$not", "$_NOT_", "$pos", "$_BUF_")) + if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($_BUF_))) { - for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) { - int A = mk.inport("\\A", i); - int Y = cell->type.in("$not", "$_NOT_") ? mk.not_gate(A) : A; - mk.outport(Y, "\\Y", i); + for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) { + int A = mk.inport(ID(A), i); + int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A; + mk.outport(Y, ID(Y), i); } goto optimize; } - if (cell->type.in("$and", "$_AND_", "$_NAND_", "$or", "$_OR_", "$_NOR_", "$xor", "$xnor", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) - { - for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) { - int A = mk.inport("\\A", i); - int B = mk.inport("\\B", i); - int Y = cell->type.in("$and", "$_AND_") ? mk.and_gate(A, B) : - cell->type.in("$_NAND_") ? mk.nand_gate(A, B) : - cell->type.in("$or", "$_OR_") ? mk.or_gate(A, B) : - cell->type.in("$_NOR_") ? mk.nor_gate(A, B) : - cell->type.in("$xor", "$_XOR_") ? mk.xor_gate(A, B) : - cell->type.in("$xnor", "$_XNOR_") ? mk.xnor_gate(A, B) : - cell->type.in("$_ANDNOT_") ? mk.andnot_gate(A, B) : - cell->type.in("$_ORNOT_") ? mk.ornot_gate(A, B) : -1; - mk.outport(Y, "\\Y", i); + if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) + { + for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) { + int A = mk.inport(ID(A), i); + int B = mk.inport(ID(B), i); + int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) : + cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) : + cell->type.in(ID($or), ID($_OR_)) ? mk.or_gate(A, B) : + cell->type.in(ID($_NOR_)) ? mk.nor_gate(A, B) : + cell->type.in(ID($xor), ID($_XOR_)) ? mk.xor_gate(A, B) : + cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) : + cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) : + cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1; + mk.outport(Y, ID(Y), i); } goto optimize; } - if (cell->type.in("$mux", "$_MUX_")) + if (cell->type.in(ID($mux), ID($_MUX_))) { - int S = mk.inport("\\S"); - for (int i = 0; i < GetSize(cell->getPort("\\Y")); i++) { - int A = mk.inport("\\A", i); - int B = mk.inport("\\B", i); + int S = mk.inport(ID(S)); + for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) { + int A = mk.inport(ID(A), i); + int B = mk.inport(ID(B), i); int Y = mk.mux_gate(A, B, S); - if (cell->type == "$_NMUX_") + if (cell->type == ID($_NMUX_)) Y = mk.not_gate(Y); - mk.outport(Y, "\\Y", i); + mk.outport(Y, ID(Y), i); } goto optimize; } - if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { - int Y = mk.inport("\\A", 0); - for (int i = 1; i < GetSize(cell->getPort("\\A")); i++) { - int A = mk.inport("\\A", i); - if (cell->type == "$reduce_and") Y = mk.and_gate(A, Y); - if (cell->type == "$reduce_or") Y = mk.or_gate(A, Y); - if (cell->type == "$reduce_bool") Y = mk.or_gate(A, Y); - if (cell->type == "$reduce_xor") Y = mk.xor_gate(A, Y); - if (cell->type == "$reduce_xnor") Y = mk.xor_gate(A, Y); + int Y = mk.inport(ID(A), 0); + for (int i = 1; i < GetSize(cell->getPort(ID(A))); i++) { + int A = mk.inport(ID(A), i); + if (cell->type == ID($reduce_and)) Y = mk.and_gate(A, Y); + if (cell->type == ID($reduce_or)) Y = mk.or_gate(A, Y); + if (cell->type == ID($reduce_bool)) Y = mk.or_gate(A, Y); + if (cell->type == ID($reduce_xor)) Y = mk.xor_gate(A, Y); + if (cell->type == ID($reduce_xnor)) Y = mk.xor_gate(A, Y); } - if (cell->type == "$reduce_xnor") + if (cell->type == ID($reduce_xnor)) Y = mk.not_gate(Y); - mk.outport(Y, "\\Y", 0); - for (int i = 1; i < GetSize(cell->getPort("\\Y")); i++) - mk.outport(mk.bool_node(false), "\\Y", i); + mk.outport(Y, ID(Y), 0); + for (int i = 1; i < GetSize(cell->getPort(ID(Y))); i++) + mk.outport(mk.bool_node(false), ID(Y), i); goto optimize; } - if (cell->type.in("$logic_not", "$logic_and", "$logic_or")) + if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or))) { - int A = mk.inport("\\A", 0), Y = -1; - for (int i = 1; i < GetSize(cell->getPort("\\A")); i++) - A = mk.or_gate(mk.inport("\\A", i), A); - if (cell->type.in("$logic_and", "$logic_or")) { - int B = mk.inport("\\B", 0); - for (int i = 1; i < GetSize(cell->getPort("\\B")); i++) - B = mk.or_gate(mk.inport("\\B", i), B); - if (cell->type == "$logic_and") Y = mk.and_gate(A, B); - if (cell->type == "$logic_or") Y = mk.or_gate(A, B); + int A = mk.inport(ID(A), 0), Y = -1; + for (int i = 1; i < GetSize(cell->getPort(ID(A))); i++) + A = mk.or_gate(mk.inport(ID(A), i), A); + if (cell->type.in(ID($logic_and), ID($logic_or))) { + int B = mk.inport(ID(B), 0); + for (int i = 1; i < GetSize(cell->getPort(ID(B))); i++) + B = mk.or_gate(mk.inport(ID(B), i), B); + if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B); + if (cell->type == ID($logic_or)) Y = mk.or_gate(A, B); } else { - if (cell->type == "$logic_not") Y = mk.not_gate(A); + if (cell->type == ID($logic_not)) Y = mk.not_gate(A); } - mk.outport_bool(Y, "\\Y"); + mk.outport_bool(Y, ID(Y)); goto optimize; } - if (cell->type.in("$add", "$sub")) + if (cell->type.in(ID($add), ID($sub))) { - int width = GetSize(cell->getPort("\\Y")); - vector A = mk.inport_vec("\\A", width); - vector B = mk.inport_vec("\\B", width); + int width = GetSize(cell->getPort(ID(Y))); + vector A = mk.inport_vec(ID(A), width); + vector B = mk.inport_vec(ID(B), width); int carry = mk.bool_node(false); - if (cell->type == "$sub") { + if (cell->type == ID($sub)) { for (auto &n : B) n = mk.not_gate(n); carry = mk.not_gate(carry); } vector Y = mk.adder(A, B, carry); - mk.outport_vec(Y, "\\Y"); + mk.outport_vec(Y, ID(Y)); goto optimize; } - if (cell->type == "$alu") + if (cell->type == ID($alu)) { - int width = GetSize(cell->getPort("\\Y")); - vector A = mk.inport_vec("\\A", width); - vector B = mk.inport_vec("\\B", width); - int carry = mk.inport("\\CI"); - int binv = mk.inport("\\BI"); + int width = GetSize(cell->getPort(ID(Y))); + vector A = mk.inport_vec(ID(A), width); + vector B = mk.inport_vec(ID(B), width); + int carry = mk.inport(ID(CI)); + int binv = mk.inport(ID(BI)); for (auto &n : B) n = mk.xor_gate(n, binv); vector X(width), CO(width); vector Y = mk.adder(A, B, carry, &X, &CO); for (int i = 0; i < width; i++) X[i] = mk.xor_gate(A[i], B[i]); - mk.outport_vec(Y, "\\Y"); - mk.outport_vec(X, "\\X"); - mk.outport_vec(CO, "\\CO"); + mk.outport_vec(Y, ID(Y)); + mk.outport_vec(X, ID(X)); + mk.outport_vec(CO, ID(CO)); goto optimize; } - if (cell->type.in("$eq", "$ne")) + if (cell->type.in(ID($eq), ID($ne))) { - int width = max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B"))); - vector A = mk.inport_vec("\\A", width); - vector B = mk.inport_vec("\\B", width); + int width = max(GetSize(cell->getPort(ID(A))), GetSize(cell->getPort(ID(B)))); + vector A = mk.inport_vec(ID(A), width); + vector B = mk.inport_vec(ID(B), width); int Y = mk.bool_node(false); for (int i = 0; i < width; i++) Y = mk.or_gate(Y, mk.xor_gate(A[i], B[i])); - if (cell->type == "$eq") + if (cell->type == ID($eq)) Y = mk.not_gate(Y); - mk.outport_bool(Y, "\\Y"); + mk.outport_bool(Y, ID(Y)); goto optimize; } - if (cell->type == "$_AOI3_") + if (cell->type == ID($_AOI3_)) { - int A = mk.inport("\\A"); - int B = mk.inport("\\B"); - int C = mk.inport("\\C"); + int A = mk.inport(ID(A)); + int B = mk.inport(ID(B)); + int C = mk.inport(ID(C)); int Y = mk.nor_gate(mk.and_gate(A, B), C); - mk.outport(Y, "\\Y"); + mk.outport(Y, ID(Y)); goto optimize; } - if (cell->type == "$_OAI3_") + if (cell->type == ID($_OAI3_)) { - int A = mk.inport("\\A"); - int B = mk.inport("\\B"); - int C = mk.inport("\\C"); + int A = mk.inport(ID(A)); + int B = mk.inport(ID(B)); + int C = mk.inport(ID(C)); int Y = mk.nand_gate(mk.or_gate(A, B), C); - mk.outport(Y, "\\Y"); + mk.outport(Y, ID(Y)); goto optimize; } - if (cell->type == "$_AOI4_") + if (cell->type == ID($_AOI4_)) { - int A = mk.inport("\\A"); - int B = mk.inport("\\B"); - int C = mk.inport("\\C"); - int D = mk.inport("\\D"); + int A = mk.inport(ID(A)); + int B = mk.inport(ID(B)); + int C = mk.inport(ID(C)); + int D = mk.inport(ID(D)); int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D)); - mk.outport(Y, "\\Y"); + mk.outport(Y, ID(Y)); goto optimize; } - if (cell->type == "$_OAI4_") + if (cell->type == ID($_OAI4_)) { - int A = mk.inport("\\A"); - int B = mk.inport("\\B"); - int C = mk.inport("\\C"); - int D = mk.inport("\\D"); + int A = mk.inport(ID(A)); + int B = mk.inport(ID(B)); + int C = mk.inport(ID(C)); + int D = mk.inport(ID(D)); int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); - mk.outport(Y, "\\Y"); + mk.outport(Y, ID(Y)); goto optimize; } diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 556e8b826..7a324a06e 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -24,9 +24,9 @@ PRIVATE_NAMESPACE_BEGIN void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = "\\A", Y = "\\Y"; + IdString A = ID(A), Y = ID(Y); - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); int y_width = GetSize(cell->getPort(Y)); @@ -41,14 +41,14 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = "\\A", B = "\\B", Y = "\\Y"; + IdString A = ID(A), B = ID(B), Y = ID(Y); - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); int y_width = GetSize(cell->getPort(Y)); - if (cell->type == "$and" && !is_signed) { + if (cell->type == ID($and) && !is_signed) { if (a_width > b_width) a_width = b_width; else @@ -71,9 +71,9 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = "\\A", Y = "\\Y"; + IdString A = ID(A), Y = ID(Y); - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); int y_width = GetSize(cell->getPort(Y)); @@ -87,14 +87,14 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = "\\A", B = "\\B", Y = "\\Y"; + IdString A = ID(A), B = ID(B), Y = ID(Y); - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); int y_width = GetSize(cell->getPort(Y)); - if (!is_signed && cell->type != "$sub") { + if (!is_signed && cell->type != ID($sub)) { int ab_width = std::max(a_width, b_width); y_width = std::min(y_width, ab_width+1); } @@ -114,7 +114,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = "\\A", Y = "\\Y"; + IdString A = ID(A), Y = ID(Y); int a_width = GetSize(cell->getPort(A)); @@ -124,7 +124,7 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = "\\A", B = "\\B", Y = "\\Y"; + IdString A = ID(A), B = ID(B), Y = ID(Y); int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); @@ -138,7 +138,7 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y"; + IdString A = ID(A), B = ID(B), S = ID(S), Y = ID(Y); int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); @@ -160,43 +160,43 @@ PRIVATE_NAMESPACE_END bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell) { - if (cell->type.in("$not", "$pos")) { + if (cell->type.in(ID($not), ID($pos))) { bitwise_unary_op(this, cell); return true; } - if (cell->type.in("$and", "$or", "$xor", "$xnor")) { + if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { bitwise_binary_op(this, cell); return true; } - if (cell->type == "$neg") { + if (cell->type == ID($neg)) { arith_neg_op(this, cell); return true; } - if (cell->type.in("$add", "$sub")) { + if (cell->type.in(ID($add), ID($sub))) { arith_binary_op(this, cell); return true; } - if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", "$logic_not")) { + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not))) { reduce_op(this, cell); return true; } // FIXME: - // if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) { + // if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { // shift_op(this, cell); // return true; // } - if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) { + if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { compare_op(this, cell); return true; } - if (cell->type.in("$mux", "$pmux")) { + if (cell->type.in(ID($mux), ID($pmux))) { mux_op(this, cell); return true; } diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 1256fbcba..ade305e83 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -84,46 +84,46 @@ struct CellTypes { setup_internals_eval(); - IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y"; - IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT"; - IdString EN_SRC = "\\EN_SRC", EN_DST = "\\EN_DST"; - - setup_type("$tribuf", {A, EN}, {Y}, true); - - setup_type("$assert", {A, EN}, pool(), true); - setup_type("$assume", {A, EN}, pool(), true); - setup_type("$live", {A, EN}, pool(), true); - setup_type("$fair", {A, EN}, pool(), true); - setup_type("$cover", {A, EN}, pool(), true); - setup_type("$initstate", pool(), {Y}, true); - setup_type("$anyconst", pool(), {Y}, true); - setup_type("$anyseq", pool(), {Y}, true); - setup_type("$allconst", pool(), {Y}, true); - setup_type("$allseq", pool(), {Y}, true); - setup_type("$equiv", {A, B}, {Y}, true); - setup_type("$specify2", {EN, SRC, DST}, pool(), true); - setup_type("$specify3", {EN, SRC, DST, DAT}, pool(), true); - setup_type("$specrule", {EN_SRC, EN_DST, SRC, DST}, pool(), true); + IdString A = ID(A), B = ID(B), EN = ID(EN), Y = ID(Y); + IdString SRC = ID(SRC), DST = ID(DST), DAT = ID(DAT); + IdString EN_SRC = ID(EN_SRC), EN_DST = ID(EN_DST); + + setup_type(ID($tribuf), {A, EN}, {Y}, true); + + setup_type(ID($assert), {A, EN}, pool(), true); + setup_type(ID($assume), {A, EN}, pool(), true); + setup_type(ID($live), {A, EN}, pool(), true); + setup_type(ID($fair), {A, EN}, pool(), true); + setup_type(ID($cover), {A, EN}, pool(), true); + setup_type(ID($initstate), pool(), {Y}, true); + setup_type(ID($anyconst), pool(), {Y}, true); + setup_type(ID($anyseq), pool(), {Y}, true); + setup_type(ID($allconst), pool(), {Y}, true); + setup_type(ID($allseq), pool(), {Y}, true); + setup_type(ID($equiv), {A, B}, {Y}, true); + setup_type(ID($specify2), {EN, SRC, DST}, pool(), true); + setup_type(ID($specify3), {EN, SRC, DST, DAT}, pool(), true); + setup_type(ID($specrule), {EN_SRC, EN_DST, SRC, DST}, pool(), true); } void setup_internals_eval() { std::vector unary_ops = { - "$not", "$pos", "$neg", - "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", - "$logic_not", "$slice", "$lut", "$sop" + ID($not), ID($pos), ID($neg), + ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), + ID($logic_not), ID($slice), ID($lut), ID($sop) }; std::vector binary_ops = { - "$and", "$or", "$xor", "$xnor", - "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", - "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", - "$add", "$sub", "$mul", "$div", "$mod", "$pow", - "$logic_and", "$logic_or", "$concat", "$macc" + ID($and), ID($or), ID($xor), ID($xnor), + ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), + ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), + ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), + ID($logic_and), ID($logic_or), ID($concat), ID($macc) }; - IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y"; - IdString P = "\\P", G = "\\G", C = "\\C", X = "\\X"; - IdString BI = "\\BI", CI = "\\CI", CO = "\\CO", EN = "\\EN"; + IdString A = ID(A), B = ID(B), S = ID(S), Y = ID(Y); + IdString P = ID(P), G = ID(G), C = ID(C), X = ID(X); + IdString BI = ID(BI), CI = ID(CI), CO = ID(CO), EN = ID(EN); for (auto type : unary_ops) setup_type(type, {A}, {Y}, true); @@ -131,27 +131,27 @@ struct CellTypes for (auto type : binary_ops) setup_type(type, {A, B}, {Y}, true); - for (auto type : std::vector({"$mux", "$pmux"})) + for (auto type : std::vector({ID($mux), ID($pmux)})) setup_type(type, {A, B, S}, {Y}, true); - setup_type("$lcu", {P, G, CI}, {CO}, true); - setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true); - setup_type("$fa", {A, B, C}, {X, Y}, true); + setup_type(ID($lcu), {P, G, CI}, {CO}, true); + setup_type(ID($alu), {A, B, CI, BI}, {X, Y, CO}, true); + setup_type(ID($fa), {A, B, C}, {X, Y}, true); } void setup_internals_ff() { - IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN"; - IdString Q = "\\Q", D = "\\D"; - - setup_type("$sr", {SET, CLR}, {Q}); - setup_type("$ff", {D}, {Q}); - setup_type("$dff", {CLK, D}, {Q}); - setup_type("$dffe", {CLK, EN, D}, {Q}); - setup_type("$dffsr", {CLK, SET, CLR, D}, {Q}); - setup_type("$adff", {CLK, ARST, D}, {Q}); - setup_type("$dlatch", {EN, D}, {Q}); - setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q}); + IdString SET = ID(SET), CLR = ID(CLR), CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN); + IdString Q = ID(Q), D = ID(D); + + setup_type(ID($sr), {SET, CLR}, {Q}); + setup_type(ID($ff), {D}, {Q}); + setup_type(ID($dff), {CLK, D}, {Q}); + setup_type(ID($dffe), {CLK, EN, D}, {Q}); + setup_type(ID($dffsr), {CLK, SET, CLR, D}, {Q}); + setup_type(ID($adff), {CLK, ARST, D}, {Q}); + setup_type(ID($dlatch), {EN, D}, {Q}); + setup_type(ID($dlatchsr), {EN, SET, CLR, D}, {Q}); } @@ -159,63 +159,63 @@ struct CellTypes { setup_internals_ff(); - IdString CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN"; - IdString ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN"; - IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN"; - IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA"; - IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT"; + IdString CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN); + IdString ADDR = ID(ADDR), DATA = ID(DATA), RD_EN = ID(RD_EN); + IdString RD_CLK = ID(RD_CLK), RD_ADDR = ID(RD_ADDR), WR_CLK = ID(WR_CLK), WR_EN = ID(WR_EN); + IdString WR_ADDR = ID(WR_ADDR), WR_DATA = ID(WR_DATA), RD_DATA = ID(RD_DATA); + IdString CTRL_IN = ID(CTRL_IN), CTRL_OUT = ID(CTRL_OUT); - setup_type("$memrd", {CLK, EN, ADDR}, {DATA}); - setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool()); - setup_type("$meminit", {ADDR, DATA}, pool()); - setup_type("$mem", {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA}); + setup_type(ID($memrd), {CLK, EN, ADDR}, {DATA}); + setup_type(ID($memwr), {CLK, EN, ADDR, DATA}, pool()); + setup_type(ID($meminit), {ADDR, DATA}, pool()); + setup_type(ID($mem), {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA}); - setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT}); + setup_type(ID($fsm), {CLK, ARST, CTRL_IN}, {CTRL_OUT}); } void setup_stdcells() { setup_stdcells_eval(); - IdString A = "\\A", E = "\\E", Y = "\\Y"; + IdString A = ID(A), E = ID(E), Y = ID(Y); - setup_type("$_TBUF_", {A, E}, {Y}, true); + setup_type(ID($_TBUF_), {A, E}, {Y}, true); } void setup_stdcells_eval() { - IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D"; - IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H"; - IdString I = "\\I", J = "\\J", K = "\\K", L = "\\L"; - IdString M = "\\M", N = "\\N", O = "\\O", P = "\\P"; - IdString S = "\\S", T = "\\T", U = "\\U", V = "\\V"; - IdString Y = "\\Y"; - - setup_type("$_BUF_", {A}, {Y}, true); - setup_type("$_NOT_", {A}, {Y}, true); - setup_type("$_AND_", {A, B}, {Y}, true); - setup_type("$_NAND_", {A, B}, {Y}, true); - setup_type("$_OR_", {A, B}, {Y}, true); - setup_type("$_NOR_", {A, B}, {Y}, true); - setup_type("$_XOR_", {A, B}, {Y}, true); - setup_type("$_XNOR_", {A, B}, {Y}, true); - setup_type("$_ANDNOT_", {A, B}, {Y}, true); - setup_type("$_ORNOT_", {A, B}, {Y}, true); - setup_type("$_MUX_", {A, B, S}, {Y}, true); - setup_type("$_NMUX_", {A, B, S}, {Y}, true); - setup_type("$_MUX4_", {A, B, C, D, S, T}, {Y}, true); - setup_type("$_MUX8_", {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true); - setup_type("$_MUX16_", {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true); - setup_type("$_AOI3_", {A, B, C}, {Y}, true); - setup_type("$_OAI3_", {A, B, C}, {Y}, true); - setup_type("$_AOI4_", {A, B, C, D}, {Y}, true); - setup_type("$_OAI4_", {A, B, C, D}, {Y}, true); + IdString A = ID(A), B = ID(B), C = ID(C), D = ID(D); + IdString E = ID(E), F = ID(F), G = ID(G), H = ID(H); + IdString I = ID(I), J = ID(J), K = ID(K), L = ID(L); + IdString M = ID(M), N = ID(N), O = ID(O), P = ID(P); + IdString S = ID(S), T = ID(T), U = ID(U), V = ID(V); + IdString Y = ID(Y); + + setup_type(ID($_BUF_), {A}, {Y}, true); + setup_type(ID($_NOT_), {A}, {Y}, true); + setup_type(ID($_AND_), {A, B}, {Y}, true); + setup_type(ID($_NAND_), {A, B}, {Y}, true); + setup_type(ID($_OR_), {A, B}, {Y}, true); + setup_type(ID($_NOR_), {A, B}, {Y}, true); + setup_type(ID($_XOR_), {A, B}, {Y}, true); + setup_type(ID($_XNOR_), {A, B}, {Y}, true); + setup_type(ID($_ANDNOT_), {A, B}, {Y}, true); + setup_type(ID($_ORNOT_), {A, B}, {Y}, true); + setup_type(ID($_MUX_), {A, B, S}, {Y}, true); + setup_type(ID($_NMUX_), {A, B, S}, {Y}, true); + setup_type(ID($_MUX4_), {A, B, C, D, S, T}, {Y}, true); + setup_type(ID($_MUX8_), {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true); + setup_type(ID($_MUX16_), {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true); + setup_type(ID($_AOI3_), {A, B, C}, {Y}, true); + setup_type(ID($_OAI3_), {A, B, C}, {Y}, true); + setup_type(ID($_AOI4_), {A, B, C, D}, {Y}, true); + setup_type(ID($_OAI4_), {A, B, C, D}, {Y}, true); } void setup_stdcells_mem() { - IdString S = "\\S", R = "\\R", C = "\\C"; - IdString D = "\\D", Q = "\\Q", E = "\\E"; + IdString S = ID(S), R = ID(R), C = ID(C); + IdString D = ID(D), Q = ID(Q), E = ID(E); std::vector list_np = {'N', 'P'}, list_01 = {'0', '1'}; @@ -223,7 +223,7 @@ struct CellTypes for (auto c2 : list_np) setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q}); - setup_type("$_FF_", {D}, {Q}); + setup_type(ID($_FF_), {D}, {Q}); for (auto c1 : list_np) setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q}); @@ -289,13 +289,13 @@ struct CellTypes static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr) { - if (type == "$sshr" && !signed1) - type = "$shr"; - if (type == "$sshl" && !signed1) - type = "$shl"; + if (type == ID($sshr) && !signed1) + type = ID($shr); + if (type == ID($sshl) && !signed1) + type = ID($shl); - if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && type != "$shift" && type != "$shiftx" && - type != "$pos" && type != "$neg" && type != "$not") { + if (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) && + type != ID($pos) && type != ID($neg) && type != ID($not)) { if (!signed1 || !signed2) signed1 = false, signed2 = false; } @@ -338,25 +338,25 @@ struct CellTypes HANDLE_CELL_TYPE(neg) #undef HANDLE_CELL_TYPE - if (type == "$_BUF_") + if (type == ID($_BUF_)) return arg1; - if (type == "$_NOT_") + if (type == ID($_NOT_)) return eval_not(arg1); - if (type == "$_AND_") + if (type == ID($_AND_)) return const_and(arg1, arg2, false, false, 1); - if (type == "$_NAND_") + if (type == ID($_NAND_)) return eval_not(const_and(arg1, arg2, false, false, 1)); - if (type == "$_OR_") + if (type == ID($_OR_)) return const_or(arg1, arg2, false, false, 1); - if (type == "$_NOR_") + if (type == ID($_NOR_)) return eval_not(const_or(arg1, arg2, false, false, 1)); - if (type == "$_XOR_") + if (type == ID($_XOR_)) return const_xor(arg1, arg2, false, false, 1); - if (type == "$_XNOR_") + if (type == ID($_XNOR_)) return const_xnor(arg1, arg2, false, false, 1); - if (type == "$_ANDNOT_") + if (type == ID($_ANDNOT_)) return const_and(arg1, eval_not(arg2), false, false, 1); - if (type == "$_ORNOT_") + if (type == ID($_ORNOT_)) return const_or(arg1, eval_not(arg2), false, false, 1); if (errp != nullptr) { @@ -369,25 +369,25 @@ struct CellTypes static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr) { - if (cell->type == "$slice") { + if (cell->type == ID($slice)) { RTLIL::Const ret; - int width = cell->parameters.at("\\Y_WIDTH").as_int(); - int offset = cell->parameters.at("\\OFFSET").as_int(); + int width = cell->parameters.at(ID(Y_WIDTH)).as_int(); + int offset = cell->parameters.at(ID(OFFSET)).as_int(); ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width); return ret; } - if (cell->type == "$concat") { + if (cell->type == ID($concat)) { RTLIL::Const ret = arg1; ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end()); return ret; } - if (cell->type == "$lut") + if (cell->type == ID($lut)) { - int width = cell->parameters.at("\\WIDTH").as_int(); + int width = cell->parameters.at(ID(WIDTH)).as_int(); - std::vector t = cell->parameters.at("\\LUT").bits; + std::vector t = cell->parameters.at(ID(LUT)).bits; while (GetSize(t) < (1 << width)) t.push_back(State::S0); t.resize(1 << width); @@ -409,11 +409,11 @@ struct CellTypes return t; } - if (cell->type == "$sop") + if (cell->type == ID($sop)) { - int width = cell->parameters.at("\\WIDTH").as_int(); - int depth = cell->parameters.at("\\DEPTH").as_int(); - std::vector t = cell->parameters.at("\\TABLE").bits; + int width = cell->parameters.at(ID(WIDTH)).as_int(); + int depth = cell->parameters.at(ID(DEPTH)).as_int(); + std::vector t = cell->parameters.at(ID(TABLE)).bits; while (GetSize(t) < width*depth*2) t.push_back(State::S0); @@ -447,15 +447,15 @@ struct CellTypes return default_ret; } - bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); - bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool(); - int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1; + bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool(); + bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool(); + int result_len = cell->parameters.count(ID(Y_WIDTH)) > 0 ? cell->parameters[ID(Y_WIDTH)].as_int() : -1; return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp); } static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr) { - if (cell->type.in("$mux", "$pmux", "$_MUX_")) { + if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) { RTLIL::Const ret = arg1; for (size_t i = 0; i < arg3.bits.size(); i++) if (arg3.bits[i] == RTLIL::State::S1) { @@ -465,9 +465,9 @@ struct CellTypes return ret; } - if (cell->type == "$_AOI3_") + if (cell->type == ID($_AOI3_)) return eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1)); - if (cell->type == "$_OAI3_") + if (cell->type == ID($_OAI3_)) return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1)); log_assert(arg3.bits.size() == 0); @@ -476,9 +476,9 @@ struct CellTypes static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr) { - if (cell->type == "$_AOI4_") + if (cell->type == ID($_AOI4_)) return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); - if (cell->type == "$_OAI4_") + if (cell->type == ID($_OAI4_)) return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1)); log_assert(arg4.bits.size() == 0); diff --git a/kernel/consteval.h b/kernel/consteval.h index 521ce96d4..09b4c434b 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -89,12 +89,12 @@ struct ConstEval bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef) { - if (cell->type == "$lcu") + if (cell->type == ID($lcu)) { - RTLIL::SigSpec sig_p = cell->getPort("\\P"); - RTLIL::SigSpec sig_g = cell->getPort("\\G"); - RTLIL::SigSpec sig_ci = cell->getPort("\\CI"); - RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort("\\CO"))); + RTLIL::SigSpec sig_p = cell->getPort(ID(P)); + RTLIL::SigSpec sig_g = cell->getPort(ID(G)); + RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); + RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID(CO)))); if (sig_co.is_fully_const()) return true; @@ -128,24 +128,24 @@ struct ConstEval RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - log_assert(cell->hasPort("\\Y")); - sig_y = values_map(assign_map(cell->getPort("\\Y"))); + log_assert(cell->hasPort(ID(Y))); + sig_y = values_map(assign_map(cell->getPort(ID(Y)))); if (sig_y.is_fully_const()) return true; - if (cell->hasPort("\\S")) { - sig_s = cell->getPort("\\S"); + if (cell->hasPort(ID(S))) { + sig_s = cell->getPort(ID(S)); if (!eval(sig_s, undef, cell)) return false; } - if (cell->hasPort("\\A")) - sig_a = cell->getPort("\\A"); + if (cell->hasPort(ID(A))) + sig_a = cell->getPort(ID(A)); - if (cell->hasPort("\\B")) - sig_b = cell->getPort("\\B"); + if (cell->hasPort(ID(B))) + sig_b = cell->getPort(ID(B)); - if (cell->type.in("$mux", "$pmux", "$_MUX_", "$_NMUX_")) + if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_))) { std::vector y_candidates; int count_maybe_set_s_bits = 0; @@ -175,7 +175,7 @@ struct ConstEval for (auto &yc : y_candidates) { if (!eval(yc, undef, cell)) return false; - if (cell->type == "$_NMUX_") + if (cell->type == ID($_NMUX_)) y_values.push_back(RTLIL::const_not(yc.as_const(), Const(), false, false, GetSize(yc))); else y_values.push_back(yc.as_const()); @@ -198,10 +198,10 @@ struct ConstEval else set(sig_y, y_values.front()); } - else if (cell->type == "$fa") + else if (cell->type == ID($fa)) { - RTLIL::SigSpec sig_c = cell->getPort("\\C"); - RTLIL::SigSpec sig_x = cell->getPort("\\X"); + RTLIL::SigSpec sig_c = cell->getPort(ID(C)); + RTLIL::SigSpec sig_x = cell->getPort(ID(X)); int width = GetSize(sig_c); if (!eval(sig_a, undef, cell)) @@ -227,13 +227,13 @@ struct ConstEval set(sig_y, val_y); set(sig_x, val_x); } - else if (cell->type == "$alu") + else if (cell->type == ID($alu)) { - bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); - bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool(); + bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool(); + bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool(); - RTLIL::SigSpec sig_ci = cell->getPort("\\CI"); - RTLIL::SigSpec sig_bi = cell->getPort("\\BI"); + RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); + RTLIL::SigSpec sig_bi = cell->getPort(ID(BI)); if (!eval(sig_a, undef, cell)) return false; @@ -247,8 +247,8 @@ struct ConstEval if (!eval(sig_bi, undef, cell)) return false; - RTLIL::SigSpec sig_x = cell->getPort("\\X"); - RTLIL::SigSpec sig_co = cell->getPort("\\CO"); + RTLIL::SigSpec sig_x = cell->getPort(ID(X)); + RTLIL::SigSpec sig_co = cell->getPort(ID(CO)); bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def()); sig_a.extend_u0(GetSize(sig_y), signed_a); @@ -283,7 +283,7 @@ struct ConstEval } } } - else if (cell->type == "$macc") + else if (cell->type == ID($macc)) { Macc macc; macc.from_cell(cell); @@ -298,21 +298,21 @@ struct ConstEval return false; } - RTLIL::Const result(0, GetSize(cell->getPort("\\Y"))); + RTLIL::Const result(0, GetSize(cell->getPort(ID(Y)))); if (!macc.eval(result)) log_abort(); - set(cell->getPort("\\Y"), result); + set(cell->getPort(ID(Y)), result); } else { RTLIL::SigSpec sig_c, sig_d; - if (cell->type.in("$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_")) { - if (cell->hasPort("\\C")) - sig_c = cell->getPort("\\C"); - if (cell->hasPort("\\D")) - sig_d = cell->getPort("\\D"); + if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { + if (cell->hasPort(ID(C))) + sig_c = cell->getPort(ID(C)); + if (cell->hasPort(ID(D))) + sig_d = cell->getPort(ID(D)); } if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) diff --git a/kernel/cost.h b/kernel/cost.h index 10fa50fb3..ea2a4c1f0 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -28,44 +28,44 @@ struct CellCosts { static const dict& default_gate_cost() { static const dict db = { - { "$_BUF_", 1 }, - { "$_NOT_", 2 }, - { "$_AND_", 4 }, - { "$_NAND_", 4 }, - { "$_OR_", 4 }, - { "$_NOR_", 4 }, - { "$_ANDNOT_", 4 }, - { "$_ORNOT_", 4 }, - { "$_XOR_", 5 }, - { "$_XNOR_", 5 }, - { "$_AOI3_", 6 }, - { "$_OAI3_", 6 }, - { "$_AOI4_", 7 }, - { "$_OAI4_", 7 }, - { "$_MUX_", 4 }, - { "$_NMUX_", 4 } + { ID($_BUF_), 1 }, + { ID($_NOT_), 2 }, + { ID($_AND_), 4 }, + { ID($_NAND_), 4 }, + { ID($_OR_), 4 }, + { ID($_NOR_), 4 }, + { ID($_ANDNOT_), 4 }, + { ID($_ORNOT_), 4 }, + { ID($_XOR_), 5 }, + { ID($_XNOR_), 5 }, + { ID($_AOI3_), 6 }, + { ID($_OAI3_), 6 }, + { ID($_AOI4_), 7 }, + { ID($_OAI4_), 7 }, + { ID($_MUX_), 4 }, + { ID($_NMUX_), 4 } }; return db; } static const dict& cmos_gate_cost() { static const dict db = { - { "$_BUF_", 1 }, - { "$_NOT_", 2 }, - { "$_AND_", 6 }, - { "$_NAND_", 4 }, - { "$_OR_", 6 }, - { "$_NOR_", 4 }, - { "$_ANDNOT_", 6 }, - { "$_ORNOT_", 6 }, - { "$_XOR_", 12 }, - { "$_XNOR_", 12 }, - { "$_AOI3_", 6 }, - { "$_OAI3_", 6 }, - { "$_AOI4_", 8 }, - { "$_OAI4_", 8 }, - { "$_MUX_", 12 }, - { "$_NMUX_", 10 } + { ID($_BUF_), 1 }, + { ID($_NOT_), 2 }, + { ID($_AND_), 6 }, + { ID($_NAND_), 4 }, + { ID($_OR_), 6 }, + { ID($_NOR_), 4 }, + { ID($_ANDNOT_), 6 }, + { ID($_ORNOT_), 6 }, + { ID($_XOR_), 12 }, + { ID($_XNOR_), 12 }, + { ID($_AOI3_), 6 }, + { ID($_OAI3_), 6 }, + { ID($_AOI4_), 8 }, + { ID($_OAI4_), 8 }, + { ID($_MUX_), 12 }, + { ID($_NMUX_), 10 } }; return db; } @@ -92,8 +92,8 @@ struct CellCosts { RTLIL::Module *mod = design->module(cell->type); - if (mod->attributes.count("\\cost")) - return mod->attributes.at("\\cost").as_int(); + if (mod->attributes.count(ID(cost))) + return mod->attributes.at(ID(cost)).as_int(); if (mod_cost_cache.count(mod->name)) return mod_cost_cache.at(mod->name); diff --git a/kernel/macc.h b/kernel/macc.h index c7595ebc1..e07e7e01a 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -99,16 +99,16 @@ struct Macc void from_cell(RTLIL::Cell *cell) { - RTLIL::SigSpec port_a = cell->getPort("\\A"); + RTLIL::SigSpec port_a = cell->getPort(ID(A)); ports.clear(); - bit_ports = cell->getPort("\\B"); + bit_ports = cell->getPort(ID(B)); - std::vector config_bits = cell->getParam("\\CONFIG").bits; + std::vector config_bits = cell->getParam(ID(CONFIG)).bits; int config_cursor = 0; #ifndef NDEBUG - int config_width = cell->getParam("\\CONFIG_WIDTH").as_int(); + int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int(); log_assert(GetSize(config_bits) >= config_width); #endif @@ -191,12 +191,12 @@ struct Macc port_a.append(port.in_b); } - cell->setPort("\\A", port_a); - cell->setPort("\\B", bit_ports); - cell->setParam("\\CONFIG", config_bits); - cell->setParam("\\CONFIG_WIDTH", GetSize(config_bits)); - cell->setParam("\\A_WIDTH", GetSize(port_a)); - cell->setParam("\\B_WIDTH", GetSize(bit_ports)); + cell->setPort(ID(A), port_a); + cell->setPort(ID(B), bit_ports); + cell->setParam(ID(CONFIG), config_bits); + cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); + cell->setParam(ID(A_WIDTH), GetSize(port_a)); + cell->setParam(ID(B_WIDTH), GetSize(bit_ports)); } bool eval(RTLIL::Const &result) const diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 91b6a1d30..30560dd7b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -38,6 +38,13 @@ int RTLIL::IdString::last_created_idx_[8]; int RTLIL::IdString::last_created_idx_ptr_; #endif +IdString RTLIL::ID::A; +IdString RTLIL::ID::B; +IdString RTLIL::ID::Y; +IdString RTLIL::ID::keep; +IdString RTLIL::ID::whitebox; +IdString RTLIL::ID::blackbox; + RTLIL::Const::Const() { flags = RTLIL::CONST_FLAG_NONE; @@ -266,16 +273,16 @@ pool RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const void RTLIL::AttrObject::set_src_attribute(const std::string &src) { if (src.empty()) - attributes.erase("\\src"); + attributes.erase(ID(src)); else - attributes["\\src"] = src; + attributes[ID(src)] = src; } std::string RTLIL::AttrObject::get_src_attribute() const { std::string src; - if (attributes.count("\\src")) - src = attributes.at("\\src").decode_string(); + if (attributes.count(ID(src))) + src = attributes.at(ID(src)).decode_string(); return src; } @@ -419,7 +426,7 @@ RTLIL::Module *RTLIL::Design::top_module() int module_count = 0; for (auto mod : selected_modules()) { - if (mod->get_bool_attribute("\\top")) + if (mod->get_bool_attribute(ID(top))) return mod; module_count++; module = mod; @@ -708,7 +715,7 @@ void RTLIL::Module::makeblackbox() processes.clear(); remove(delwires); - set_bool_attribute("\\blackbox"); + set_bool_attribute(ID(blackbox)); } void RTLIL::Module::reprocess_module(RTLIL::Design *, dict) @@ -756,7 +763,7 @@ namespace { cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str()); } - int param(const char *name) + int param(RTLIL::IdString name) { if (cell->parameters.count(name) == 0) error(__LINE__); @@ -764,7 +771,7 @@ namespace { return cell->parameters.at(name).as_int(); } - int param_bool(const char *name) + int param_bool(RTLIL::IdString name) { int v = param(name); if (cell->parameters.at(name).bits.size() > 32) @@ -774,14 +781,14 @@ namespace { return v; } - void param_bits(const char *name, int width) + void param_bits(RTLIL::IdString name, int width) { param(name); if (int(cell->parameters.at(name).bits.size()) != width) error(__LINE__); } - void port(const char *name, int width) + void port(RTLIL::IdString name, int width) { if (!cell->hasPort(name)) error(__LINE__); @@ -799,9 +806,9 @@ namespace { if (expected_ports.count(conn.first) == 0) error(__LINE__); - if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) { - bool a_is_signed = param("\\A_SIGNED") != 0; - bool b_is_signed = param("\\B_SIGNED") != 0; + if (expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) && check_matched_sign) { + bool a_is_signed = param(ID(A_SIGNED)) != 0; + bool b_is_signed = param(ID(B_SIGNED)) != 0; if (a_is_signed != b_is_signed) error(__LINE__); } @@ -834,478 +841,478 @@ namespace { cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:")) return; - if (cell->type.in("$not", "$pos", "$neg")) { - param_bool("\\A_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); + if (cell->type.in(ID($not), ID($pos), ID($neg))) { + param_bool(ID(A_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); check_expected(); return; } - if (cell->type.in("$and", "$or", "$xor", "$xnor")) { - param_bool("\\A_SIGNED"); - param_bool("\\B_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\B", param("\\B_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); + if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { + param_bool(ID(A_SIGNED)); + param_bool(ID(B_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(B), param(ID(B_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); check_expected(); return; } - if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) { - param_bool("\\A_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { + param_bool(ID(A_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); check_expected(); return; } - if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) { - param_bool("\\A_SIGNED"); - param_bool("\\B_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\B", param("\\B_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); + if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { + param_bool(ID(A_SIGNED)); + param_bool(ID(B_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(B), param(ID(B_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); check_expected(false); return; } - if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) { - param_bool("\\A_SIGNED"); - param_bool("\\B_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\B", param("\\B_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); + if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { + param_bool(ID(A_SIGNED)); + param_bool(ID(B_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(B), param(ID(B_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); check_expected(); return; } - if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) { - param_bool("\\A_SIGNED"); - param_bool("\\B_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\B", param("\\B_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); - check_expected(cell->type != "$pow"); + if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) { + param_bool(ID(A_SIGNED)); + param_bool(ID(B_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(B), param(ID(B_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); + check_expected(cell->type != ID($pow)); return; } - if (cell->type == "$fa") { - port("\\A", param("\\WIDTH")); - port("\\B", param("\\WIDTH")); - port("\\C", param("\\WIDTH")); - port("\\X", param("\\WIDTH")); - port("\\Y", param("\\WIDTH")); + if (cell->type == ID($fa)) { + port(ID(A), param(ID(WIDTH))); + port(ID(B), param(ID(WIDTH))); + port(ID(C), param(ID(WIDTH))); + port(ID(X), param(ID(WIDTH))); + port(ID(Y), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$lcu") { - port("\\P", param("\\WIDTH")); - port("\\G", param("\\WIDTH")); - port("\\CI", 1); - port("\\CO", param("\\WIDTH")); + if (cell->type == ID($lcu)) { + port(ID(P), param(ID(WIDTH))); + port(ID(G), param(ID(WIDTH))); + port(ID(CI), 1); + port(ID(CO), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$alu") { - param_bool("\\A_SIGNED"); - param_bool("\\B_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\B", param("\\B_WIDTH")); - port("\\CI", 1); - port("\\BI", 1); - port("\\X", param("\\Y_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); - port("\\CO", param("\\Y_WIDTH")); + if (cell->type == ID($alu)) { + param_bool(ID(A_SIGNED)); + param_bool(ID(B_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(B), param(ID(B_WIDTH))); + port(ID(CI), 1); + port(ID(BI), 1); + port(ID(X), param(ID(Y_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); + port(ID(CO), param(ID(Y_WIDTH))); check_expected(); return; } - if (cell->type == "$macc") { - param("\\CONFIG"); - param("\\CONFIG_WIDTH"); - port("\\A", param("\\A_WIDTH")); - port("\\B", param("\\B_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); + if (cell->type == ID($macc)) { + param(ID(CONFIG)); + param(ID(CONFIG_WIDTH)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(B), param(ID(B_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); check_expected(); Macc().from_cell(cell); return; } - if (cell->type == "$logic_not") { - param_bool("\\A_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); + if (cell->type == ID($logic_not)) { + param_bool(ID(A_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); check_expected(); return; } - if (cell->type.in("$logic_and", "$logic_or")) { - param_bool("\\A_SIGNED"); - param_bool("\\B_SIGNED"); - port("\\A", param("\\A_WIDTH")); - port("\\B", param("\\B_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); + if (cell->type.in(ID($logic_and), ID($logic_or))) { + param_bool(ID(A_SIGNED)); + param_bool(ID(B_SIGNED)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(B), param(ID(B_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); check_expected(false); return; } - if (cell->type == "$slice") { - param("\\OFFSET"); - port("\\A", param("\\A_WIDTH")); - port("\\Y", param("\\Y_WIDTH")); - if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH")) + if (cell->type == ID($slice)) { + param(ID(OFFSET)); + port(ID(A), param(ID(A_WIDTH))); + port(ID(Y), param(ID(Y_WIDTH))); + if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH))) error(__LINE__); check_expected(); return; } - if (cell->type == "$concat") { - port("\\A", param("\\A_WIDTH")); - port("\\B", param("\\B_WIDTH")); - port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH")); + if (cell->type == ID($concat)) { + port(ID(A), param(ID(A_WIDTH))); + port(ID(B), param(ID(B_WIDTH))); + port(ID(Y), param(ID(A_WIDTH)) + param(ID(B_WIDTH))); check_expected(); return; } - if (cell->type == "$mux") { - port("\\A", param("\\WIDTH")); - port("\\B", param("\\WIDTH")); - port("\\S", 1); - port("\\Y", param("\\WIDTH")); + if (cell->type == ID($mux)) { + port(ID(A), param(ID(WIDTH))); + port(ID(B), param(ID(WIDTH))); + port(ID(S), 1); + port(ID(Y), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$pmux") { - port("\\A", param("\\WIDTH")); - port("\\B", param("\\WIDTH") * param("\\S_WIDTH")); - port("\\S", param("\\S_WIDTH")); - port("\\Y", param("\\WIDTH")); + if (cell->type == ID($pmux)) { + port(ID(A), param(ID(WIDTH))); + port(ID(B), param(ID(WIDTH)) * param(ID(S_WIDTH))); + port(ID(S), param(ID(S_WIDTH))); + port(ID(Y), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$lut") { - param("\\LUT"); - port("\\A", param("\\WIDTH")); - port("\\Y", 1); + if (cell->type == ID($lut)) { + param(ID(LUT)); + port(ID(A), param(ID(WIDTH))); + port(ID(Y), 1); check_expected(); return; } - if (cell->type == "$sop") { - param("\\DEPTH"); - param("\\TABLE"); - port("\\A", param("\\WIDTH")); - port("\\Y", 1); + if (cell->type == ID($sop)) { + param(ID(DEPTH)); + param(ID(TABLE)); + port(ID(A), param(ID(WIDTH))); + port(ID(Y), 1); check_expected(); return; } - if (cell->type == "$sr") { - param_bool("\\SET_POLARITY"); - param_bool("\\CLR_POLARITY"); - port("\\SET", param("\\WIDTH")); - port("\\CLR", param("\\WIDTH")); - port("\\Q", param("\\WIDTH")); + if (cell->type == ID($sr)) { + param_bool(ID(SET_POLARITY)); + param_bool(ID(CLR_POLARITY)); + port(ID(SET), param(ID(WIDTH))); + port(ID(CLR), param(ID(WIDTH))); + port(ID(Q), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$ff") { - port("\\D", param("\\WIDTH")); - port("\\Q", param("\\WIDTH")); + if (cell->type == ID($ff)) { + port(ID(D), param(ID(WIDTH))); + port(ID(Q), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$dff") { - param_bool("\\CLK_POLARITY"); - port("\\CLK", 1); - port("\\D", param("\\WIDTH")); - port("\\Q", param("\\WIDTH")); + if (cell->type == ID($dff)) { + param_bool(ID(CLK_POLARITY)); + port(ID(CLK), 1); + port(ID(D), param(ID(WIDTH))); + port(ID(Q), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$dffe") { - param_bool("\\CLK_POLARITY"); - param_bool("\\EN_POLARITY"); - port("\\CLK", 1); - port("\\EN", 1); - port("\\D", param("\\WIDTH")); - port("\\Q", param("\\WIDTH")); + if (cell->type == ID($dffe)) { + param_bool(ID(CLK_POLARITY)); + param_bool(ID(EN_POLARITY)); + port(ID(CLK), 1); + port(ID(EN), 1); + port(ID(D), param(ID(WIDTH))); + port(ID(Q), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$dffsr") { - param_bool("\\CLK_POLARITY"); - param_bool("\\SET_POLARITY"); - param_bool("\\CLR_POLARITY"); - port("\\CLK", 1); - port("\\SET", param("\\WIDTH")); - port("\\CLR", param("\\WIDTH")); - port("\\D", param("\\WIDTH")); - port("\\Q", param("\\WIDTH")); + if (cell->type == ID($dffsr)) { + param_bool(ID(CLK_POLARITY)); + param_bool(ID(SET_POLARITY)); + param_bool(ID(CLR_POLARITY)); + port(ID(CLK), 1); + port(ID(SET), param(ID(WIDTH))); + port(ID(CLR), param(ID(WIDTH))); + port(ID(D), param(ID(WIDTH))); + port(ID(Q), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$adff") { - param_bool("\\CLK_POLARITY"); - param_bool("\\ARST_POLARITY"); - param_bits("\\ARST_VALUE", param("\\WIDTH")); - port("\\CLK", 1); - port("\\ARST", 1); - port("\\D", param("\\WIDTH")); - port("\\Q", param("\\WIDTH")); + if (cell->type == ID($adff)) { + param_bool(ID(CLK_POLARITY)); + param_bool(ID(ARST_POLARITY)); + param_bits(ID(ARST_VALUE), param(ID(WIDTH))); + port(ID(CLK), 1); + port(ID(ARST), 1); + port(ID(D), param(ID(WIDTH))); + port(ID(Q), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$dlatch") { - param_bool("\\EN_POLARITY"); - port("\\EN", 1); - port("\\D", param("\\WIDTH")); - port("\\Q", param("\\WIDTH")); + if (cell->type == ID($dlatch)) { + param_bool(ID(EN_POLARITY)); + port(ID(EN), 1); + port(ID(D), param(ID(WIDTH))); + port(ID(Q), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$dlatchsr") { - param_bool("\\EN_POLARITY"); - param_bool("\\SET_POLARITY"); - param_bool("\\CLR_POLARITY"); - port("\\EN", 1); - port("\\SET", param("\\WIDTH")); - port("\\CLR", param("\\WIDTH")); - port("\\D", param("\\WIDTH")); - port("\\Q", param("\\WIDTH")); + if (cell->type == ID($dlatchsr)) { + param_bool(ID(EN_POLARITY)); + param_bool(ID(SET_POLARITY)); + param_bool(ID(CLR_POLARITY)); + port(ID(EN), 1); + port(ID(SET), param(ID(WIDTH))); + port(ID(CLR), param(ID(WIDTH))); + port(ID(D), param(ID(WIDTH))); + port(ID(Q), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$fsm") { - param("\\NAME"); - param_bool("\\CLK_POLARITY"); - param_bool("\\ARST_POLARITY"); - param("\\STATE_BITS"); - param("\\STATE_NUM"); - param("\\STATE_NUM_LOG2"); - param("\\STATE_RST"); - param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM")); - param("\\TRANS_NUM"); - param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH"))); - port("\\CLK", 1); - port("\\ARST", 1); - port("\\CTRL_IN", param("\\CTRL_IN_WIDTH")); - port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH")); + if (cell->type == ID($fsm)) { + param(ID(NAME)); + param_bool(ID(CLK_POLARITY)); + param_bool(ID(ARST_POLARITY)); + param(ID(STATE_BITS)); + param(ID(STATE_NUM)); + param(ID(STATE_NUM_LOG2)); + param(ID(STATE_RST)); + param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM))); + param(ID(TRANS_NUM)); + param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH)))); + port(ID(CLK), 1); + port(ID(ARST), 1); + port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH))); + port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH))); check_expected(); return; } - if (cell->type == "$memrd") { - param("\\MEMID"); - param_bool("\\CLK_ENABLE"); - param_bool("\\CLK_POLARITY"); - param_bool("\\TRANSPARENT"); - port("\\CLK", 1); - port("\\EN", 1); - port("\\ADDR", param("\\ABITS")); - port("\\DATA", param("\\WIDTH")); + if (cell->type == ID($memrd)) { + param(ID(MEMID)); + param_bool(ID(CLK_ENABLE)); + param_bool(ID(CLK_POLARITY)); + param_bool(ID(TRANSPARENT)); + port(ID(CLK), 1); + port(ID(EN), 1); + port(ID(ADDR), param(ID(ABITS))); + port(ID(DATA), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$memwr") { - param("\\MEMID"); - param_bool("\\CLK_ENABLE"); - param_bool("\\CLK_POLARITY"); - param("\\PRIORITY"); - port("\\CLK", 1); - port("\\EN", param("\\WIDTH")); - port("\\ADDR", param("\\ABITS")); - port("\\DATA", param("\\WIDTH")); + if (cell->type == ID($memwr)) { + param(ID(MEMID)); + param_bool(ID(CLK_ENABLE)); + param_bool(ID(CLK_POLARITY)); + param(ID(PRIORITY)); + port(ID(CLK), 1); + port(ID(EN), param(ID(WIDTH))); + port(ID(ADDR), param(ID(ABITS))); + port(ID(DATA), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$meminit") { - param("\\MEMID"); - param("\\PRIORITY"); - port("\\ADDR", param("\\ABITS")); - port("\\DATA", param("\\WIDTH") * param("\\WORDS")); + if (cell->type == ID($meminit)) { + param(ID(MEMID)); + param(ID(PRIORITY)); + port(ID(ADDR), param(ID(ABITS))); + port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS))); check_expected(); return; } - if (cell->type == "$mem") { - param("\\MEMID"); - param("\\SIZE"); - param("\\OFFSET"); - param("\\INIT"); - param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS"))); - param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS"))); - param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS"))); - param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS"))); - param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS"))); - port("\\RD_CLK", param("\\RD_PORTS")); - port("\\RD_EN", param("\\RD_PORTS")); - port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS")); - port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH")); - port("\\WR_CLK", param("\\WR_PORTS")); - port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH")); - port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS")); - port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH")); + if (cell->type == ID($mem)) { + param(ID(MEMID)); + param(ID(SIZE)); + param(ID(OFFSET)); + param(ID(INIT)); + param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS)))); + param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS)))); + param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS)))); + param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS)))); + param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS)))); + port(ID(RD_CLK), param(ID(RD_PORTS))); + port(ID(RD_EN), param(ID(RD_PORTS))); + port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS))); + port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH))); + port(ID(WR_CLK), param(ID(WR_PORTS))); + port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH))); + port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS))); + port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$tribuf") { - port("\\A", param("\\WIDTH")); - port("\\Y", param("\\WIDTH")); - port("\\EN", 1); + if (cell->type == ID($tribuf)) { + port(ID(A), param(ID(WIDTH))); + port(ID(Y), param(ID(WIDTH))); + port(ID(EN), 1); check_expected(); return; } - if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) { - port("\\A", 1); - port("\\EN", 1); + if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) { + port(ID(A), 1); + port(ID(EN), 1); check_expected(); return; } - if (cell->type == "$initstate") { - port("\\Y", 1); + if (cell->type == ID($initstate)) { + port(ID(Y), 1); check_expected(); return; } - if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) { - port("\\Y", param("\\WIDTH")); + if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) { + port(ID(Y), param(ID(WIDTH))); check_expected(); return; } - if (cell->type == "$equiv") { - port("\\A", 1); - port("\\B", 1); - port("\\Y", 1); + if (cell->type == ID($equiv)) { + port(ID(A), 1); + port(ID(B), 1); + port(ID(Y), 1); check_expected(); return; } - if (cell->type.in("$specify2", "$specify3")) { - param_bool("\\FULL"); - param_bool("\\SRC_DST_PEN"); - param_bool("\\SRC_DST_POL"); - param("\\T_RISE_MIN"); - param("\\T_RISE_TYP"); - param("\\T_RISE_MAX"); - param("\\T_FALL_MIN"); - param("\\T_FALL_TYP"); - param("\\T_FALL_MAX"); - port("\\EN", 1); - port("\\SRC", param("\\SRC_WIDTH")); - port("\\DST", param("\\DST_WIDTH")); - if (cell->type == "$specify3") { - param_bool("\\EDGE_EN"); - param_bool("\\EDGE_POL"); - param_bool("\\DAT_DST_PEN"); - param_bool("\\DAT_DST_POL"); - port("\\DAT", param("\\DST_WIDTH")); + if (cell->type.in(ID($specify2), ID($specify3))) { + param_bool(ID(FULL)); + param_bool(ID(SRC_DST_PEN)); + param_bool(ID(SRC_DST_POL)); + param(ID(T_RISE_MIN)); + param(ID(T_RISE_TYP)); + param(ID(T_RISE_MAX)); + param(ID(T_FALL_MIN)); + param(ID(T_FALL_TYP)); + param(ID(T_FALL_MAX)); + port(ID(EN), 1); + port(ID(SRC), param(ID(SRC_WIDTH))); + port(ID(DST), param(ID(DST_WIDTH))); + if (cell->type == ID($specify3)) { + param_bool(ID(EDGE_EN)); + param_bool(ID(EDGE_POL)); + param_bool(ID(DAT_DST_PEN)); + param_bool(ID(DAT_DST_POL)); + port(ID(DAT), param(ID(DST_WIDTH))); } check_expected(); return; } - if (cell->type == "$specrule") { - param("\\TYPE"); - param_bool("\\SRC_PEN"); - param_bool("\\SRC_POL"); - param_bool("\\DST_PEN"); - param_bool("\\DST_POL"); - param("\\T_LIMIT"); - param("\\T_LIMIT2"); - port("\\SRC_EN", 1); - port("\\DST_EN", 1); - port("\\SRC", param("\\SRC_WIDTH")); - port("\\DST", param("\\DST_WIDTH")); + if (cell->type == ID($specrule)) { + param(ID(TYPE)); + param_bool(ID(SRC_PEN)); + param_bool(ID(SRC_POL)); + param_bool(ID(DST_PEN)); + param_bool(ID(DST_POL)); + param(ID(T_LIMIT)); + param(ID(T_LIMIT2)); + port(ID(SRC_EN), 1); + port(ID(DST_EN), 1); + port(ID(SRC), param(ID(SRC_WIDTH))); + port(ID(DST), param(ID(DST_WIDTH))); check_expected(); return; } - if (cell->type == "$_BUF_") { check_gate("AY"); return; } - if (cell->type == "$_NOT_") { check_gate("AY"); return; } - if (cell->type == "$_AND_") { check_gate("ABY"); return; } - if (cell->type == "$_NAND_") { check_gate("ABY"); return; } - if (cell->type == "$_OR_") { check_gate("ABY"); return; } - if (cell->type == "$_NOR_") { check_gate("ABY"); return; } - if (cell->type == "$_XOR_") { check_gate("ABY"); return; } - if (cell->type == "$_XNOR_") { check_gate("ABY"); return; } - if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; } - if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; } - if (cell->type == "$_MUX_") { check_gate("ABSY"); return; } - if (cell->type == "$_NMUX_") { check_gate("ABSY"); return; } - if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; } - if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; } - if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; } - if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; } - - if (cell->type == "$_TBUF_") { check_gate("AYE"); return; } - - if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; } - if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; } - if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; } - - if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; } - if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; } - if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; } - if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; } - - if (cell->type == "$_FF_") { check_gate("DQ"); return; } - if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; } - if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; } - - if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; } - if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; } - if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; } - if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; } - - if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; } - if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; } - if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; } - if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; } - if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; } - if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; } - if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; } - if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; } - - if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; } - if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; } - if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; } - if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; } - if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; } - if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; } - if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; } - if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; } - - if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; } - if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; } - - if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; } - if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; } - if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; } - if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; } - if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; } - if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; } - if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; } - if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; } + if (cell->type == ID($_BUF_)) { check_gate("AY"); return; } + if (cell->type == ID($_NOT_)) { check_gate("AY"); return; } + if (cell->type == ID($_AND_)) { check_gate("ABY"); return; } + if (cell->type == ID($_NAND_)) { check_gate("ABY"); return; } + if (cell->type == ID($_OR_)) { check_gate("ABY"); return; } + if (cell->type == ID($_NOR_)) { check_gate("ABY"); return; } + if (cell->type == ID($_XOR_)) { check_gate("ABY"); return; } + if (cell->type == ID($_XNOR_)) { check_gate("ABY"); return; } + if (cell->type == ID($_ANDNOT_)) { check_gate("ABY"); return; } + if (cell->type == ID($_ORNOT_)) { check_gate("ABY"); return; } + if (cell->type == ID($_MUX_)) { check_gate("ABSY"); return; } + if (cell->type == ID($_NMUX_)) { check_gate("ABSY"); return; } + if (cell->type == ID($_AOI3_)) { check_gate("ABCY"); return; } + if (cell->type == ID($_OAI3_)) { check_gate("ABCY"); return; } + if (cell->type == ID($_AOI4_)) { check_gate("ABCDY"); return; } + if (cell->type == ID($_OAI4_)) { check_gate("ABCDY"); return; } + + if (cell->type == ID($_TBUF_)) { check_gate("AYE"); return; } + + if (cell->type == ID($_MUX4_)) { check_gate("ABCDSTY"); return; } + if (cell->type == ID($_MUX8_)) { check_gate("ABCDEFGHSTUY"); return; } + if (cell->type == ID($_MUX16_)) { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; } + + if (cell->type == ID($_SR_NN_)) { check_gate("SRQ"); return; } + if (cell->type == ID($_SR_NP_)) { check_gate("SRQ"); return; } + if (cell->type == ID($_SR_PN_)) { check_gate("SRQ"); return; } + if (cell->type == ID($_SR_PP_)) { check_gate("SRQ"); return; } + + if (cell->type == ID($_FF_)) { check_gate("DQ"); return; } + if (cell->type == ID($_DFF_N_)) { check_gate("DQC"); return; } + if (cell->type == ID($_DFF_P_)) { check_gate("DQC"); return; } + + if (cell->type == ID($_DFFE_NN_)) { check_gate("DQCE"); return; } + if (cell->type == ID($_DFFE_NP_)) { check_gate("DQCE"); return; } + if (cell->type == ID($_DFFE_PN_)) { check_gate("DQCE"); return; } + if (cell->type == ID($_DFFE_PP_)) { check_gate("DQCE"); return; } + + if (cell->type == ID($_DFF_NN0_)) { check_gate("DQCR"); return; } + if (cell->type == ID($_DFF_NN1_)) { check_gate("DQCR"); return; } + if (cell->type == ID($_DFF_NP0_)) { check_gate("DQCR"); return; } + if (cell->type == ID($_DFF_NP1_)) { check_gate("DQCR"); return; } + if (cell->type == ID($_DFF_PN0_)) { check_gate("DQCR"); return; } + if (cell->type == ID($_DFF_PN1_)) { check_gate("DQCR"); return; } + if (cell->type == ID($_DFF_PP0_)) { check_gate("DQCR"); return; } + if (cell->type == ID($_DFF_PP1_)) { check_gate("DQCR"); return; } + + if (cell->type == ID($_DFFSR_NNN_)) { check_gate("CSRDQ"); return; } + if (cell->type == ID($_DFFSR_NNP_)) { check_gate("CSRDQ"); return; } + if (cell->type == ID($_DFFSR_NPN_)) { check_gate("CSRDQ"); return; } + if (cell->type == ID($_DFFSR_NPP_)) { check_gate("CSRDQ"); return; } + if (cell->type == ID($_DFFSR_PNN_)) { check_gate("CSRDQ"); return; } + if (cell->type == ID($_DFFSR_PNP_)) { check_gate("CSRDQ"); return; } + if (cell->type == ID($_DFFSR_PPN_)) { check_gate("CSRDQ"); return; } + if (cell->type == ID($_DFFSR_PPP_)) { check_gate("CSRDQ"); return; } + + if (cell->type == ID($_DLATCH_N_)) { check_gate("EDQ"); return; } + if (cell->type == ID($_DLATCH_P_)) { check_gate("EDQ"); return; } + + if (cell->type == ID($_DLATCHSR_NNN_)) { check_gate("ESRDQ"); return; } + if (cell->type == ID($_DLATCHSR_NNP_)) { check_gate("ESRDQ"); return; } + if (cell->type == ID($_DLATCHSR_NPN_)) { check_gate("ESRDQ"); return; } + if (cell->type == ID($_DLATCHSR_NPP_)) { check_gate("ESRDQ"); return; } + if (cell->type == ID($_DLATCHSR_PNN_)) { check_gate("ESRDQ"); return; } + if (cell->type == ID($_DLATCHSR_PNP_)) { check_gate("ESRDQ"); return; } + if (cell->type == ID($_DLATCHSR_PPN_)) { check_gate("ESRDQ"); return; } + if (cell->type == ID($_DLATCHSR_PPP_)) { check_gate("ESRDQ"); return; } error(__LINE__); } @@ -1819,11 +1826,11 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters["\\A_SIGNED"] = is_signed; \ - cell->parameters["\\A_WIDTH"] = sig_a.size(); \ - cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->setPort("\\A", sig_a); \ - cell->setPort("\\Y", sig_y); \ + cell->parameters[ID(A_SIGNED)] = is_signed; \ + cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ + cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ + cell->setPort(ID(A), sig_a); \ + cell->setPort(ID(Y), sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ @@ -1832,28 +1839,28 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ } -DEF_METHOD(Not, sig_a.size(), "$not") -DEF_METHOD(Pos, sig_a.size(), "$pos") -DEF_METHOD(Neg, sig_a.size(), "$neg") -DEF_METHOD(ReduceAnd, 1, "$reduce_and") -DEF_METHOD(ReduceOr, 1, "$reduce_or") -DEF_METHOD(ReduceXor, 1, "$reduce_xor") -DEF_METHOD(ReduceXnor, 1, "$reduce_xnor") -DEF_METHOD(ReduceBool, 1, "$reduce_bool") -DEF_METHOD(LogicNot, 1, "$logic_not") +DEF_METHOD(Not, sig_a.size(), ID($not)) +DEF_METHOD(Pos, sig_a.size(), ID($pos)) +DEF_METHOD(Neg, sig_a.size(), ID($neg)) +DEF_METHOD(ReduceAnd, 1, ID($reduce_and)) +DEF_METHOD(ReduceOr, 1, ID($reduce_or)) +DEF_METHOD(ReduceXor, 1, ID($reduce_xor)) +DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor)) +DEF_METHOD(ReduceBool, 1, ID($reduce_bool)) +DEF_METHOD(LogicNot, 1, ID($logic_not)) #undef DEF_METHOD #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters["\\A_SIGNED"] = is_signed; \ - cell->parameters["\\B_SIGNED"] = is_signed; \ - cell->parameters["\\A_WIDTH"] = sig_a.size(); \ - cell->parameters["\\B_WIDTH"] = sig_b.size(); \ - cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ - cell->setPort("\\A", sig_a); \ - cell->setPort("\\B", sig_b); \ - cell->setPort("\\Y", sig_y); \ + cell->parameters[ID(A_SIGNED)] = is_signed; \ + cell->parameters[ID(B_SIGNED)] = is_signed; \ + cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ + cell->parameters[ID(B_WIDTH)] = sig_b.size(); \ + cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ + cell->setPort(ID(A), sig_a); \ + cell->setPort(ID(B), sig_b); \ + cell->setPort(ID(Y), sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ @@ -1862,42 +1869,42 @@ DEF_METHOD(LogicNot, 1, "$logic_not") add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ return sig_y; \ } -DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and") -DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or") -DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor") -DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor") -DEF_METHOD(Shl, sig_a.size(), "$shl") -DEF_METHOD(Shr, sig_a.size(), "$shr") -DEF_METHOD(Sshl, sig_a.size(), "$sshl") -DEF_METHOD(Sshr, sig_a.size(), "$sshr") -DEF_METHOD(Shift, sig_a.size(), "$shift") -DEF_METHOD(Shiftx, sig_a.size(), "$shiftx") -DEF_METHOD(Lt, 1, "$lt") -DEF_METHOD(Le, 1, "$le") -DEF_METHOD(Eq, 1, "$eq") -DEF_METHOD(Ne, 1, "$ne") -DEF_METHOD(Eqx, 1, "$eqx") -DEF_METHOD(Nex, 1, "$nex") -DEF_METHOD(Ge, 1, "$ge") -DEF_METHOD(Gt, 1, "$gt") -DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add") -DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub") -DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul") -DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div") -DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod") -DEF_METHOD(LogicAnd, 1, "$logic_and") -DEF_METHOD(LogicOr, 1, "$logic_or") +DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and)) +DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or)) +DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor)) +DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor)) +DEF_METHOD(Shl, sig_a.size(), ID($shl)) +DEF_METHOD(Shr, sig_a.size(), ID($shr)) +DEF_METHOD(Sshl, sig_a.size(), ID($sshl)) +DEF_METHOD(Sshr, sig_a.size(), ID($sshr)) +DEF_METHOD(Shift, sig_a.size(), ID($shift)) +DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx)) +DEF_METHOD(Lt, 1, ID($lt)) +DEF_METHOD(Le, 1, ID($le)) +DEF_METHOD(Eq, 1, ID($eq)) +DEF_METHOD(Ne, 1, ID($ne)) +DEF_METHOD(Eqx, 1, ID($eqx)) +DEF_METHOD(Nex, 1, ID($nex)) +DEF_METHOD(Ge, 1, ID($ge)) +DEF_METHOD(Gt, 1, ID($gt)) +DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add)) +DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub)) +DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul)) +DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div)) +DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod)) +DEF_METHOD(LogicAnd, 1, ID($logic_and)) +DEF_METHOD(LogicOr, 1, ID($logic_or)) #undef DEF_METHOD #define DEF_METHOD(_func, _type, _pmux) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters["\\WIDTH"] = sig_a.size(); \ - if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \ - cell->setPort("\\A", sig_a); \ - cell->setPort("\\B", sig_b); \ - cell->setPort("\\S", sig_s); \ - cell->setPort("\\Y", sig_y); \ + cell->parameters[ID(WIDTH)] = sig_a.size(); \ + if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \ + cell->setPort(ID(A), sig_a); \ + cell->setPort(ID(B), sig_b); \ + cell->setPort(ID(S), sig_s); \ + cell->setPort(ID(Y), sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ @@ -1906,8 +1913,8 @@ DEF_METHOD(LogicOr, 1, "$logic_or") add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \ return sig_y; \ } -DEF_METHOD(Mux, "$mux", 0) -DEF_METHOD(Pmux, "$pmux", 1) +DEF_METHOD(Mux, ID($mux), 0) +DEF_METHOD(Pmux, ID($pmux), 1) #undef DEF_METHOD #define DEF_METHOD_2(_func, _type, _P1, _P2) \ @@ -1968,22 +1975,22 @@ DEF_METHOD(Pmux, "$pmux", 1) add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \ return sig5; \ } -DEF_METHOD_2(BufGate, "$_BUF_", A, Y) -DEF_METHOD_2(NotGate, "$_NOT_", A, Y) -DEF_METHOD_3(AndGate, "$_AND_", A, B, Y) -DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y) -DEF_METHOD_3(OrGate, "$_OR_", A, B, Y) -DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y) -DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y) -DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y) -DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y) -DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y) -DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y) -DEF_METHOD_4(NmuxGate, "$_NMUX_", A, B, S, Y) -DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y) -DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y) -DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y) -DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y) +DEF_METHOD_2(BufGate, ID($_BUF_), A, Y) +DEF_METHOD_2(NotGate, ID($_NOT_), A, Y) +DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y) +DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y) +DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y) +DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y) +DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y) +DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y) +DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y) +DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y) +DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y) +DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y) +DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y) +DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y) +DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y) +DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y) #undef DEF_METHOD_2 #undef DEF_METHOD_3 #undef DEF_METHOD_4 @@ -1991,165 +1998,165 @@ DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y) RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$pow"); - cell->parameters["\\A_SIGNED"] = a_signed; - cell->parameters["\\B_SIGNED"] = b_signed; - cell->parameters["\\A_WIDTH"] = sig_a.size(); - cell->parameters["\\B_WIDTH"] = sig_b.size(); - cell->parameters["\\Y_WIDTH"] = sig_y.size(); - cell->setPort("\\A", sig_a); - cell->setPort("\\B", sig_b); - cell->setPort("\\Y", sig_y); + RTLIL::Cell *cell = addCell(name, ID($pow)); + cell->parameters[ID(A_SIGNED)] = a_signed; + cell->parameters[ID(B_SIGNED)] = b_signed; + cell->parameters[ID(A_WIDTH)] = sig_a.size(); + cell->parameters[ID(B_WIDTH)] = sig_b.size(); + cell->parameters[ID(Y_WIDTH)] = sig_y.size(); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(B), sig_b); + cell->setPort(ID(Y), sig_y); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$slice"); - cell->parameters["\\A_WIDTH"] = sig_a.size(); - cell->parameters["\\Y_WIDTH"] = sig_y.size(); - cell->parameters["\\OFFSET"] = offset; - cell->setPort("\\A", sig_a); - cell->setPort("\\Y", sig_y); + RTLIL::Cell *cell = addCell(name, ID($slice)); + cell->parameters[ID(A_WIDTH)] = sig_a.size(); + cell->parameters[ID(Y_WIDTH)] = sig_y.size(); + cell->parameters[ID(OFFSET)] = offset; + cell->setPort(ID(A), sig_a); + cell->setPort(ID(Y), sig_y); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$concat"); - cell->parameters["\\A_WIDTH"] = sig_a.size(); - cell->parameters["\\B_WIDTH"] = sig_b.size(); - cell->setPort("\\A", sig_a); - cell->setPort("\\B", sig_b); - cell->setPort("\\Y", sig_y); + RTLIL::Cell *cell = addCell(name, ID($concat)); + cell->parameters[ID(A_WIDTH)] = sig_a.size(); + cell->parameters[ID(B_WIDTH)] = sig_b.size(); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(B), sig_b); + cell->setPort(ID(Y), sig_y); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$lut"); - cell->parameters["\\LUT"] = lut; - cell->parameters["\\WIDTH"] = sig_a.size(); - cell->setPort("\\A", sig_a); - cell->setPort("\\Y", sig_y); + RTLIL::Cell *cell = addCell(name, ID($lut)); + cell->parameters[ID(LUT)] = lut; + cell->parameters[ID(WIDTH)] = sig_a.size(); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(Y), sig_y); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$tribuf"); - cell->parameters["\\WIDTH"] = sig_a.size(); - cell->setPort("\\A", sig_a); - cell->setPort("\\EN", sig_en); - cell->setPort("\\Y", sig_y); + RTLIL::Cell *cell = addCell(name, ID($tribuf)); + cell->parameters[ID(WIDTH)] = sig_a.size(); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(EN), sig_en); + cell->setPort(ID(Y), sig_y); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$assert"); - cell->setPort("\\A", sig_a); - cell->setPort("\\EN", sig_en); + RTLIL::Cell *cell = addCell(name, ID($assert)); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$assume"); - cell->setPort("\\A", sig_a); - cell->setPort("\\EN", sig_en); + RTLIL::Cell *cell = addCell(name, ID($assume)); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$live"); - cell->setPort("\\A", sig_a); - cell->setPort("\\EN", sig_en); + RTLIL::Cell *cell = addCell(name, ID($live)); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$fair"); - cell->setPort("\\A", sig_a); - cell->setPort("\\EN", sig_en); + RTLIL::Cell *cell = addCell(name, ID($fair)); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$cover"); - cell->setPort("\\A", sig_a); - cell->setPort("\\EN", sig_en); + RTLIL::Cell *cell = addCell(name, ID($cover)); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$equiv"); - cell->setPort("\\A", sig_a); - cell->setPort("\\B", sig_b); - cell->setPort("\\Y", sig_y); + RTLIL::Cell *cell = addCell(name, ID($equiv)); + cell->setPort(ID(A), sig_a); + cell->setPort(ID(B), sig_b); + cell->setPort(ID(Y), sig_y); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$sr"); - cell->parameters["\\SET_POLARITY"] = set_polarity; - cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.size(); - cell->setPort("\\SET", sig_set); - cell->setPort("\\CLR", sig_clr); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($sr)); + cell->parameters[ID(SET_POLARITY)] = set_polarity; + cell->parameters[ID(CLR_POLARITY)] = clr_polarity; + cell->parameters[ID(WIDTH)] = sig_q.size(); + cell->setPort(ID(SET), sig_set); + cell->setPort(ID(CLR), sig_clr); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$ff"); - cell->parameters["\\WIDTH"] = sig_q.size(); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($ff)); + cell->parameters[ID(WIDTH)] = sig_q.size(); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$dff"); - cell->parameters["\\CLK_POLARITY"] = clk_polarity; - cell->parameters["\\WIDTH"] = sig_q.size(); - cell->setPort("\\CLK", sig_clk); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($dff)); + cell->parameters[ID(CLK_POLARITY)] = clk_polarity; + cell->parameters[ID(WIDTH)] = sig_q.size(); + cell->setPort(ID(CLK), sig_clk); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$dffe"); - cell->parameters["\\CLK_POLARITY"] = clk_polarity; - cell->parameters["\\EN_POLARITY"] = en_polarity; - cell->parameters["\\WIDTH"] = sig_q.size(); - cell->setPort("\\CLK", sig_clk); - cell->setPort("\\EN", sig_en); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($dffe)); + cell->parameters[ID(CLK_POLARITY)] = clk_polarity; + cell->parameters[ID(EN_POLARITY)] = en_polarity; + cell->parameters[ID(WIDTH)] = sig_q.size(); + cell->setPort(ID(CLK), sig_clk); + cell->setPort(ID(EN), sig_en); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2157,16 +2164,16 @@ RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$dffsr"); - cell->parameters["\\CLK_POLARITY"] = clk_polarity; - cell->parameters["\\SET_POLARITY"] = set_polarity; - cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.size(); - cell->setPort("\\CLK", sig_clk); - cell->setPort("\\SET", sig_set); - cell->setPort("\\CLR", sig_clr); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($dffsr)); + cell->parameters[ID(CLK_POLARITY)] = clk_polarity; + cell->parameters[ID(SET_POLARITY)] = set_polarity; + cell->parameters[ID(CLR_POLARITY)] = clr_polarity; + cell->parameters[ID(WIDTH)] = sig_q.size(); + cell->setPort(ID(CLK), sig_clk); + cell->setPort(ID(SET), sig_set); + cell->setPort(ID(CLR), sig_clr); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2174,27 +2181,27 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$adff"); - cell->parameters["\\CLK_POLARITY"] = clk_polarity; - cell->parameters["\\ARST_POLARITY"] = arst_polarity; - cell->parameters["\\ARST_VALUE"] = arst_value; - cell->parameters["\\WIDTH"] = sig_q.size(); - cell->setPort("\\CLK", sig_clk); - cell->setPort("\\ARST", sig_arst); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($adff)); + cell->parameters[ID(CLK_POLARITY)] = clk_polarity; + cell->parameters[ID(ARST_POLARITY)] = arst_polarity; + cell->parameters[ID(ARST_VALUE)] = arst_value; + cell->parameters[ID(WIDTH)] = sig_q.size(); + cell->setPort(ID(CLK), sig_clk); + cell->setPort(ID(ARST), sig_arst); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$dlatch"); - cell->parameters["\\EN_POLARITY"] = en_polarity; - cell->parameters["\\WIDTH"] = sig_q.size(); - cell->setPort("\\EN", sig_en); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($dlatch)); + cell->parameters[ID(EN_POLARITY)] = en_polarity; + cell->parameters[ID(WIDTH)] = sig_q.size(); + cell->setPort(ID(EN), sig_en); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2202,25 +2209,25 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$dlatchsr"); - cell->parameters["\\EN_POLARITY"] = en_polarity; - cell->parameters["\\SET_POLARITY"] = set_polarity; - cell->parameters["\\CLR_POLARITY"] = clr_polarity; - cell->parameters["\\WIDTH"] = sig_q.size(); - cell->setPort("\\EN", sig_en); - cell->setPort("\\SET", sig_set); - cell->setPort("\\CLR", sig_clr); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($dlatchsr)); + cell->parameters[ID(EN_POLARITY)] = en_polarity; + cell->parameters[ID(SET_POLARITY)] = set_polarity; + cell->parameters[ID(CLR_POLARITY)] = clr_polarity; + cell->parameters[ID(WIDTH)] = sig_q.size(); + cell->setPort(ID(EN), sig_en); + cell->setPort(ID(SET), sig_set); + cell->setPort(ID(CLR), sig_clr); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src) { - RTLIL::Cell *cell = addCell(name, "$_FF_"); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + RTLIL::Cell *cell = addCell(name, ID($_FF_)); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2228,9 +2235,9 @@ RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')); - cell->setPort("\\C", sig_clk); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + cell->setPort(ID(C), sig_clk); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2238,10 +2245,10 @@ RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_ RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort("\\C", sig_clk); - cell->setPort("\\E", sig_en); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + cell->setPort(ID(C), sig_clk); + cell->setPort(ID(E), sig_en); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2250,11 +2257,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort("\\C", sig_clk); - cell->setPort("\\S", sig_set); - cell->setPort("\\R", sig_clr); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + cell->setPort(ID(C), sig_clk); + cell->setPort(ID(S), sig_set); + cell->setPort(ID(R), sig_clr); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2263,10 +2270,10 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); - cell->setPort("\\C", sig_clk); - cell->setPort("\\R", sig_arst); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + cell->setPort(ID(C), sig_clk); + cell->setPort(ID(R), sig_arst); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2274,9 +2281,9 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')); - cell->setPort("\\E", sig_en); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + cell->setPort(ID(E), sig_en); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2285,11 +2292,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort("\\E", sig_en); - cell->setPort("\\S", sig_set); - cell->setPort("\\R", sig_clr); - cell->setPort("\\D", sig_d); - cell->setPort("\\Q", sig_q); + cell->setPort(ID(E), sig_en); + cell->setPort(ID(S), sig_set); + cell->setPort(ID(R), sig_clr); + cell->setPort(ID(D), sig_d); + cell->setPort(ID(Q), sig_q); cell->set_src_attribute(src); return cell; } @@ -2297,9 +2304,9 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src) { RTLIL::SigSpec sig = addWire(NEW_ID, width); - Cell *cell = addCell(name, "$anyconst"); - cell->setParam("\\WIDTH", width); - cell->setPort("\\Y", sig); + Cell *cell = addCell(name, ID($anyconst)); + cell->setParam(ID(WIDTH), width); + cell->setPort(ID(Y), sig); cell->set_src_attribute(src); return sig; } @@ -2307,9 +2314,9 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const st RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src) { RTLIL::SigSpec sig = addWire(NEW_ID, width); - Cell *cell = addCell(name, "$anyseq"); - cell->setParam("\\WIDTH", width); - cell->setPort("\\Y", sig); + Cell *cell = addCell(name, ID($anyseq)); + cell->setParam(ID(WIDTH), width); + cell->setPort(ID(Y), sig); cell->set_src_attribute(src); return sig; } @@ -2317,9 +2324,9 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std: RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src) { RTLIL::SigSpec sig = addWire(NEW_ID, width); - Cell *cell = addCell(name, "$allconst"); - cell->setParam("\\WIDTH", width); - cell->setPort("\\Y", sig); + Cell *cell = addCell(name, ID($allconst)); + cell->setParam(ID(WIDTH), width); + cell->setPort(ID(Y), sig); cell->set_src_attribute(src); return sig; } @@ -2327,9 +2334,9 @@ RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const st RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src) { RTLIL::SigSpec sig = addWire(NEW_ID, width); - Cell *cell = addCell(name, "$allseq"); - cell->setParam("\\WIDTH", width); - cell->setPort("\\Y", sig); + Cell *cell = addCell(name, ID($allseq)); + cell->setParam(ID(WIDTH), width); + cell->setPort(ID(Y), sig); cell->set_src_attribute(src); return sig; } @@ -2337,8 +2344,8 @@ RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std: RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src) { RTLIL::SigSpec sig = addWire(NEW_ID); - Cell *cell = addCell(name, "$initstate"); - cell->setPort("\\Y", sig); + Cell *cell = addCell(name, ID($initstate)); + cell->setPort(ID(Y), sig); cell->set_src_attribute(src); return sig; } @@ -2559,56 +2566,56 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:")) return; - if (type == "$mux" || type == "$pmux") { - parameters["\\WIDTH"] = GetSize(connections_["\\Y"]); - if (type == "$pmux") - parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]); + if (type == ID($mux) || type == ID($pmux)) { + parameters[ID(WIDTH)] = GetSize(connections_[ID(Y)]); + if (type == ID($pmux)) + parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]); check(); return; } - if (type == "$lut" || type == "$sop") { - parameters["\\WIDTH"] = GetSize(connections_["\\A"]); + if (type == ID($lut) || type == ID($sop)) { + parameters[ID(WIDTH)] = GetSize(connections_[ID(A)]); return; } - if (type == "$fa") { - parameters["\\WIDTH"] = GetSize(connections_["\\Y"]); + if (type == ID($fa)) { + parameters[ID(WIDTH)] = GetSize(connections_[ID(Y)]); return; } - if (type == "$lcu") { - parameters["\\WIDTH"] = GetSize(connections_["\\CO"]); + if (type == ID($lcu)) { + parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]); return; } - bool signedness_ab = !type.in("$slice", "$concat", "$macc"); + bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc)); - if (connections_.count("\\A")) { + if (connections_.count(ID(A))) { if (signedness_ab) { if (set_a_signed) - parameters["\\A_SIGNED"] = true; - else if (parameters.count("\\A_SIGNED") == 0) - parameters["\\A_SIGNED"] = false; + parameters[ID(A_SIGNED)] = true; + else if (parameters.count(ID(A_SIGNED)) == 0) + parameters[ID(A_SIGNED)] = false; } - parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]); + parameters[ID(A_WIDTH)] = GetSize(connections_[ID(A)]); } - if (connections_.count("\\B")) { + if (connections_.count(ID(B))) { if (signedness_ab) { if (set_b_signed) - parameters["\\B_SIGNED"] = true; - else if (parameters.count("\\B_SIGNED") == 0) - parameters["\\B_SIGNED"] = false; + parameters[ID(B_SIGNED)] = true; + else if (parameters.count(ID(B_SIGNED)) == 0) + parameters[ID(B_SIGNED)] = false; } - parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]); + parameters[ID(B_WIDTH)] = GetSize(connections_[ID(B)]); } - if (connections_.count("\\Y")) - parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]); + if (connections_.count(ID(Y))) + parameters[ID(Y_WIDTH)] = GetSize(connections_[ID(Y)]); - if (connections_.count("\\Q")) - parameters["\\WIDTH"] = GetSize(connections_["\\Q"]); + if (connections_.count(ID(Q))) + parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]); check(); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e771655d7..c879d22e5 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -348,6 +348,14 @@ namespace RTLIL bool in(const pool &rhs) const { return rhs.count(*this) != 0; } }; + namespace ID { + // defined in rtlil.cc, initialized in yosys.cc + extern IdString A, B, Y; + extern IdString keep; + extern IdString whitebox; + extern IdString blackbox; + }; + static inline std::string escape_id(std::string str) { if (str.size() > 0 && str[0] != '\\' && str[0] != '$') return "\\" + str; @@ -620,7 +628,7 @@ struct RTLIL::AttrObject bool get_bool_attribute(RTLIL::IdString id) const; bool get_blackbox_attribute(bool ignore_wb=false) const { - return get_bool_attribute("\\blackbox") || (!ignore_wb && get_bool_attribute("\\whitebox")); + return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox)); } void set_strpool_attribute(RTLIL::IdString id, const pool &data); @@ -1355,8 +1363,8 @@ public: void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false); bool has_keep_attr() const { - return get_bool_attribute("\\keep") || (module && module->design && module->design->module(type) && - module->design->module(type)->get_bool_attribute("\\keep")); + return get_bool_attribute(ID::keep) || (module && module->design && module->design->module(type) && + module->design->module(type)->get_bool_attribute(ID::keep)); } template void rewrite_sigspecs(T &functor); diff --git a/kernel/satgen.h b/kernel/satgen.h index 596f522ec..de480f28e 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -224,8 +224,8 @@ struct SatGen void extendSignalWidth(std::vector &vec_a, std::vector &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false) { bool is_signed = forced_signed; - if (!forced_signed && cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters.count("\\B_SIGNED") > 0) - is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool(); + if (!forced_signed && cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters.count(ID(B_SIGNED)) > 0) + is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); while (vec_a.size() < vec_b.size() || vec_a.size() < y_width) vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); while (vec_b.size() < vec_a.size() || vec_b.size() < y_width) @@ -241,7 +241,7 @@ struct SatGen void extendSignalWidthUnary(std::vector &vec_a, std::vector &vec_y, RTLIL::Cell *cell, bool forced_signed = false) { - bool is_signed = forced_signed || (cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool()); + bool is_signed = forced_signed || (cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool()); while (vec_a.size() < vec_y.size()) vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); while (vec_y.size() < vec_a.size()) @@ -277,13 +277,13 @@ struct SatGen bool importCell(RTLIL::Cell *cell, int timestep = -1) { bool arith_undef_handled = false; - bool is_arith_compare = cell->type.in("$lt", "$le", "$ge", "$gt"); + bool is_arith_compare = cell->type.in(ID($lt), ID($le), ID($ge), ID($gt)); - if (model_undef && (cell->type.in("$add", "$sub", "$mul", "$div", "$mod") || is_arith_compare)) + if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod)) || is_arith_compare)) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); if (is_arith_compare) extendSignalWidth(undef_a, undef_b, cell, true); else @@ -293,8 +293,8 @@ struct SatGen int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); int undef_y_bit = ez->OR(undef_any_a, undef_any_b); - if (cell->type == "$div" || cell->type == "$mod") { - std::vector b = importSigSpec(cell->getPort("\\B"), timestep); + if (cell->type == ID($div) || cell->type == ID($mod)) { + std::vector b = importSigSpec(cell->getPort(ID(B)), timestep); undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b))); } @@ -310,68 +310,68 @@ struct SatGen arith_undef_handled = true; } - if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", - "$and", "$or", "$xor", "$xnor", "$add", "$sub")) + if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), + ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($sub))) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == "$and" || cell->type == "$_AND_") + if (cell->type == ID($and) || cell->type == ID($_AND_)) ez->assume(ez->vec_eq(ez->vec_and(a, b), yy)); - if (cell->type == "$_NAND_") + if (cell->type == ID($_NAND_)) ez->assume(ez->vec_eq(ez->vec_not(ez->vec_and(a, b)), yy)); - if (cell->type == "$or" || cell->type == "$_OR_") + if (cell->type == ID($or) || cell->type == ID($_OR_)) ez->assume(ez->vec_eq(ez->vec_or(a, b), yy)); - if (cell->type == "$_NOR_") + if (cell->type == ID($_NOR_)) ez->assume(ez->vec_eq(ez->vec_not(ez->vec_or(a, b)), yy)); - if (cell->type == "$xor" || cell->type == "$_XOR_") + if (cell->type == ID($xor) || cell->type == ID($_XOR_)) ez->assume(ez->vec_eq(ez->vec_xor(a, b), yy)); - if (cell->type == "$xnor" || cell->type == "$_XNOR_") + if (cell->type == ID($xnor) || cell->type == ID($_XNOR_)) ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), yy)); - if (cell->type == "$_ANDNOT_") + if (cell->type == ID($_ANDNOT_)) ez->assume(ez->vec_eq(ez->vec_and(a, ez->vec_not(b)), yy)); - if (cell->type == "$_ORNOT_") + if (cell->type == ID($_ORNOT_)) ez->assume(ez->vec_eq(ez->vec_or(a, ez->vec_not(b)), yy)); - if (cell->type == "$add") + if (cell->type == ID($add)) ez->assume(ez->vec_eq(ez->vec_add(a, b), yy)); - if (cell->type == "$sub") + if (cell->type == ID($sub)) ez->assume(ez->vec_eq(ez->vec_sub(a, b), yy)); if (model_undef && !arith_undef_handled) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell, false); - if (cell->type.in("$and", "$_AND_", "$_NAND_")) { + if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_))) { std::vector a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)); std::vector b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b)); std::vector yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b0))); ez->assume(ez->vec_eq(yX, undef_y)); } - else if (cell->type.in("$or", "$_OR_", "$_NOR_")) { + else if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_))) { std::vector a1 = ez->vec_and(a, ez->vec_not(undef_a)); std::vector b1 = ez->vec_and(b, ez->vec_not(undef_b)); std::vector yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a1, b1))); ez->assume(ez->vec_eq(yX, undef_y)); } - else if (cell->type.in("$xor", "$xnor", "$_XOR_", "$_XNOR_")) { + else if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) { std::vector yX = ez->vec_or(undef_a, undef_b); ez->assume(ez->vec_eq(yX, undef_y)); } - else if (cell->type == "$_ANDNOT_") { + else if (cell->type == ID($_ANDNOT_)) { std::vector a0 = ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a)); std::vector b1 = ez->vec_and(b, ez->vec_not(undef_b)); std::vector yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a0, b1))); ez->assume(ez->vec_eq(yX, undef_y)); } - else if (cell->type == "$_ORNOT_") { + else if (cell->type == ID($_ORNOT_)) { std::vector a1 = ez->vec_and(a, ez->vec_not(undef_a)); std::vector b0 = ez->vec_and(ez->vec_not(b), ez->vec_not(undef_b)); std::vector yX = ez->vec_and(ez->vec_or(undef_a, undef_b), ez->vec_not(ez->vec_or(a1, b0))); @@ -384,36 +384,36 @@ struct SatGen } else if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); undefGating(y, yy, undef_y); } return true; } - if (cell->type.in("$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_")) + if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { - bool aoi_mode = cell->type.in("$_AOI3_", "$_AOI4_"); - bool three_mode = cell->type.in("$_AOI3_", "$_OAI3_"); - - int a = importDefSigSpec(cell->getPort("\\A"), timestep).at(0); - int b = importDefSigSpec(cell->getPort("\\B"), timestep).at(0); - int c = importDefSigSpec(cell->getPort("\\C"), timestep).at(0); - int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort("\\D"), timestep).at(0); - int y = importDefSigSpec(cell->getPort("\\Y"), timestep).at(0); + bool aoi_mode = cell->type.in(ID($_AOI3_), ID($_AOI4_)); + bool three_mode = cell->type.in(ID($_AOI3_), ID($_OAI3_)); + + int a = importDefSigSpec(cell->getPort(ID(A)), timestep).at(0); + int b = importDefSigSpec(cell->getPort(ID(B)), timestep).at(0); + int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0); + int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0); + int y = importDefSigSpec(cell->getPort(ID(Y)), timestep).at(0); int yy = model_undef ? ez->literal() : y; - if (cell->type.in("$_AOI3_", "$_AOI4_")) + if (cell->type.in(ID($_AOI3_), ID($_AOI4_))) ez->assume(ez->IFF(ez->NOT(ez->OR(ez->AND(a, b), ez->AND(c, d))), yy)); else ez->assume(ez->IFF(ez->NOT(ez->AND(ez->OR(a, b), ez->OR(c, d))), yy)); if (model_undef) { - int undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep).at(0); - int undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep).at(0); - int undef_c = importUndefSigSpec(cell->getPort("\\C"), timestep).at(0); - int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort("\\D"), timestep).at(0); - int undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep).at(0); + int undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep).at(0); + int undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep).at(0); + int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0); + int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0); + int undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep).at(0); if (aoi_mode) { @@ -456,18 +456,18 @@ struct SatGen return true; } - if (cell->type == "$_NOT_" || cell->type == "$not") + if (cell->type == ID($_NOT_) || cell->type == ID($not)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_not(a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, false); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -475,25 +475,25 @@ struct SatGen return true; } - if (cell->type == "$_MUX_" || cell->type == "$mux" || cell->type == "$_NMUX_") + if (cell->type == ID($_MUX_) || cell->type == ID($mux) || cell->type == ID($_NMUX_)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector s = importDefSigSpec(cell->getPort("\\S"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector s = importDefSigSpec(cell->getPort(ID(S)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == "$_NMUX_") + if (cell->type == ID($_NMUX_)) ez->assume(ez->vec_eq(ez->vec_not(ez->vec_ite(s.at(0), b, a)), yy)); else ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); std::vector unequal_ab = ez->vec_not(ez->vec_iff(a, b)); std::vector undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b)); @@ -504,12 +504,12 @@ struct SatGen return true; } - if (cell->type == "$pmux") + if (cell->type == ID($pmux)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector s = importDefSigSpec(cell->getPort("\\S"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector s = importDefSigSpec(cell->getPort(ID(S)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -522,10 +522,10 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); int maybe_a = ez->CONST_TRUE; @@ -555,15 +555,15 @@ struct SatGen return true; } - if (cell->type == "$pos" || cell->type == "$neg") + if (cell->type == ID($pos) || cell->type == ID($neg)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == "$pos") { + if (cell->type == ID($pos)) { ez->assume(ez->vec_eq(a, yy)); } else { std::vector zero(a.size(), ez->CONST_FALSE); @@ -572,11 +572,11 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidthUnary(undef_a, undef_y, cell); - if (cell->type == "$pos") { + if (cell->type == ID($pos)) { ez->assume(ez->vec_eq(undef_a, undef_y)); } else { int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); @@ -589,42 +589,42 @@ struct SatGen return true; } - if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" || - cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not") + if (cell->type == ID($reduce_and) || cell->type == ID($reduce_or) || cell->type == ID($reduce_xor) || + cell->type == ID($reduce_xnor) || cell->type == ID($reduce_bool) || cell->type == ID($logic_not)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == "$reduce_and") + if (cell->type == ID($reduce_and)) ez->SET(ez->expression(ez->OpAnd, a), yy.at(0)); - if (cell->type == "$reduce_or" || cell->type == "$reduce_bool") + if (cell->type == ID($reduce_or) || cell->type == ID($reduce_bool)) ez->SET(ez->expression(ez->OpOr, a), yy.at(0)); - if (cell->type == "$reduce_xor") + if (cell->type == ID($reduce_xor)) ez->SET(ez->expression(ez->OpXor, a), yy.at(0)); - if (cell->type == "$reduce_xnor") + if (cell->type == ID($reduce_xnor)) ez->SET(ez->NOT(ez->expression(ez->OpXor, a)), yy.at(0)); - if (cell->type == "$logic_not") + if (cell->type == ID($logic_not)) ez->SET(ez->NOT(ez->expression(ez->OpOr, a)), yy.at(0)); for (size_t i = 1; i < y.size(); i++) ez->SET(ez->CONST_FALSE, yy.at(i)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); int aX = ez->expression(ezSAT::OpOr, undef_a); - if (cell->type == "$reduce_and") { + if (cell->type == ID($reduce_and)) { int a0 = ez->expression(ezSAT::OpOr, ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a))); ez->assume(ez->IFF(ez->AND(ez->NOT(a0), aX), undef_y.at(0))); } - else if (cell->type == "$reduce_or" || cell->type == "$reduce_bool" || cell->type == "$logic_not") { + else if (cell->type == ID($reduce_or) || cell->type == ID($reduce_bool) || cell->type == ID($logic_not)) { int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(a, ez->vec_not(undef_a))); ez->assume(ez->IFF(ez->AND(ez->NOT(a1), aX), undef_y.at(0))); } - else if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") { + else if (cell->type == ID($reduce_xor) || cell->type == ID($reduce_xnor)) { ez->assume(ez->IFF(aX, undef_y.at(0))); } else log_abort(); @@ -637,18 +637,18 @@ struct SatGen return true; } - if (cell->type == "$logic_and" || cell->type == "$logic_or") + if (cell->type == ID($logic_and) || cell->type == ID($logic_or)) { - std::vector vec_a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector vec_b = importDefSigSpec(cell->getPort("\\B"), timestep); + std::vector vec_a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector vec_b = importDefSigSpec(cell->getPort(ID(B)), timestep); int a = ez->expression(ez->OpOr, vec_a); int b = ez->expression(ez->OpOr, vec_b); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == "$logic_and") + if (cell->type == ID($logic_and)) ez->SET(ez->expression(ez->OpAnd, a, b), yy.at(0)); else ez->SET(ez->expression(ez->OpOr, a, b), yy.at(0)); @@ -657,9 +657,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a))); int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b))); @@ -668,9 +668,9 @@ struct SatGen int aX = ez->expression(ezSAT::OpOr, undef_a); int bX = ez->expression(ezSAT::OpOr, undef_b); - if (cell->type == "$logic_and") + if (cell->type == ID($logic_and)) ez->SET(ez->AND(ez->OR(aX, bX), ez->NOT(ez->AND(a1, b1)), ez->NOT(a0), ez->NOT(b0)), undef_y.at(0)); - else if (cell->type == "$logic_or") + else if (cell->type == ID($logic_or)) ez->SET(ez->AND(ez->OR(aX, bX), ez->NOT(ez->AND(a0, b0)), ez->NOT(a1), ez->NOT(b1)), undef_y.at(0)); else log_abort(); @@ -683,47 +683,47 @@ struct SatGen return true; } - if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") + if (cell->type == ID($lt) || cell->type == ID($le) || cell->type == ID($eq) || cell->type == ID($ne) || cell->type == ID($eqx) || cell->type == ID($nex) || cell->type == ID($ge) || cell->type == ID($gt)) { - bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool(); - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidth(a, b, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + if (model_undef && (cell->type == ID($eqx) || cell->type == ID($nex))) { + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); extendSignalWidth(undef_a, undef_b, cell, true); a = ez->vec_or(a, undef_a); b = ez->vec_or(b, undef_b); } - if (cell->type == "$lt") + if (cell->type == ID($lt)) ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), yy.at(0)); - if (cell->type == "$le") + if (cell->type == ID($le)) ez->SET(is_signed ? ez->vec_le_signed(a, b) : ez->vec_le_unsigned(a, b), yy.at(0)); - if (cell->type == "$eq" || cell->type == "$eqx") + if (cell->type == ID($eq) || cell->type == ID($eqx)) ez->SET(ez->vec_eq(a, b), yy.at(0)); - if (cell->type == "$ne" || cell->type == "$nex") + if (cell->type == ID($ne) || cell->type == ID($nex)) ez->SET(ez->vec_ne(a, b), yy.at(0)); - if (cell->type == "$ge") + if (cell->type == ID($ge)) ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), yy.at(0)); - if (cell->type == "$gt") + if (cell->type == ID($gt)) ez->SET(is_signed ? ez->vec_gt_signed(a, b) : ez->vec_gt_unsigned(a, b), yy.at(0)); for (size_t i = 1; i < y.size(); i++) ez->SET(ez->CONST_FALSE, yy.at(i)); - if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) + if (model_undef && (cell->type == ID($eqx) || cell->type == ID($nex))) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidth(undef_a, undef_b, cell, true); - if (cell->type == "$eqx") + if (cell->type == ID($eqx)) yy.at(0) = ez->AND(yy.at(0), ez->vec_eq(undef_a, undef_b)); else yy.at(0) = ez->OR(yy.at(0), ez->vec_ne(undef_a, undef_b)); @@ -733,11 +733,11 @@ struct SatGen ez->assume(ez->vec_eq(y, yy)); } - else if (model_undef && (cell->type == "$eq" || cell->type == "$ne")) + else if (model_undef && (cell->type == ID($eq) || cell->type == ID($ne))) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidth(undef_a, undef_b, cell, true); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); @@ -759,7 +759,7 @@ struct SatGen else { if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); undefGating(y, yy, undef_y); } log_assert(!model_undef || arith_undef_handled); @@ -767,15 +767,15 @@ struct SatGen return true; } - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") + if (cell->type == ID($shl) || cell->type == ID($shr) || cell->type == ID($sshl) || cell->type == ID($sshr) || cell->type == ID($shift) || cell->type == ID($shiftx)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); int extend_bit = ez->CONST_FALSE; - if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool()) + if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool()) extend_bit = a.back(); while (y.size() < a.size()) @@ -786,29 +786,29 @@ struct SatGen std::vector yy = model_undef ? ez->vec_var(y.size()) : y; std::vector shifted_a; - if (cell->type == "$shl" || cell->type == "$sshl") + if (cell->type == ID($shl) || cell->type == ID($sshl)) shifted_a = ez->vec_shift_left(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); - if (cell->type == "$shr") + if (cell->type == ID($shr)) shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); - if (cell->type == "$sshr") - shifted_a = ez->vec_shift_right(a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); + if (cell->type == ID($sshr)) + shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); - if (cell->type == "$shift" || cell->type == "$shiftx") - shifted_a = ez->vec_shift_right(a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); + if (cell->type == ID($shift) || cell->type == ID($shiftx)) + shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); ez->assume(ez->vec_eq(shifted_a, yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); std::vector undef_a_shifted; - extend_bit = cell->type == "$shiftx" ? ez->CONST_TRUE : ez->CONST_FALSE; - if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool()) + extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE; + if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool()) extend_bit = undef_a.back(); while (undef_y.size() < undef_a.size()) @@ -816,20 +816,20 @@ struct SatGen while (undef_y.size() > undef_a.size()) undef_a.push_back(extend_bit); - if (cell->type == "$shl" || cell->type == "$sshl") + if (cell->type == ID($shl) || cell->type == ID($sshl)) undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); - if (cell->type == "$shr") + if (cell->type == ID($shr)) undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); - if (cell->type == "$sshr") - undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE); + if (cell->type == ID($sshr)) + undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE); - if (cell->type == "$shift") - undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); + if (cell->type == ID($shift)) + undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); - if (cell->type == "$shiftx") - undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE); + if (cell->type == ID($shiftx)) + undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); std::vector undef_all_y_bits(undef_y.size(), undef_any_b); @@ -839,11 +839,11 @@ struct SatGen return true; } - if (cell->type == "$mul") + if (cell->type == ID($mul)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -860,17 +860,17 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); undefGating(y, yy, undef_y); } return true; } - if (cell->type == "$macc") + if (cell->type == ID($macc)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); Macc macc; macc.from_cell(cell); @@ -919,13 +919,13 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); ez->assume(ez->vec_eq(undef_y, std::vector(GetSize(y), ez->OR(undef_any_a, undef_any_b)))); undefGating(y, tmp, undef_y); @@ -936,17 +936,17 @@ struct SatGen return true; } - if (cell->type == "$div" || cell->type == "$mod") + if (cell->type == ID($div) || cell->type == ID($mod)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; std::vector a_u, b_u; - if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) { + if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) { a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a); b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b); } else { @@ -971,13 +971,13 @@ struct SatGen } std::vector y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size()); - if (cell->type == "$div") { - if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) + if (cell->type == ID($div)) { + if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u))); else ez->assume(ez->vec_eq(y_tmp, y_u)); } else { - if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) + if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf))); else ez->assume(ez->vec_eq(y_tmp, chain_buf)); @@ -987,20 +987,20 @@ struct SatGen ez->assume(ez->expression(ezSAT::OpOr, b)); } else { std::vector div_zero_result; - if (cell->type == "$div") { - if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) { + if (cell->type == ID($div)) { + if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) { std::vector all_ones(y.size(), ez->CONST_TRUE); std::vector only_first_one(y.size(), ez->CONST_FALSE); only_first_one.at(0) = ez->CONST_TRUE; div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones); } else { - div_zero_result.insert(div_zero_result.end(), cell->getPort("\\A").size(), ez->CONST_TRUE); + div_zero_result.insert(div_zero_result.end(), cell->getPort(ID(A)).size(), ez->CONST_TRUE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE); } } else { - int copy_a_bits = min(cell->getPort("\\A").size(), cell->getPort("\\B").size()); + int copy_a_bits = min(cell->getPort(ID(A)).size(), cell->getPort(ID(B)).size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); - if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()) + if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); else div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE); @@ -1010,19 +1010,19 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); undefGating(y, yy, undef_y); } return true; } - if (cell->type == "$lut") + if (cell->type == ID($lut)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector lut; - for (auto bit : cell->getParam("\\LUT").bits) + for (auto bit : cell->getParam(ID(LUT)).bits) lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); while (GetSize(lut) < (1 << GetSize(a))) lut.push_back(ez->CONST_FALSE); @@ -1030,7 +1030,7 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); std::vector t(lut), u(GetSize(t), ez->CONST_FALSE); for (int i = GetSize(a)-1; i >= 0; i--) @@ -1048,7 +1048,7 @@ struct SatGen log_assert(GetSize(t) == 1); log_assert(GetSize(u) == 1); undefGating(y, t, u); - ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort("\\Y"), timestep), u)); + ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID(Y)), timestep), u)); } else { @@ -1066,15 +1066,15 @@ struct SatGen return true; } - if (cell->type == "$sop") + if (cell->type == ID($sop)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - int y = importDefSigSpec(cell->getPort("\\Y"), timestep).at(0); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + int y = importDefSigSpec(cell->getPort(ID(Y)), timestep).at(0); - int width = cell->getParam("\\WIDTH").as_int(); - int depth = cell->getParam("\\DEPTH").as_int(); + int width = cell->getParam(ID(WIDTH)).as_int(); + int depth = cell->getParam(ID(DEPTH)).as_int(); - vector table_raw = cell->getParam("\\TABLE").bits; + vector table_raw = cell->getParam(ID(TABLE)).bits; while (GetSize(table_raw) < 2*width*depth) table_raw.push_back(State::S0); @@ -1097,8 +1097,8 @@ struct SatGen if (model_undef) { std::vector products, undef_products; - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - int undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep).at(0); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + int undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep).at(0); for (int i = 0; i < depth; i++) { @@ -1148,13 +1148,13 @@ struct SatGen return true; } - if (cell->type == "$fa") + if (cell->type == ID($fa)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector c = importDefSigSpec(cell->getPort("\\C"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); - std::vector x = importDefSigSpec(cell->getPort("\\X"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector c = importDefSigSpec(cell->getPort(ID(C)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector x = importDefSigSpec(cell->getPort(ID(X)), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; std::vector xx = model_undef ? ez->vec_var(x.size()) : x; @@ -1168,12 +1168,12 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_c = importUndefSigSpec(cell->getPort("\\C"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); - std::vector undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); ez->assume(ez->vec_eq(undef_x, undef_y)); @@ -1184,12 +1184,12 @@ struct SatGen return true; } - if (cell->type == "$lcu") + if (cell->type == ID($lcu)) { - std::vector p = importDefSigSpec(cell->getPort("\\P"), timestep); - std::vector g = importDefSigSpec(cell->getPort("\\G"), timestep); - std::vector ci = importDefSigSpec(cell->getPort("\\CI"), timestep); - std::vector co = importDefSigSpec(cell->getPort("\\CO"), timestep); + std::vector p = importDefSigSpec(cell->getPort(ID(P)), timestep); + std::vector g = importDefSigSpec(cell->getPort(ID(G)), timestep); + std::vector ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); + std::vector co = importDefSigSpec(cell->getPort(ID(CO)), timestep); std::vector yy = model_undef ? ez->vec_var(co.size()) : co; @@ -1198,10 +1198,10 @@ struct SatGen if (model_undef) { - std::vector undef_p = importUndefSigSpec(cell->getPort("\\P"), timestep); - std::vector undef_g = importUndefSigSpec(cell->getPort("\\G"), timestep); - std::vector undef_ci = importUndefSigSpec(cell->getPort("\\CI"), timestep); - std::vector undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep); + std::vector undef_p = importUndefSigSpec(cell->getPort(ID(P)), timestep); + std::vector undef_g = importUndefSigSpec(cell->getPort(ID(G)), timestep); + std::vector undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); + std::vector undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); int undef_any_p = ez->expression(ezSAT::OpOr, undef_p); int undef_any_g = ez->expression(ezSAT::OpOr, undef_g); @@ -1216,15 +1216,15 @@ struct SatGen return true; } - if (cell->type == "$alu") + if (cell->type == ID($alu)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector b = importDefSigSpec(cell->getPort("\\B"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); - std::vector x = importDefSigSpec(cell->getPort("\\X"), timestep); - std::vector ci = importDefSigSpec(cell->getPort("\\CI"), timestep); - std::vector bi = importDefSigSpec(cell->getPort("\\BI"), timestep); - std::vector co = importDefSigSpec(cell->getPort("\\CO"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector x = importDefSigSpec(cell->getPort(ID(X)), timestep); + std::vector ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); + std::vector bi = importDefSigSpec(cell->getPort(ID(BI)), timestep); + std::vector co = importDefSigSpec(cell->getPort(ID(CO)), timestep); extendSignalWidth(a, b, y, cell); extendSignalWidth(a, b, x, cell); @@ -1249,14 +1249,14 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep); - std::vector undef_ci = importUndefSigSpec(cell->getPort("\\CI"), timestep); - std::vector undef_bi = importUndefSigSpec(cell->getPort("\\BI"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); + std::vector undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); - std::vector undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep); - std::vector undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); + std::vector undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell); extendSignalWidth(undef_a, undef_b, undef_x, cell); @@ -1282,19 +1282,19 @@ struct SatGen return true; } - if (cell->type == "$slice") + if (cell->type == ID($slice)) { - RTLIL::SigSpec a = cell->getPort("\\A"); - RTLIL::SigSpec y = cell->getPort("\\Y"); - ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep)); + RTLIL::SigSpec a = cell->getPort(ID(A)); + RTLIL::SigSpec y = cell->getPort(ID(Y)); + ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep)); return true; } - if (cell->type == "$concat") + if (cell->type == ID($concat)) { - RTLIL::SigSpec a = cell->getPort("\\A"); - RTLIL::SigSpec b = cell->getPort("\\B"); - RTLIL::SigSpec y = cell->getPort("\\Y"); + RTLIL::SigSpec a = cell->getPort(ID(A)); + RTLIL::SigSpec b = cell->getPort(ID(B)); + RTLIL::SigSpec y = cell->getPort(ID(Y)); RTLIL::SigSpec ab = a; ab.append(b); @@ -1303,24 +1303,24 @@ struct SatGen return true; } - if (timestep > 0 && cell->type.in("$ff", "$dff", "$_FF_", "$_DFF_N_", "$_DFF_P_")) + if (timestep > 0 && cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_N_), ID($_DFF_P_))) { if (timestep == 1) { - initial_state.add((*sigmap)(cell->getPort("\\Q"))); + initial_state.add((*sigmap)(cell->getPort(ID(Q)))); } else { - std::vector d = importDefSigSpec(cell->getPort("\\D"), timestep-1); - std::vector q = importDefSigSpec(cell->getPort("\\Q"), timestep); + std::vector d = importDefSigSpec(cell->getPort(ID(D)), timestep-1); + std::vector q = importDefSigSpec(cell->getPort(ID(Q)), timestep); std::vector qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1); - std::vector undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep); + std::vector undef_d = importUndefSigSpec(cell->getPort(ID(D)), timestep-1); + std::vector undef_q = importUndefSigSpec(cell->getPort(ID(Q)), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -1329,21 +1329,21 @@ struct SatGen return true; } - if (cell->type == "$anyconst") + if (cell->type == ID($anyconst)) { if (timestep < 2) return true; - std::vector d = importDefSigSpec(cell->getPort("\\Y"), timestep-1); - std::vector q = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector d = importDefSigSpec(cell->getPort(ID(Y)), timestep-1); + std::vector q = importDefSigSpec(cell->getPort(ID(Y)), timestep); std::vector qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector undef_d = importUndefSigSpec(cell->getPort("\\Y"), timestep-1); - std::vector undef_q = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_d = importUndefSigSpec(cell->getPort(ID(Y)), timestep-1); + std::vector undef_q = importUndefSigSpec(cell->getPort(ID(Y)), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -1351,23 +1351,23 @@ struct SatGen return true; } - if (cell->type == "$anyseq") + if (cell->type == ID($anyseq)) { return true; } - if (cell->type == "$_BUF_" || cell->type == "$equiv") + if (cell->type == ID($_BUF_) || cell->type == ID($equiv)) { - std::vector a = importDefSigSpec(cell->getPort("\\A"), timestep); - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(a, yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, false); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -1375,18 +1375,18 @@ struct SatGen return true; } - if (cell->type == "$initstate") + if (cell->type == ID($initstate)) { auto key = make_pair(prefix, timestep); if (initstates.count(key) == 0) initstates[key] = false; - std::vector y = importDefSigSpec(cell->getPort("\\Y"), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); log_assert(GetSize(y) == 1); ez->SET(y[0], initstates[key] ? ez->CONST_TRUE : ez->CONST_FALSE); if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); log_assert(GetSize(undef_y) == 1); ez->SET(undef_y[0], ez->CONST_FALSE); } @@ -1394,19 +1394,19 @@ struct SatGen return true; } - if (cell->type == "$assert") + if (cell->type == ID($assert)) { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - asserts_a[pf].append((*sigmap)(cell->getPort("\\A"))); - asserts_en[pf].append((*sigmap)(cell->getPort("\\EN"))); + asserts_a[pf].append((*sigmap)(cell->getPort(ID(A)))); + asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); return true; } - if (cell->type == "$assume") + if (cell->type == ID($assume)) { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - assumes_a[pf].append((*sigmap)(cell->getPort("\\A"))); - assumes_en[pf].append((*sigmap)(cell->getPort("\\EN"))); + assumes_a[pf].append((*sigmap)(cell->getPort(ID(A)))); + assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); return true; } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index fc9bd96fe..747f2d739 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -511,6 +511,13 @@ void yosys_setup() return; already_setup = true; + RTLIL::ID::A = "\\A"; + RTLIL::ID::B = "\\B"; + RTLIL::ID::Y = "\\Y"; + RTLIL::ID::keep = "\\keep"; + RTLIL::ID::whitebox = "\\whitebox"; + RTLIL::ID::blackbox = "\\blackbox"; + #ifdef WITH_PYTHON PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); Py_Initialize(); -- cgit v1.2.3 From b25cf3685666b66daa7e6a82f137ad3d633a17aa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 11 Aug 2019 12:23:16 +0200 Subject: Add YOSYS_NO_IDS_REFCNT configuration macro Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 4 +++- kernel/rtlil.h | 23 ++++++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 30560dd7b..d01bd0c62 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -29,10 +29,12 @@ YOSYS_NAMESPACE_BEGIN RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard; -std::vector RTLIL::IdString::global_refcount_storage_; std::vector RTLIL::IdString::global_id_storage_; dict RTLIL::IdString::global_id_index_; +#ifndef YOSYS_NO_IDS_REFCNT +std::vector RTLIL::IdString::global_refcount_storage_; std::vector RTLIL::IdString::global_free_idx_list_; +#endif #ifdef YOSYS_USE_STICKY_IDS int RTLIL::IdString::last_created_idx_[8]; int RTLIL::IdString::last_created_idx_ptr_; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c879d22e5..c08653b65 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -79,6 +79,7 @@ namespace RTLIL #undef YOSYS_XTRACE_GET_PUT #undef YOSYS_SORT_ID_FREE_LIST #undef YOSYS_USE_STICKY_IDS + #undef YOSYS_NO_IDS_REFCNT // the global id string cache @@ -88,10 +89,12 @@ namespace RTLIL ~destruct_guard_t() { ok = false; } } destruct_guard; - static std::vector global_refcount_storage_; static std::vector global_id_storage_; static dict global_id_index_; + #ifndef YOSYS_NO_IDS_REFCNT + static std::vector global_refcount_storage_; static std::vector global_free_idx_list_; + #endif #ifdef YOSYS_USE_STICKY_IDS static int last_created_idx_ptr_; @@ -129,7 +132,9 @@ namespace RTLIL static inline int get_reference(int idx) { if (idx) { + #ifndef YOSYS_NO_IDS_REFCNT global_refcount_storage_[idx]++; + #endif #ifdef YOSYS_XTRACE_GET_PUT if (yosys_xtrace) log("#X# GET-BY-INDEX '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); @@ -150,7 +155,9 @@ namespace RTLIL auto it = global_id_index_.find((char*)p); if (it != global_id_index_.end()) { + #ifndef YOSYS_NO_IDS_REFCNT global_refcount_storage_.at(it->second)++; + #endif #ifdef YOSYS_XTRACE_GET_PUT if (yosys_xtrace) log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second)); @@ -158,6 +165,7 @@ namespace RTLIL return it->second; } + #ifndef YOSYS_NO_IDS_REFCNT if (global_free_idx_list_.empty()) { if (global_id_storage_.empty()) { global_refcount_storage_.push_back(0); @@ -175,6 +183,15 @@ namespace RTLIL global_id_storage_.at(idx) = strdup(p); global_id_index_[global_id_storage_.at(idx)] = idx; global_refcount_storage_.at(idx)++; + #else + if (global_id_storage_.empty()) { + global_id_storage_.push_back((char*)""); + global_id_index_[global_id_storage_.back()] = 0; + } + int idx = global_id_storage_.size(); + global_id_storage_.push_back(strdup(p)); + global_id_index_[global_id_storage_.back()] = idx; + #endif if (yosys_xtrace) { log("#X# New IdString '%s' with index %d.\n", p, idx); @@ -198,6 +215,7 @@ namespace RTLIL return idx; } + #ifndef YOSYS_NO_IDS_REFCNT static inline void put_reference(int idx) { // put_reference() may be called from destructors after the destructor of @@ -228,6 +246,9 @@ namespace RTLIL global_id_storage_.at(idx) = nullptr; global_free_idx_list_.push_back(idx); } + #else + static inline void put_reference(int) { } + #endif // the actual IdString object is just is a single int -- cgit v1.2.3 From 0c5db07cd6cc3c19b926da21a46599f97592b20f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 11 Aug 2019 23:25:46 +0200 Subject: Fix various NDEBUG compiler warnings, closes #1255 Signed-off-by: Clifford Wolf --- kernel/log.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/log.h b/kernel/log.h index 3e1facae8..5f53f533a 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -91,7 +91,7 @@ YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(prin static inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; } # define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0) #else -static inline bool ys_debug(int n = 0) { return false; } +static inline bool ys_debug(int = 0) { return false; } # define log_debug(_fmt, ...) do { } while (0) #endif -- cgit v1.2.3 From 4cfefae21e872bb5a4dc13473316352da2b7a916 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 15 Aug 2019 09:23:57 -0700 Subject: More use of IdString::in() --- kernel/satgen.h | 51 +++++++++++++++++++++++++-------------------------- 1 file changed, 25 insertions(+), 26 deletions(-) (limited to 'kernel') diff --git a/kernel/satgen.h b/kernel/satgen.h index de480f28e..aab3017c2 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -293,7 +293,7 @@ struct SatGen int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); int undef_y_bit = ez->OR(undef_any_a, undef_any_b); - if (cell->type == ID($div) || cell->type == ID($mod)) { + if (cell->type.in(ID($div), ID($mod))) { std::vector b = importSigSpec(cell->getPort(ID(B)), timestep); undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b))); } @@ -320,17 +320,17 @@ struct SatGen std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == ID($and) || cell->type == ID($_AND_)) + if (cell->type.in(ID($and), ID($_AND_))) ez->assume(ez->vec_eq(ez->vec_and(a, b), yy)); if (cell->type == ID($_NAND_)) ez->assume(ez->vec_eq(ez->vec_not(ez->vec_and(a, b)), yy)); - if (cell->type == ID($or) || cell->type == ID($_OR_)) + if (cell->type.in(ID($or), ID($_OR_))) ez->assume(ez->vec_eq(ez->vec_or(a, b), yy)); if (cell->type == ID($_NOR_)) ez->assume(ez->vec_eq(ez->vec_not(ez->vec_or(a, b)), yy)); - if (cell->type == ID($xor) || cell->type == ID($_XOR_)) + if (cell->type.in(ID($xor), ID($_XOR_))) ez->assume(ez->vec_eq(ez->vec_xor(a, b), yy)); - if (cell->type == ID($xnor) || cell->type == ID($_XNOR_)) + if (cell->type.in(ID($xnor), ID($_XNOR_))) ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), yy)); if (cell->type == ID($_ANDNOT_)) ez->assume(ez->vec_eq(ez->vec_and(a, ez->vec_not(b)), yy)); @@ -456,7 +456,7 @@ struct SatGen return true; } - if (cell->type == ID($_NOT_) || cell->type == ID($not)) + if (cell->type.in(ID($_NOT_), ID($not))) { std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); @@ -475,7 +475,7 @@ struct SatGen return true; } - if (cell->type == ID($_MUX_) || cell->type == ID($mux) || cell->type == ID($_NMUX_)) + if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_))) { std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); @@ -555,7 +555,7 @@ struct SatGen return true; } - if (cell->type == ID($pos) || cell->type == ID($neg)) + if (cell->type.in(ID($pos), ID($neg))) { std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); @@ -589,8 +589,7 @@ struct SatGen return true; } - if (cell->type == ID($reduce_and) || cell->type == ID($reduce_or) || cell->type == ID($reduce_xor) || - cell->type == ID($reduce_xnor) || cell->type == ID($reduce_bool) || cell->type == ID($logic_not)) + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not))) { std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); @@ -599,7 +598,7 @@ struct SatGen if (cell->type == ID($reduce_and)) ez->SET(ez->expression(ez->OpAnd, a), yy.at(0)); - if (cell->type == ID($reduce_or) || cell->type == ID($reduce_bool)) + if (cell->type.in(ID($reduce_or), ID($reduce_bool))) ez->SET(ez->expression(ez->OpOr, a), yy.at(0)); if (cell->type == ID($reduce_xor)) ez->SET(ez->expression(ez->OpXor, a), yy.at(0)); @@ -620,11 +619,11 @@ struct SatGen int a0 = ez->expression(ezSAT::OpOr, ez->vec_and(ez->vec_not(a), ez->vec_not(undef_a))); ez->assume(ez->IFF(ez->AND(ez->NOT(a0), aX), undef_y.at(0))); } - else if (cell->type == ID($reduce_or) || cell->type == ID($reduce_bool) || cell->type == ID($logic_not)) { + else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) { int a1 = ez->expression(ezSAT::OpOr, ez->vec_and(a, ez->vec_not(undef_a))); ez->assume(ez->IFF(ez->AND(ez->NOT(a1), aX), undef_y.at(0))); } - else if (cell->type == ID($reduce_xor) || cell->type == ID($reduce_xnor)) { + else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { ez->assume(ez->IFF(aX, undef_y.at(0))); } else log_abort(); @@ -637,7 +636,7 @@ struct SatGen return true; } - if (cell->type == ID($logic_and) || cell->type == ID($logic_or)) + if (cell->type.in(ID($logic_and), ID($logic_or))) { std::vector vec_a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector vec_b = importDefSigSpec(cell->getPort(ID(B)), timestep); @@ -683,7 +682,7 @@ struct SatGen return true; } - if (cell->type == ID($lt) || cell->type == ID($le) || cell->type == ID($eq) || cell->type == ID($ne) || cell->type == ID($eqx) || cell->type == ID($nex) || cell->type == ID($ge) || cell->type == ID($gt)) + if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); @@ -693,7 +692,7 @@ struct SatGen std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (model_undef && (cell->type == ID($eqx) || cell->type == ID($nex))) { + if (model_undef && cell->type.in(ID($eqx), ID($nex))) { std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); extendSignalWidth(undef_a, undef_b, cell, true); @@ -705,9 +704,9 @@ struct SatGen ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), yy.at(0)); if (cell->type == ID($le)) ez->SET(is_signed ? ez->vec_le_signed(a, b) : ez->vec_le_unsigned(a, b), yy.at(0)); - if (cell->type == ID($eq) || cell->type == ID($eqx)) + if (cell->type.in(ID($eq), ID($eqx))) ez->SET(ez->vec_eq(a, b), yy.at(0)); - if (cell->type == ID($ne) || cell->type == ID($nex)) + if (cell->type.in(ID($ne), ID($nex))) ez->SET(ez->vec_ne(a, b), yy.at(0)); if (cell->type == ID($ge)) ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), yy.at(0)); @@ -716,7 +715,7 @@ struct SatGen for (size_t i = 1; i < y.size(); i++) ez->SET(ez->CONST_FALSE, yy.at(i)); - if (model_undef && (cell->type == ID($eqx) || cell->type == ID($nex))) + if (model_undef && cell->type.in(ID($eqx), ID($nex))) { std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); @@ -733,7 +732,7 @@ struct SatGen ez->assume(ez->vec_eq(y, yy)); } - else if (model_undef && (cell->type == ID($eq) || cell->type == ID($ne))) + else if (model_undef && cell->type.in(ID($eq), ID($ne))) { std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); @@ -767,7 +766,7 @@ struct SatGen return true; } - if (cell->type == ID($shl) || cell->type == ID($shr) || cell->type == ID($sshl) || cell->type == ID($sshr) || cell->type == ID($shift) || cell->type == ID($shiftx)) + if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); @@ -786,7 +785,7 @@ struct SatGen std::vector yy = model_undef ? ez->vec_var(y.size()) : y; std::vector shifted_a; - if (cell->type == ID($shl) || cell->type == ID($sshl)) + if (cell->type.in( ID($shl), ID($sshl))) shifted_a = ez->vec_shift_left(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($shr)) @@ -795,7 +794,7 @@ struct SatGen if (cell->type == ID($sshr)) shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); - if (cell->type == ID($shift) || cell->type == ID($shiftx)) + if (cell->type.in(ID($shift), ID($shiftx))) shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); ez->assume(ez->vec_eq(shifted_a, yy)); @@ -816,7 +815,7 @@ struct SatGen while (undef_y.size() > undef_a.size()) undef_a.push_back(extend_bit); - if (cell->type == ID($shl) || cell->type == ID($sshl)) + if (cell->type.in(ID($shl), ID($sshl))) undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($shr)) @@ -936,7 +935,7 @@ struct SatGen return true; } - if (cell->type == ID($div) || cell->type == ID($mod)) + if (cell->type.in(ID($div), ID($mod))) { std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); @@ -1356,7 +1355,7 @@ struct SatGen return true; } - if (cell->type == ID($_BUF_) || cell->type == ID($equiv)) + if (cell->type.in(ID($_BUF_), ID($equiv))) { std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); -- cgit v1.2.3 From 52355f5185fe42e28775e897f458b38a439c0ec5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 15 Aug 2019 14:50:10 -0700 Subject: Use more ID::{A,B,Y,blackbox,whitebox} --- kernel/cellaigs.cc | 96 ++++++++++----------- kernel/celledges.cc | 14 ++-- kernel/celltypes.h | 10 +-- kernel/consteval.h | 16 ++-- kernel/macc.h | 8 +- kernel/rtlil.cc | 192 +++++++++++++++++++++--------------------- kernel/satgen.h | 236 ++++++++++++++++++++++++++-------------------------- kernel/yosys.h | 2 + 8 files changed, 288 insertions(+), 286 deletions(-) (limited to 'kernel') diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 6d496db45..02854edb2 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -292,19 +292,19 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($_BUF_))) { - for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) { - int A = mk.inport(ID(A), i); + for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { + int A = mk.inport(ID::A, i); int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A; - mk.outport(Y, ID(Y), i); + mk.outport(Y, ID::Y, i); } goto optimize; } if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { - for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) { - int A = mk.inport(ID(A), i); - int B = mk.inport(ID(B), i); + for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { + int A = mk.inport(ID::A, i); + int B = mk.inport(ID::B, i); int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) : cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) : cell->type.in(ID($or), ID($_OR_)) ? mk.or_gate(A, B) : @@ -313,7 +313,7 @@ Aig::Aig(Cell *cell) cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) : cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) : cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1; - mk.outport(Y, ID(Y), i); + mk.outport(Y, ID::Y, i); } goto optimize; } @@ -321,22 +321,22 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($mux), ID($_MUX_))) { int S = mk.inport(ID(S)); - for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) { - int A = mk.inport(ID(A), i); - int B = mk.inport(ID(B), i); + for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { + int A = mk.inport(ID::A, i); + int B = mk.inport(ID::B, i); int Y = mk.mux_gate(A, B, S); if (cell->type == ID($_NMUX_)) Y = mk.not_gate(Y); - mk.outport(Y, ID(Y), i); + mk.outport(Y, ID::Y, i); } goto optimize; } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { - int Y = mk.inport(ID(A), 0); - for (int i = 1; i < GetSize(cell->getPort(ID(A))); i++) { - int A = mk.inport(ID(A), i); + int Y = mk.inport(ID::A, 0); + for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) { + int A = mk.inport(ID::A, i); if (cell->type == ID($reduce_and)) Y = mk.and_gate(A, Y); if (cell->type == ID($reduce_or)) Y = mk.or_gate(A, Y); if (cell->type == ID($reduce_bool)) Y = mk.or_gate(A, Y); @@ -345,35 +345,35 @@ Aig::Aig(Cell *cell) } if (cell->type == ID($reduce_xnor)) Y = mk.not_gate(Y); - mk.outport(Y, ID(Y), 0); - for (int i = 1; i < GetSize(cell->getPort(ID(Y))); i++) - mk.outport(mk.bool_node(false), ID(Y), i); + mk.outport(Y, ID::Y, 0); + for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++) + mk.outport(mk.bool_node(false), ID::Y, i); goto optimize; } if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or))) { - int A = mk.inport(ID(A), 0), Y = -1; - for (int i = 1; i < GetSize(cell->getPort(ID(A))); i++) - A = mk.or_gate(mk.inport(ID(A), i), A); + int A = mk.inport(ID::A, 0), Y = -1; + for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) + A = mk.or_gate(mk.inport(ID::A, i), A); if (cell->type.in(ID($logic_and), ID($logic_or))) { - int B = mk.inport(ID(B), 0); - for (int i = 1; i < GetSize(cell->getPort(ID(B))); i++) - B = mk.or_gate(mk.inport(ID(B), i), B); + int B = mk.inport(ID::B, 0); + for (int i = 1; i < GetSize(cell->getPort(ID::B)); i++) + B = mk.or_gate(mk.inport(ID::B, i), B); if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B); if (cell->type == ID($logic_or)) Y = mk.or_gate(A, B); } else { if (cell->type == ID($logic_not)) Y = mk.not_gate(A); } - mk.outport_bool(Y, ID(Y)); + mk.outport_bool(Y, ID::Y); goto optimize; } if (cell->type.in(ID($add), ID($sub))) { - int width = GetSize(cell->getPort(ID(Y))); - vector A = mk.inport_vec(ID(A), width); - vector B = mk.inport_vec(ID(B), width); + int width = GetSize(cell->getPort(ID::Y)); + vector A = mk.inport_vec(ID::A, width); + vector B = mk.inport_vec(ID::B, width); int carry = mk.bool_node(false); if (cell->type == ID($sub)) { for (auto &n : B) @@ -381,15 +381,15 @@ Aig::Aig(Cell *cell) carry = mk.not_gate(carry); } vector Y = mk.adder(A, B, carry); - mk.outport_vec(Y, ID(Y)); + mk.outport_vec(Y, ID::Y); goto optimize; } if (cell->type == ID($alu)) { - int width = GetSize(cell->getPort(ID(Y))); - vector A = mk.inport_vec(ID(A), width); - vector B = mk.inport_vec(ID(B), width); + int width = GetSize(cell->getPort(ID::Y)); + vector A = mk.inport_vec(ID::A, width); + vector B = mk.inport_vec(ID::B, width); int carry = mk.inport(ID(CI)); int binv = mk.inport(ID(BI)); for (auto &n : B) @@ -398,7 +398,7 @@ Aig::Aig(Cell *cell) vector Y = mk.adder(A, B, carry, &X, &CO); for (int i = 0; i < width; i++) X[i] = mk.xor_gate(A[i], B[i]); - mk.outport_vec(Y, ID(Y)); + mk.outport_vec(Y, ID::Y); mk.outport_vec(X, ID(X)); mk.outport_vec(CO, ID(CO)); goto optimize; @@ -406,57 +406,57 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($eq), ID($ne))) { - int width = max(GetSize(cell->getPort(ID(A))), GetSize(cell->getPort(ID(B)))); - vector A = mk.inport_vec(ID(A), width); - vector B = mk.inport_vec(ID(B), width); + int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B))); + vector A = mk.inport_vec(ID::A, width); + vector B = mk.inport_vec(ID::B, width); int Y = mk.bool_node(false); for (int i = 0; i < width; i++) Y = mk.or_gate(Y, mk.xor_gate(A[i], B[i])); if (cell->type == ID($eq)) Y = mk.not_gate(Y); - mk.outport_bool(Y, ID(Y)); + mk.outport_bool(Y, ID::Y); goto optimize; } if (cell->type == ID($_AOI3_)) { - int A = mk.inport(ID(A)); - int B = mk.inport(ID(B)); + int A = mk.inport(ID::A); + int B = mk.inport(ID::B); int C = mk.inport(ID(C)); int Y = mk.nor_gate(mk.and_gate(A, B), C); - mk.outport(Y, ID(Y)); + mk.outport(Y, ID::Y); goto optimize; } if (cell->type == ID($_OAI3_)) { - int A = mk.inport(ID(A)); - int B = mk.inport(ID(B)); + int A = mk.inport(ID::A); + int B = mk.inport(ID::B); int C = mk.inport(ID(C)); int Y = mk.nand_gate(mk.or_gate(A, B), C); - mk.outport(Y, ID(Y)); + mk.outport(Y, ID::Y); goto optimize; } if (cell->type == ID($_AOI4_)) { - int A = mk.inport(ID(A)); - int B = mk.inport(ID(B)); + int A = mk.inport(ID::A); + int B = mk.inport(ID::B); int C = mk.inport(ID(C)); int D = mk.inport(ID(D)); int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D)); - mk.outport(Y, ID(Y)); + mk.outport(Y, ID::Y); goto optimize; } if (cell->type == ID($_OAI4_)) { - int A = mk.inport(ID(A)); - int B = mk.inport(ID(B)); + int A = mk.inport(ID::A); + int B = mk.inport(ID::B); int C = mk.inport(ID(C)); int D = mk.inport(ID(D)); int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); - mk.outport(Y, ID(Y)); + mk.outport(Y, ID::Y); goto optimize; } diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 7a324a06e..d0bb99e83 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -41,7 +41,7 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -71,7 +71,7 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -87,7 +87,7 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -114,7 +114,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; int a_width = GetSize(cell->getPort(A)); @@ -124,7 +124,7 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); @@ -138,7 +138,7 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), S = ID(S), Y = ID(Y); + IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); diff --git a/kernel/celltypes.h b/kernel/celltypes.h index ade305e83..bc96fd602 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -84,7 +84,7 @@ struct CellTypes { setup_internals_eval(); - IdString A = ID(A), B = ID(B), EN = ID(EN), Y = ID(Y); + IdString A = ID::A, B = ID::B, EN = ID(EN), Y = ID::Y; IdString SRC = ID(SRC), DST = ID(DST), DAT = ID(DAT); IdString EN_SRC = ID(EN_SRC), EN_DST = ID(EN_DST); @@ -121,7 +121,7 @@ struct CellTypes ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($logic_and), ID($logic_or), ID($concat), ID($macc) }; - IdString A = ID(A), B = ID(B), S = ID(S), Y = ID(Y); + IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; IdString P = ID(P), G = ID(G), C = ID(C), X = ID(X); IdString BI = ID(BI), CI = ID(CI), CO = ID(CO), EN = ID(EN); @@ -177,19 +177,19 @@ struct CellTypes { setup_stdcells_eval(); - IdString A = ID(A), E = ID(E), Y = ID(Y); + IdString A = ID::A, E = ID(E), Y = ID::Y; setup_type(ID($_TBUF_), {A, E}, {Y}, true); } void setup_stdcells_eval() { - IdString A = ID(A), B = ID(B), C = ID(C), D = ID(D); + IdString A = ID::A, B = ID::B, C = ID(C), D = ID(D); IdString E = ID(E), F = ID(F), G = ID(G), H = ID(H); IdString I = ID(I), J = ID(J), K = ID(K), L = ID(L); IdString M = ID(M), N = ID(N), O = ID(O), P = ID(P); IdString S = ID(S), T = ID(T), U = ID(U), V = ID(V); - IdString Y = ID(Y); + IdString Y = ID::Y; setup_type(ID($_BUF_), {A}, {Y}, true); setup_type(ID($_NOT_), {A}, {Y}, true); diff --git a/kernel/consteval.h b/kernel/consteval.h index 09b4c434b..7a83d28e7 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -128,8 +128,8 @@ struct ConstEval RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - log_assert(cell->hasPort(ID(Y))); - sig_y = values_map(assign_map(cell->getPort(ID(Y)))); + log_assert(cell->hasPort(ID::Y)); + sig_y = values_map(assign_map(cell->getPort(ID::Y))); if (sig_y.is_fully_const()) return true; @@ -139,11 +139,11 @@ struct ConstEval return false; } - if (cell->hasPort(ID(A))) - sig_a = cell->getPort(ID(A)); + if (cell->hasPort(ID::A)) + sig_a = cell->getPort(ID::A); - if (cell->hasPort(ID(B))) - sig_b = cell->getPort(ID(B)); + if (cell->hasPort(ID::B)) + sig_b = cell->getPort(ID::B); if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_))) { @@ -298,11 +298,11 @@ struct ConstEval return false; } - RTLIL::Const result(0, GetSize(cell->getPort(ID(Y)))); + RTLIL::Const result(0, GetSize(cell->getPort(ID::Y))); if (!macc.eval(result)) log_abort(); - set(cell->getPort(ID(Y)), result); + set(cell->getPort(ID::Y), result); } else { diff --git a/kernel/macc.h b/kernel/macc.h index e07e7e01a..371f6737d 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -99,10 +99,10 @@ struct Macc void from_cell(RTLIL::Cell *cell) { - RTLIL::SigSpec port_a = cell->getPort(ID(A)); + RTLIL::SigSpec port_a = cell->getPort(ID::A); ports.clear(); - bit_ports = cell->getPort(ID(B)); + bit_ports = cell->getPort(ID::B); std::vector config_bits = cell->getParam(ID(CONFIG)).bits; int config_cursor = 0; @@ -191,8 +191,8 @@ struct Macc port_a.append(port.in_b); } - cell->setPort(ID(A), port_a); - cell->setPort(ID(B), bit_ports); + cell->setPort(ID::A, port_a); + cell->setPort(ID::B, bit_ports); cell->setParam(ID(CONFIG), config_bits); cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); cell->setParam(ID(A_WIDTH), GetSize(port_a)); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d01bd0c62..1d380135b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -717,7 +717,7 @@ void RTLIL::Module::makeblackbox() processes.clear(); remove(delwires); - set_bool_attribute(ID(blackbox)); + set_bool_attribute(ID::blackbox); } void RTLIL::Module::reprocess_module(RTLIL::Design *, dict) @@ -845,8 +845,8 @@ namespace { if (cell->type.in(ID($not), ID($pos), ID($neg))) { param_bool(ID(A_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(); return; } @@ -854,17 +854,17 @@ namespace { if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { param_bool(ID(A_SIGNED)); param_bool(ID(B_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(B), param(ID(B_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::B, param(ID(B_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(); return; } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { param_bool(ID(A_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(); return; } @@ -872,9 +872,9 @@ namespace { if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { param_bool(ID(A_SIGNED)); param_bool(ID(B_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(B), param(ID(B_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::B, param(ID(B_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(false); return; } @@ -882,9 +882,9 @@ namespace { if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { param_bool(ID(A_SIGNED)); param_bool(ID(B_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(B), param(ID(B_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::B, param(ID(B_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(); return; } @@ -892,19 +892,19 @@ namespace { if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) { param_bool(ID(A_SIGNED)); param_bool(ID(B_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(B), param(ID(B_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::B, param(ID(B_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(cell->type != ID($pow)); return; } if (cell->type == ID($fa)) { - port(ID(A), param(ID(WIDTH))); - port(ID(B), param(ID(WIDTH))); + port(ID::A, param(ID(WIDTH))); + port(ID::B, param(ID(WIDTH))); port(ID(C), param(ID(WIDTH))); port(ID(X), param(ID(WIDTH))); - port(ID(Y), param(ID(WIDTH))); + port(ID::Y, param(ID(WIDTH))); check_expected(); return; } @@ -921,12 +921,12 @@ namespace { if (cell->type == ID($alu)) { param_bool(ID(A_SIGNED)); param_bool(ID(B_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(B), param(ID(B_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::B, param(ID(B_WIDTH))); port(ID(CI), 1); port(ID(BI), 1); port(ID(X), param(ID(Y_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); port(ID(CO), param(ID(Y_WIDTH))); check_expected(); return; @@ -935,9 +935,9 @@ namespace { if (cell->type == ID($macc)) { param(ID(CONFIG)); param(ID(CONFIG_WIDTH)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(B), param(ID(B_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::B, param(ID(B_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(); Macc().from_cell(cell); return; @@ -945,8 +945,8 @@ namespace { if (cell->type == ID($logic_not)) { param_bool(ID(A_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(); return; } @@ -954,17 +954,17 @@ namespace { if (cell->type.in(ID($logic_and), ID($logic_or))) { param_bool(ID(A_SIGNED)); param_bool(ID(B_SIGNED)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(B), param(ID(B_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::B, param(ID(B_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); check_expected(false); return; } if (cell->type == ID($slice)) { param(ID(OFFSET)); - port(ID(A), param(ID(A_WIDTH))); - port(ID(Y), param(ID(Y_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::Y, param(ID(Y_WIDTH))); if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH))) error(__LINE__); check_expected(); @@ -972,35 +972,35 @@ namespace { } if (cell->type == ID($concat)) { - port(ID(A), param(ID(A_WIDTH))); - port(ID(B), param(ID(B_WIDTH))); - port(ID(Y), param(ID(A_WIDTH)) + param(ID(B_WIDTH))); + port(ID::A, param(ID(A_WIDTH))); + port(ID::B, param(ID(B_WIDTH))); + port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH))); check_expected(); return; } if (cell->type == ID($mux)) { - port(ID(A), param(ID(WIDTH))); - port(ID(B), param(ID(WIDTH))); + port(ID::A, param(ID(WIDTH))); + port(ID::B, param(ID(WIDTH))); port(ID(S), 1); - port(ID(Y), param(ID(WIDTH))); + port(ID::Y, param(ID(WIDTH))); check_expected(); return; } if (cell->type == ID($pmux)) { - port(ID(A), param(ID(WIDTH))); - port(ID(B), param(ID(WIDTH)) * param(ID(S_WIDTH))); + port(ID::A, param(ID(WIDTH))); + port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH))); port(ID(S), param(ID(S_WIDTH))); - port(ID(Y), param(ID(WIDTH))); + port(ID::Y, param(ID(WIDTH))); check_expected(); return; } if (cell->type == ID($lut)) { param(ID(LUT)); - port(ID(A), param(ID(WIDTH))); - port(ID(Y), 1); + port(ID::A, param(ID(WIDTH))); + port(ID::Y, 1); check_expected(); return; } @@ -1008,8 +1008,8 @@ namespace { if (cell->type == ID($sop)) { param(ID(DEPTH)); param(ID(TABLE)); - port(ID(A), param(ID(WIDTH))); - port(ID(Y), 1); + port(ID::A, param(ID(WIDTH))); + port(ID::Y, 1); check_expected(); return; } @@ -1175,36 +1175,36 @@ namespace { } if (cell->type == ID($tribuf)) { - port(ID(A), param(ID(WIDTH))); - port(ID(Y), param(ID(WIDTH))); + port(ID::A, param(ID(WIDTH))); + port(ID::Y, param(ID(WIDTH))); port(ID(EN), 1); check_expected(); return; } if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) { - port(ID(A), 1); + port(ID::A, 1); port(ID(EN), 1); check_expected(); return; } if (cell->type == ID($initstate)) { - port(ID(Y), 1); + port(ID::Y, 1); check_expected(); return; } if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) { - port(ID(Y), param(ID(WIDTH))); + port(ID::Y, param(ID(WIDTH))); check_expected(); return; } if (cell->type == ID($equiv)) { - port(ID(A), 1); - port(ID(B), 1); - port(ID(Y), 1); + port(ID::A, 1); + port(ID::B, 1); + port(ID::Y, 1); check_expected(); return; } @@ -1831,8 +1831,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth cell->parameters[ID(A_SIGNED)] = is_signed; \ cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ - cell->setPort(ID(A), sig_a); \ - cell->setPort(ID(Y), sig_y); \ + cell->setPort(ID::A, sig_a); \ + cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ @@ -1860,9 +1860,9 @@ DEF_METHOD(LogicNot, 1, ID($logic_not)) cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ cell->parameters[ID(B_WIDTH)] = sig_b.size(); \ cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ - cell->setPort(ID(A), sig_a); \ - cell->setPort(ID(B), sig_b); \ - cell->setPort(ID(Y), sig_y); \ + cell->setPort(ID::A, sig_a); \ + cell->setPort(ID::B, sig_b); \ + cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ @@ -1903,10 +1903,10 @@ DEF_METHOD(LogicOr, 1, ID($logic_or)) RTLIL::Cell *cell = addCell(name, _type); \ cell->parameters[ID(WIDTH)] = sig_a.size(); \ if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \ - cell->setPort(ID(A), sig_a); \ - cell->setPort(ID(B), sig_b); \ + cell->setPort(ID::A, sig_a); \ + cell->setPort(ID::B, sig_b); \ cell->setPort(ID(S), sig_s); \ - cell->setPort(ID(Y), sig_y); \ + cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ } \ @@ -2006,9 +2006,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R cell->parameters[ID(A_WIDTH)] = sig_a.size(); cell->parameters[ID(B_WIDTH)] = sig_b.size(); cell->parameters[ID(Y_WIDTH)] = sig_y.size(); - cell->setPort(ID(A), sig_a); - cell->setPort(ID(B), sig_b); - cell->setPort(ID(Y), sig_y); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::B, sig_b); + cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } @@ -2019,8 +2019,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, cell->parameters[ID(A_WIDTH)] = sig_a.size(); cell->parameters[ID(Y_WIDTH)] = sig_y.size(); cell->parameters[ID(OFFSET)] = offset; - cell->setPort(ID(A), sig_a); - cell->setPort(ID(Y), sig_y); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } @@ -2030,9 +2030,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell *cell = addCell(name, ID($concat)); cell->parameters[ID(A_WIDTH)] = sig_a.size(); cell->parameters[ID(B_WIDTH)] = sig_b.size(); - cell->setPort(ID(A), sig_a); - cell->setPort(ID(B), sig_b); - cell->setPort(ID(Y), sig_y); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::B, sig_b); + cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } @@ -2042,8 +2042,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, R RTLIL::Cell *cell = addCell(name, ID($lut)); cell->parameters[ID(LUT)] = lut; cell->parameters[ID(WIDTH)] = sig_a.size(); - cell->setPort(ID(A), sig_a); - cell->setPort(ID(Y), sig_y); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } @@ -2052,9 +2052,9 @@ RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a { RTLIL::Cell *cell = addCell(name, ID($tribuf)); cell->parameters[ID(WIDTH)] = sig_a.size(); - cell->setPort(ID(A), sig_a); + cell->setPort(ID::A, sig_a); cell->setPort(ID(EN), sig_en); - cell->setPort(ID(Y), sig_y); + cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } @@ -2062,7 +2062,7 @@ RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($assert)); - cell->setPort(ID(A), sig_a); + cell->setPort(ID::A, sig_a); cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; @@ -2071,7 +2071,7 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($assume)); - cell->setPort(ID(A), sig_a); + cell->setPort(ID::A, sig_a); cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; @@ -2080,7 +2080,7 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($live)); - cell->setPort(ID(A), sig_a); + cell->setPort(ID::A, sig_a); cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; @@ -2089,7 +2089,7 @@ RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($fair)); - cell->setPort(ID(A), sig_a); + cell->setPort(ID::A, sig_a); cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; @@ -2098,7 +2098,7 @@ RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($cover)); - cell->setPort(ID(A), sig_a); + cell->setPort(ID::A, sig_a); cell->setPort(ID(EN), sig_en); cell->set_src_attribute(src); return cell; @@ -2107,9 +2107,9 @@ RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($equiv)); - cell->setPort(ID(A), sig_a); - cell->setPort(ID(B), sig_b); - cell->setPort(ID(Y), sig_y); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::B, sig_b); + cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; } @@ -2308,7 +2308,7 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const st RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($anyconst)); cell->setParam(ID(WIDTH), width); - cell->setPort(ID(Y), sig); + cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; } @@ -2318,7 +2318,7 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std: RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($anyseq)); cell->setParam(ID(WIDTH), width); - cell->setPort(ID(Y), sig); + cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; } @@ -2328,7 +2328,7 @@ RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const st RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($allconst)); cell->setParam(ID(WIDTH), width); - cell->setPort(ID(Y), sig); + cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; } @@ -2338,7 +2338,7 @@ RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std: RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($allseq)); cell->setParam(ID(WIDTH), width); - cell->setPort(ID(Y), sig); + cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; } @@ -2347,7 +2347,7 @@ RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string { RTLIL::SigSpec sig = addWire(NEW_ID); Cell *cell = addCell(name, ID($initstate)); - cell->setPort(ID(Y), sig); + cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; } @@ -2569,7 +2569,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; if (type == ID($mux) || type == ID($pmux)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID(Y)]); + parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]); if (type == ID($pmux)) parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]); check(); @@ -2577,12 +2577,12 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) } if (type == ID($lut) || type == ID($sop)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID(A)]); + parameters[ID(WIDTH)] = GetSize(connections_[ID::A]); return; } if (type == ID($fa)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID(Y)]); + parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]); return; } @@ -2593,28 +2593,28 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc)); - if (connections_.count(ID(A))) { + if (connections_.count(ID::A)) { if (signedness_ab) { if (set_a_signed) parameters[ID(A_SIGNED)] = true; else if (parameters.count(ID(A_SIGNED)) == 0) parameters[ID(A_SIGNED)] = false; } - parameters[ID(A_WIDTH)] = GetSize(connections_[ID(A)]); + parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]); } - if (connections_.count(ID(B))) { + if (connections_.count(ID::B)) { if (signedness_ab) { if (set_b_signed) parameters[ID(B_SIGNED)] = true; else if (parameters.count(ID(B_SIGNED)) == 0) parameters[ID(B_SIGNED)] = false; } - parameters[ID(B_WIDTH)] = GetSize(connections_[ID(B)]); + parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]); } - if (connections_.count(ID(Y))) - parameters[ID(Y_WIDTH)] = GetSize(connections_[ID(Y)]); + if (connections_.count(ID::Y)) + parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]); if (connections_.count(ID(Q))) parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]); diff --git a/kernel/satgen.h b/kernel/satgen.h index aab3017c2..133389eee 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -281,9 +281,9 @@ struct SatGen if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod)) || is_arith_compare)) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); if (is_arith_compare) extendSignalWidth(undef_a, undef_b, cell, true); else @@ -294,7 +294,7 @@ struct SatGen int undef_y_bit = ez->OR(undef_any_a, undef_any_b); if (cell->type.in(ID($div), ID($mod))) { - std::vector b = importSigSpec(cell->getPort(ID(B)), timestep); + std::vector b = importSigSpec(cell->getPort(ID::B), timestep); undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b))); } @@ -313,9 +313,9 @@ struct SatGen if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($sub))) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -343,9 +343,9 @@ struct SatGen if (model_undef && !arith_undef_handled) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell, false); if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_))) { @@ -384,7 +384,7 @@ struct SatGen } else if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); undefGating(y, yy, undef_y); } return true; @@ -395,11 +395,11 @@ struct SatGen bool aoi_mode = cell->type.in(ID($_AOI3_), ID($_AOI4_)); bool three_mode = cell->type.in(ID($_AOI3_), ID($_OAI3_)); - int a = importDefSigSpec(cell->getPort(ID(A)), timestep).at(0); - int b = importDefSigSpec(cell->getPort(ID(B)), timestep).at(0); + int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0); + int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0); int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0); int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0); - int y = importDefSigSpec(cell->getPort(ID(Y)), timestep).at(0); + int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); int yy = model_undef ? ez->literal() : y; if (cell->type.in(ID($_AOI3_), ID($_AOI4_))) @@ -409,11 +409,11 @@ struct SatGen if (model_undef) { - int undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep).at(0); - int undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep).at(0); + int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0); + int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0); int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0); int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0); - int undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep).at(0); + int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0); if (aoi_mode) { @@ -458,16 +458,16 @@ struct SatGen if (cell->type.in(ID($_NOT_), ID($not))) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(ez->vec_not(a), yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, false); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -477,10 +477,10 @@ struct SatGen if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_))) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector s = importDefSigSpec(cell->getPort(ID(S)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; if (cell->type == ID($_NMUX_)) @@ -490,10 +490,10 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); std::vector undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector unequal_ab = ez->vec_not(ez->vec_iff(a, b)); std::vector undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b)); @@ -506,10 +506,10 @@ struct SatGen if (cell->type == ID($pmux)) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector s = importDefSigSpec(cell->getPort(ID(S)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -522,10 +522,10 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); std::vector undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); int maybe_a = ez->CONST_TRUE; @@ -557,8 +557,8 @@ struct SatGen if (cell->type.in(ID($pos), ID($neg))) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -572,8 +572,8 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidthUnary(undef_a, undef_y, cell); if (cell->type == ID($pos)) { @@ -591,8 +591,8 @@ struct SatGen if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not))) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -611,8 +611,8 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); int aX = ez->expression(ezSAT::OpOr, undef_a); if (cell->type == ID($reduce_and)) { @@ -638,12 +638,12 @@ struct SatGen if (cell->type.in(ID($logic_and), ID($logic_or))) { - std::vector vec_a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector vec_b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector vec_a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector vec_b = importDefSigSpec(cell->getPort(ID::B), timestep); int a = ez->expression(ez->OpOr, vec_a); int b = ez->expression(ez->OpOr, vec_b); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -656,9 +656,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a))); int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b))); @@ -685,16 +685,16 @@ struct SatGen if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidth(a, b, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; if (model_undef && cell->type.in(ID($eqx), ID($nex))) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); extendSignalWidth(undef_a, undef_b, cell, true); a = ez->vec_or(a, undef_a); b = ez->vec_or(b, undef_b); @@ -717,9 +717,9 @@ struct SatGen if (model_undef && cell->type.in(ID($eqx), ID($nex))) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidth(undef_a, undef_b, cell, true); if (cell->type == ID($eqx)) @@ -734,9 +734,9 @@ struct SatGen } else if (model_undef && cell->type.in(ID($eq), ID($ne))) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidth(undef_a, undef_b, cell, true); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); @@ -758,7 +758,7 @@ struct SatGen else { if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); undefGating(y, yy, undef_y); } log_assert(!model_undef || arith_undef_handled); @@ -768,9 +768,9 @@ struct SatGen if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); int extend_bit = ez->CONST_FALSE; @@ -801,9 +801,9 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector undef_a_shifted; extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE; @@ -840,9 +840,9 @@ struct SatGen if (cell->type == ID($mul)) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -859,7 +859,7 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); undefGating(y, yy, undef_y); } return true; @@ -867,9 +867,9 @@ struct SatGen if (cell->type == ID($macc)) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); Macc macc; macc.from_cell(cell); @@ -918,13 +918,13 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); ez->assume(ez->vec_eq(undef_y, std::vector(GetSize(y), ez->OR(undef_any_a, undef_any_b)))); undefGating(y, tmp, undef_y); @@ -937,9 +937,9 @@ struct SatGen if (cell->type.in(ID($div), ID($mod))) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidth(a, b, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -993,11 +993,11 @@ struct SatGen only_first_one.at(0) = ez->CONST_TRUE; div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones); } else { - div_zero_result.insert(div_zero_result.end(), cell->getPort(ID(A)).size(), ez->CONST_TRUE); + div_zero_result.insert(div_zero_result.end(), cell->getPort(ID::A).size(), ez->CONST_TRUE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE); } } else { - int copy_a_bits = min(cell->getPort(ID(A)).size(), cell->getPort(ID(B)).size()); + int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); @@ -1009,7 +1009,7 @@ struct SatGen if (model_undef) { log_assert(arith_undef_handled); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); undefGating(y, yy, undef_y); } return true; @@ -1017,8 +1017,8 @@ struct SatGen if (cell->type == ID($lut)) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector lut; for (auto bit : cell->getParam(ID(LUT)).bits) @@ -1029,7 +1029,7 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector t(lut), u(GetSize(t), ez->CONST_FALSE); for (int i = GetSize(a)-1; i >= 0; i--) @@ -1047,7 +1047,7 @@ struct SatGen log_assert(GetSize(t) == 1); log_assert(GetSize(u) == 1); undefGating(y, t, u); - ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID(Y)), timestep), u)); + ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID::Y), timestep), u)); } else { @@ -1067,8 +1067,8 @@ struct SatGen if (cell->type == ID($sop)) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - int y = importDefSigSpec(cell->getPort(ID(Y)), timestep).at(0); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); int width = cell->getParam(ID(WIDTH)).as_int(); int depth = cell->getParam(ID(DEPTH)).as_int(); @@ -1096,8 +1096,8 @@ struct SatGen if (model_undef) { std::vector products, undef_products; - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - int undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep).at(0); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0); for (int i = 0; i < depth; i++) { @@ -1149,10 +1149,10 @@ struct SatGen if (cell->type == ID($fa)) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector c = importDefSigSpec(cell->getPort(ID(C)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector x = importDefSigSpec(cell->getPort(ID(X)), timestep); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; @@ -1167,11 +1167,11 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); std::vector undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); @@ -1217,9 +1217,9 @@ struct SatGen if (cell->type == ID($alu)) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector b = importDefSigSpec(cell->getPort(ID(B)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector b = importDefSigSpec(cell->getPort(ID::B), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector x = importDefSigSpec(cell->getPort(ID(X)), timestep); std::vector ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); std::vector bi = importDefSigSpec(cell->getPort(ID(BI)), timestep); @@ -1248,12 +1248,12 @@ struct SatGen if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); std::vector undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); std::vector undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); std::vector undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); @@ -1283,17 +1283,17 @@ struct SatGen if (cell->type == ID($slice)) { - RTLIL::SigSpec a = cell->getPort(ID(A)); - RTLIL::SigSpec y = cell->getPort(ID(Y)); + RTLIL::SigSpec a = cell->getPort(ID::A); + RTLIL::SigSpec y = cell->getPort(ID::Y); ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep)); return true; } if (cell->type == ID($concat)) { - RTLIL::SigSpec a = cell->getPort(ID(A)); - RTLIL::SigSpec b = cell->getPort(ID(B)); - RTLIL::SigSpec y = cell->getPort(ID(Y)); + RTLIL::SigSpec a = cell->getPort(ID::A); + RTLIL::SigSpec b = cell->getPort(ID::B); + RTLIL::SigSpec y = cell->getPort(ID::Y); RTLIL::SigSpec ab = a; ab.append(b); @@ -1333,16 +1333,16 @@ struct SatGen if (timestep < 2) return true; - std::vector d = importDefSigSpec(cell->getPort(ID(Y)), timestep-1); - std::vector q = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector d = importDefSigSpec(cell->getPort(ID::Y), timestep-1); + std::vector q = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector undef_d = importUndefSigSpec(cell->getPort(ID(Y)), timestep-1); - std::vector undef_q = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_d = importUndefSigSpec(cell->getPort(ID::Y), timestep-1); + std::vector undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -1357,16 +1357,16 @@ struct SatGen if (cell->type.in(ID($_BUF_), ID($equiv))) { - std::vector a = importDefSigSpec(cell->getPort(ID(A)), timestep); - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidthUnary(a, y, cell); std::vector yy = model_undef ? ez->vec_var(y.size()) : y; ez->assume(ez->vec_eq(a, yy)); if (model_undef) { - std::vector undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep); - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidthUnary(undef_a, undef_y, cell, false); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); @@ -1380,12 +1380,12 @@ struct SatGen if (initstates.count(key) == 0) initstates[key] = false; - std::vector y = importDefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); log_assert(GetSize(y) == 1); ez->SET(y[0], initstates[key] ? ez->CONST_TRUE : ez->CONST_FALSE); if (model_undef) { - std::vector undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep); + std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); log_assert(GetSize(undef_y) == 1); ez->SET(undef_y[0], ez->CONST_FALSE); } @@ -1396,7 +1396,7 @@ struct SatGen if (cell->type == ID($assert)) { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - asserts_a[pf].append((*sigmap)(cell->getPort(ID(A)))); + asserts_a[pf].append((*sigmap)(cell->getPort(ID::A))); asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); return true; } @@ -1404,7 +1404,7 @@ struct SatGen if (cell->type == ID($assume)) { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); - assumes_a[pf].append((*sigmap)(cell->getPort(ID(A)))); + assumes_a[pf].append((*sigmap)(cell->getPort(ID::A))); assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); return true; } diff --git a/kernel/yosys.h b/kernel/yosys.h index 49716ed52..52e7b3383 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -210,6 +210,7 @@ namespace RTLIL { struct Module; struct Design; struct Monitor; + namespace ID {} } namespace AST { @@ -224,6 +225,7 @@ using RTLIL::Wire; using RTLIL::Cell; using RTLIL::Module; using RTLIL::Design; +namespace ID = RTLIL::ID; namespace hashlib { template<> struct hash_ops : hash_obj_ops {}; -- cgit v1.2.3 From 453a9429b67551f94f8c714c24f12929e472052c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 15 Aug 2019 14:54:41 -0700 Subject: Fix spacing --- kernel/yosys.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index 52e7b3383..0cf230722 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -210,7 +210,7 @@ namespace RTLIL { struct Module; struct Design; struct Monitor; - namespace ID {} + namespace ID {} } namespace AST { -- cgit v1.2.3 From 0b9ee4fbbf3a5fc818e5ae39a013cdd9e17f641f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 15 Aug 2019 16:20:54 -0700 Subject: Try this for gcc-4.8? --- kernel/yosys.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index 0cf230722..895286a53 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -225,7 +225,7 @@ using RTLIL::Wire; using RTLIL::Cell; using RTLIL::Module; using RTLIL::Design; -namespace ID = RTLIL::ID; +namespace ID = ::YOSYS_NAMESPACE::RTLIL::ID; namespace hashlib { template<> struct hash_ops : hash_obj_ops {}; -- cgit v1.2.3 From 3b19c3657cda6d972bd3b1c3eeacdfca5fb35de8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 16 Aug 2019 19:37:11 +0000 Subject: Move namespace alias --- kernel/yosys.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.h b/kernel/yosys.h index 895286a53..a80cb00b4 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -210,7 +210,6 @@ namespace RTLIL { struct Module; struct Design; struct Monitor; - namespace ID {} } namespace AST { @@ -225,7 +224,6 @@ using RTLIL::Wire; using RTLIL::Cell; using RTLIL::Module; using RTLIL::Design; -namespace ID = ::YOSYS_NAMESPACE::RTLIL::ID; namespace hashlib { template<> struct hash_ops : hash_obj_ops {}; @@ -317,6 +315,7 @@ RTLIL::IdString new_id(std::string file, int line, std::string func); // #define ID(_id) ([]() { const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \ static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })() +namespace ID = RTLIL::ID; RTLIL::Design *yosys_get_design(); std::string proc_self_dirname(); -- cgit v1.2.3 From e9f3eb97607bc49b6bb77229f1fad9796aea1483 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 22 Aug 2019 18:43:16 +0200 Subject: Bump year in copyright notice Signed-off-by: Clifford Wolf --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 747f2d739..5018a4888 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -129,7 +129,7 @@ void yosys_banner() log(" | |\n"); log(" | yosys -- Yosys Open SYnthesis Suite |\n"); log(" | |\n"); - log(" | Copyright (C) 2012 - 2018 Clifford Wolf |\n"); + log(" | Copyright (C) 2012 - 2019 Clifford Wolf |\n"); log(" | |\n"); log(" | Permission to use, copy, modify, and/or distribute this software for any |\n"); log(" | purpose with or without fee is hereby granted, provided that the above |\n"); -- cgit v1.2.3 From 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 11:45:02 -0700 Subject: SigSet to use stable compare class --- kernel/consteval.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index 7a83d28e7..c1c0c45cc 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -33,7 +33,7 @@ struct ConstEval SigMap assign_map; SigMap values_map; SigPool stop_signals; - SigSet sig2driver; + SigSet> sig2driver; std::set busy; std::vector stack; RTLIL::State defaultval; -- cgit v1.2.3 From c05a403dd10cdc847c81baff962068d9b401053a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 11:45:17 -0700 Subject: static_assert to enforce this going forward --- kernel/sigtools.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel') diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 4e97bb775..094d73941 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -138,6 +138,8 @@ struct SigPool template > struct SigSet { + static_assert(!std::is_pointer::value || !std::is_same>::value, "Explicit `Compare' class require for SigSet with pointer-type values!"); + struct bitDef_t : public std::pair { bitDef_t() : std::pair(NULL, 0) { } bitDef_t(const RTLIL::SigBit &bit) : std::pair(bit.wire, bit.offset) { } -- cgit v1.2.3 From c487a8ff25a89506423e868ff3b4345bc36a8e00 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 12:00:34 -0700 Subject: Grammar --- kernel/sigtools.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 094d73941..2f2d3f5c6 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -138,7 +138,7 @@ struct SigPool template > struct SigSet { - static_assert(!std::is_pointer::value || !std::is_same>::value, "Explicit `Compare' class require for SigSet with pointer-type values!"); + static_assert(!std::is_pointer::value || !std::is_same>::value, "Explicit `Compare' class required for SigSet with pointer-type values!"); struct bitDef_t : public std::pair { bitDef_t() : std::pair(NULL, 0) { } -- cgit v1.2.3 From 95e80809a5801743fabb2836fa25f3c3732a9a24 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 09:49:15 -0700 Subject: Revert "SigSet to use stable compare class" This reverts commit 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11. --- kernel/consteval.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/consteval.h b/kernel/consteval.h index c1c0c45cc..7a83d28e7 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -33,7 +33,7 @@ struct ConstEval SigMap assign_map; SigMap values_map; SigPool stop_signals; - SigSet> sig2driver; + SigSet sig2driver; std::set busy; std::vector stack; RTLIL::State defaultval; -- cgit v1.2.3 From 5473e597bf5aa7a5dc7c831be332baeeddae086f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 11:13:57 -0700 Subject: Use template specialisation --- kernel/sigtools.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 2f2d3f5c6..8c0434ceb 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -135,10 +135,10 @@ struct SigPool } }; -template > +template struct SigSet { - static_assert(!std::is_pointer::value || !std::is_same>::value, "Explicit `Compare' class required for SigSet with pointer-type values!"); + static_assert(!std::is_same::value, "Default value for `Compare' class not found for SigSet. Please specify."); struct bitDef_t : public std::pair { bitDef_t() : std::pair(NULL, 0) { } @@ -222,6 +222,13 @@ struct SigSet } }; +template +class SigSet::value>::type> : public SigSet> {}; +template +using sort_by_name_id_guard = typename std::enable_if::value>::type; +template +class SigSet> : public SigSet::type>> {}; + struct SigMap { mfp database; -- cgit v1.2.3 From 9a84e4711cfa7a6ee82b8d67a48be96064659651 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 16:30:44 -0700 Subject: Spacing --- kernel/sigtools.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/sigtools.h b/kernel/sigtools.h index 8c0434ceb..2517d6de3 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -135,7 +135,7 @@ struct SigPool } }; -template +template struct SigSet { static_assert(!std::is_same::value, "Default value for `Compare' class not found for SigSet. Please specify."); -- cgit v1.2.3 From 435300f9304a230680bdc054d0f0b3a3205b05f7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 26 Sep 2019 19:35:12 +0200 Subject: Make read/write gzip files on macos works, fixes #1357 --- kernel/register.cc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/register.cc b/kernel/register.cc index 1fd1bad1d..8131fa279 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -48,7 +48,7 @@ using zlib to write gzip-compressed data every time the stream is flushed. */ class gzip_ostream : public std::ostream { public: - gzip_ostream() + gzip_ostream() : std::ostream(nullptr) { rdbuf(&outbuf); } @@ -71,7 +71,7 @@ private: str(""); return 0; } - ~gzip_streambuf() + virtual ~gzip_streambuf() { sync(); gzclose(gzf); @@ -498,7 +498,15 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector(magic), 3); + int n = 0; + while (n < 3) + { + int c = ff->get(); + if (c != EOF) { + magic[n] = (unsigned char) c; + } + n++; + } if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { #ifdef YOSYS_ENABLE_ZLIB log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); -- cgit v1.2.3