From c50afc4246d552db079aec303b0d79ae92107a67 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 13 Oct 2018 20:34:44 +0200
Subject: Documentation improvements etc.

- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
---
 kernel/rtlil.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 07dd4bfa0..14259f8ed 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -639,11 +639,9 @@ RTLIL::Module::~Module()
 		delete it->second;
 }
 
-void RTLIL::Module::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces)
+void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
 {
 	log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
-	(void)local_interfaces; // To remove build warning
-	(void)design;           // To remove build warning
 }
 
 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
-- 
cgit v1.2.3