From 178ff3e7f6f9766f0b1a3e8dcc96e030aea59b15 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 18 Jun 2016 10:24:21 +0200
Subject: Added support for SystemVerilog packages with localparam definitions

---
 kernel/rtlil.cc | 2 ++
 kernel/rtlil.h  | 2 ++
 2 files changed, 4 insertions(+)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index bcd87d3ff..9e09d9f04 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -304,6 +304,8 @@ RTLIL::Design::~Design()
 {
 	for (auto it = modules_.begin(); it != modules_.end(); ++it)
 		delete it->second;
+	for (auto n : packages)
+		delete n;
 }
 
 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 940e36ab3..275ba6820 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -18,6 +18,7 @@
  */
 
 #include "kernel/yosys.h"
+#include "frontends/ast/ast.h"
 
 #ifndef RTLIL_H
 #define RTLIL_H
@@ -792,6 +793,7 @@ struct RTLIL::Design
 
 	int refcount_modules_;
 	dict<RTLIL::IdString, RTLIL::Module*> modules_;
+	std::vector<AST::AstNode*> packages;
 
 	std::vector<RTLIL::Selection> selection_stack;
 	dict<RTLIL::IdString, RTLIL::Selection> selection_vars;
-- 
cgit v1.2.3


From a8200a773fb8cf2ce2d8793716b62e01c97dd731 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 18 Jun 2016 14:13:36 +0200
Subject: A few modifications after pull request comments

- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
---
 kernel/rtlil.cc | 2 +-
 kernel/rtlil.h  | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

(limited to 'kernel')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9e09d9f04..9da6d2816 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -304,7 +304,7 @@ RTLIL::Design::~Design()
 {
 	for (auto it = modules_.begin(); it != modules_.end(); ++it)
 		delete it->second;
-	for (auto n : packages)
+	for (auto n : verilog_packages)
 		delete n;
 }
 
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 275ba6820..274f97023 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -18,7 +18,6 @@
  */
 
 #include "kernel/yosys.h"
-#include "frontends/ast/ast.h"
 
 #ifndef RTLIL_H
 #define RTLIL_H
@@ -793,7 +792,7 @@ struct RTLIL::Design
 
 	int refcount_modules_;
 	dict<RTLIL::IdString, RTLIL::Module*> modules_;
-	std::vector<AST::AstNode*> packages;
+	std::vector<AST::AstNode*> verilog_packages;
 
 	std::vector<RTLIL::Selection> selection_stack;
 	dict<RTLIL::IdString, RTLIL::Selection> selection_vars;
-- 
cgit v1.2.3