From 95757efb25dc51a73b384b475b0fc87d0e11d10e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 17 Jun 2016 16:31:16 +0200 Subject: Improved support for $sop cells --- kernel/celltypes.h | 18 +++++++++++++++--- kernel/rtlil.cc | 2 +- 2 files changed, 16 insertions(+), 4 deletions(-) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 41dd51ed8..cf7bc2dcf 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -366,21 +366,33 @@ struct CellTypes while (GetSize(t) < width*depth*2) t.push_back(RTLIL::S0); + RTLIL::State default_ret = State::S0; + for (int i = 0; i < depth; i++) { bool match = true; + bool match_x = true; for (int j = 0; j < width; j++) { RTLIL::State a = arg1.bits.at(j); - if (t.at(2*width*i + 2*j + 0) == State::S1 && a == State::S1) match = false; - if (t.at(2*width*i + 2*j + 1) == State::S1 && a == State::S0) match = false; + if (t.at(2*width*i + 2*j + 0) == State::S1) { + if (a == State::S1) match_x = false; + if (a != State::S0) match = false; + } + if (t.at(2*width*i + 2*j + 1) == State::S1) { + if (a == State::S0) match_x = false; + if (a != State::S1) match = false; + } } if (match) return State::S1; + + if (match_x) + default_ret = State::Sx; } - return State::S0; + return default_ret; } bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3b1df4406..bcd87d3ff 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2142,7 +2142,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } - if (type == "$lut") { + if (type == "$lut" || type == "$sop") { parameters["\\WIDTH"] = GetSize(connections_["\\A"]); return; } -- cgit v1.2.3