From d20e971725a780458ccd18d08be7ecfb67884eaf Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 1 Dec 2019 01:51:16 +0000 Subject: write_cxxrtl: new backend. This commit adds a basic implementation that isn't very performant but implements most of the planned features. --- kernel/yosys.cc | 2 ++ kernel/yosys.h | 3 +++ 2 files changed, 5 insertions(+) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 380f7030b..cbf041f79 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1034,6 +1034,8 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig command = "verilog"; else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0) command = "ilang"; + else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".cc") == 0) + command = "cxxrtl"; else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0) command = "aiger"; else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".blif") == 0) diff --git a/kernel/yosys.h b/kernel/yosys.h index 16e0aaf1c..6aed7c96a 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -207,6 +207,7 @@ namespace RTLIL { struct SigSpec; struct Wire; struct Cell; + struct Memory; struct Module; struct Design; struct Monitor; @@ -229,6 +230,7 @@ using RTLIL::Design; namespace hashlib { template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; + template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; @@ -236,6 +238,7 @@ namespace hashlib { template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; + template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; -- cgit v1.2.3