From d39a5a77a9ec58ea97af91c961b02b5a55deaaa7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Jun 2019 13:13:48 -0700
Subject: Add ConstEvalAig specialised for AIGs

---
 kernel/consteval.h | 157 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 157 insertions(+)

(limited to 'kernel')

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 154373a8d..59e3ef20f 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -390,6 +390,163 @@ struct ConstEval
 	}
 };
 
+struct ConstEvalAig
+{
+	RTLIL::Module *module;
+	//SigMap assign_map;
+	SigMap values_map;
+	//SigPool stop_signals;
+	SigSet<RTLIL::Cell*> sig2driver;
+	std::set<RTLIL::Cell*> busy;
+	std::vector<SigMap> stack;
+	//RTLIL::State defaultval;
+
+	ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/
+	{
+		CellTypes ct;
+		ct.setup_internals();
+		ct.setup_stdcells();
+
+		for (auto &it : module->cells_) {
+			if (!ct.cell_known(it.second->type))
+				continue;
+			for (auto &it2 : it.second->connections())
+				if (ct.cell_output(it.second->type, it2.first))
+					sig2driver.insert(/*assign_map*/(it2.second), it.second);
+		}
+	}
+
+	void clear()
+	{
+		values_map.clear();
+		//stop_signals.clear();
+	}
+
+	void push()
+	{
+		stack.push_back(values_map);
+	}
+
+	void pop()
+	{
+		values_map.swap(stack.back());
+		stack.pop_back();
+	}
+
+	void set(RTLIL::SigSpec sig, RTLIL::Const value)
+	{
+		//assign_map.apply(sig);
+#ifndef NDEBUG
+		RTLIL::SigSpec current_val = values_map(sig);
+		for (int i = 0; i < GetSize(current_val); i++)
+			log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
+#endif
+		values_map.add(sig, RTLIL::SigSpec(value));
+	}
+
+	//void stop(RTLIL::SigSpec sig)
+	//{
+	//	assign_map.apply(sig);
+	//	stop_signals.add(sig);
+	//}
+
+	bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)
+	{
+		RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y")));
+		if (sig_y.is_fully_const())
+			return true;
+
+		RTLIL::SigSpec sig_a = cell->getPort("\\A");
+		if (sig_a.size() > 0 && !eval(sig_a, undef, cell))
+			return false;
+
+		RTLIL::Const eval_ret;
+		if (cell->type == "$_NOT_") {
+			if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
+			else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
+		}
+		else if (cell->type == "$_AND_") {
+			if (sig_a == RTLIL::S0) {
+				eval_ret = RTLIL::S0;
+				goto eval_end;
+			}
+
+			{
+				RTLIL::SigSpec sig_b = cell->getPort("\\B");
+				if (sig_b.size() > 0 && !eval(sig_b, undef, cell))
+					return false;
+				if (sig_b == RTLIL::S0) {
+					eval_ret = RTLIL::S0;
+					goto eval_end;
+				}
+
+				if (sig_a != RTLIL::State::S1 || sig_b != RTLIL::State::S1) {
+					eval_ret = RTLIL::State::Sx;
+					goto eval_end;
+				}
+
+				eval_ret = RTLIL::State::S1;
+			}
+		}
+		else log_abort();
+
+
+eval_end:
+		set(sig_y, eval_ret);
+		return true;
+	}
+
+	bool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)
+	{
+		//assign_map.apply(sig);
+		values_map.apply(sig);
+
+		if (sig.is_fully_const())
+			return true;
+
+		//if (stop_signals.check_any(sig)) {
+		//	undef = stop_signals.extract(sig);
+		//	return false;
+		//}
+
+		if (busy_cell) {
+			if (busy.count(busy_cell) > 0) {
+				undef = sig;
+				return false;
+			}
+			busy.insert(busy_cell);
+		}
+
+		std::set<RTLIL::Cell*> driver_cells;
+		sig2driver.find(sig, driver_cells);
+		for (auto cell : driver_cells) {
+			if (!eval(cell, undef)) {
+				if (busy_cell)
+					busy.erase(busy_cell);
+				return false;
+			}
+		}
+
+		if (busy_cell)
+			busy.erase(busy_cell);
+
+		values_map.apply(sig);
+		if (sig.is_fully_const())
+			return true;
+
+		for (auto &c : sig.chunks())
+			if (c.wire != NULL)
+				undef.append(c);
+		return false;
+	}
+
+	bool eval(RTLIL::SigSpec &sig)
+	{
+		RTLIL::SigSpec undef;
+		return eval(sig, undef);
+	}
+};
+
 YOSYS_NAMESPACE_END
 
 #endif
-- 
cgit v1.2.3


From 63e2f83632a760d64e64f8e03529de941301125e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Jun 2019 13:29:03 -0700
Subject: More slimming

---
 kernel/consteval.h | 70 +++++++++++++++++++++++++++---------------------------
 1 file changed, 35 insertions(+), 35 deletions(-)

(limited to 'kernel')

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 59e3ef20f..e0131b233 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -397,8 +397,8 @@ struct ConstEvalAig
 	SigMap values_map;
 	//SigPool stop_signals;
 	SigSet<RTLIL::Cell*> sig2driver;
-	std::set<RTLIL::Cell*> busy;
-	std::vector<SigMap> stack;
+	//std::set<RTLIL::Cell*> busy;
+	//std::vector<SigMap> stack;
 	//RTLIL::State defaultval;
 
 	ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/
@@ -422,16 +422,16 @@ struct ConstEvalAig
 		//stop_signals.clear();
 	}
 
-	void push()
-	{
-		stack.push_back(values_map);
-	}
+	//void push()
+	//{
+	//	stack.push_back(values_map);
+	//}
 
-	void pop()
-	{
-		values_map.swap(stack.back());
-		stack.pop_back();
-	}
+	//void pop()
+	//{
+	//	values_map.swap(stack.back());
+	//	stack.pop_back();
+	//}
 
 	void set(RTLIL::SigSpec sig, RTLIL::Const value)
 	{
@@ -450,14 +450,14 @@ struct ConstEvalAig
 	//	stop_signals.add(sig);
 	//}
 
-	bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)
+	bool eval(RTLIL::Cell *cell /*, RTLIL::SigSpec &undef*/)
 	{
 		RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y")));
 		if (sig_y.is_fully_const())
 			return true;
 
 		RTLIL::SigSpec sig_a = cell->getPort("\\A");
-		if (sig_a.size() > 0 && !eval(sig_a, undef, cell))
+		if (sig_a.size() > 0 && !eval(sig_a /*, undef, cell*/))
 			return false;
 
 		RTLIL::Const eval_ret;
@@ -473,7 +473,7 @@ struct ConstEvalAig
 
 			{
 				RTLIL::SigSpec sig_b = cell->getPort("\\B");
-				if (sig_b.size() > 0 && !eval(sig_b, undef, cell))
+				if (sig_b.size() > 0 && !eval(sig_b /*, undef, cell*/))
 					return false;
 				if (sig_b == RTLIL::S0) {
 					eval_ret = RTLIL::S0;
@@ -496,7 +496,7 @@ eval_end:
 		return true;
 	}
 
-	bool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)
+	bool eval(RTLIL::SigSpec &sig /*, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL*/)
 	{
 		//assign_map.apply(sig);
 		values_map.apply(sig);
@@ -509,42 +509,42 @@ eval_end:
 		//	return false;
 		//}
 
-		if (busy_cell) {
-			if (busy.count(busy_cell) > 0) {
-				undef = sig;
-				return false;
-			}
-			busy.insert(busy_cell);
-		}
+		//if (busy_cell) {
+		//	if (busy.count(busy_cell) > 0) {
+		//		undef = sig;
+		//		return false;
+		//	}
+		//	busy.insert(busy_cell);
+		//}
 
 		std::set<RTLIL::Cell*> driver_cells;
 		sig2driver.find(sig, driver_cells);
 		for (auto cell : driver_cells) {
-			if (!eval(cell, undef)) {
-				if (busy_cell)
-					busy.erase(busy_cell);
+			if (!eval(cell /*, undef*/)) {
+				//if (busy_cell)
+				//	busy.erase(busy_cell);
 				return false;
 			}
 		}
 
-		if (busy_cell)
-			busy.erase(busy_cell);
+		//if (busy_cell)
+		//	busy.erase(busy_cell);
 
 		values_map.apply(sig);
 		if (sig.is_fully_const())
 			return true;
 
-		for (auto &c : sig.chunks())
-			if (c.wire != NULL)
-				undef.append(c);
+		//for (auto &c : sig.chunks())
+		//	if (c.wire != NULL)
+		//		undef.append(c);
 		return false;
 	}
 
-	bool eval(RTLIL::SigSpec &sig)
-	{
-		RTLIL::SigSpec undef;
-		return eval(sig, undef);
-	}
+	//bool eval(RTLIL::SigSpec &sig)
+	//{
+	//	RTLIL::SigSpec undef;
+	//	return eval(sig, undef);
+	//}
 };
 
 YOSYS_NAMESPACE_END
-- 
cgit v1.2.3


From d09d4e0706e806d53b3b83986f49c1d59435d2ed Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Jun 2019 16:28:11 -0700
Subject: Move ConstEvalAig to aigerparse.cc

---
 kernel/consteval.h | 157 -----------------------------------------------------
 1 file changed, 157 deletions(-)

(limited to 'kernel')

diff --git a/kernel/consteval.h b/kernel/consteval.h
index e0131b233..154373a8d 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -390,163 +390,6 @@ struct ConstEval
 	}
 };
 
-struct ConstEvalAig
-{
-	RTLIL::Module *module;
-	//SigMap assign_map;
-	SigMap values_map;
-	//SigPool stop_signals;
-	SigSet<RTLIL::Cell*> sig2driver;
-	//std::set<RTLIL::Cell*> busy;
-	//std::vector<SigMap> stack;
-	//RTLIL::State defaultval;
-
-	ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/
-	{
-		CellTypes ct;
-		ct.setup_internals();
-		ct.setup_stdcells();
-
-		for (auto &it : module->cells_) {
-			if (!ct.cell_known(it.second->type))
-				continue;
-			for (auto &it2 : it.second->connections())
-				if (ct.cell_output(it.second->type, it2.first))
-					sig2driver.insert(/*assign_map*/(it2.second), it.second);
-		}
-	}
-
-	void clear()
-	{
-		values_map.clear();
-		//stop_signals.clear();
-	}
-
-	//void push()
-	//{
-	//	stack.push_back(values_map);
-	//}
-
-	//void pop()
-	//{
-	//	values_map.swap(stack.back());
-	//	stack.pop_back();
-	//}
-
-	void set(RTLIL::SigSpec sig, RTLIL::Const value)
-	{
-		//assign_map.apply(sig);
-#ifndef NDEBUG
-		RTLIL::SigSpec current_val = values_map(sig);
-		for (int i = 0; i < GetSize(current_val); i++)
-			log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
-#endif
-		values_map.add(sig, RTLIL::SigSpec(value));
-	}
-
-	//void stop(RTLIL::SigSpec sig)
-	//{
-	//	assign_map.apply(sig);
-	//	stop_signals.add(sig);
-	//}
-
-	bool eval(RTLIL::Cell *cell /*, RTLIL::SigSpec &undef*/)
-	{
-		RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y")));
-		if (sig_y.is_fully_const())
-			return true;
-
-		RTLIL::SigSpec sig_a = cell->getPort("\\A");
-		if (sig_a.size() > 0 && !eval(sig_a /*, undef, cell*/))
-			return false;
-
-		RTLIL::Const eval_ret;
-		if (cell->type == "$_NOT_") {
-			if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
-			else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
-		}
-		else if (cell->type == "$_AND_") {
-			if (sig_a == RTLIL::S0) {
-				eval_ret = RTLIL::S0;
-				goto eval_end;
-			}
-
-			{
-				RTLIL::SigSpec sig_b = cell->getPort("\\B");
-				if (sig_b.size() > 0 && !eval(sig_b /*, undef, cell*/))
-					return false;
-				if (sig_b == RTLIL::S0) {
-					eval_ret = RTLIL::S0;
-					goto eval_end;
-				}
-
-				if (sig_a != RTLIL::State::S1 || sig_b != RTLIL::State::S1) {
-					eval_ret = RTLIL::State::Sx;
-					goto eval_end;
-				}
-
-				eval_ret = RTLIL::State::S1;
-			}
-		}
-		else log_abort();
-
-
-eval_end:
-		set(sig_y, eval_ret);
-		return true;
-	}
-
-	bool eval(RTLIL::SigSpec &sig /*, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL*/)
-	{
-		//assign_map.apply(sig);
-		values_map.apply(sig);
-
-		if (sig.is_fully_const())
-			return true;
-
-		//if (stop_signals.check_any(sig)) {
-		//	undef = stop_signals.extract(sig);
-		//	return false;
-		//}
-
-		//if (busy_cell) {
-		//	if (busy.count(busy_cell) > 0) {
-		//		undef = sig;
-		//		return false;
-		//	}
-		//	busy.insert(busy_cell);
-		//}
-
-		std::set<RTLIL::Cell*> driver_cells;
-		sig2driver.find(sig, driver_cells);
-		for (auto cell : driver_cells) {
-			if (!eval(cell /*, undef*/)) {
-				//if (busy_cell)
-				//	busy.erase(busy_cell);
-				return false;
-			}
-		}
-
-		//if (busy_cell)
-		//	busy.erase(busy_cell);
-
-		values_map.apply(sig);
-		if (sig.is_fully_const())
-			return true;
-
-		//for (auto &c : sig.chunks())
-		//	if (c.wire != NULL)
-		//		undef.append(c);
-		return false;
-	}
-
-	//bool eval(RTLIL::SigSpec &sig)
-	//{
-	//	RTLIL::SigSpec undef;
-	//	return eval(sig, undef);
-	//}
-};
-
 YOSYS_NAMESPACE_END
 
 #endif
-- 
cgit v1.2.3


From a48b5bfaa5c55bfe4e5ff859b453ee00a1dd68c6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 12:25:06 -0700
Subject: Further cleanup based on @daveshah1

---
 kernel/rtlil.h | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'kernel')

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index d3ad57d72..f4fcf5dcf 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -276,6 +276,12 @@ namespace RTLIL
 				return std::string(c_str() + pos, len);
 		}
 
+		bool begins_with(const char* prefix) const {
+			size_t len = strlen(prefix);
+			if (size() < len) return false;
+			return substr(0, len) == prefix;
+		}
+
 		bool ends_with(const char* suffix) const {
 			size_t len = strlen(suffix);
 			if (size() < len) return false;
-- 
cgit v1.2.3