From 5c166e76e52cdaf6ea97952c17d3d79185a59f96 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Jul 2016 14:23:22 +0200
Subject: Added $initstate cell type and vlog function

---
 kernel/celltypes.h | 1 +
 kernel/rtlil.cc    | 6 ++++++
 kernel/satgen.h    | 6 +++---
 3 files changed, 10 insertions(+), 3 deletions(-)

(limited to 'kernel')

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index c3f05de57..1eea0530c 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -117,6 +117,7 @@ struct CellTypes
 		setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
 		setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
 		setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true);
+		setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
 		setup_type("$equiv", {A, B}, {Y}, true);
 	}
 
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index cf3c80604..2e5157e85 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1024,6 +1024,12 @@ namespace {
 				return;
 			}
 
+			if (cell->type == "$initstate") {
+				port("\\Y", 1);
+				check_expected();
+				return;
+			}
+
 			if (cell->type == "$equiv") {
 				port("\\A", 1);
 				port("\\B", 1);
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 22b11fe26..eb1c6fe36 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -69,7 +69,7 @@ struct SatGen
 	SigPool initial_state;
 	std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;
 	std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;
-	std::map<std::string, RTLIL::SigSpec> expects_a, expects_en;
+	std::map<std::string, RTLIL::SigSpec> predict_a, predict_en;
 	std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;
 	bool ignore_div_by_zero;
 	bool model_undef;
@@ -1350,8 +1350,8 @@ struct SatGen
 		if (cell->type == "$predict")
 		{
 			std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
-			expects_a[pf].append((*sigmap)(cell->getPort("\\A")));
-			expects_en[pf].append((*sigmap)(cell->getPort("\\EN")));
+			predict_a[pf].append((*sigmap)(cell->getPort("\\A")));
+			predict_en[pf].append((*sigmap)(cell->getPort("\\EN")));
 			return true;
 		}
 
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