From 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 20:58:44 +0200
Subject: SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only,
 created interim RTLIL::SigSpec::chunks_rw()

---
 kernel/consteval.h | 2 +-
 kernel/rtlil.cc    | 2 +-
 kernel/rtlil.h     | 2 +-
 kernel/sigtools.h  | 8 ++++----
 4 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'kernel')

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 564098c6a..5836cdd5b 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -73,7 +73,7 @@ struct ConstEval
 		RTLIL::SigSpec current_val = values_map(sig);
 		current_val.expand();
 		for (size_t i = 0; i < current_val.chunks().size(); i++) {
-			RTLIL::SigChunk &chunk = current_val.chunks()[i];
+			const RTLIL::SigChunk &chunk = current_val.chunks()[i];
 			assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]);
 		}
 #endif
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 43511304e..361cd5f04 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 		RTLIL::Module *mod;
 		void operator()(RTLIL::SigSpec &sig)
 		{
-			for (auto &c : sig.chunks())
+			for (auto &c : sig.chunks_rw())
 				if (c.wire != NULL)
 					c.wire = mod->wires.at(c.wire->name);
 		}
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6bbf69602..9d5b3b304 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -501,7 +501,7 @@ private:
 	int width_;
 
 public:
-	std::vector<RTLIL::SigChunk> &chunks() { return chunks_; }
+	std::vector<RTLIL::SigChunk> &chunks_rw() { return chunks_; }
 	const std::vector<RTLIL::SigChunk> &chunks() const { return chunks_; }
 
 	int size() const { return width_; }
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 27abd8670..826f84179 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -423,8 +423,8 @@ struct SigMap
 		assert(from.chunks().size() == to.chunks().size());
 		for (size_t i = 0; i < from.chunks().size(); i++)
 		{
-			RTLIL::SigChunk &cf = from.chunks()[i];
-			RTLIL::SigChunk &ct = to.chunks()[i];
+			const RTLIL::SigChunk &cf = from.chunks()[i];
+			const RTLIL::SigChunk &ct = to.chunks()[i];
 
 			if (cf.wire == NULL)
 				continue;
@@ -444,7 +444,7 @@ struct SigMap
 		sig.expand();
 		for (size_t i = 0; i < sig.chunks().size(); i++)
 		{
-			RTLIL::SigChunk &c = sig.chunks()[i];
+			const RTLIL::SigChunk &c = sig.chunks()[i];
 			if (c.wire != NULL) {
 				register_bit(c);
 				set_bit(c, c);
@@ -462,7 +462,7 @@ struct SigMap
 	void apply(RTLIL::SigSpec &sig) const
 	{
 		sig.expand();
-		for (auto &c : sig.chunks())
+		for (auto &c : sig.chunks_rw())
 			map_bit(c);
 		sig.optimize();
 	}
-- 
cgit v1.2.3