From 1bf7a18fec76cf46a5b8710a75371e23b68d147d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Aug 2014 16:13:42 +0200
Subject: Added module->ports

---
 kernel/celltypes.h |  3 ++-
 kernel/rtlil.cc    | 10 +++++++++-
 kernel/rtlil.h     |  2 ++
 3 files changed, 13 insertions(+), 2 deletions(-)

(limited to 'kernel')

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 6beaa3fed..5486f6acb 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -67,7 +67,8 @@ struct CellTypes
 	void setup_module(RTLIL::Module *module)
 	{
 		std::set<RTLIL::IdString> inputs, outputs;
-		for (auto wire : module->wires()) {
+		for (RTLIL::IdString wire_name : module->ports) {
+			RTLIL::Wire *wire = module->wire(wire_name);
 			if (wire->port_input)
 				inputs.insert(wire->name);
 			if (wire->port_output)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index fdb33ed82..96ae0f97a 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -821,6 +821,8 @@ void RTLIL::Module::check()
 		for (auto &it2 : it.second->attributes)
 			log_assert(!it2.first.empty());
 		if (it.second->port_id) {
+			log_assert(SIZE(ports) >= it.second->port_id);
+			log_assert(ports.at(it.second->port_id-1) == it.first);
 			log_assert(it.second->port_input || it.second->port_output);
 			if (SIZE(ports_declared) < it.second->port_id)
 				ports_declared.resize(it.second->port_id);
@@ -831,6 +833,7 @@ void RTLIL::Module::check()
 	}
 	for (auto port_declared : ports_declared)
 		log_assert(port_declared == true);
+	log_assert(SIZE(ports) == SIZE(ports_declared));
 
 	for (auto &it : memories) {
 		log_assert(it.first == it.second->name);
@@ -915,6 +918,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 	RewriteSigSpecWorker rewriteSigSpecWorker;
 	rewriteSigSpecWorker.mod = new_mod;
 	new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
+	new_mod->fixup_ports();
 }
 
 RTLIL::Module *RTLIL::Module::clone() const
@@ -1154,8 +1158,12 @@ void RTLIL::Module::fixup_ports()
 			w.second->port_id = 0;
 
 	std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
-	for (size_t i = 0; i < all_ports.size(); i++)
+
+	ports.clear();
+	for (size_t i = 0; i < all_ports.size(); i++) {
+		ports.push_back(all_ports[i]->name);
 		all_ports[i]->port_id = i+1;
+	}
 }
 
 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 10da74636..0093b8a1b 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -575,6 +575,8 @@ public:
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
 	void new_connections(const std::vector<RTLIL::SigSig> &new_conn);
 	const std::vector<RTLIL::SigSig> &connections() const;
+
+	std::vector<RTLIL::IdString> ports;
 	void fixup_ports();
 
 	template<typename T> void rewrite_sigspecs(T functor);
-- 
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