From 8ebaeecd83b22db5c196356844f01ce69d0b4bea Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 9 Jul 2018 15:48:06 +0200 Subject: multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues --- kernel/rtlil.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'kernel/rtlil.h') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 54d0b8c22..232a8c13a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -874,6 +874,10 @@ struct RTLIL::Design } } +#ifdef WITH_PYTHON + static std::map *get_all_designs(void); +#endif + std::vector selected_modules() const; std::vector selected_whole_modules() const; std::vector selected_whole_modules_warn() const; @@ -1130,6 +1134,10 @@ public: RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = ""); + +#ifdef WITH_PYTHON + static std::map *get_all_modules(void); +#endif }; struct RTLIL::Wire : public RTLIL::AttrObject @@ -1152,6 +1160,10 @@ public: RTLIL::IdString name; int width, start_offset, port_id; bool port_input, port_output, upto; + +#ifdef WITH_PYTHON + static std::map *get_all_wires(void); +#endif }; struct RTLIL::Memory : public RTLIL::AttrObject @@ -1214,6 +1226,10 @@ public: } template void rewrite_sigspecs(T &functor); + +#ifdef WITH_PYTHON + static std::map *get_all_cells(void); +#endif }; struct RTLIL::CaseRule -- cgit v1.2.3 From e7d3f3cd464fe323872285bed40e6f347683147b Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 10 Jul 2018 08:52:36 +0200 Subject: added destructors for wires and cells --- kernel/rtlil.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel/rtlil.h') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 232a8c13a..e71a5fceb 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1149,7 +1149,7 @@ protected: // use module->addWire() and module->remove() to create or destroy wires friend struct RTLIL::Module; Wire(); - ~Wire() { }; + ~Wire(); public: // do not simply copy wires @@ -1186,6 +1186,7 @@ protected: // use module->addCell() and module->remove() to create or destroy cells friend struct RTLIL::Module; Cell(); + ~Cell(); public: // do not simply copy cells -- cgit v1.2.3 From bf7b73acfc2b5e46206e5688b8a6e8d9b0d60d8f Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 13 Aug 2018 15:18:46 +0200 Subject: Added Wrappers for: -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h --- kernel/rtlil.h | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'kernel/rtlil.h') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e71a5fceb..89413a166 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -463,6 +463,7 @@ struct RTLIL::Const Const(RTLIL::State bit, int width = 1); Const(const std::vector &bits) : bits(bits) { flags = CONST_FLAG_NONE; } Const(const std::vector &bits); + Const(const RTLIL::Const &c); bool operator <(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const; @@ -529,6 +530,7 @@ struct RTLIL::SigChunk SigChunk(int val, int width = 32); SigChunk(RTLIL::State bit, int width = 1); SigChunk(RTLIL::SigBit bit); + SigChunk(const RTLIL::SigChunk &sigchunk); RTLIL::SigChunk extract(int offset, int length) const; @@ -553,6 +555,7 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigChunk &chunk); SigBit(const RTLIL::SigChunk &chunk, int index); SigBit(const RTLIL::SigSpec &sig); + SigBit(const RTLIL::SigBit &sigbit); bool operator <(const RTLIL::SigBit &other) const; bool operator ==(const RTLIL::SigBit &other) const; @@ -874,13 +877,13 @@ struct RTLIL::Design } } -#ifdef WITH_PYTHON - static std::map *get_all_designs(void); -#endif std::vector selected_modules() const; std::vector selected_whole_modules() const; std::vector selected_whole_modules_warn() const; +#ifdef WITH_PYTHON + static std::map *get_all_designs(void); +#endif }; struct RTLIL::Module : public RTLIL::AttrObject @@ -1175,6 +1178,10 @@ struct RTLIL::Memory : public RTLIL::AttrObject RTLIL::IdString name; int width, start_offset, size; +#ifdef WITH_PYTHON + ~Memory(); + static std::map *get_all_memorys(void); +#endif }; struct RTLIL::Cell : public RTLIL::AttrObject @@ -1287,6 +1294,7 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; } +inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){if(wire) offset = sigbit.offset;} inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const { if (wire == other.wire) -- cgit v1.2.3 From 95d65971f3f114adb8b62a9d29bc0829467e3d81 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Mon, 20 Aug 2018 16:04:43 +0200 Subject: added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile --- kernel/rtlil.h | 1 + 1 file changed, 1 insertion(+) (limited to 'kernel/rtlil.h') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 89413a166..0e5159be2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1175,6 +1175,7 @@ struct RTLIL::Memory : public RTLIL::AttrObject unsigned int hash() const { return hashidx_; } Memory(); + ~Memory(); RTLIL::IdString name; int width, start_offset, size; -- cgit v1.2.3 From 29efc9d0b1b003113e1faf1e76ce32cffb0ff95a Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Tue, 21 Aug 2018 11:07:59 +0200 Subject: Deleted duplicate Destructor --- kernel/rtlil.h | 1 - 1 file changed, 1 deletion(-) (limited to 'kernel/rtlil.h') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0e5159be2..89413a166 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1175,7 +1175,6 @@ struct RTLIL::Memory : public RTLIL::AttrObject unsigned int hash() const { return hashidx_; } Memory(); - ~Memory(); RTLIL::IdString name; int width, start_offset, size; -- cgit v1.2.3