From 2ef2aa997cbe75732535946b25c35dcb3fe5eec4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 09:07:53 -0700 Subject: read_aiger to not require clk_name for latches, plus debug --- frontends/aiger/aigerparse.cc | 58 +++++++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 21 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d378a07b7..281e1cc9d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -495,8 +495,7 @@ void AigerReader::parse_aiger_ascii() // Parse latches RTLIL::Wire *clk_wire = nullptr; - if (L > 0) { - log_assert(clk_name != ""); + if (L > 0 && !clk_name.empty()) { clk_wire = module->wire(clk_name); log_assert(!clk_wire); log_debug("Creating %s\n", clk_name.c_str()); @@ -512,7 +511,10 @@ void AigerReader::parse_aiger_ascii() RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); - module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); + if (clk_wire) + module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); + else + module->addFfGate(NEW_ID, d_wire, q_wire); // Reset logic is optional in AIGER 1.9 if (f.peek() == ' ') { @@ -620,8 +622,7 @@ void AigerReader::parse_aiger_binary() // Parse latches RTLIL::Wire *clk_wire = nullptr; - if (L > 0) { - log_assert(clk_name != ""); + if (L > 0 && !clk_name.empty()) { clk_wire = module->wire(clk_name); log_assert(!clk_wire); log_debug("Creating %s\n", clk_name.c_str()); @@ -637,7 +638,10 @@ void AigerReader::parse_aiger_binary() RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); - module->addDff(NEW_ID, clk_wire, d_wire, q_wire); + if (clk_wire) + module->addDff(NEW_ID, clk_wire, d_wire, q_wire); + else + module->addFf(NEW_ID, d_wire, q_wire); // Reset logic is optional in AIGER 1.9 if (f.peek() == ' ') { @@ -731,7 +735,14 @@ void AigerReader::post_process() RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); - if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { + RTLIL::Module* flop_module = nullptr; + if (box_module->attributes.count("\\abc_flop")) { + log_assert(flop_count < flopNum); + log_assert(box_module->name.begins_with("$__ABC_")); + flop_module = design->module("\\" + box_module->name.substr(7)); + log_assert(flop_module); + } + else if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; RTLIL::Wire* last_in = nullptr, *last_out = nullptr; for (const auto &port_name : box_module->ports) { @@ -766,39 +777,36 @@ void AigerReader::post_process() } } - bool flop = box_module->attributes.count("\\abc_flop"); - log_assert(!flop || flop_count < flopNum); - // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) for (auto port_name : box_module->ports) { - RTLIL::Wire* w = box_module->wire(port_name); - log_assert(w); + RTLIL::Wire* port = box_module->wire(port_name); + log_assert(port); RTLIL::SigSpec rhs; RTLIL::Wire* wire = nullptr; - for (int i = 0; i < GetSize(w); i++) { - if (w->port_input) { + for (int i = 0; i < GetSize(port); i++) { + if (port->port_input) { log_assert(co_count < outputs.size()); wire = outputs[co_count++]; log_assert(wire); log_assert(wire->port_output); wire->port_output = false; - if (flop && w->attributes.count("\\abc_flop_d")) { + if (flop_module && port->attributes.count("\\abc_flop_d")) { RTLIL::Wire* d = outputs[outputs.size() - flopNum + flop_count]; log_assert(d); log_assert(d->port_output); d->port_output = false; } } - if (w->port_output) { + if (port->port_output) { log_assert((piNum + ci_count) < inputs.size()); wire = inputs[piNum + ci_count++]; log_assert(wire); log_assert(wire->port_input); wire->port_input = false; - if (flop && w->attributes.count("\\abc_flop_q")) { + if (flop_module && port->attributes.count("\\abc_flop_q")) { wire = inputs[piNum - flopNum + flop_count]; log_assert(wire); log_assert(wire->port_input); @@ -807,10 +815,14 @@ void AigerReader::post_process() } rhs.append(wire); } - cell->setPort(port_name, rhs); + if (!flop_module || !port->attributes.count("\\abc_discard")) + cell->setPort(port_name, rhs); } - if (flop) flop_count++; + if (flop_module) { + flop_count++; + cell->type = flop_module->name; + } } dict wideports_cache; @@ -826,6 +838,7 @@ void AigerReader::post_process() RTLIL::Wire* wire = inputs[variable]; log_assert(wire); log_assert(wire->port_input); + log_debug("Renaming input %s", log_id(wire)); if (index == 0) { // Cope with the fact that a CI might be identical @@ -852,12 +865,14 @@ void AigerReader::post_process() wire->port_input = false; } } + log_debug(" -> %s\n", log_id(wire)); } else if (type == "output") { log_assert(static_cast(variable + co_count) < outputs.size()); RTLIL::Wire* wire = outputs[variable + co_count]; log_assert(wire); log_assert(wire->port_output); + log_debug("Renaming output %s", log_id(wire)); if (index == 0) { // Cope with the fact that a CO might be identical @@ -904,6 +919,7 @@ void AigerReader::post_process() wire->port_output = false; } } + log_debug(" -> %s\n", log_id(wire)); } else if (type == "box") { RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); @@ -1009,8 +1025,8 @@ struct AigerFrontend : public Frontend { log(" Name of module to be created (default: )\n"); log("\n"); log(" -clk_name \n"); - log(" AIGER latches to be transformed into posedge DFFs clocked by wire of"); - log(" this name (default: clk)\n"); + log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n" + log(" clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n"); log("\n"); log(" -map \n"); log(" read file with port and latch symbols\n"); -- cgit v1.2.3 From 7a3c403ba0e411c990be59da44e1decb6aafc8f8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 09:10:01 -0700 Subject: Missing close bracket --- frontends/aiger/aigerparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 281e1cc9d..d0d2ffdba 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -1025,7 +1025,7 @@ struct AigerFrontend : public Frontend { log(" Name of module to be created (default: )\n"); log("\n"); log(" -clk_name \n"); - log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n" + log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n"); log(" clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n"); log("\n"); log(" -map \n"); -- cgit v1.2.3 From b706ae82de2fa82b68c327740820c03cc203a217 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 12:42:18 -0700 Subject: Fix log_debug messages --- frontends/aiger/aigerparse.cc | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d0d2ffdba..833c0023b 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -429,6 +429,7 @@ void AigerReader::parse_xaiger() else if (c == 'r') { uint32_t dataSize = parse_xaiger_literal(f); flopNum = parse_xaiger_literal(f); + log_debug("flopNum: %u\n", flopNum); log_assert(dataSize == (flopNum+1) * sizeof(uint32_t)); f.ignore(flopNum * sizeof(uint32_t)); } @@ -450,7 +451,7 @@ void AigerReader::parse_xaiger() uint32_t poNum = parse_xaiger_literal(f); log_debug("poNum = %u\n", poNum); uint32_t boxNum = parse_xaiger_literal(f); - log_debug("boxNum = %u\n", poNum); + log_debug("boxNum = %u\n", boxNum); for (unsigned i = 0; i < boxNum; i++) { f.ignore(2*sizeof(uint32_t)); uint32_t boxUniqueId = parse_xaiger_literal(f); @@ -777,51 +778,56 @@ void AigerReader::post_process() } } + RTLIL::Wire *d = nullptr; + RTLIL::Wire *q = nullptr; // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) for (auto port_name : box_module->ports) { RTLIL::Wire* port = box_module->wire(port_name); log_assert(port); RTLIL::SigSpec rhs; - RTLIL::Wire* wire = nullptr; for (int i = 0; i < GetSize(port); i++) { + RTLIL::Wire* wire = nullptr; if (port->port_input) { - log_assert(co_count < outputs.size()); - wire = outputs[co_count++]; - log_assert(wire); - log_assert(wire->port_output); - wire->port_output = false; - if (flop_module && port->attributes.count("\\abc_flop_d")) { - RTLIL::Wire* d = outputs[outputs.size() - flopNum + flop_count]; + log_assert(!d); + d = outputs[outputs.size() - flopNum + flop_count]; log_assert(d); log_assert(d->port_output); d->port_output = false; } + + log_assert(co_count < outputs.size()); + wire = outputs[co_count++]; + log_assert(wire); + log_assert(wire->port_output); + wire->port_output = false; } if (port->port_output) { + if (flop_module && port->attributes.count("\\abc_flop_q")) { + log_assert(!q); + q = inputs[piNum - flopNum + flop_count]; + log_assert(q); + log_assert(q->port_input); + q->port_input = false; + } + log_assert((piNum + ci_count) < inputs.size()); wire = inputs[piNum + ci_count++]; log_assert(wire); log_assert(wire->port_input); wire->port_input = false; - - if (flop_module && port->attributes.count("\\abc_flop_q")) { - wire = inputs[piNum - flopNum + flop_count]; - log_assert(wire); - log_assert(wire->port_input); - wire->port_input = false; - } } rhs.append(wire); } if (!flop_module || !port->attributes.count("\\abc_discard")) cell->setPort(port_name, rhs); } - if (flop_module) { flop_count++; cell->type = flop_module->name; + //module->addFfGate(NEW_ID, d1 q); + module->connect(q, d); } } -- cgit v1.2.3 From c04921c3a8391d2335fab42ef354bb2bb2f3ac2a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 18:13:44 -0700 Subject: Fix debug message --- frontends/aiger/aigerparse.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 833c0023b..d2657c9da 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -900,6 +900,7 @@ void AigerReader::post_process() else { wire->port_output = false; module->connect(wire, existing); + wire = existing; } } else if (index > 0) { -- cgit v1.2.3 From 3d1185b835e16cc0613aa7a31e810dd6da69599f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 22:41:42 -0700 Subject: Read init from outputs --- frontends/aiger/aigerparse.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d2657c9da..5a6db8481 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -927,6 +927,10 @@ void AigerReader::post_process() } } log_debug(" -> %s\n", log_id(wire)); + int init; + mf >> init; + if (init < 2) + wire->attributes["\\init"] = init; } else if (type == "box") { RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); -- cgit v1.2.3 From 0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 16 Jun 2019 10:42:00 -0700 Subject: Cleanup --- frontends/aiger/aigerparse.cc | 41 ++++++++++++++++++----------------------- 1 file changed, 18 insertions(+), 23 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 5a6db8481..60cbde857 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -737,11 +737,13 @@ void AigerReader::post_process() log_assert(box_module); RTLIL::Module* flop_module = nullptr; - if (box_module->attributes.count("\\abc_flop")) { + auto flop_module_name = box_module->attributes.at("\\abc_flop", RTLIL::Const()); + RTLIL::IdString flop_past_q; + if (flop_module_name.size() > 0) { log_assert(flop_count < flopNum); - log_assert(box_module->name.begins_with("$__ABC_")); - flop_module = design->module("\\" + box_module->name.substr(7)); + flop_module = design->module(RTLIL::escape_id(flop_module_name.decode_string())); log_assert(flop_module); + flop_past_q = box_module->attributes.at("\\abc_flop_past_q").decode_string(); } else if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; @@ -778,8 +780,6 @@ void AigerReader::post_process() } } - RTLIL::Wire *d = nullptr; - RTLIL::Wire *q = nullptr; // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) for (auto port_name : box_module->ports) { @@ -789,14 +789,6 @@ void AigerReader::post_process() for (int i = 0; i < GetSize(port); i++) { RTLIL::Wire* wire = nullptr; if (port->port_input) { - if (flop_module && port->attributes.count("\\abc_flop_d")) { - log_assert(!d); - d = outputs[outputs.size() - flopNum + flop_count]; - log_assert(d); - log_assert(d->port_output); - d->port_output = false; - } - log_assert(co_count < outputs.size()); wire = outputs[co_count++]; log_assert(wire); @@ -804,14 +796,6 @@ void AigerReader::post_process() wire->port_output = false; } if (port->port_output) { - if (flop_module && port->attributes.count("\\abc_flop_q")) { - log_assert(!q); - q = inputs[piNum - flopNum + flop_count]; - log_assert(q); - log_assert(q->port_input); - q->port_input = false; - } - log_assert((piNum + ci_count) < inputs.size()); wire = inputs[piNum + ci_count++]; log_assert(wire); @@ -820,13 +804,24 @@ void AigerReader::post_process() } rhs.append(wire); } - if (!flop_module || !port->attributes.count("\\abc_discard")) + + if (!flop_module || port_name != flop_past_q) cell->setPort(port_name, rhs); } + if (flop_module) { + RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count]; + log_assert(d); + log_assert(d->port_output); + d->port_output = false; + + RTLIL::Wire *q = inputs[piNum - flopNum + flop_count]; + log_assert(q); + log_assert(q->port_input); + q->port_input = false; + flop_count++; cell->type = flop_module->name; - //module->addFfGate(NEW_ID, d1 q); module->connect(q, d); } } -- cgit v1.2.3 From ac5f3d500db46a4312d77f43fded2feb25545a3a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 11:10:44 -0700 Subject: Fix spacing --- frontends/aiger/aigerparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7f81a4c89..57a164f1b 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -756,7 +756,7 @@ void AigerReader::post_process() log_assert(flop_module); flop_past_q = box_module->attributes.at("\\abc_flop_past_q").decode_string(); } - else if (seen_boxes.insert(cell->type).second) { + else if (seen_boxes.insert(cell->type).second) { auto it = box_module->attributes.find("\\abc_carry"); if (it != box_module->attributes.end()) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; -- cgit v1.2.3 From a31e17182d7f9437fb78f5018dfccbd66d9704ea Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 11:50:34 -0700 Subject: Refactor and cope with new abc_flop format --- frontends/aiger/aigerparse.cc | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 57a164f1b..30e35da01 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -742,22 +742,29 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { pool seen_boxes; + dict> flop_data; unsigned ci_count = 0, co_count = 0, flop_count = 0; for (auto cell : boxes) { RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); RTLIL::Module* flop_module = nullptr; - auto flop_module_name = box_module->attributes.at("\\abc_flop", RTLIL::Const()); RTLIL::IdString flop_past_q; - if (flop_module_name.size() > 0) { - log_assert(flop_count < flopNum); - flop_module = design->module(RTLIL::escape_id(flop_module_name.decode_string())); - log_assert(flop_module); - flop_past_q = box_module->attributes.at("\\abc_flop_past_q").decode_string(); - } - else if (seen_boxes.insert(cell->type).second) { - auto it = box_module->attributes.find("\\abc_carry"); + if (seen_boxes.insert(cell->type).second) { + auto it = box_module->attributes.find("\\abc_flop"); + if (it != box_module->attributes.end()) { + log_assert(flop_count < flopNum); + std::string abc_flop = it->second.decode_string(); + auto pos = abc_flop.find(','); + log_assert(pos != std::string::npos); + flop_module = design->module(RTLIL::escape_id(abc_flop.substr(0, pos))); + log_assert(flop_module); + pos = abc_flop.rfind(','); + log_assert(pos != std::string::npos); + flop_past_q = RTLIL::escape_id(abc_flop.substr(pos+1)); + flop_data[cell->type] = std::make_pair(flop_module, flop_past_q); + } + it = box_module->attributes.find("\\abc_carry"); if (it != box_module->attributes.end()) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; auto carry_in_out = it->second.decode_string(); @@ -796,6 +803,11 @@ void AigerReader::post_process() carry_out->port_id = ports.size(); } } + else { + auto it = flop_data.find(cell->type); + if (it != flop_data.end()) + std::tie(flop_module,flop_past_q) = it->second; + } // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) -- cgit v1.2.3 From a092c48f036b71cc4014ec6f2865297d49589d40 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 17:34:51 -0700 Subject: Use split_tokens() --- frontends/aiger/aigerparse.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 30e35da01..35b7f6a97 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -754,14 +754,14 @@ void AigerReader::post_process() auto it = box_module->attributes.find("\\abc_flop"); if (it != box_module->attributes.end()) { log_assert(flop_count < flopNum); - std::string abc_flop = it->second.decode_string(); - auto pos = abc_flop.find(','); - log_assert(pos != std::string::npos); - flop_module = design->module(RTLIL::escape_id(abc_flop.substr(0, pos))); - log_assert(flop_module); - pos = abc_flop.rfind(','); - log_assert(pos != std::string::npos); - flop_past_q = RTLIL::escape_id(abc_flop.substr(pos+1)); + auto abc_flop = it->second.decode_string(); + auto tokens = split_tokens(abc_flop, ","); + if (tokens.size() != 4) + log_error("'abc_flop' attribute on module '%s' does not contain exactly four comma-separated tokens.\n", log_id(cell->type)); + flop_module = design->module(RTLIL::escape_id(tokens[0])); + if (!flop_module) + log_error("First token '%s' in 'abc_flop' attribute on module '%s' is not a valid module.\n", tokens[0].c_str(), log_id(cell->type)); + flop_past_q = RTLIL::escape_id(tokens[3]); flop_data[cell->type] = std::make_pair(flop_module, flop_past_q); } it = box_module->attributes.find("\\abc_carry"); -- cgit v1.2.3 From 4a995c5d80735baf1431a088c2faf81eb75fdaf6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 17:54:56 -0700 Subject: Change how to specify flops to ABC again --- frontends/aiger/aigerparse.cc | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 35b7f6a97..11c5e3570 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -742,27 +742,23 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { pool seen_boxes; - dict> flop_data; + dict flop_data; unsigned ci_count = 0, co_count = 0, flop_count = 0; for (auto cell : boxes) { RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); RTLIL::Module* flop_module = nullptr; - RTLIL::IdString flop_past_q; + const RTLIL::IdString flop_past_q = RTLIL::escape_id("\\$pastQ"); if (seen_boxes.insert(cell->type).second) { auto it = box_module->attributes.find("\\abc_flop"); if (it != box_module->attributes.end()) { log_assert(flop_count < flopNum); auto abc_flop = it->second.decode_string(); - auto tokens = split_tokens(abc_flop, ","); - if (tokens.size() != 4) - log_error("'abc_flop' attribute on module '%s' does not contain exactly four comma-separated tokens.\n", log_id(cell->type)); - flop_module = design->module(RTLIL::escape_id(tokens[0])); + flop_module = design->module(RTLIL::escape_id(abc_flop)); if (!flop_module) - log_error("First token '%s' in 'abc_flop' attribute on module '%s' is not a valid module.\n", tokens[0].c_str(), log_id(cell->type)); - flop_past_q = RTLIL::escape_id(tokens[3]); - flop_data[cell->type] = std::make_pair(flop_module, flop_past_q); + log_error("'abc_flop' attribute value '%s' on module '%s' is not a valid module.\n", abc_flop.c_str(), log_id(cell->type)); + flop_data[cell->type] = flop_module; } it = box_module->attributes.find("\\abc_carry"); if (it != box_module->attributes.end()) { @@ -806,7 +802,7 @@ void AigerReader::post_process() else { auto it = flop_data.find(cell->type); if (it != flop_data.end()) - std::tie(flop_module,flop_past_q) = it->second; + flop_module = it->second; } // NB: Assume box_module->ports are sorted alphabetically -- cgit v1.2.3 From f8f0ffe786eabd016e0f9a0e4f4de10743638cdf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 18:56:50 -0700 Subject: Small opt --- frontends/aiger/aigerparse.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 11c5e3570..b599160cf 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -749,7 +749,6 @@ void AigerReader::post_process() log_assert(box_module); RTLIL::Module* flop_module = nullptr; - const RTLIL::IdString flop_past_q = RTLIL::escape_id("\\$pastQ"); if (seen_boxes.insert(cell->type).second) { auto it = box_module->attributes.find("\\abc_flop"); if (it != box_module->attributes.end()) { @@ -830,7 +829,7 @@ void AigerReader::post_process() rhs.append(wire); } - if (!flop_module || port_name != flop_past_q) + if (!flop_module || port_name != "\\$pastQ") cell->setPort(port_name, rhs); } -- cgit v1.2.3 From bd198aa803bdfc3b21bfa920822805df992e3120 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 10:07:14 -0700 Subject: Missing debug message --- frontends/aiger/aigerparse.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index b599160cf..77ef75cd5 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -901,6 +901,7 @@ void AigerReader::post_process() wire->port_output = false; continue; } + log_debug("Renaming output %s", log_id(wire)); if (index == 0) { // Cope with the fact that a CO might be identical -- cgit v1.2.3 From a314565ad448c1d5a76604bbd25ac2c901c08f8f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 10:52:45 -0700 Subject: Short out async box --- frontends/aiger/aigerparse.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 77ef75cd5..b984e846a 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -741,6 +741,9 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { + const RTLIL::Wire* n0 = module->wire("\\__0__"); + const RTLIL::Wire* n1 = module->wire("\\__1__"); + pool seen_boxes; dict flop_data; unsigned ci_count = 0, co_count = 0, flop_count = 0; @@ -847,6 +850,17 @@ void AigerReader::post_process() flop_count++; cell->type = flop_module->name; module->connect(q, d); + continue; + } + + // Remove the async mux by shorting out its input and output + if (cell->type == "$__ABC_ASYNC") { + RTLIL::Wire* A = cell->getPort("\\A").as_wire(); + if (A == n0 || A == n1) A = nullptr; + auto it = cell->connections_.find("\\Y"); + log_assert(it != cell->connections_.end()); + module->connect(it->second, A); + cell->connections_.erase(it); } } -- cgit v1.2.3 From 9bfe924e17a87fac8a35fcb7ff5e067f6c520e07 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 09:40:01 -0700 Subject: Set abc_flop and use it in toposort --- frontends/aiger/aigerparse.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index f2b38da67..6fd9e0432 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -840,6 +840,7 @@ void AigerReader::post_process() flop_count++; cell->type = flop_module->name; module->connect(q, d); + cell->set_bool_attribute("\\abc_flop"); continue; } -- cgit v1.2.3 From be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 12:39:11 -0700 Subject: Use abc_{map,unmap,model}.v --- frontends/aiger/aigerparse.cc | 41 ++++++++++------------------------------- 1 file changed, 10 insertions(+), 31 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index cb4ec6183..7a467b91e 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -731,28 +731,21 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { - const RTLIL::Wire* n0 = module->wire("\\__0__"); - const RTLIL::Wire* n1 = module->wire("\\__1__"); - pool seen_boxes; - dict flop_data; + pool flops; unsigned ci_count = 0, co_count = 0, flop_count = 0; for (auto cell : boxes) { RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); - RTLIL::Module* flop_module = nullptr; + bool is_flop = false; if (seen_boxes.insert(cell->type).second) { - auto it = box_module->attributes.find("\\abc_flop"); - if (it != box_module->attributes.end()) { + if (box_module->attributes.count("\\abc_flop")) { log_assert(flop_count < flopNum); - auto abc_flop = it->second.decode_string(); - flop_module = design->module(RTLIL::escape_id(abc_flop)); - if (!flop_module) - log_error("'abc_flop' attribute value '%s' on module '%s' is not a valid module.\n", abc_flop.c_str(), log_id(cell->type)); - flop_data[cell->type] = flop_module; + flops.insert(cell->type); + is_flop = true; } - it = box_module->attributes.find("\\abc_carry"); + auto it = box_module->attributes.find("\\abc_carry"); if (it != box_module->attributes.end()) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; auto carry_in_out = it->second.decode_string(); @@ -791,11 +784,8 @@ void AigerReader::post_process() carry_out->port_id = ports.size(); } } - else { - auto it = flop_data.find(cell->type); - if (it != flop_data.end()) - flop_module = it->second; - } + else + is_flop = flops.count(cell->type); // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) @@ -822,11 +812,11 @@ void AigerReader::post_process() rhs.append(wire); } - if (!flop_module || port_name != "\\$pastQ") + if (!is_flop || port_name != "\\$pastQ") cell->setPort(port_name, rhs); } - if (flop_module) { + if (is_flop) { RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count]; log_assert(d); log_assert(d->port_output); @@ -838,21 +828,10 @@ void AigerReader::post_process() q->port_input = false; flop_count++; - cell->type = flop_module->name; module->connect(q, d); cell->set_bool_attribute("\\abc_flop"); continue; } - - // Remove the async mux by shorting out its input and output - if (cell->type == "$__ABC_ASYNC") { - RTLIL::Wire* A = cell->getPort("\\A").as_wire(); - if (A == n0 || A == n1) A = nullptr; - auto it = cell->connections_.find("\\Y"); - log_assert(it != cell->connections_.end()); - module->connect(it->second, A); - cell->connections_.erase(it); - } } dict wideports_cache; -- cgit v1.2.3 From 091bf4a18b2f4bf84fe62b61577c88d961468b3c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:16:37 -0700 Subject: Remove sequential extension --- frontends/aiger/aigerparse.cc | 35 ++--------------------------------- 1 file changed, 2 insertions(+), 33 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7a467b91e..e8ee487e5 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -732,19 +732,12 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { pool seen_boxes; - pool flops; - unsigned ci_count = 0, co_count = 0, flop_count = 0; + unsigned ci_count = 0, co_count = 0; for (auto cell : boxes) { RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); - bool is_flop = false; if (seen_boxes.insert(cell->type).second) { - if (box_module->attributes.count("\\abc_flop")) { - log_assert(flop_count < flopNum); - flops.insert(cell->type); - is_flop = true; - } auto it = box_module->attributes.find("\\abc_carry"); if (it != box_module->attributes.end()) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; @@ -784,8 +777,6 @@ void AigerReader::post_process() carry_out->port_id = ports.size(); } } - else - is_flop = flops.count(cell->type); // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) @@ -812,25 +803,7 @@ void AigerReader::post_process() rhs.append(wire); } - if (!is_flop || port_name != "\\$pastQ") - cell->setPort(port_name, rhs); - } - - if (is_flop) { - RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count]; - log_assert(d); - log_assert(d->port_output); - d->port_output = false; - - RTLIL::Wire *q = inputs[piNum - flopNum + flop_count]; - log_assert(q); - log_assert(q->port_input); - q->port_input = false; - - flop_count++; - module->connect(q, d); - cell->set_bool_attribute("\\abc_flop"); - continue; + cell->setPort(port_name, rhs); } } @@ -934,10 +907,6 @@ void AigerReader::post_process() } } log_debug(" -> %s\n", log_id(wire)); - int init; - mf >> init; - if (init < 2) - wire->attributes["\\init"] = init; } else if (type == "box") { RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); -- cgit v1.2.3 From 25e5fbac9096a872f7be1a481e6798103f40ccf5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 2 Sep 2019 22:56:38 +0200 Subject: Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf --- frontends/ast/simplify.cc | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 86dd80c65..52fcf3ee7 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1530,10 +1530,16 @@ skip_dynamic_range_lvalue_expansion:; current_scope[wire_en->str] = wire_en; while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } - std::vector x_bit; - x_bit.push_back(RTLIL::State::Sx); + AstNode *check_defval; + if (type == AST_LIVE || type == AST_FAIR) { + check_defval = new AstNode(AST_REDUCE_BOOL, children[0]->clone()); + } else { + std::vector x_bit; + x_bit.push_back(RTLIL::State::Sx); + check_defval = mkconst_bits(x_bit, false); + } - AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bit, false)); + AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), check_defval); assign_check->children[0]->str = id_check; assign_check->children[0]->was_checked = true; @@ -1546,9 +1552,13 @@ skip_dynamic_range_lvalue_expansion:; default_signals->children.push_back(assign_en); current_top_block->children.insert(current_top_block->children.begin(), default_signals); - assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone())); - assign_check->children[0]->str = id_check; - assign_check->children[0]->was_checked = true; + if (type == AST_LIVE || type == AST_FAIR) { + assign_check = nullptr; + } else { + assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone())); + assign_check->children[0]->str = id_check; + assign_check->children[0]->was_checked = true; + } if (current_always == nullptr || current_always->type != AST_INITIAL) { assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1)); @@ -1560,7 +1570,8 @@ skip_dynamic_range_lvalue_expansion:; assign_en->children[0]->was_checked = true; newNode = new AstNode(AST_BLOCK); - newNode->children.push_back(assign_check); + if (assign_check != nullptr) + newNode->children.push_back(assign_check); newNode->children.push_back(assign_en); AstNode *assertnode = new AstNode(type); -- cgit v1.2.3