From f9a307a50b5ce67b67d2b53e8c1334ea23ffd997 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 27 Sep 2014 16:17:53 +0200 Subject: namespace Yosys --- frontends/ast/dpicall.cc | 8 ++++++++ frontends/ilang/ilang_frontend.cc | 6 +++--- frontends/ilang/lexer.l | 2 ++ frontends/liberty/liberty.cc | 1 - frontends/verilog/verilog_frontend.cc | 32 ++++++++++++++++---------------- 5 files changed, 29 insertions(+), 20 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/dpicall.cc b/frontends/ast/dpicall.cc index 2eb104fa0..e5b1ff9c0 100644 --- a/frontends/ast/dpicall.cc +++ b/frontends/ast/dpicall.cc @@ -24,6 +24,8 @@ #include #include +YOSYS_NAMESPACE_BEGIN + typedef void (*ffi_fptr) (); static ffi_fptr resolve_fn (std::string symbol_name) @@ -129,12 +131,18 @@ AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname, return newNode; } +YOSYS_NAMESPACE_END + #else /* YOSYS_ENABLE_PLUGINS */ +YOSYS_NAMESPACE_BEGIN + AST::AstNode *AST::dpi_call(const std::string&, const std::string &fname, const std::vector&, const std::vector&) { log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname.c_str()); } +YOSYS_NAMESPACE_END + #endif /* YOSYS_ENABLE_PLUGINS */ diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc index f6f926db1..7a4687a3c 100644 --- a/frontends/ilang/ilang_frontend.cc +++ b/frontends/ilang/ilang_frontend.cc @@ -26,13 +26,13 @@ #include "kernel/register.h" #include "kernel/log.h" -YOSYS_NAMESPACE_BEGIN - void rtlil_frontend_ilang_yyerror(char const *s) { - log_error("Parser error in line %d: %s\n", rtlil_frontend_ilang_yyget_lineno(), s); + YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_ilang_yyget_lineno(), s); } +YOSYS_NAMESPACE_BEGIN + struct IlangFrontend : public Frontend { IlangFrontend() : Frontend("ilang", "read modules from ilang file") { } virtual void help() diff --git a/frontends/ilang/lexer.l b/frontends/ilang/lexer.l index 4109cd4bc..292321e88 100644 --- a/frontends/ilang/lexer.l +++ b/frontends/ilang/lexer.l @@ -32,6 +32,8 @@ #include "ilang_frontend.h" #include "parser.tab.h" +USING_YOSYS_NAMESPACE + #define YY_INPUT(buf,result,max_size) \ result = ILANG_FRONTEND::lexin->readsome(buf, max_size); diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index a9ab022a4..464c5c942 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -22,7 +22,6 @@ #include "kernel/log.h" YOSYS_NAMESPACE_BEGIN -using namespace PASS_DFFLIBMAP; struct token_t { char type; diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index c6d4a0b79..1e1cd852a 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -300,22 +300,6 @@ struct VerilogFrontend : public Frontend { } } VerilogFrontend; -// the yyerror function used by bison to report parser errors -void frontend_verilog_yyerror(char const *fmt, ...) -{ - va_list ap; - char buffer[1024]; - char *p = buffer; - p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ", - AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); - va_start(ap, fmt); - p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap); - va_end(ap); - p += snprintf(p, buffer + sizeof(buffer) - p, "\n"); - log_error("%s", buffer); - exit(1); -} - struct VerilogDefaults : public Pass { VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { } virtual void help() @@ -376,3 +360,19 @@ struct VerilogDefaults : public Pass { YOSYS_NAMESPACE_END +// the yyerror function used by bison to report parser errors +void frontend_verilog_yyerror(char const *fmt, ...) +{ + va_list ap; + char buffer[1024]; + char *p = buffer; + p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ", + YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); + va_start(ap, fmt); + p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap); + va_end(ap); + p += snprintf(p, buffer + sizeof(buffer) - p, "\n"); + YOSYS_NAMESPACE_PREFIX log_error("%s", buffer); + exit(1); +} + -- cgit v1.2.3 From 4569a747f8af3880e23408eb93323afc8088b78b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 10 Oct 2014 16:59:44 +0200 Subject: Renamed SIZE() to GetSize() because of name collision on Win32 --- frontends/ast/dpicall.cc | 4 ++-- frontends/ast/genrtlil.cc | 16 ++++++++-------- frontends/ast/simplify.cc | 20 ++++++++++---------- frontends/verific/verific.cc | 16 ++++++++-------- frontends/verilog/parser.y | 2 +- 5 files changed, 29 insertions(+), 29 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/dpicall.cc b/frontends/ast/dpicall.cc index e5b1ff9c0..e566d653d 100644 --- a/frontends/ast/dpicall.cc +++ b/frontends/ast/dpicall.cc @@ -75,8 +75,8 @@ AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname, log("Calling DPI function `%s' and returning `%s':\n", fname.c_str(), rtype.c_str()); - log_assert(SIZE(args) == SIZE(argtypes)); - for (int i = 0; i < SIZE(args); i++) { + log_assert(GetSize(args) == GetSize(argtypes)); + for (int i = 0; i < GetSize(args); i++) { if (argtypes[i] == "real") { log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed)); value_store[i].f64 = args[i]->asReal(args[i]->is_signed); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index f87a68f67..68c45179d 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -254,7 +254,7 @@ struct AST_INTERNAL::ProcessGenerator // create initial assignments for the temporary signals if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) { - subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, SIZE(subst_lvalue_from))); + subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from))); } else { addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from); } @@ -289,8 +289,8 @@ struct AST_INTERNAL::ProcessGenerator { RTLIL::SigSpec new_lhs, new_rhs; - log_assert(SIZE(lhs) == SIZE(rhs)); - for (int i = 0; i < SIZE(lhs); i++) { + log_assert(GetSize(lhs) == GetSize(rhs)); + for (int i = 0; i < GetSize(lhs); i++) { if (lhs[i].wire == nullptr) continue; new_lhs.append(lhs[i]); @@ -306,7 +306,7 @@ struct AST_INTERNAL::ProcessGenerator { std::vector chunks = sig.chunks(); - for (int i = 0; i < SIZE(chunks); i++) + for (int i = 0; i < GetSize(chunks); i++) { RTLIL::SigChunk &chunk = chunks[i]; if (chunk.wire == NULL) @@ -430,7 +430,7 @@ struct AST_INTERNAL::ProcessGenerator lvalue.replace(subst_lvalue_map.stdmap()); if (ast->type == AST_ASSIGN_EQ) { - for (int i = 0; i < SIZE(unmapped_lvalue); i++) + for (int i = 0; i < GetSize(unmapped_lvalue); i++) subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]); } @@ -472,7 +472,7 @@ struct AST_INTERNAL::ProcessGenerator subst_lvalue_map.save(); subst_rvalue_map.save(); - for (int i = 0; i < SIZE(this_case_eq_lvalue); i++) + for (int i = 0; i < GetSize(this_case_eq_lvalue); i++) subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]); RTLIL::CaseRule *backup_case = current_case; @@ -507,7 +507,7 @@ struct AST_INTERNAL::ProcessGenerator sw->cases.push_back(default_case); } - for (int i = 0; i < SIZE(this_case_eq_lvalue); i++) + for (int i = 0; i < GetSize(this_case_eq_lvalue); i++) subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]); this_case_eq_lvalue.replace(subst_lvalue_map.stdmap()); @@ -941,7 +941,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed); fake_ast->children[1]->is_signed = true; } - if (SIZE(shift_val) >= 32) + if (GetSize(shift_val) >= 32) fake_ast->children[1]->is_signed = true; RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val); delete left_at_zero_ast; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 969cc2302..9f33ea780 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -575,9 +575,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { AstNode *index_expr = nullptr; - for (int i = 0; 2*i < SIZE(id2ast->multirange_dimensions); i++) + for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++) { - if (SIZE(children[0]->children) < i) + if (GetSize(children[0]->children) < i) log_error("Insufficient number of array indices for %s at %s:%d.\n", log_id(str), filename.c_str(), linenum); AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone(); @@ -591,7 +591,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, index_expr = new AstNode(AST_ADD, new AstNode(AST_MUL, index_expr, AstNode::mkconst_int(id2ast->multirange_dimensions[2*i-1], true)), new_index_expr); } - for (int i = SIZE(id2ast->multirange_dimensions)/1; i < SIZE(children[0]->children); i++) + for (int i = GetSize(id2ast->multirange_dimensions)/1; i < GetSize(children[0]->children); i++) children.push_back(children[0]->children[i]->clone()); delete children[0]; @@ -1366,7 +1366,7 @@ skip_dynamic_range_lvalue_expansion:; RTLIL::Const arg_value = buf->bitsAsConst(); if (arg_value.as_bool()) - arg_value = const_sub(arg_value, 1, false, false, SIZE(arg_value)); + arg_value = const_sub(arg_value, 1, false, false, GetSize(arg_value)); delete buf; uint32_t result = 0; @@ -1455,9 +1455,9 @@ skip_dynamic_range_lvalue_expansion:; rtype = RTLIL::unescape_id(dpi_decl->children.at(0)->str); fname = RTLIL::unescape_id(dpi_decl->children.at(1)->str); - for (int i = 2; i < SIZE(dpi_decl->children); i++) + for (int i = 2; i < GetSize(dpi_decl->children); i++) { - if (i-2 >= SIZE(children)) + if (i-2 >= GetSize(children)) log_error("Insufficient number of arguments in DPI function call at %s:%d.\n", filename.c_str(), linenum); argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str)); @@ -1558,7 +1558,7 @@ skip_dynamic_range_lvalue_expansion:; celltype = RTLIL::escape_id(celltype); AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE)); - cell->str = prefix.substr(0, SIZE(prefix)-1); + cell->str = prefix.substr(0, GetSize(prefix)-1); cell->children[0]->str = celltype; for (auto attr : decl->attributes) @@ -1681,7 +1681,7 @@ skip_dynamic_range_lvalue_expansion:; bool param_upto = current_scope[str]->range_valid && current_scope[str]->range_swapped; int param_offset = current_scope[str]->range_valid ? current_scope[str]->range_right : 0; int param_width = current_scope[str]->range_valid ? current_scope[str]->range_left - current_scope[str]->range_right + 1 : - SIZE(current_scope[str]->children[0]->bits); + GetSize(current_scope[str]->children[0]->bits); int tmp_range_left = children[0]->range_left, tmp_range_right = children[0]->range_right; if (param_upto) { tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1; @@ -1847,7 +1847,7 @@ skip_dynamic_range_lvalue_expansion:; if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { std::vector new_children; new_children.push_back(children[0]); - for (int i = 1; i < SIZE(children); i++) { + for (int i = 1; i < GetSize(children); i++) { AstNode *child = children[i]; log_assert(child->type == AST_COND); for (auto v : child->children) { @@ -1857,7 +1857,7 @@ skip_dynamic_range_lvalue_expansion:; continue; if (v->type == AST_CONSTANT && v->bits_only_01()) { if (v->bits == children[0]->bits) { - while (i+1 < SIZE(children)) + while (i+1 < GetSize(children)) delete children[++i]; goto keep_const_cond; } diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d0f148386..5e1894cfd 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -324,7 +324,7 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::mapGetCin()->IsGnd()) { module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, out, SIGNED); } else { - RTLIL::SigSpec tmp = module->addWire(NEW_ID, SIZE(out)); + RTLIL::SigSpec tmp = module->addWire(NEW_ID, GetSize(out)); module->addAdd(NEW_ID, IN1, IN2, tmp, SIGNED); module->addAdd(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetCin()), out, false); } @@ -687,8 +687,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::setparameters["\\CLK_ENABLE"] = false; cell->parameters["\\CLK_POLARITY"] = true; cell->parameters["\\TRANSPARENT"] = false; - cell->parameters["\\ABITS"] = SIZE(addr); - cell->parameters["\\WIDTH"] = SIZE(data); + cell->parameters["\\ABITS"] = GetSize(addr); + cell->parameters["\\WIDTH"] = GetSize(data); cell->setPort("\\CLK", RTLIL::State::S0); cell->setPort("\\ADDR", addr); cell->setPort("\\DATA", data); @@ -709,9 +709,9 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::setparameters["\\CLK_ENABLE"] = false; cell->parameters["\\CLK_POLARITY"] = true; cell->parameters["\\PRIORITY"] = 0; - cell->parameters["\\ABITS"] = SIZE(addr); - cell->parameters["\\WIDTH"] = SIZE(data); - cell->setPort("\\EN", RTLIL::SigSpec(net_map.at(inst->GetControl())).repeat(SIZE(data))); + cell->parameters["\\ABITS"] = GetSize(addr); + cell->parameters["\\WIDTH"] = GetSize(data); + cell->setPort("\\EN", RTLIL::SigSpec(net_map.at(inst->GetControl())).repeat(GetSize(data))); cell->setPort("\\CLK", RTLIL::State::S0); cell->setPort("\\ADDR", addr); cell->setPort("\\DATA", data); @@ -753,9 +753,9 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::sethasPort(RTLIL::escape_id(port_name))) conn = cell->getPort(RTLIL::escape_id(port_name)); - while (SIZE(conn) <= port_offset) { + while (GetSize(conn) <= port_offset) { if (pr->GetPort()->GetDir() != DIR_IN) - conn.append(module->addWire(NEW_ID, port_offset - SIZE(conn))); + conn.append(module->addWire(NEW_ID, port_offset - GetSize(conn))); conn.append(RTLIL::State::Sz); } conn.replace(port_offset, net_map.at(pr->GetNet())); diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index a9f69a49c..cf02a56a9 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -142,7 +142,7 @@ input: { ast_stack.push_back(current_ast); } design { ast_stack.pop_back(); - log_assert(SIZE(ast_stack) == 0); + log_assert(GetSize(ast_stack) == 0); for (auto &it : default_attr_list) delete it.second; default_attr_list.clear(); -- cgit v1.2.3 From bbd808072be859074a023795a15bebab87cbfba8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 10 Oct 2014 17:22:08 +0200 Subject: Added format __attribute__ to stringf() --- frontends/verilog/preproc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index f83433219..7e14fcb84 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -422,7 +422,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons if (tok == "(" || tok == "{" || tok == "[") level++; } - for (size_t i = 0; i < args.size(); i++) + for (int i = 0; i < GetSize(args); i++) defines_map[stringf("macro_%s_arg%d", name.c_str(), i+1)] = args[i]; } else { insert_input(tok); -- cgit v1.2.3 From 0a651f112fe62fdf86e4b288988a9ed9ac90068d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 11 Oct 2014 10:46:19 +0200 Subject: Disabled vhdl2verilog command for win32 builds --- frontends/vhdl2verilog/vhdl2verilog.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'frontends') diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index b408d621b..a8c411c7b 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -120,6 +120,10 @@ struct Vhdl2verilogPass : public Pass { if (top_entity.empty()) log_cmd_error("Missing -top option.\n"); +#ifdef _WIN32 + #warning Fixme: The vhdl2veriog command has not been ported to win32. + log_cmd_error("The vhdl2veriog command has not been ported to win32.\n"); +#else char tempdir_name[] = "/tmp/yosys-vhdl2verilog-XXXXXX"; char *p = mkdtemp(tempdir_name); log("Using temp directory %s.\n", tempdir_name); @@ -189,6 +193,7 @@ struct Vhdl2verilogPass : public Pass { log_error("Execution of \"rm -rf '%s'\" failed!\n", tempdir_name); log_pop(); +#endif } } Vhdl2verilogPass; -- cgit v1.2.3 From 8263f6a74a822579f3c1da7d8b128ea8ab7b4d79 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 11 Oct 2014 11:36:22 +0200 Subject: Fixed win32 troubles with f.readsome() --- frontends/ilang/lexer.l | 2 +- frontends/verilog/lexer.l | 2 +- frontends/verilog/preproc.cc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/ilang/lexer.l b/frontends/ilang/lexer.l index 292321e88..9669f0924 100644 --- a/frontends/ilang/lexer.l +++ b/frontends/ilang/lexer.l @@ -35,7 +35,7 @@ USING_YOSYS_NAMESPACE #define YY_INPUT(buf,result,max_size) \ - result = ILANG_FRONTEND::lexin->readsome(buf, max_size); + result = readsome(*ILANG_FRONTEND::lexin, buf, max_size); %} diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l index c9302aba8..98f360885 100644 --- a/frontends/verilog/lexer.l +++ b/frontends/verilog/lexer.l @@ -64,7 +64,7 @@ YOSYS_NAMESPACE_END return TOK_ID; #define YY_INPUT(buf,result,max_size) \ - result = lexin->readsome(buf, max_size); + result = readsome(*lexin, buf, max_size); %} diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7e14fcb84..b4e77c31b 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -202,7 +202,7 @@ static void input_file(std::istream &f, std::string filename) auto it = input_buffer.begin(); input_buffer.insert(it, "`file_push " + filename + "\n"); - while ((rc = f.readsome(buffer, sizeof(buffer)-1)) > 0) { + while ((rc = readsome(f, buffer, sizeof(buffer)-1)) > 0) { buffer[rc] = 0; input_buffer.insert(it, buffer); } -- cgit v1.2.3 From 35fbc0b35fb2dafa1b7d1df98ed72688e2eeead6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 11 Oct 2014 11:42:08 +0200 Subject: Do not the 'z' modifier in format string (another win32 fix) --- frontends/ast/ast.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 1e43875ae..87b073ff3 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -267,7 +267,7 @@ void AstNode::dumpAst(FILE *f, std::string indent) bits[i-1] == RTLIL::S1 ? '1' : bits[i-1] == RTLIL::Sx ? 'x' : bits[i-1] == RTLIL::Sz ? 'z' : '?'); - fprintf(f, "'(%zd)", bits.size()); + fprintf(f, "'(%d)", GetSize(bits)); } if (is_input) fprintf(f, " input"); @@ -471,7 +471,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) else if (bits.size() == 32) fprintf(f, "%d", RTLIL::Const(bits).as_int()); else - fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str()); + fprintf(f, "%d'b %s", GetSize(bits), RTLIL::Const(bits).as_string().c_str()); break; case AST_REALVALUE: -- cgit v1.2.3 From b1596bc0e7e5269fd610508f608f65f3aa696bd9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 12 Oct 2014 10:57:15 +0200 Subject: Added run_command() api to replace system() and popen() --- frontends/vhdl2verilog/vhdl2verilog.cc | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) (limited to 'frontends') diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index a8c411c7b..3895ecfd2 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -165,20 +165,9 @@ struct Vhdl2verilogPass : public Pass { log("Running '%s'..\n", command.c_str()); - errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand - f = popen(command.c_str(), "r"); - if (f == NULL) - log_error("Opening pipe to `%s' for reading failed: %s\n", command.c_str(), strerror(errno)); - - char logbuf[1024]; - while (fgets(logbuf, 1024, f) != NULL) - log("%s", logbuf); - - int ret = pclose(f); - if (ret < 0) - log_error("Closing pipe to `%s' failed: %s\n", command.c_str(), strerror(errno)); - if (WEXITSTATUS(ret) != 0) - log_error("Execution of command \"%s\" failed: the shell returned %d\n", command.c_str(), WEXITSTATUS(ret)); + int ret = run_command(command, [](const std::string &line) { log("%s", line.c_str()); }); + if (ret != 0) + log_error("Execution of command \"%s\" failed: return code %d.\n", command.c_str(), ret); if (out_file.empty()) { std::ifstream ff; @@ -189,7 +178,7 @@ struct Vhdl2verilogPass : public Pass { } log_header("Removing temp directory `%s':\n", tempdir_name); - if (system(stringf("rm -rf '%s'", tempdir_name).c_str()) != 0) + if (run_command(stringf("rm -rf '%s'", tempdir_name).c_str()) != 0) log_error("Execution of \"rm -rf '%s'\" failed!\n", tempdir_name); log_pop(); -- cgit v1.2.3 From 0b9282a779867459fe5babfff300795c343c46ea Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 12 Oct 2014 12:11:57 +0200 Subject: Added make_temp_{file,dir}() and remove_directory() APIs --- frontends/vhdl2verilog/vhdl2verilog.cc | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) (limited to 'frontends') diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index 3895ecfd2..39b4f1496 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -120,15 +120,8 @@ struct Vhdl2verilogPass : public Pass { if (top_entity.empty()) log_cmd_error("Missing -top option.\n"); -#ifdef _WIN32 - #warning Fixme: The vhdl2veriog command has not been ported to win32. - log_cmd_error("The vhdl2veriog command has not been ported to win32.\n"); -#else - char tempdir_name[] = "/tmp/yosys-vhdl2verilog-XXXXXX"; - char *p = mkdtemp(tempdir_name); - log("Using temp directory %s.\n", tempdir_name); - if (p == NULL) - log_error("For some reason mkdtemp() failed!\n"); + std::string tempdir_name = make_temp_dir("/tmp/yosys-vhdl2verilog-XXXXXX"); + log("Using temp directory %s.\n", tempdir_name.c_str()); if (!out_file.empty() && out_file[0] != '/') { char pwd[PATH_MAX]; @@ -139,7 +132,7 @@ struct Vhdl2verilogPass : public Pass { out_file = pwd + ("/" + out_file); } - FILE *f = fopen(stringf("%s/files.list", tempdir_name).c_str(), "wt"); + FILE *f = fopen(stringf("%s/files.list", tempdir_name.c_str()).c_str(), "wt"); while (argidx < args.size()) { std::string file = args[argidx++]; if (file.empty()) @@ -160,7 +153,7 @@ struct Vhdl2verilogPass : public Pass { std::string command = "exec 2>&1; "; if (!vhdl2verilog_dir.empty()) command += stringf("cd '%s'; . ./setup_env.sh; ", vhdl2verilog_dir.c_str()); - command += stringf("cd '%s'; vhdl2verilog -out '%s' -filelist files.list -top '%s'%s", tempdir_name, + command += stringf("cd '%s'; vhdl2verilog -out '%s' -filelist files.list -top '%s'%s", tempdir_name.c_str(), out_file.empty() ? "vhdl2verilog_output.v" : out_file.c_str(), top_entity.c_str(), extra_opts.c_str()); log("Running '%s'..\n", command.c_str()); @@ -171,18 +164,15 @@ struct Vhdl2verilogPass : public Pass { if (out_file.empty()) { std::ifstream ff; - ff.open(stringf("%s/vhdl2verilog_output.v", tempdir_name).c_str()); + ff.open(stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()).c_str()); if (ff.fail()) log_error("Can't open vhdl2verilog output file `vhdl2verilog_output.v'.\n"); - Frontend::frontend_call(design, &ff, stringf("%s/vhdl2verilog_output.v", tempdir_name), "verilog"); + Frontend::frontend_call(design, &ff, stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()), "verilog"); } - log_header("Removing temp directory `%s':\n", tempdir_name); - if (run_command(stringf("rm -rf '%s'", tempdir_name).c_str()) != 0) - log_error("Execution of \"rm -rf '%s'\" failed!\n", tempdir_name); - + log_header("Removing temp directory `%s':\n", tempdir_name.c_str()); + remove_directory(tempdir_name); log_pop(); -#endif } } Vhdl2verilogPass; -- cgit v1.2.3 From fad0b0c506f2d7cb1158a3dac53139b8dec7a04e Mon Sep 17 00:00:00 2001 From: William Speirs Date: Tue, 14 Oct 2014 17:06:02 -0400 Subject: Updated lexers & parsers to include prefixes --- frontends/ilang/Makefile.inc | 22 +- frontends/ilang/ilang_lexer.l | 141 ++++ frontends/ilang/ilang_parser.y | 409 ++++++++++ frontends/ilang/lexer.l | 137 ---- frontends/ilang/parser.y | 409 ---------- frontends/verilog/Makefile.inc | 24 +- frontends/verilog/lexer.l | 355 --------- frontends/verilog/parser.y | 1434 ------------------------------------ frontends/verilog/verilog_lexer.l | 359 +++++++++ frontends/verilog/verilog_parser.y | 1434 ++++++++++++++++++++++++++++++++++++ 10 files changed, 2366 insertions(+), 2358 deletions(-) create mode 100644 frontends/ilang/ilang_lexer.l create mode 100644 frontends/ilang/ilang_parser.y delete mode 100644 frontends/ilang/lexer.l delete mode 100644 frontends/ilang/parser.y delete mode 100644 frontends/verilog/lexer.l delete mode 100644 frontends/verilog/parser.y create mode 100644 frontends/verilog/verilog_lexer.l create mode 100644 frontends/verilog/verilog_parser.y (limited to 'frontends') diff --git a/frontends/ilang/Makefile.inc b/frontends/ilang/Makefile.inc index e832cfed8..984d436c6 100644 --- a/frontends/ilang/Makefile.inc +++ b/frontends/ilang/Makefile.inc @@ -1,18 +1,18 @@ -GENFILES += frontends/ilang/parser.tab.cc -GENFILES += frontends/ilang/parser.tab.h -GENFILES += frontends/ilang/parser.output -GENFILES += frontends/ilang/lexer.cc +GENFILES += frontends/ilang/ilang_parser.tab.cc +GENFILES += frontends/ilang/ilang_parser.tab.h +GENFILES += frontends/ilang/ilang_parser.output +GENFILES += frontends/ilang/ilang_lexer.cc -frontends/ilang/parser.tab.cc: frontends/ilang/parser.y - $(P) bison -d -r all -b frontends/ilang/parser frontends/ilang/parser.y - $(Q) mv frontends/ilang/parser.tab.c frontends/ilang/parser.tab.cc +frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y + $(P) bison -d -r all -b frontends/ilang/ilang_parser frontends/ilang/ilang_parser.y + $(Q) mv frontends/ilang/ilang_parser.tab.c frontends/ilang/ilang_parser.tab.cc -frontends/ilang/parser.tab.h: frontends/ilang/parser.tab.cc +frontends/ilang/ilang_parser.tab.h: frontends/ilang/ilang_parser.tab.cc -frontends/ilang/lexer.cc: frontends/ilang/lexer.l - $(P) flex -o frontends/ilang/lexer.cc frontends/ilang/lexer.l +frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l + $(P) flex -o frontends/ilang/ilang_lexer.cc frontends/ilang/ilang_lexer.l -OBJS += frontends/ilang/parser.tab.o frontends/ilang/lexer.o +OBJS += frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o OBJS += frontends/ilang/ilang_frontend.o diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l new file mode 100644 index 000000000..dcbc6b6d7 --- /dev/null +++ b/frontends/ilang/ilang_lexer.l @@ -0,0 +1,141 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * A very simple and straightforward frontend for the RTLIL text + * representation (as generated by the 'ilang' backend). + * + */ + +%{ + +#ifdef __clang__ +// bison generates code using the 'register' storage class specifier +#pragma clang diagnostic ignored "-Wdeprecated-register" +#endif + +#include "ilang_frontend.h" +#include "ilang_parser.tab.h" + +USING_YOSYS_NAMESPACE + +#define YY_INPUT(buf,result,max_size) \ + do { \ + ILANG_FRONTEND::lexin->read(buf, max_size-1); \ + result = ILANG_FRONTEND::lexin->gcount(); \ + if (result >= 0) buf[result] = '\0'; \ + } while (0) + +%} + +%option yylineno +%option noyywrap +%option nounput +%option prefix="rtlil_frontend_ilang_yy" + +%x STRING + +%% + +"autoidx" { return TOK_AUTOIDX; } +"module" { return TOK_MODULE; } +"attribute" { return TOK_ATTRIBUTE; } +"parameter" { return TOK_PARAMETER; } +"signed" { return TOK_SIGNED; } +"wire" { return TOK_WIRE; } +"memory" { return TOK_MEMORY; } +"width" { return TOK_WIDTH; } +"upto" { return TOK_UPTO; } +"offset" { return TOK_OFFSET; } +"size" { return TOK_SIZE; } +"input" { return TOK_INPUT; } +"output" { return TOK_OUTPUT; } +"inout" { return TOK_INOUT; } +"cell" { return TOK_CELL; } +"connect" { return TOK_CONNECT; } +"switch" { return TOK_SWITCH; } +"case" { return TOK_CASE; } +"assign" { return TOK_ASSIGN; } +"sync" { return TOK_SYNC; } +"low" { return TOK_LOW; } +"high" { return TOK_HIGH; } +"posedge" { return TOK_POSEDGE; } +"negedge" { return TOK_NEGEDGE; } +"edge" { return TOK_EDGE; } +"always" { return TOK_ALWAYS; } +"init" { return TOK_INIT; } +"update" { return TOK_UPDATE; } +"process" { return TOK_PROCESS; } +"end" { return TOK_END; } + +[a-z]+ { return TOK_INVALID; } + +"\\"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } +"$"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } +"."[0-9]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } + +[0-9]+'[01xzm-]* { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; } +-?[0-9]+ { rtlil_frontend_ilang_yylval.integer = atoi(yytext); return TOK_INT; } + +\" { BEGIN(STRING); } +\\. { yymore(); } +\" { + BEGIN(0); + char *yystr = strdup(yytext); + yystr[strlen(yytext) - 1] = 0; + int i = 0, j = 0; + while (yystr[i]) { + if (yystr[i] == '\\' && yystr[i + 1]) { + i++; + if (yystr[i] == 'n') + yystr[i] = '\n'; + else if (yystr[i] == 't') + yystr[i] = '\t'; + else if ('0' <= yystr[i] && yystr[i] <= '7') { + yystr[i] = yystr[i] - '0'; + if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { + yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; + i++; + } + if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { + yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; + i++; + } + } + } + yystr[j++] = yystr[i++]; + } + yystr[j] = 0; + rtlil_frontend_ilang_yylval.string = yystr; + return TOK_STRING; +} +. { yymore(); } + +"#"[^\n]* /* ignore comments */ +[ \t] /* ignore non-newline whitespaces */ +[\r\n]+ { return TOK_EOL; } + +. { return *yytext; } + +%% + +// this is a hack to avoid the 'yyinput defined but not used' error msgs +void *rtlil_frontend_ilang_avoid_input_warnings() { + return (void*)&yyinput; +} + diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y new file mode 100644 index 000000000..a5cc06898 --- /dev/null +++ b/frontends/ilang/ilang_parser.y @@ -0,0 +1,409 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * A very simple and straightforward frontend for the RTLIL text + * representation (as generated by the 'ilang' backend). + * + */ + +%{ +#include +#include "ilang_frontend.h" +YOSYS_NAMESPACE_BEGIN +namespace ILANG_FRONTEND { + std::istream *lexin; + RTLIL::Design *current_design; + RTLIL::Module *current_module; + RTLIL::Wire *current_wire; + RTLIL::Memory *current_memory; + RTLIL::Cell *current_cell; + RTLIL::Process *current_process; + std::vector*> switch_stack; + std::vector case_stack; + std::map attrbuf; +} +using namespace ILANG_FRONTEND; +YOSYS_NAMESPACE_END +USING_YOSYS_NAMESPACE +%} + +%name-prefix "rtlil_frontend_ilang_yy" + +%union { + char *string; + int integer; + YOSYS_NAMESPACE_PREFIX RTLIL::Const *data; + YOSYS_NAMESPACE_PREFIX RTLIL::SigSpec *sigspec; +} + +%token TOK_ID TOK_VALUE TOK_STRING +%token TOK_INT +%token TOK_AUTOIDX TOK_MODULE TOK_WIRE TOK_WIDTH TOK_INPUT TOK_OUTPUT TOK_INOUT +%token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC +%token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_INIT +%token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET +%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED TOK_UPTO + +%type sigspec sigspec_list +%type sync_type +%type constant + +%expect 0 +%debug + +%% + +input: + optional_eol { + attrbuf.clear(); + } design { + if (attrbuf.size() != 0) + rtlil_frontend_ilang_yyerror("dangling attribute"); + }; + +EOL: + optional_eol TOK_EOL; + +optional_eol: + optional_eol TOK_EOL | /* empty */; + +design: + design module | + design attr_stmt | + design autoidx_stmt | + /* empty */; + +module: + TOK_MODULE TOK_ID EOL { + if (current_design->has($2)) + rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str()); + current_module = new RTLIL::Module; + current_module->name = $2; + current_module->attributes = attrbuf; + current_design->add(current_module); + attrbuf.clear(); + free($2); + } module_body TOK_END { + if (attrbuf.size() != 0) + rtlil_frontend_ilang_yyerror("dangling attribute"); + current_module->fixup_ports(); + } EOL; + +module_body: + module_body module_stmt | + /* empty */; + +module_stmt: + attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt; + +attr_stmt: + TOK_ATTRIBUTE TOK_ID constant EOL { + attrbuf[$2] = *$3; + delete $3; + free($2); + }; + +autoidx_stmt: + TOK_AUTOIDX TOK_INT EOL { + autoidx = std::max(autoidx, $2); + }; + +wire_stmt: + TOK_WIRE { + current_wire = current_module->addWire("$__ilang_frontend_tmp__"); + current_wire->attributes = attrbuf; + attrbuf.clear(); + } wire_options TOK_ID EOL { + if (current_module->wires_.count($4) != 0) + rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str()); + current_module->rename(current_wire, $4); + free($4); + }; + +wire_options: + wire_options TOK_WIDTH TOK_INT { + current_wire->width = $3; + } | + wire_options TOK_UPTO { + current_wire->upto = true; + } | + wire_options TOK_OFFSET TOK_INT { + current_wire->start_offset = $3; + } | + wire_options TOK_INPUT TOK_INT { + current_wire->port_id = $3; + current_wire->port_input = true; + current_wire->port_output = false; + } | + wire_options TOK_OUTPUT TOK_INT { + current_wire->port_id = $3; + current_wire->port_input = false; + current_wire->port_output = true; + } | + wire_options TOK_INOUT TOK_INT { + current_wire->port_id = $3; + current_wire->port_input = true; + current_wire->port_output = true; + } | + /* empty */; + +memory_stmt: + TOK_MEMORY { + current_memory = new RTLIL::Memory; + current_memory->attributes = attrbuf; + attrbuf.clear(); + } memory_options TOK_ID EOL { + if (current_module->memories.count($4) != 0) + rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of memory %s.", $4).c_str()); + current_memory->name = $4; + current_module->memories[$4] = current_memory; + free($4); + }; + +memory_options: + memory_options TOK_WIDTH TOK_INT { + current_memory->width = $3; + } | + memory_options TOK_SIZE TOK_INT { + current_memory->size = $3; + } | + /* empty */; + +cell_stmt: + TOK_CELL TOK_ID TOK_ID EOL { + if (current_module->cells_.count($3) != 0) + rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str()); + current_cell = current_module->addCell($3, $2); + current_cell->attributes = attrbuf; + attrbuf.clear(); + free($2); + free($3); + } cell_body TOK_END EOL; + +cell_body: + cell_body TOK_PARAMETER TOK_ID constant EOL { + current_cell->parameters[$3] = *$4; + free($3); + delete $4; + } | + cell_body TOK_PARAMETER TOK_SIGNED TOK_ID constant EOL { + current_cell->parameters[$4] = *$5; + current_cell->parameters[$4].flags |= RTLIL::CONST_FLAG_SIGNED; + free($4); + delete $5; + } | + cell_body TOK_CONNECT TOK_ID sigspec EOL { + if (current_cell->hasPort($3)) + rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str()); + current_cell->setPort($3, *$4); + delete $4; + free($3); + } | + /* empty */; + +proc_stmt: + TOK_PROCESS TOK_ID EOL { + if (current_module->processes.count($2) != 0) + rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of process %s.", $2).c_str()); + current_process = new RTLIL::Process; + current_process->name = $2; + current_process->attributes = attrbuf; + current_module->processes[$2] = current_process; + switch_stack.clear(); + switch_stack.push_back(¤t_process->root_case.switches); + case_stack.clear(); + case_stack.push_back(¤t_process->root_case); + attrbuf.clear(); + free($2); + } case_body sync_list TOK_END EOL; + +switch_stmt: + attr_list TOK_SWITCH sigspec EOL { + RTLIL::SwitchRule *rule = new RTLIL::SwitchRule; + rule->signal = *$3; + rule->attributes = attrbuf; + switch_stack.back()->push_back(rule); + attrbuf.clear(); + delete $3; + } switch_body TOK_END EOL; + +attr_list: + /* empty */ | + attr_list attr_stmt; + +switch_body: + switch_body TOK_CASE { + RTLIL::CaseRule *rule = new RTLIL::CaseRule; + switch_stack.back()->back()->cases.push_back(rule); + switch_stack.push_back(&rule->switches); + case_stack.push_back(rule); + } compare_list EOL case_body { + switch_stack.pop_back(); + case_stack.pop_back(); + } | + /* empty */; + +compare_list: + sigspec { + case_stack.back()->compare.push_back(*$1); + delete $1; + } | + compare_list ',' sigspec { + case_stack.back()->compare.push_back(*$3); + delete $3; + } | + /* empty */; + +case_body: + switch_stmt case_body | + assign_stmt case_body | + /* empty */; + +assign_stmt: + TOK_ASSIGN sigspec sigspec EOL { + case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3)); + delete $2; + delete $3; + }; + +sync_list: + sync_list TOK_SYNC sync_type sigspec EOL { + RTLIL::SyncRule *rule = new RTLIL::SyncRule; + rule->type = RTLIL::SyncType($3); + rule->signal = *$4; + current_process->syncs.push_back(rule); + delete $4; + } update_list | + sync_list TOK_SYNC TOK_ALWAYS EOL { + RTLIL::SyncRule *rule = new RTLIL::SyncRule; + rule->type = RTLIL::SyncType::STa; + rule->signal = RTLIL::SigSpec(); + current_process->syncs.push_back(rule); + } update_list | + sync_list TOK_SYNC TOK_INIT EOL { + RTLIL::SyncRule *rule = new RTLIL::SyncRule; + rule->type = RTLIL::SyncType::STi; + rule->signal = RTLIL::SigSpec(); + current_process->syncs.push_back(rule); + } update_list | + /* empty */; + +sync_type: + TOK_LOW { $$ = RTLIL::ST0; } | + TOK_HIGH { $$ = RTLIL::ST1; } | + TOK_POSEDGE { $$ = RTLIL::STp; } | + TOK_NEGEDGE { $$ = RTLIL::STn; } | + TOK_EDGE { $$ = RTLIL::STe; }; + +update_list: + update_list TOK_UPDATE sigspec sigspec EOL { + current_process->syncs.back()->actions.push_back(RTLIL::SigSig(*$3, *$4)); + delete $3; + delete $4; + } | + /* empty */; + +constant: + TOK_VALUE { + char *ep; + int width = strtol($1, &ep, 10); + std::list bits; + while (*(++ep) != 0) { + RTLIL::State bit = RTLIL::Sx; + switch (*ep) { + case '0': bit = RTLIL::S0; break; + case '1': bit = RTLIL::S1; break; + case 'x': bit = RTLIL::Sx; break; + case 'z': bit = RTLIL::Sz; break; + case '-': bit = RTLIL::Sa; break; + case 'm': bit = RTLIL::Sm; break; + } + bits.push_front(bit); + } + if (bits.size() == 0) + bits.push_back(RTLIL::Sx); + while ((int)bits.size() < width) { + RTLIL::State bit = bits.back(); + if (bit == RTLIL::S1) + bit = RTLIL::S0; + bits.push_back(bit); + } + while ((int)bits.size() > width) + bits.pop_back(); + $$ = new RTLIL::Const; + for (auto it = bits.begin(); it != bits.end(); it++) + $$->bits.push_back(*it); + free($1); + } | + TOK_INT { + $$ = new RTLIL::Const($1, 32); + } | + TOK_STRING { + $$ = new RTLIL::Const($1); + free($1); + }; + +sigspec: + constant { + $$ = new RTLIL::SigSpec(*$1); + delete $1; + } | + TOK_ID { + if (current_module->wires_.count($1) == 0) + rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); + $$ = new RTLIL::SigSpec(current_module->wires_[$1]); + free($1); + } | + TOK_ID '[' TOK_INT ']' { + if (current_module->wires_.count($1) == 0) + rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); + $$ = new RTLIL::SigSpec(current_module->wires_[$1], $3); + free($1); + } | + TOK_ID '[' TOK_INT ':' TOK_INT ']' { + if (current_module->wires_.count($1) == 0) + rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); + $$ = new RTLIL::SigSpec(current_module->wires_[$1], $5, $3 - $5 + 1); + free($1); + } | + '{' sigspec_list '}' { + $$ = $2; + }; + +sigspec_list: + sigspec_list sigspec { + $$ = new RTLIL::SigSpec; + $$->append(*$2); + $$->append(*$1); + delete $1; + delete $2; + } | + /* empty */ { + $$ = new RTLIL::SigSpec; + }; + +conn_stmt: + TOK_CONNECT sigspec sigspec EOL { + if (attrbuf.size() != 0) + rtlil_frontend_ilang_yyerror("dangling attribute"); + current_module->connect(*$2, *$3); + delete $2; + delete $3; + }; + diff --git a/frontends/ilang/lexer.l b/frontends/ilang/lexer.l deleted file mode 100644 index 9669f0924..000000000 --- a/frontends/ilang/lexer.l +++ /dev/null @@ -1,137 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * --- - * - * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). - * - */ - -%{ - -#ifdef __clang__ -// bison generates code using the 'register' storage class specifier -#pragma clang diagnostic ignored "-Wdeprecated-register" -#endif - -#include "ilang_frontend.h" -#include "parser.tab.h" - -USING_YOSYS_NAMESPACE - -#define YY_INPUT(buf,result,max_size) \ - result = readsome(*ILANG_FRONTEND::lexin, buf, max_size); - -%} - -%option yylineno -%option noyywrap -%option nounput -%option prefix="rtlil_frontend_ilang_yy" - -%x STRING - -%% - -"autoidx" { return TOK_AUTOIDX; } -"module" { return TOK_MODULE; } -"attribute" { return TOK_ATTRIBUTE; } -"parameter" { return TOK_PARAMETER; } -"signed" { return TOK_SIGNED; } -"wire" { return TOK_WIRE; } -"memory" { return TOK_MEMORY; } -"width" { return TOK_WIDTH; } -"upto" { return TOK_UPTO; } -"offset" { return TOK_OFFSET; } -"size" { return TOK_SIZE; } -"input" { return TOK_INPUT; } -"output" { return TOK_OUTPUT; } -"inout" { return TOK_INOUT; } -"cell" { return TOK_CELL; } -"connect" { return TOK_CONNECT; } -"switch" { return TOK_SWITCH; } -"case" { return TOK_CASE; } -"assign" { return TOK_ASSIGN; } -"sync" { return TOK_SYNC; } -"low" { return TOK_LOW; } -"high" { return TOK_HIGH; } -"posedge" { return TOK_POSEDGE; } -"negedge" { return TOK_NEGEDGE; } -"edge" { return TOK_EDGE; } -"always" { return TOK_ALWAYS; } -"init" { return TOK_INIT; } -"update" { return TOK_UPDATE; } -"process" { return TOK_PROCESS; } -"end" { return TOK_END; } - -[a-z]+ { return TOK_INVALID; } - -"\\"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } -"$"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } -"."[0-9]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } - -[0-9]+'[01xzm-]* { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; } --?[0-9]+ { rtlil_frontend_ilang_yylval.integer = atoi(yytext); return TOK_INT; } - -\" { BEGIN(STRING); } -\\. { yymore(); } -\" { - BEGIN(0); - char *yystr = strdup(yytext); - yystr[strlen(yytext) - 1] = 0; - int i = 0, j = 0; - while (yystr[i]) { - if (yystr[i] == '\\' && yystr[i + 1]) { - i++; - if (yystr[i] == 'n') - yystr[i] = '\n'; - else if (yystr[i] == 't') - yystr[i] = '\t'; - else if ('0' <= yystr[i] && yystr[i] <= '7') { - yystr[i] = yystr[i] - '0'; - if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { - yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; - i++; - } - if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { - yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; - i++; - } - } - } - yystr[j++] = yystr[i++]; - } - yystr[j] = 0; - rtlil_frontend_ilang_yylval.string = yystr; - return TOK_STRING; -} -. { yymore(); } - -"#"[^\n]* /* ignore comments */ -[ \t] /* ignore non-newline whitespaces */ -[\r\n]+ { return TOK_EOL; } - -. { return *yytext; } - -%% - -// this is a hack to avoid the 'yyinput defined but not used' error msgs -void *rtlil_frontend_ilang_avoid_input_warnings() { - return (void*)&yyinput; -} - diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y deleted file mode 100644 index a5cc06898..000000000 --- a/frontends/ilang/parser.y +++ /dev/null @@ -1,409 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * --- - * - * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). - * - */ - -%{ -#include -#include "ilang_frontend.h" -YOSYS_NAMESPACE_BEGIN -namespace ILANG_FRONTEND { - std::istream *lexin; - RTLIL::Design *current_design; - RTLIL::Module *current_module; - RTLIL::Wire *current_wire; - RTLIL::Memory *current_memory; - RTLIL::Cell *current_cell; - RTLIL::Process *current_process; - std::vector*> switch_stack; - std::vector case_stack; - std::map attrbuf; -} -using namespace ILANG_FRONTEND; -YOSYS_NAMESPACE_END -USING_YOSYS_NAMESPACE -%} - -%name-prefix "rtlil_frontend_ilang_yy" - -%union { - char *string; - int integer; - YOSYS_NAMESPACE_PREFIX RTLIL::Const *data; - YOSYS_NAMESPACE_PREFIX RTLIL::SigSpec *sigspec; -} - -%token TOK_ID TOK_VALUE TOK_STRING -%token TOK_INT -%token TOK_AUTOIDX TOK_MODULE TOK_WIRE TOK_WIDTH TOK_INPUT TOK_OUTPUT TOK_INOUT -%token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC -%token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_INIT -%token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET -%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED TOK_UPTO - -%type sigspec sigspec_list -%type sync_type -%type constant - -%expect 0 -%debug - -%% - -input: - optional_eol { - attrbuf.clear(); - } design { - if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); - }; - -EOL: - optional_eol TOK_EOL; - -optional_eol: - optional_eol TOK_EOL | /* empty */; - -design: - design module | - design attr_stmt | - design autoidx_stmt | - /* empty */; - -module: - TOK_MODULE TOK_ID EOL { - if (current_design->has($2)) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str()); - current_module = new RTLIL::Module; - current_module->name = $2; - current_module->attributes = attrbuf; - current_design->add(current_module); - attrbuf.clear(); - free($2); - } module_body TOK_END { - if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); - current_module->fixup_ports(); - } EOL; - -module_body: - module_body module_stmt | - /* empty */; - -module_stmt: - attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt; - -attr_stmt: - TOK_ATTRIBUTE TOK_ID constant EOL { - attrbuf[$2] = *$3; - delete $3; - free($2); - }; - -autoidx_stmt: - TOK_AUTOIDX TOK_INT EOL { - autoidx = std::max(autoidx, $2); - }; - -wire_stmt: - TOK_WIRE { - current_wire = current_module->addWire("$__ilang_frontend_tmp__"); - current_wire->attributes = attrbuf; - attrbuf.clear(); - } wire_options TOK_ID EOL { - if (current_module->wires_.count($4) != 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str()); - current_module->rename(current_wire, $4); - free($4); - }; - -wire_options: - wire_options TOK_WIDTH TOK_INT { - current_wire->width = $3; - } | - wire_options TOK_UPTO { - current_wire->upto = true; - } | - wire_options TOK_OFFSET TOK_INT { - current_wire->start_offset = $3; - } | - wire_options TOK_INPUT TOK_INT { - current_wire->port_id = $3; - current_wire->port_input = true; - current_wire->port_output = false; - } | - wire_options TOK_OUTPUT TOK_INT { - current_wire->port_id = $3; - current_wire->port_input = false; - current_wire->port_output = true; - } | - wire_options TOK_INOUT TOK_INT { - current_wire->port_id = $3; - current_wire->port_input = true; - current_wire->port_output = true; - } | - /* empty */; - -memory_stmt: - TOK_MEMORY { - current_memory = new RTLIL::Memory; - current_memory->attributes = attrbuf; - attrbuf.clear(); - } memory_options TOK_ID EOL { - if (current_module->memories.count($4) != 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of memory %s.", $4).c_str()); - current_memory->name = $4; - current_module->memories[$4] = current_memory; - free($4); - }; - -memory_options: - memory_options TOK_WIDTH TOK_INT { - current_memory->width = $3; - } | - memory_options TOK_SIZE TOK_INT { - current_memory->size = $3; - } | - /* empty */; - -cell_stmt: - TOK_CELL TOK_ID TOK_ID EOL { - if (current_module->cells_.count($3) != 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str()); - current_cell = current_module->addCell($3, $2); - current_cell->attributes = attrbuf; - attrbuf.clear(); - free($2); - free($3); - } cell_body TOK_END EOL; - -cell_body: - cell_body TOK_PARAMETER TOK_ID constant EOL { - current_cell->parameters[$3] = *$4; - free($3); - delete $4; - } | - cell_body TOK_PARAMETER TOK_SIGNED TOK_ID constant EOL { - current_cell->parameters[$4] = *$5; - current_cell->parameters[$4].flags |= RTLIL::CONST_FLAG_SIGNED; - free($4); - delete $5; - } | - cell_body TOK_CONNECT TOK_ID sigspec EOL { - if (current_cell->hasPort($3)) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str()); - current_cell->setPort($3, *$4); - delete $4; - free($3); - } | - /* empty */; - -proc_stmt: - TOK_PROCESS TOK_ID EOL { - if (current_module->processes.count($2) != 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of process %s.", $2).c_str()); - current_process = new RTLIL::Process; - current_process->name = $2; - current_process->attributes = attrbuf; - current_module->processes[$2] = current_process; - switch_stack.clear(); - switch_stack.push_back(¤t_process->root_case.switches); - case_stack.clear(); - case_stack.push_back(¤t_process->root_case); - attrbuf.clear(); - free($2); - } case_body sync_list TOK_END EOL; - -switch_stmt: - attr_list TOK_SWITCH sigspec EOL { - RTLIL::SwitchRule *rule = new RTLIL::SwitchRule; - rule->signal = *$3; - rule->attributes = attrbuf; - switch_stack.back()->push_back(rule); - attrbuf.clear(); - delete $3; - } switch_body TOK_END EOL; - -attr_list: - /* empty */ | - attr_list attr_stmt; - -switch_body: - switch_body TOK_CASE { - RTLIL::CaseRule *rule = new RTLIL::CaseRule; - switch_stack.back()->back()->cases.push_back(rule); - switch_stack.push_back(&rule->switches); - case_stack.push_back(rule); - } compare_list EOL case_body { - switch_stack.pop_back(); - case_stack.pop_back(); - } | - /* empty */; - -compare_list: - sigspec { - case_stack.back()->compare.push_back(*$1); - delete $1; - } | - compare_list ',' sigspec { - case_stack.back()->compare.push_back(*$3); - delete $3; - } | - /* empty */; - -case_body: - switch_stmt case_body | - assign_stmt case_body | - /* empty */; - -assign_stmt: - TOK_ASSIGN sigspec sigspec EOL { - case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3)); - delete $2; - delete $3; - }; - -sync_list: - sync_list TOK_SYNC sync_type sigspec EOL { - RTLIL::SyncRule *rule = new RTLIL::SyncRule; - rule->type = RTLIL::SyncType($3); - rule->signal = *$4; - current_process->syncs.push_back(rule); - delete $4; - } update_list | - sync_list TOK_SYNC TOK_ALWAYS EOL { - RTLIL::SyncRule *rule = new RTLIL::SyncRule; - rule->type = RTLIL::SyncType::STa; - rule->signal = RTLIL::SigSpec(); - current_process->syncs.push_back(rule); - } update_list | - sync_list TOK_SYNC TOK_INIT EOL { - RTLIL::SyncRule *rule = new RTLIL::SyncRule; - rule->type = RTLIL::SyncType::STi; - rule->signal = RTLIL::SigSpec(); - current_process->syncs.push_back(rule); - } update_list | - /* empty */; - -sync_type: - TOK_LOW { $$ = RTLIL::ST0; } | - TOK_HIGH { $$ = RTLIL::ST1; } | - TOK_POSEDGE { $$ = RTLIL::STp; } | - TOK_NEGEDGE { $$ = RTLIL::STn; } | - TOK_EDGE { $$ = RTLIL::STe; }; - -update_list: - update_list TOK_UPDATE sigspec sigspec EOL { - current_process->syncs.back()->actions.push_back(RTLIL::SigSig(*$3, *$4)); - delete $3; - delete $4; - } | - /* empty */; - -constant: - TOK_VALUE { - char *ep; - int width = strtol($1, &ep, 10); - std::list bits; - while (*(++ep) != 0) { - RTLIL::State bit = RTLIL::Sx; - switch (*ep) { - case '0': bit = RTLIL::S0; break; - case '1': bit = RTLIL::S1; break; - case 'x': bit = RTLIL::Sx; break; - case 'z': bit = RTLIL::Sz; break; - case '-': bit = RTLIL::Sa; break; - case 'm': bit = RTLIL::Sm; break; - } - bits.push_front(bit); - } - if (bits.size() == 0) - bits.push_back(RTLIL::Sx); - while ((int)bits.size() < width) { - RTLIL::State bit = bits.back(); - if (bit == RTLIL::S1) - bit = RTLIL::S0; - bits.push_back(bit); - } - while ((int)bits.size() > width) - bits.pop_back(); - $$ = new RTLIL::Const; - for (auto it = bits.begin(); it != bits.end(); it++) - $$->bits.push_back(*it); - free($1); - } | - TOK_INT { - $$ = new RTLIL::Const($1, 32); - } | - TOK_STRING { - $$ = new RTLIL::Const($1); - free($1); - }; - -sigspec: - constant { - $$ = new RTLIL::SigSpec(*$1); - delete $1; - } | - TOK_ID { - if (current_module->wires_.count($1) == 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); - $$ = new RTLIL::SigSpec(current_module->wires_[$1]); - free($1); - } | - TOK_ID '[' TOK_INT ']' { - if (current_module->wires_.count($1) == 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); - $$ = new RTLIL::SigSpec(current_module->wires_[$1], $3); - free($1); - } | - TOK_ID '[' TOK_INT ':' TOK_INT ']' { - if (current_module->wires_.count($1) == 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); - $$ = new RTLIL::SigSpec(current_module->wires_[$1], $5, $3 - $5 + 1); - free($1); - } | - '{' sigspec_list '}' { - $$ = $2; - }; - -sigspec_list: - sigspec_list sigspec { - $$ = new RTLIL::SigSpec; - $$->append(*$2); - $$->append(*$1); - delete $1; - delete $2; - } | - /* empty */ { - $$ = new RTLIL::SigSpec; - }; - -conn_stmt: - TOK_CONNECT sigspec sigspec EOL { - if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); - current_module->connect(*$2, *$3); - delete $2; - delete $3; - }; - diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc index 49eb320ec..1b6854bb5 100644 --- a/frontends/verilog/Makefile.inc +++ b/frontends/verilog/Makefile.inc @@ -1,20 +1,20 @@ -GENFILES += frontends/verilog/parser.tab.cc -GENFILES += frontends/verilog/parser.tab.h -GENFILES += frontends/verilog/parser.output -GENFILES += frontends/verilog/lexer.cc +GENFILES += frontends/verilog/verilog_parser.tab.cc +GENFILES += frontends/verilog/verilog_parser.tab.h +GENFILES += frontends/verilog/verilog_parser.output +GENFILES += frontends/verilog/verilog_lexer.cc -frontends/verilog/parser.tab.cc: frontends/verilog/parser.y - $(P) bison -d -r all -b frontends/verilog/parser frontends/verilog/parser.y - $(Q) mv frontends/verilog/parser.tab.c frontends/verilog/parser.tab.cc +frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y + $(P) bison -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y + $(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc -frontends/verilog/parser.tab.h: frontends/verilog/parser.tab.cc +frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc -frontends/verilog/lexer.cc: frontends/verilog/lexer.l - $(P) flex -o frontends/verilog/lexer.cc frontends/verilog/lexer.l +frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l + $(P) flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l -OBJS += frontends/verilog/parser.tab.o -OBJS += frontends/verilog/lexer.o +OBJS += frontends/verilog/verilog_parser.tab.o +OBJS += frontends/verilog/verilog_lexer.o OBJS += frontends/verilog/preproc.o OBJS += frontends/verilog/verilog_frontend.o OBJS += frontends/verilog/const2ast.o diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l deleted file mode 100644 index 98f360885..000000000 --- a/frontends/verilog/lexer.l +++ /dev/null @@ -1,355 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * --- - * - * The Verilog frontend. - * - * This frontend is using the AST frontend library (see frontends/ast/). - * Thus this frontend does not generate RTLIL code directly but creates an - * AST directly from the Verilog parse tree and then passes this AST to - * the AST frontend library. - * - * --- - * - * A simple lexer for Verilog code. Non-preprocessor compiler directives are - * handled here. The preprocessor stuff is handled in preproc.cc. Everything - * else is left to the bison parser (see parser.y). - * - */ - -%{ - -#ifdef __clang__ -// bison generates code using the 'register' storage class specifier -#pragma clang diagnostic ignored "-Wdeprecated-register" -#endif - -#include "kernel/log.h" -#include "verilog_frontend.h" -#include "frontends/ast/ast.h" -#include "parser.tab.h" - -USING_YOSYS_NAMESPACE -using namespace AST; -using namespace VERILOG_FRONTEND; - -YOSYS_NAMESPACE_BEGIN -namespace VERILOG_FRONTEND { - std::vector fn_stack; - std::vector ln_stack; -} -YOSYS_NAMESPACE_END - -#define SV_KEYWORD(_tok) \ - if (sv_mode) return _tok; \ - log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\ - "recognized unless read_verilog is called with -sv!\n", yytext, \ - AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \ - frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \ - return TOK_ID; - -#define YY_INPUT(buf,result,max_size) \ - result = readsome(*lexin, buf, max_size); - -%} - -%option yylineno -%option noyywrap -%option nounput -%option prefix="frontend_verilog_yy" - -%x COMMENT -%x STRING -%x SYNOPSYS_TRANSLATE_OFF -%x SYNOPSYS_FLAGS -%x IMPORT_DPI - -%% - -"`file_push "[^\n]* { - fn_stack.push_back(current_filename); - ln_stack.push_back(frontend_verilog_yyget_lineno()); - current_filename = yytext+11; - frontend_verilog_yyset_lineno(0); -} - -"`file_pop"[^\n]*\n { - current_filename = fn_stack.back(); - fn_stack.pop_back(); - frontend_verilog_yyset_lineno(ln_stack.back()); - ln_stack.pop_back(); -} - -"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n { - char *p = yytext + 5; - while (*p == ' ' || *p == '\t') p++; - frontend_verilog_yyset_lineno(atoi(p)); - while (*p && *p != ' ' && *p != '\t') p++; - while (*p == ' ' || *p == '\t') p++; - char *q = *p ? p + 1 : p; - while (*q && *q != '"') q++; - current_filename = std::string(p).substr(1, q-p-1); -} - -"`file_notfound "[^\n]* { - log_error("Can't open include file `%s'!\n", yytext + 15); -} - -"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */ - -"`default_nettype"[ \t]+[^ \t\r\n/]+ { - char *p = yytext; - while (*p != 0 && *p != ' ' && *p != '\t') p++; - while (*p == ' ' || *p == '\t') p++; - if (!strcmp(p, "none")) - VERILOG_FRONTEND::default_nettype_wire = false; - else if (!strcmp(p, "wire")) - VERILOG_FRONTEND::default_nettype_wire = true; - else - frontend_verilog_yyerror("Unsupported default nettype: %s", p); -} - -"`"[a-zA-Z_$][a-zA-Z0-9_$]* { - frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext); -} - -"module" { return TOK_MODULE; } -"endmodule" { return TOK_ENDMODULE; } -"function" { return TOK_FUNCTION; } -"endfunction" { return TOK_ENDFUNCTION; } -"task" { return TOK_TASK; } -"endtask" { return TOK_ENDTASK; } -"parameter" { return TOK_PARAMETER; } -"localparam" { return TOK_LOCALPARAM; } -"defparam" { return TOK_DEFPARAM; } -"assign" { return TOK_ASSIGN; } -"always" { return TOK_ALWAYS; } -"initial" { return TOK_INITIAL; } -"begin" { return TOK_BEGIN; } -"end" { return TOK_END; } -"if" { return TOK_IF; } -"else" { return TOK_ELSE; } -"for" { return TOK_FOR; } -"posedge" { return TOK_POSEDGE; } -"negedge" { return TOK_NEGEDGE; } -"or" { return TOK_OR; } -"case" { return TOK_CASE; } -"casex" { return TOK_CASEX; } -"casez" { return TOK_CASEZ; } -"endcase" { return TOK_ENDCASE; } -"default" { return TOK_DEFAULT; } -"generate" { return TOK_GENERATE; } -"endgenerate" { return TOK_ENDGENERATE; } -"while" { return TOK_WHILE; } -"repeat" { return TOK_REPEAT; } - -"always_comb" { SV_KEYWORD(TOK_ALWAYS); } -"always_ff" { SV_KEYWORD(TOK_ALWAYS); } -"always_latch" { SV_KEYWORD(TOK_ALWAYS); } - -"assert" { SV_KEYWORD(TOK_ASSERT); } -"property" { SV_KEYWORD(TOK_PROPERTY); } -"logic" { SV_KEYWORD(TOK_REG); } -"bit" { SV_KEYWORD(TOK_REG); } - -"input" { return TOK_INPUT; } -"output" { return TOK_OUTPUT; } -"inout" { return TOK_INOUT; } -"wire" { return TOK_WIRE; } -"reg" { return TOK_REG; } -"integer" { return TOK_INTEGER; } -"signed" { return TOK_SIGNED; } -"genvar" { return TOK_GENVAR; } -"real" { return TOK_REAL; } - -[0-9]+ { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_CONST; -} - -[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_CONST; -} - -[0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_REALVAL; -} - -[0-9][0-9_]*[eE][-+]?[0-9_]+ { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_REALVAL; -} - -\" { BEGIN(STRING); } -\\. { yymore(); } -\" { - BEGIN(0); - char *yystr = strdup(yytext); - yystr[strlen(yytext) - 1] = 0; - int i = 0, j = 0; - while (yystr[i]) { - if (yystr[i] == '\\' && yystr[i + 1]) { - i++; - if (yystr[i] == 'n') - yystr[i] = '\n'; - else if (yystr[i] == 't') - yystr[i] = '\t'; - else if ('0' <= yystr[i] && yystr[i] <= '7') { - yystr[i] = yystr[i] - '0'; - if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { - yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; - i++; - } - if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { - yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; - i++; - } - } - } - yystr[j++] = yystr[i++]; - } - yystr[j] = 0; - frontend_verilog_yylval.string = new std::string(yystr); - free(yystr); - return TOK_STRING; -} -. { yymore(); } - -and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_PRIMITIVE; -} - -supply0 { return TOK_SUPPLY0; } -supply1 { return TOK_SUPPLY1; } - -"$"(display|time|stop|finish) { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_ID; -} - -"$signed" { return TOK_TO_SIGNED; } -"$unsigned" { return TOK_TO_UNSIGNED; } - -[a-zA-Z_$][a-zA-Z0-9_$]* { - frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); - return TOK_ID; -} - -"/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" { - log("Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"); - log("It is strongly suggested to use `ifdef constructs instead!\n"); - BEGIN(SYNOPSYS_TRANSLATE_OFF); -} -. /* ignore synopsys translate_off body */ -\n /* ignore synopsys translate_off body */ -"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); } - -"/*"[ \t]*(synopsys|synthesis)[ \t]+ { - BEGIN(SYNOPSYS_FLAGS); -} -full_case { - log("Warning: Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"); - log("It is strongly suggested to use verilog x-values and default branches instead!\n"); - return TOK_SYNOPSYS_FULL_CASE; -} -parallel_case { - log("Warning: Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"); - log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n"); - return TOK_SYNOPSYS_PARALLEL_CASE; -} -. /* ignore everything else */ -"*/" { BEGIN(0); } - -import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { - BEGIN(IMPORT_DPI); - return TOK_DPI_FUNCTION; -} - -[a-zA-Z_$][a-zA-Z0-9_$]* { - frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); - return TOK_ID; -} - -[ \t\r\n] /* ignore whitespaces */ - -";" { - BEGIN(0); - return *yytext; -} - -. { - return *yytext; -} - -"\\"[^ \t\r\n]+ { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_ID; -} - -"(*" { return ATTR_BEGIN; } -"*)" { return ATTR_END; } - -"{*" { return DEFATTR_BEGIN; } -"*}" { return DEFATTR_END; } - -"**" { return OP_POW; } -"||" { return OP_LOR; } -"&&" { return OP_LAND; } -"==" { return OP_EQ; } -"!=" { return OP_NE; } -"<=" { return OP_LE; } -">=" { return OP_GE; } - -"===" { return OP_EQX; } -"!==" { return OP_NEX; } - -"~&" { return OP_NAND; } -"~|" { return OP_NOR; } -"~^" { return OP_XNOR; } -"^~" { return OP_XNOR; } - -"<<" { return OP_SHL; } -">>" { return OP_SHR; } -"<<<" { return OP_SSHL; } -">>>" { return OP_SSHR; } - -"+:" { return TOK_POS_INDEXED; } -"-:" { return TOK_NEG_INDEXED; } - -"/*" { BEGIN(COMMENT); } -. /* ignore comment body */ -\n /* ignore comment body */ -"*/" { BEGIN(0); } - -[ \t\r\n] /* ignore whitespaces */ -\\[\r\n] /* ignore continuation sequence */ -"//"[^\r\n]* /* ignore one-line comments */ -"#"[$a-zA-Z_0-9\.]+ /* ignore simulation timings */ - -. { return *yytext; } - -%% - -// this is a hack to avoid the 'yyinput defined but not used' error msgs -void *frontend_verilog_avoid_input_warnings() { - return (void*)&yyinput; -} - diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y deleted file mode 100644 index cf02a56a9..000000000 --- a/frontends/verilog/parser.y +++ /dev/null @@ -1,1434 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * --- - * - * The Verilog frontend. - * - * This frontend is using the AST frontend library (see frontends/ast/). - * Thus this frontend does not generate RTLIL code directly but creates an - * AST directly from the Verilog parse tree and then passes this AST to - * the AST frontend library. - * - * --- - * - * This is the actual bison parser for Verilog code. The AST ist created directly - * from the bison reduce functions here. Note that this code uses a few global - * variables to hold the state of the AST generator and therefore this parser is - * not reentrant. - * - */ - -%{ -#include -#include -#include "verilog_frontend.h" -#include "kernel/log.h" - -USING_YOSYS_NAMESPACE -using namespace AST; -using namespace VERILOG_FRONTEND; - -YOSYS_NAMESPACE_BEGIN -namespace VERILOG_FRONTEND { - int port_counter; - std::map port_stubs; - std::map attr_list, default_attr_list; - std::map *albuf; - std::vector ast_stack; - struct AstNode *astbuf1, *astbuf2, *astbuf3; - struct AstNode *current_function_or_task; - struct AstNode *current_ast, *current_ast_mod; - int current_function_or_task_port_id; - std::vector case_type_stack; - bool do_not_require_port_stubs; - bool default_nettype_wire; - bool sv_mode; - std::istream *lexin; -} -YOSYS_NAMESPACE_END - -static void append_attr(AstNode *ast, std::map *al) -{ - for (auto &it : *al) { - if (ast->attributes.count(it.first) > 0) - delete ast->attributes[it.first]; - ast->attributes[it.first] = it.second; - } - delete al; -} - -static void append_attr_clone(AstNode *ast, std::map *al) -{ - for (auto &it : *al) { - if (ast->attributes.count(it.first) > 0) - delete ast->attributes[it.first]; - ast->attributes[it.first] = it.second->clone(); - } -} - -static void free_attr(std::map *al) -{ - for (auto &it : *al) - delete it.second; - delete al; -} - -%} - -%name-prefix "frontend_verilog_yy" - -%union { - std::string *string; - struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast; - std::map *al; - bool boolean; -} - -%token TOK_STRING TOK_ID TOK_CONST TOK_REALVAL TOK_PRIMITIVE -%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END -%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM -%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG -%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL -%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT -%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR -%token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT -%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK -%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL -%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE -%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED -%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_PROPERTY - -%type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int -%type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list -%type opt_label tok_prim_wrapper hierarchical_id -%type opt_signed -%type attr - -// operator precedence from low to high -%left OP_LOR -%left OP_LAND -%left '|' OP_NOR -%left '^' OP_XNOR -%left '&' OP_NAND -%left OP_EQ OP_NE OP_EQX OP_NEX -%left '<' OP_LE OP_GE '>' -%left OP_SHL OP_SHR OP_SSHL OP_SSHR -%left '+' '-' -%left '*' '/' '%' -%left OP_POW -%right UNARY_OPS - -%expect 2 -%debug - -%% - -input: { - ast_stack.push_back(current_ast); -} design { - ast_stack.pop_back(); - log_assert(GetSize(ast_stack) == 0); - for (auto &it : default_attr_list) - delete it.second; - default_attr_list.clear(); -}; - -design: - module design | - defattr design | - task_func_decl design | - /* empty */; - -attr: - { - for (auto &it : attr_list) - delete it.second; - attr_list.clear(); - for (auto &it : default_attr_list) - attr_list[it.first] = it.second->clone(); - } attr_opt { - std::map *al = new std::map; - al->swap(attr_list); - $$ = al; - }; - -attr_opt: - attr_opt ATTR_BEGIN opt_attr_list ATTR_END | - /* empty */; - -defattr: - DEFATTR_BEGIN { - for (auto &it : default_attr_list) - delete it.second; - default_attr_list.clear(); - for (auto &it : attr_list) - delete it.second; - attr_list.clear(); - } opt_attr_list { - default_attr_list = attr_list; - attr_list.clear(); - } DEFATTR_END; - -opt_attr_list: - attr_list | /* empty */; - -attr_list: - attr_assign | - attr_list ',' attr_assign; - -attr_assign: - hierarchical_id { - if (attr_list.count(*$1) != 0) - delete attr_list[*$1]; - attr_list[*$1] = AstNode::mkconst_int(1, false); - delete $1; - } | - hierarchical_id '=' expr { - if (attr_list.count(*$1) != 0) - delete attr_list[*$1]; - attr_list[*$1] = $3; - delete $1; - }; - -hierarchical_id: - TOK_ID { - $$ = $1; - } | - hierarchical_id '.' TOK_ID { - if ($3->substr(0, 1) == "\\") - *$1 += "." + $3->substr(1); - else - *$1 += "." + *$3; - delete $3; - $$ = $1; - }; - -module: - attr TOK_MODULE TOK_ID { - do_not_require_port_stubs = false; - AstNode *mod = new AstNode(AST_MODULE); - ast_stack.back()->children.push_back(mod); - ast_stack.push_back(mod); - current_ast_mod = mod; - port_stubs.clear(); - port_counter = 0; - mod->str = *$3; - append_attr(mod, $1); - delete $3; - } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE { - if (port_stubs.size() != 0) - frontend_verilog_yyerror("Missing details for module port `%s'.", - port_stubs.begin()->first.c_str()); - ast_stack.pop_back(); - log_assert(ast_stack.size() == 1); - current_ast_mod = NULL; - }; - -module_para_opt: - '#' '(' module_para_list ')' | /* empty */; - -module_para_list: - single_module_para | - single_module_para ',' module_para_list | - /* empty */; - -single_module_para: - TOK_PARAMETER { - astbuf1 = new AstNode(AST_PARAMETER); - astbuf1->children.push_back(AstNode::mkconst_int(0, true)); - } param_signed param_integer param_range single_param_decl { - delete astbuf1; - }; - -module_args_opt: - '(' ')' | /* empty */ | '(' module_args optional_comma ')'; - -module_args: - module_arg | module_args ',' module_arg; - -optional_comma: - ',' | /* empty */; - -module_arg_opt_assignment: - '=' expr { - if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { - AstNode *wire = new AstNode(AST_IDENTIFIER); - wire->str = ast_stack.back()->children.back()->str; - if (ast_stack.back()->children.back()->is_reg) - ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2)))); - else - ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); - } else - frontend_verilog_yyerror("Syntax error."); - } | - /* empty */; - -module_arg: - TOK_ID { - if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { - AstNode *node = ast_stack.back()->children.back()->clone(); - node->str = *$1; - node->port_id = ++port_counter; - ast_stack.back()->children.push_back(node); - } else { - if (port_stubs.count(*$1) != 0) - frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str()); - port_stubs[*$1] = ++port_counter; - } - delete $1; - } module_arg_opt_assignment | - attr wire_type range TOK_ID { - AstNode *node = $2; - node->str = *$4; - node->port_id = ++port_counter; - if ($3 != NULL) - node->children.push_back($3); - if (!node->is_input && !node->is_output) - frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str()); - if (node->is_reg && node->is_input && !node->is_output) - frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str()); - ast_stack.back()->children.push_back(node); - append_attr(node, $1); - delete $4; - } module_arg_opt_assignment | - '.' '.' '.' { - do_not_require_port_stubs = true; - }; - -wire_type: - { - astbuf3 = new AstNode(AST_WIRE); - } wire_type_token_list { - $$ = astbuf3; - }; - -wire_type_token_list: - wire_type_token | wire_type_token_list wire_type_token; - -wire_type_token: - TOK_INPUT { - astbuf3->is_input = true; - } | - TOK_OUTPUT { - astbuf3->is_output = true; - } | - TOK_INOUT { - astbuf3->is_input = true; - astbuf3->is_output = true; - } | - TOK_WIRE { - } | - TOK_REG { - astbuf3->is_reg = true; - } | - TOK_INTEGER { - astbuf3->is_reg = true; - astbuf3->range_left = 31; - astbuf3->range_right = 0; - astbuf3->is_signed = true; - } | - TOK_GENVAR { - astbuf3->type = AST_GENVAR; - astbuf3->is_reg = true; - astbuf3->range_left = 31; - astbuf3->range_right = 0; - } | - TOK_SIGNED { - astbuf3->is_signed = true; - }; - -non_opt_range: - '[' expr ':' expr ']' { - $$ = new AstNode(AST_RANGE); - $$->children.push_back($2); - $$->children.push_back($4); - } | - '[' expr TOK_POS_INDEXED expr ']' { - $$ = new AstNode(AST_RANGE); - $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true))); - $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true))); - } | - '[' expr TOK_NEG_INDEXED expr ']' { - $$ = new AstNode(AST_RANGE); - $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true))); - $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4)); - } | - '[' expr ']' { - $$ = new AstNode(AST_RANGE); - $$->children.push_back($2); - }; - -non_opt_multirange: - non_opt_range non_opt_range { - $$ = new AstNode(AST_MULTIRANGE, $1, $2); - } | - non_opt_multirange non_opt_range { - $$ = $1; - $$->children.push_back($2); - }; - -range: - non_opt_range { - $$ = $1; - } | - /* empty */ { - $$ = NULL; - }; - -range_or_multirange: - range { $$ = $1; } | - non_opt_multirange { $$ = $1; }; - -range_or_signed_int: - range { - $$ = $1; - } | - TOK_INTEGER { - $$ = new AstNode(AST_RANGE); - $$->children.push_back(AstNode::mkconst_int(31, true)); - $$->children.push_back(AstNode::mkconst_int(0, true)); - $$->is_signed = true; - }; - -module_body: - module_body module_body_stmt | - /* the following line makes the generate..endgenrate keywords optional */ - module_body gen_stmt | - /* empty */; - -module_body_stmt: - task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt | - always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property; - -task_func_decl: - attr TOK_DPI_FUNCTION TOK_ID TOK_ID { - current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4)); - current_function_or_task->str = *$4; - append_attr(current_function_or_task, $1); - ast_stack.back()->children.push_back(current_function_or_task); - delete $3; - delete $4; - } opt_dpi_function_args ';' { - current_function_or_task = NULL; - } | - attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID { - current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3)); - current_function_or_task->str = *$6; - append_attr(current_function_or_task, $1); - ast_stack.back()->children.push_back(current_function_or_task); - delete $3; - delete $5; - delete $6; - } opt_dpi_function_args ';' { - current_function_or_task = NULL; - } | - attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID { - current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5))); - current_function_or_task->str = *$8; - append_attr(current_function_or_task, $1); - ast_stack.back()->children.push_back(current_function_or_task); - delete $3; - delete $5; - delete $7; - delete $8; - } opt_dpi_function_args ';' { - current_function_or_task = NULL; - } | - attr TOK_TASK TOK_ID ';' { - current_function_or_task = new AstNode(AST_TASK); - current_function_or_task->str = *$3; - append_attr(current_function_or_task, $1); - ast_stack.back()->children.push_back(current_function_or_task); - ast_stack.push_back(current_function_or_task); - current_function_or_task_port_id = 1; - delete $3; - } task_func_body TOK_ENDTASK { - current_function_or_task = NULL; - ast_stack.pop_back(); - } | - attr TOK_FUNCTION opt_signed range_or_signed_int TOK_ID ';' { - current_function_or_task = new AstNode(AST_FUNCTION); - current_function_or_task->str = *$5; - append_attr(current_function_or_task, $1); - ast_stack.back()->children.push_back(current_function_or_task); - ast_stack.push_back(current_function_or_task); - AstNode *outreg = new AstNode(AST_WIRE); - outreg->str = *$5; - outreg->is_signed = $3; - if ($4 != NULL) { - outreg->children.push_back($4); - outreg->is_signed = $3 || $4->is_signed; - $4->is_signed = false; - } - current_function_or_task->children.push_back(outreg); - current_function_or_task_port_id = 1; - delete $5; - } task_func_body TOK_ENDFUNCTION { - current_function_or_task = NULL; - ast_stack.pop_back(); - }; - -dpi_function_arg: - TOK_ID TOK_ID { - current_function_or_task->children.push_back(AstNode::mkconst_str(*$1)); - delete $1; - delete $2; - } | - TOK_ID { - current_function_or_task->children.push_back(AstNode::mkconst_str(*$1)); - delete $1; - }; - -opt_dpi_function_args: - '(' dpi_function_args ')' | - /* empty */; - -dpi_function_args: - dpi_function_args ',' dpi_function_arg | - dpi_function_args ',' | - dpi_function_arg | - /* empty */; - -opt_signed: - TOK_SIGNED { - $$ = true; - } | - /* empty */ { - $$ = false; - }; - -task_func_body: - task_func_body behavioral_stmt | - /* empty */; - -param_signed: - TOK_SIGNED { - astbuf1->is_signed = true; - } | /* empty */; - -param_integer: - TOK_INTEGER { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Syntax error."); - astbuf1->children.push_back(new AstNode(AST_RANGE)); - astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true)); - astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true)); - astbuf1->is_signed = true; - } | /* empty */; - -param_real: - TOK_REAL { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Syntax error."); - astbuf1->children.push_back(new AstNode(AST_REALVALUE)); - } | /* empty */; - -param_range: - range { - if ($1 != NULL) { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Syntax error."); - astbuf1->children.push_back($1); - } - }; - -param_decl: - TOK_PARAMETER { - astbuf1 = new AstNode(AST_PARAMETER); - astbuf1->children.push_back(AstNode::mkconst_int(0, true)); - } param_signed param_integer param_real param_range param_decl_list ';' { - delete astbuf1; - }; - -localparam_decl: - TOK_LOCALPARAM { - astbuf1 = new AstNode(AST_LOCALPARAM); - astbuf1->children.push_back(AstNode::mkconst_int(0, true)); - } param_signed param_integer param_real param_range param_decl_list ';' { - delete astbuf1; - }; - -param_decl_list: - single_param_decl | param_decl_list ',' single_param_decl; - -single_param_decl: - TOK_ID '=' expr { - AstNode *node = astbuf1->clone(); - node->str = *$1; - delete node->children[0]; - node->children[0] = $3; - ast_stack.back()->children.push_back(node); - delete $1; - }; - -defparam_decl: - TOK_DEFPARAM defparam_decl_list ';'; - -defparam_decl_list: - single_defparam_decl | defparam_decl_list ',' single_defparam_decl; - -single_defparam_decl: - range hierarchical_id '=' expr { - AstNode *node = new AstNode(AST_DEFPARAM); - node->str = *$2; - node->children.push_back($4); - if ($1 != NULL) - node->children.push_back($1); - ast_stack.back()->children.push_back(node); - delete $2; - }; - -wire_decl: - attr wire_type range { - albuf = $1; - astbuf1 = $2; - astbuf2 = $3; - if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { - if (astbuf2) { - frontend_verilog_yyerror("Syntax error."); - } else { - astbuf2 = new AstNode(AST_RANGE); - astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true)); - astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true)); - } - } - if (astbuf2 && astbuf2->children.size() != 2) - frontend_verilog_yyerror("Syntax error."); - } wire_name_list ';' { - delete astbuf1; - if (astbuf2 != NULL) - delete astbuf2; - free_attr(albuf); - } | - attr TOK_SUPPLY0 TOK_ID ';' { - ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); - ast_stack.back()->children.back()->str = *$3; - append_attr(ast_stack.back()->children.back(), $1); - ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1))); - ast_stack.back()->children.back()->children[0]->str = *$3; - delete $3; - } | - attr TOK_SUPPLY1 TOK_ID ';' { - ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); - ast_stack.back()->children.back()->str = *$3; - append_attr(ast_stack.back()->children.back(), $1); - ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1))); - ast_stack.back()->children.back()->children[0]->str = *$3; - delete $3; - }; - -wire_name_list: - wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign; - -wire_name_and_opt_assign: - wire_name | - wire_name '=' expr { - AstNode *wire = new AstNode(AST_IDENTIFIER); - wire->str = ast_stack.back()->children.back()->str; - if (astbuf1->is_reg) - ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3)))); - else - ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3)); - }; - -wire_name: - TOK_ID range_or_multirange { - AstNode *node = astbuf1->clone(); - node->str = *$1; - append_attr_clone(node, albuf); - if (astbuf2 != NULL) - node->children.push_back(astbuf2->clone()); - if ($2 != NULL) { - if (node->is_input || node->is_output) - frontend_verilog_yyerror("Syntax error."); - if (!astbuf2) { - AstNode *rng = new AstNode(AST_RANGE); - rng->children.push_back(AstNode::mkconst_int(0, true)); - rng->children.push_back(AstNode::mkconst_int(0, true)); - node->children.push_back(rng); - } - node->type = AST_MEMORY; - node->children.push_back($2); - } - if (current_function_or_task == NULL) { - if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { - port_stubs[*$1] = ++port_counter; - } - if (port_stubs.count(*$1) != 0) { - if (!node->is_input && !node->is_output) - frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str()); - if (node->is_reg && node->is_input && !node->is_output) - frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str()); - node->port_id = port_stubs[*$1]; - port_stubs.erase(*$1); - } else { - if (node->is_input || node->is_output) - frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str()); - } - } else { - if (node->is_input || node->is_output) - node->port_id = current_function_or_task_port_id++; - } - ast_stack.back()->children.push_back(node); - delete $1; - }; - -assign_stmt: - TOK_ASSIGN assign_expr_list ';'; - -assign_expr_list: - assign_expr | assign_expr_list ',' assign_expr; - -assign_expr: - expr '=' expr { - ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3)); - }; - -cell_stmt: - attr TOK_ID { - astbuf1 = new AstNode(AST_CELL); - append_attr(astbuf1, $1); - astbuf1->children.push_back(new AstNode(AST_CELLTYPE)); - astbuf1->children[0]->str = *$2; - delete $2; - } cell_parameter_list_opt cell_list ';' { - delete astbuf1; - } | - attr tok_prim_wrapper { - astbuf1 = new AstNode(AST_PRIMITIVE); - astbuf1->str = *$2; - append_attr(astbuf1, $1); - delete $2; - } prim_list ';' { - delete astbuf1; - }; - -tok_prim_wrapper: - TOK_PRIMITIVE { - $$ = $1; - } | - TOK_OR { - $$ = new std::string("or"); - }; - -cell_list: - single_cell | - cell_list ',' single_cell; - -single_cell: - TOK_ID { - astbuf2 = astbuf1->clone(); - if (astbuf2->type != AST_PRIMITIVE) - astbuf2->str = *$1; - delete $1; - ast_stack.back()->children.push_back(astbuf2); - } '(' cell_port_list ')' | - TOK_ID non_opt_range { - astbuf2 = astbuf1->clone(); - if (astbuf2->type != AST_PRIMITIVE) - astbuf2->str = *$1; - delete $1; - ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2)); - } '(' cell_port_list ')'; - -prim_list: - single_prim | - prim_list ',' single_prim; - -single_prim: - single_cell | - /* no name */ { - astbuf2 = astbuf1->clone(); - ast_stack.back()->children.push_back(astbuf2); - } '(' cell_port_list ')'; - -cell_parameter_list_opt: - '#' '(' cell_parameter_list ')' | /* empty */; - -cell_parameter_list: - /* empty */ | cell_parameter | - cell_parameter ',' cell_parameter_list; - -cell_parameter: - expr { - AstNode *node = new AstNode(AST_PARASET); - astbuf1->children.push_back(node); - node->children.push_back($1); - } | - '.' TOK_ID '(' expr ')' { - AstNode *node = new AstNode(AST_PARASET); - node->str = *$2; - astbuf1->children.push_back(node); - node->children.push_back($4); - delete $2; - }; - -cell_port_list: - /* empty */ | cell_port | - cell_port ',' cell_port_list | - /* empty */ ',' { - AstNode *node = new AstNode(AST_ARGUMENT); - astbuf2->children.push_back(node); - } cell_port_list; - -cell_port: - expr { - AstNode *node = new AstNode(AST_ARGUMENT); - astbuf2->children.push_back(node); - node->children.push_back($1); - } | - '.' TOK_ID '(' expr ')' { - AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; - astbuf2->children.push_back(node); - node->children.push_back($4); - delete $2; - } | - '.' TOK_ID '(' ')' { - AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; - astbuf2->children.push_back(node); - delete $2; - }; - -always_stmt: - attr TOK_ALWAYS { - AstNode *node = new AstNode(AST_ALWAYS); - append_attr(node, $1); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - } always_cond { - AstNode *block = new AstNode(AST_BLOCK); - ast_stack.back()->children.push_back(block); - ast_stack.push_back(block); - } behavioral_stmt { - ast_stack.pop_back(); - ast_stack.pop_back(); - } | - attr TOK_INITIAL { - AstNode *node = new AstNode(AST_INITIAL); - append_attr(node, $1); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - AstNode *block = new AstNode(AST_BLOCK); - ast_stack.back()->children.push_back(block); - ast_stack.push_back(block); - } behavioral_stmt { - ast_stack.pop_back(); - ast_stack.pop_back(); - }; - -always_cond: - '@' '(' always_events ')' | - '@' '(' '*' ')' | - '@' ATTR_BEGIN ')' | - '@' '(' ATTR_END | - '@' '*' | - /* empty */; - -always_events: - always_event | - always_events TOK_OR always_event | - always_events ',' always_event; - -always_event: - TOK_POSEDGE expr { - AstNode *node = new AstNode(AST_POSEDGE); - ast_stack.back()->children.push_back(node); - node->children.push_back($2); - } | - TOK_NEGEDGE expr { - AstNode *node = new AstNode(AST_NEGEDGE); - ast_stack.back()->children.push_back(node); - node->children.push_back($2); - } | - expr { - AstNode *node = new AstNode(AST_EDGE); - ast_stack.back()->children.push_back(node); - node->children.push_back($1); - }; - -opt_label: - ':' TOK_ID { - $$ = $2; - } | - /* empty */ { - $$ = NULL; - }; - -assert: - TOK_ASSERT '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $3)); - }; - -assert_property: - TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $4)); - }; - -simple_behavioral_stmt: - lvalue '=' expr { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $3); - ast_stack.back()->children.push_back(node); - } | - lvalue OP_LE expr { - AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $3); - ast_stack.back()->children.push_back(node); - }; - -// this production creates the obligatory if-else shift/reduce conflict -behavioral_stmt: - defattr | assert | wire_decl | - simple_behavioral_stmt ';' | - hierarchical_id attr { - AstNode *node = new AstNode(AST_TCALL); - node->str = *$1; - delete $1; - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - append_attr(node, $2); - } opt_arg_list ';'{ - ast_stack.pop_back(); - } | - attr TOK_BEGIN opt_label { - AstNode *node = new AstNode(AST_BLOCK); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - append_attr(node, $1); - if ($3 != NULL) - node->str = *$3; - } behavioral_stmt_list TOK_END opt_label { - if ($3 != NULL && $7 != NULL && *$3 != *$7) - frontend_verilog_yyerror("Syntax error."); - if ($3 != NULL) - delete $3; - if ($7 != NULL) - delete $7; - ast_stack.pop_back(); - } | - attr TOK_FOR '(' { - AstNode *node = new AstNode(AST_FOR); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - append_attr(node, $1); - } simple_behavioral_stmt ';' expr { - ast_stack.back()->children.push_back($7); - } ';' simple_behavioral_stmt ')' { - AstNode *block = new AstNode(AST_BLOCK); - ast_stack.back()->children.push_back(block); - ast_stack.push_back(block); - } behavioral_stmt { - ast_stack.pop_back(); - ast_stack.pop_back(); - } | - attr TOK_WHILE '(' expr ')' { - AstNode *node = new AstNode(AST_WHILE); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - append_attr(node, $1); - AstNode *block = new AstNode(AST_BLOCK); - ast_stack.back()->children.push_back($4); - ast_stack.back()->children.push_back(block); - ast_stack.push_back(block); - } behavioral_stmt { - ast_stack.pop_back(); - ast_stack.pop_back(); - } | - attr TOK_REPEAT '(' expr ')' { - AstNode *node = new AstNode(AST_REPEAT); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - append_attr(node, $1); - AstNode *block = new AstNode(AST_BLOCK); - ast_stack.back()->children.push_back($4); - ast_stack.back()->children.push_back(block); - ast_stack.push_back(block); - } behavioral_stmt { - ast_stack.pop_back(); - ast_stack.pop_back(); - } | - attr TOK_IF '(' expr ')' { - AstNode *node = new AstNode(AST_CASE); - AstNode *block = new AstNode(AST_BLOCK); - AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block); - ast_stack.back()->children.push_back(node); - node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4)); - node->children.push_back(cond); - ast_stack.push_back(node); - ast_stack.push_back(block); - append_attr(node, $1); - } behavioral_stmt optional_else { - ast_stack.pop_back(); - ast_stack.pop_back(); - } | - attr case_type '(' expr ')' { - AstNode *node = new AstNode(AST_CASE, $4); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - append_attr(node, $1); - } opt_synopsys_attr case_body TOK_ENDCASE { - case_type_stack.pop_back(); - ast_stack.pop_back(); - }; - -case_type: - TOK_CASE { - case_type_stack.push_back(0); - } | - TOK_CASEX { - case_type_stack.push_back('x'); - } | - TOK_CASEZ { - case_type_stack.push_back('z'); - }; - -opt_synopsys_attr: - opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE { - if (ast_stack.back()->attributes.count("\\full_case") == 0) - ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false); - } | - opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE { - if (ast_stack.back()->attributes.count("\\parallel_case") == 0) - ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false); - } | - /* empty */; - -behavioral_stmt_opt: - behavioral_stmt | - ';' ; - -behavioral_stmt_list: - behavioral_stmt_list behavioral_stmt | - /* empty */; - -optional_else: - TOK_ELSE { - AstNode *block = new AstNode(AST_BLOCK); - AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block); - ast_stack.pop_back(); - ast_stack.back()->children.push_back(cond); - ast_stack.push_back(block); - } behavioral_stmt | - /* empty */; - -case_body: - case_body case_item | - /* empty */; - -case_item: - { - AstNode *node = new AstNode(AST_COND); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - } case_select { - AstNode *block = new AstNode(AST_BLOCK); - ast_stack.back()->children.push_back(block); - ast_stack.push_back(block); - case_type_stack.push_back(0); - } behavioral_stmt_opt { - case_type_stack.pop_back(); - ast_stack.pop_back(); - ast_stack.pop_back(); - }; - -gen_case_body: - gen_case_body gen_case_item | - /* empty */; - -gen_case_item: - { - AstNode *node = new AstNode(AST_COND); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - } case_select { - case_type_stack.push_back(0); - } gen_stmt_or_null { - case_type_stack.pop_back(); - ast_stack.pop_back(); - }; - -case_select: - case_expr_list ':' | - TOK_DEFAULT; - -case_expr_list: - TOK_DEFAULT { - ast_stack.back()->children.push_back(new AstNode(AST_DEFAULT)); - } | - expr { - ast_stack.back()->children.push_back($1); - } | - case_expr_list ',' expr { - ast_stack.back()->children.push_back($3); - }; - -rvalue: - hierarchical_id '[' expr ']' '.' rvalue { - $$ = new AstNode(AST_PREFIX, $3, $6); - $$->str = *$1; - delete $1; - } | - hierarchical_id range { - $$ = new AstNode(AST_IDENTIFIER, $2); - $$->str = *$1; - delete $1; - } | - hierarchical_id non_opt_multirange { - $$ = new AstNode(AST_IDENTIFIER, $2); - $$->str = *$1; - delete $1; - }; - -lvalue: - rvalue { - $$ = $1; - } | - '{' lvalue_concat_list '}' { - $$ = $2; - }; - -lvalue_concat_list: - expr { - $$ = new AstNode(AST_CONCAT); - $$->children.push_back($1); - } | - expr ',' lvalue_concat_list { - $$ = $3; - $$->children.push_back($1); - }; - -opt_arg_list: - '(' arg_list optional_comma ')' | - /* empty */; - -arg_list: - arg_list2 | - /* empty */; - -arg_list2: - single_arg | - arg_list ',' single_arg; - -single_arg: - expr { - ast_stack.back()->children.push_back($1); - }; - -module_gen_body: - module_gen_body gen_stmt_or_module_body_stmt | - /* empty */; - -gen_stmt_or_module_body_stmt: - gen_stmt | module_body_stmt; - -// this production creates the obligatory if-else shift/reduce conflict -gen_stmt: - TOK_FOR '(' { - AstNode *node = new AstNode(AST_GENFOR); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - } simple_behavioral_stmt ';' expr { - ast_stack.back()->children.push_back($6); - } ';' simple_behavioral_stmt ')' gen_stmt_block { - ast_stack.pop_back(); - } | - TOK_IF '(' expr ')' { - AstNode *node = new AstNode(AST_GENIF); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - ast_stack.back()->children.push_back($3); - } gen_stmt_block opt_gen_else { - ast_stack.pop_back(); - } | - case_type '(' expr ')' { - AstNode *node = new AstNode(AST_GENCASE, $3); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - } gen_case_body TOK_ENDCASE { - case_type_stack.pop_back(); - ast_stack.pop_back(); - } | - TOK_BEGIN opt_label { - AstNode *node = new AstNode(AST_GENBLOCK); - node->str = $2 ? *$2 : std::string(); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - } module_gen_body TOK_END opt_label { - if ($2 != NULL) - delete $2; - if ($6 != NULL) - delete $6; - ast_stack.pop_back(); - }; - -gen_stmt_block: - { - AstNode *node = new AstNode(AST_GENBLOCK); - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - } gen_stmt_or_module_body_stmt { - ast_stack.pop_back(); - }; - -gen_stmt_or_null: - gen_stmt_block | ';'; - -opt_gen_else: - TOK_ELSE gen_stmt_or_null | /* empty */; - -expr: - basic_expr { - $$ = $1; - } | - basic_expr '?' attr expr ':' expr { - $$ = new AstNode(AST_TERNARY); - $$->children.push_back($1); - $$->children.push_back($4); - $$->children.push_back($6); - append_attr($$, $3); - }; - -basic_expr: - rvalue { - $$ = $1; - } | - '(' expr ')' TOK_CONST { - if ($4->substr(0, 1) != "'") - frontend_verilog_yyerror("Syntax error."); - AstNode *bits = $2; - AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); - if (val == NULL) - log_error("Value conversion failed: `%s'\n", $4->c_str()); - $$ = new AstNode(AST_TO_BITS, bits, val); - delete $4; - } | - hierarchical_id TOK_CONST { - if ($2->substr(0, 1) != "'") - frontend_verilog_yyerror("Syntax error."); - AstNode *bits = new AstNode(AST_IDENTIFIER); - bits->str = *$1; - AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); - if (val == NULL) - log_error("Value conversion failed: `%s'\n", $2->c_str()); - $$ = new AstNode(AST_TO_BITS, bits, val); - delete $1; - delete $2; - } | - TOK_CONST TOK_CONST { - $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); - if ($$ == NULL || (*$2)[0] != '\'') - log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str()); - delete $1; - delete $2; - } | - TOK_CONST { - $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); - if ($$ == NULL) - log_error("Value conversion failed: `%s'\n", $1->c_str()); - delete $1; - } | - TOK_REALVAL { - $$ = new AstNode(AST_REALVALUE); - char *p = strdup($1->c_str()), *q; - for (int i = 0, j = 0; !p[j]; j++) - if (p[j] != '_') - p[i++] = p[j], p[i] = 0; - $$->realvalue = strtod(p, &q); - log_assert(*q == 0); - delete $1; - free(p); - } | - TOK_STRING { - $$ = AstNode::mkconst_str(*$1); - delete $1; - } | - hierarchical_id attr { - AstNode *node = new AstNode(AST_FCALL); - node->str = *$1; - delete $1; - ast_stack.push_back(node); - append_attr(node, $2); - } '(' arg_list optional_comma ')' { - $$ = ast_stack.back(); - ast_stack.pop_back(); - } | - TOK_TO_SIGNED attr '(' expr ')' { - $$ = new AstNode(AST_TO_SIGNED, $4); - append_attr($$, $2); - } | - TOK_TO_UNSIGNED attr '(' expr ')' { - $$ = new AstNode(AST_TO_UNSIGNED, $4); - append_attr($$, $2); - } | - '(' expr ')' { - $$ = $2; - } | - '{' concat_list '}' { - $$ = $2; - } | - '{' expr '{' expr '}' '}' { - $$ = new AstNode(AST_REPLICATE, $2, $4); - } | - '~' attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_BIT_NOT, $3); - append_attr($$, $2); - } | - basic_expr '&' attr basic_expr { - $$ = new AstNode(AST_BIT_AND, $1, $4); - append_attr($$, $3); - } | - basic_expr '|' attr basic_expr { - $$ = new AstNode(AST_BIT_OR, $1, $4); - append_attr($$, $3); - } | - basic_expr '^' attr basic_expr { - $$ = new AstNode(AST_BIT_XOR, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_XNOR attr basic_expr { - $$ = new AstNode(AST_BIT_XNOR, $1, $4); - append_attr($$, $3); - } | - '&' attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_REDUCE_AND, $3); - append_attr($$, $2); - } | - OP_NAND attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_REDUCE_AND, $3); - append_attr($$, $2); - $$ = new AstNode(AST_LOGIC_NOT, $$); - } | - '|' attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_REDUCE_OR, $3); - append_attr($$, $2); - } | - OP_NOR attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_REDUCE_OR, $3); - append_attr($$, $2); - $$ = new AstNode(AST_LOGIC_NOT, $$); - } | - '^' attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_REDUCE_XOR, $3); - append_attr($$, $2); - } | - OP_XNOR attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_REDUCE_XNOR, $3); - append_attr($$, $2); - } | - basic_expr OP_SHL attr basic_expr { - $$ = new AstNode(AST_SHIFT_LEFT, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_SHR attr basic_expr { - $$ = new AstNode(AST_SHIFT_RIGHT, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_SSHL attr basic_expr { - $$ = new AstNode(AST_SHIFT_SLEFT, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_SSHR attr basic_expr { - $$ = new AstNode(AST_SHIFT_SRIGHT, $1, $4); - append_attr($$, $3); - } | - basic_expr '<' attr basic_expr { - $$ = new AstNode(AST_LT, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_LE attr basic_expr { - $$ = new AstNode(AST_LE, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_EQ attr basic_expr { - $$ = new AstNode(AST_EQ, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_NE attr basic_expr { - $$ = new AstNode(AST_NE, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_EQX attr basic_expr { - $$ = new AstNode(AST_EQX, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_NEX attr basic_expr { - $$ = new AstNode(AST_NEX, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_GE attr basic_expr { - $$ = new AstNode(AST_GE, $1, $4); - append_attr($$, $3); - } | - basic_expr '>' attr basic_expr { - $$ = new AstNode(AST_GT, $1, $4); - append_attr($$, $3); - } | - basic_expr '+' attr basic_expr { - $$ = new AstNode(AST_ADD, $1, $4); - append_attr($$, $3); - } | - basic_expr '-' attr basic_expr { - $$ = new AstNode(AST_SUB, $1, $4); - append_attr($$, $3); - } | - basic_expr '*' attr basic_expr { - $$ = new AstNode(AST_MUL, $1, $4); - append_attr($$, $3); - } | - basic_expr '/' attr basic_expr { - $$ = new AstNode(AST_DIV, $1, $4); - append_attr($$, $3); - } | - basic_expr '%' attr basic_expr { - $$ = new AstNode(AST_MOD, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_POW attr basic_expr { - $$ = new AstNode(AST_POW, $1, $4); - append_attr($$, $3); - } | - '+' attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_POS, $3); - append_attr($$, $2); - } | - '-' attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_NEG, $3); - append_attr($$, $2); - } | - basic_expr OP_LAND attr basic_expr { - $$ = new AstNode(AST_LOGIC_AND, $1, $4); - append_attr($$, $3); - } | - basic_expr OP_LOR attr basic_expr { - $$ = new AstNode(AST_LOGIC_OR, $1, $4); - append_attr($$, $3); - } | - '!' attr basic_expr %prec UNARY_OPS { - $$ = new AstNode(AST_LOGIC_NOT, $3); - append_attr($$, $2); - }; - -concat_list: - expr { - $$ = new AstNode(AST_CONCAT, $1); - } | - expr ',' concat_list { - $$ = $3; - $$->children.push_back($1); - }; - diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l new file mode 100644 index 000000000..0d28e2e7f --- /dev/null +++ b/frontends/verilog/verilog_lexer.l @@ -0,0 +1,359 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * The Verilog frontend. + * + * This frontend is using the AST frontend library (see frontends/ast/). + * Thus this frontend does not generate RTLIL code directly but creates an + * AST directly from the Verilog parse tree and then passes this AST to + * the AST frontend library. + * + * --- + * + * A simple lexer for Verilog code. Non-preprocessor compiler directives are + * handled here. The preprocessor stuff is handled in preproc.cc. Everything + * else is left to the bison parser (see parser.y). + * + */ + +%{ + +#ifdef __clang__ +// bison generates code using the 'register' storage class specifier +#pragma clang diagnostic ignored "-Wdeprecated-register" +#endif + +#include "kernel/log.h" +#include "verilog_frontend.h" +#include "frontends/ast/ast.h" +#include "verilog_parser.tab.h" + +USING_YOSYS_NAMESPACE +using namespace AST; +using namespace VERILOG_FRONTEND; + +YOSYS_NAMESPACE_BEGIN +namespace VERILOG_FRONTEND { + std::vector fn_stack; + std::vector ln_stack; +} +YOSYS_NAMESPACE_END + +#define SV_KEYWORD(_tok) \ + if (sv_mode) return _tok; \ + log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\ + "recognized unless read_verilog is called with -sv!\n", yytext, \ + AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \ + frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \ + return TOK_ID; + +#define YY_INPUT(buf,result,max_size) \ + do { \ + lexin->read(buf, max_size-1); \ + result = lexin->gcount(); \ + if (result >= 0) buf[result] = '\0'; \ + } while (0) + +%} + +%option yylineno +%option noyywrap +%option nounput +%option prefix="frontend_verilog_yy" + +%x COMMENT +%x STRING +%x SYNOPSYS_TRANSLATE_OFF +%x SYNOPSYS_FLAGS +%x IMPORT_DPI + +%% + +"`file_push "[^\n]* { + fn_stack.push_back(current_filename); + ln_stack.push_back(frontend_verilog_yyget_lineno()); + current_filename = yytext+11; + frontend_verilog_yyset_lineno(0); +} + +"`file_pop"[^\n]*\n { + current_filename = fn_stack.back(); + fn_stack.pop_back(); + frontend_verilog_yyset_lineno(ln_stack.back()); + ln_stack.pop_back(); +} + +"`line"[ \t]+[^ \t\r\n]+[ \t]+\"[^ \r\n]+\"[^\r\n]*\n { + char *p = yytext + 5; + while (*p == ' ' || *p == '\t') p++; + frontend_verilog_yyset_lineno(atoi(p)); + while (*p && *p != ' ' && *p != '\t') p++; + while (*p == ' ' || *p == '\t') p++; + char *q = *p ? p + 1 : p; + while (*q && *q != '"') q++; + current_filename = std::string(p).substr(1, q-p-1); +} + +"`file_notfound "[^\n]* { + log_error("Can't open include file `%s'!\n", yytext + 15); +} + +"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */ + +"`default_nettype"[ \t]+[^ \t\r\n/]+ { + char *p = yytext; + while (*p != 0 && *p != ' ' && *p != '\t') p++; + while (*p == ' ' || *p == '\t') p++; + if (!strcmp(p, "none")) + VERILOG_FRONTEND::default_nettype_wire = false; + else if (!strcmp(p, "wire")) + VERILOG_FRONTEND::default_nettype_wire = true; + else + frontend_verilog_yyerror("Unsupported default nettype: %s", p); +} + +"`"[a-zA-Z_$][a-zA-Z0-9_$]* { + frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext); +} + +"module" { return TOK_MODULE; } +"endmodule" { return TOK_ENDMODULE; } +"function" { return TOK_FUNCTION; } +"endfunction" { return TOK_ENDFUNCTION; } +"task" { return TOK_TASK; } +"endtask" { return TOK_ENDTASK; } +"parameter" { return TOK_PARAMETER; } +"localparam" { return TOK_LOCALPARAM; } +"defparam" { return TOK_DEFPARAM; } +"assign" { return TOK_ASSIGN; } +"always" { return TOK_ALWAYS; } +"initial" { return TOK_INITIAL; } +"begin" { return TOK_BEGIN; } +"end" { return TOK_END; } +"if" { return TOK_IF; } +"else" { return TOK_ELSE; } +"for" { return TOK_FOR; } +"posedge" { return TOK_POSEDGE; } +"negedge" { return TOK_NEGEDGE; } +"or" { return TOK_OR; } +"case" { return TOK_CASE; } +"casex" { return TOK_CASEX; } +"casez" { return TOK_CASEZ; } +"endcase" { return TOK_ENDCASE; } +"default" { return TOK_DEFAULT; } +"generate" { return TOK_GENERATE; } +"endgenerate" { return TOK_ENDGENERATE; } +"while" { return TOK_WHILE; } +"repeat" { return TOK_REPEAT; } + +"always_comb" { SV_KEYWORD(TOK_ALWAYS); } +"always_ff" { SV_KEYWORD(TOK_ALWAYS); } +"always_latch" { SV_KEYWORD(TOK_ALWAYS); } + +"assert" { SV_KEYWORD(TOK_ASSERT); } +"property" { SV_KEYWORD(TOK_PROPERTY); } +"logic" { SV_KEYWORD(TOK_REG); } +"bit" { SV_KEYWORD(TOK_REG); } + +"input" { return TOK_INPUT; } +"output" { return TOK_OUTPUT; } +"inout" { return TOK_INOUT; } +"wire" { return TOK_WIRE; } +"reg" { return TOK_REG; } +"integer" { return TOK_INTEGER; } +"signed" { return TOK_SIGNED; } +"genvar" { return TOK_GENVAR; } +"real" { return TOK_REAL; } + +[0-9]+ { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_CONST; +} + +[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_CONST; +} + +[0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_REALVAL; +} + +[0-9][0-9_]*[eE][-+]?[0-9_]+ { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_REALVAL; +} + +\" { BEGIN(STRING); } +\\. { yymore(); } +\" { + BEGIN(0); + char *yystr = strdup(yytext); + yystr[strlen(yytext) - 1] = 0; + int i = 0, j = 0; + while (yystr[i]) { + if (yystr[i] == '\\' && yystr[i + 1]) { + i++; + if (yystr[i] == 'n') + yystr[i] = '\n'; + else if (yystr[i] == 't') + yystr[i] = '\t'; + else if ('0' <= yystr[i] && yystr[i] <= '7') { + yystr[i] = yystr[i] - '0'; + if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { + yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; + i++; + } + if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { + yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; + i++; + } + } + } + yystr[j++] = yystr[i++]; + } + yystr[j] = 0; + frontend_verilog_yylval.string = new std::string(yystr); + free(yystr); + return TOK_STRING; +} +. { yymore(); } + +and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_PRIMITIVE; +} + +supply0 { return TOK_SUPPLY0; } +supply1 { return TOK_SUPPLY1; } + +"$"(display|time|stop|finish) { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_ID; +} + +"$signed" { return TOK_TO_SIGNED; } +"$unsigned" { return TOK_TO_UNSIGNED; } + +[a-zA-Z_$][a-zA-Z0-9_$]* { + frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); + return TOK_ID; +} + +"/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" { + log("Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"); + log("It is strongly suggested to use `ifdef constructs instead!\n"); + BEGIN(SYNOPSYS_TRANSLATE_OFF); +} +. /* ignore synopsys translate_off body */ +\n /* ignore synopsys translate_off body */ +"/*"[ \t]*(synopsys|synthesis)[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); } + +"/*"[ \t]*(synopsys|synthesis)[ \t]+ { + BEGIN(SYNOPSYS_FLAGS); +} +full_case { + log("Warning: Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"); + log("It is strongly suggested to use verilog x-values and default branches instead!\n"); + return TOK_SYNOPSYS_FULL_CASE; +} +parallel_case { + log("Warning: Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"); + log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n"); + return TOK_SYNOPSYS_PARALLEL_CASE; +} +. /* ignore everything else */ +"*/" { BEGIN(0); } + +import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { + BEGIN(IMPORT_DPI); + return TOK_DPI_FUNCTION; +} + +[a-zA-Z_$][a-zA-Z0-9_$]* { + frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); + return TOK_ID; +} + +[ \t\r\n] /* ignore whitespaces */ + +";" { + BEGIN(0); + return *yytext; +} + +. { + return *yytext; +} + +"\\"[^ \t\r\n]+ { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_ID; +} + +"(*" { return ATTR_BEGIN; } +"*)" { return ATTR_END; } + +"{*" { return DEFATTR_BEGIN; } +"*}" { return DEFATTR_END; } + +"**" { return OP_POW; } +"||" { return OP_LOR; } +"&&" { return OP_LAND; } +"==" { return OP_EQ; } +"!=" { return OP_NE; } +"<=" { return OP_LE; } +">=" { return OP_GE; } + +"===" { return OP_EQX; } +"!==" { return OP_NEX; } + +"~&" { return OP_NAND; } +"~|" { return OP_NOR; } +"~^" { return OP_XNOR; } +"^~" { return OP_XNOR; } + +"<<" { return OP_SHL; } +">>" { return OP_SHR; } +"<<<" { return OP_SSHL; } +">>>" { return OP_SSHR; } + +"+:" { return TOK_POS_INDEXED; } +"-:" { return TOK_NEG_INDEXED; } + +"/*" { BEGIN(COMMENT); } +. /* ignore comment body */ +\n /* ignore comment body */ +"*/" { BEGIN(0); } + +[ \t\r\n] /* ignore whitespaces */ +\\[\r\n] /* ignore continuation sequence */ +"//"[^\r\n]* /* ignore one-line comments */ +"#"[$a-zA-Z_0-9\.]+ /* ignore simulation timings */ + +. { return *yytext; } + +%% + +// this is a hack to avoid the 'yyinput defined but not used' error msgs +void *frontend_verilog_avoid_input_warnings() { + return (void*)&yyinput; +} + diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y new file mode 100644 index 000000000..cf02a56a9 --- /dev/null +++ b/frontends/verilog/verilog_parser.y @@ -0,0 +1,1434 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * The Verilog frontend. + * + * This frontend is using the AST frontend library (see frontends/ast/). + * Thus this frontend does not generate RTLIL code directly but creates an + * AST directly from the Verilog parse tree and then passes this AST to + * the AST frontend library. + * + * --- + * + * This is the actual bison parser for Verilog code. The AST ist created directly + * from the bison reduce functions here. Note that this code uses a few global + * variables to hold the state of the AST generator and therefore this parser is + * not reentrant. + * + */ + +%{ +#include +#include +#include "verilog_frontend.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +using namespace AST; +using namespace VERILOG_FRONTEND; + +YOSYS_NAMESPACE_BEGIN +namespace VERILOG_FRONTEND { + int port_counter; + std::map port_stubs; + std::map attr_list, default_attr_list; + std::map *albuf; + std::vector ast_stack; + struct AstNode *astbuf1, *astbuf2, *astbuf3; + struct AstNode *current_function_or_task; + struct AstNode *current_ast, *current_ast_mod; + int current_function_or_task_port_id; + std::vector case_type_stack; + bool do_not_require_port_stubs; + bool default_nettype_wire; + bool sv_mode; + std::istream *lexin; +} +YOSYS_NAMESPACE_END + +static void append_attr(AstNode *ast, std::map *al) +{ + for (auto &it : *al) { + if (ast->attributes.count(it.first) > 0) + delete ast->attributes[it.first]; + ast->attributes[it.first] = it.second; + } + delete al; +} + +static void append_attr_clone(AstNode *ast, std::map *al) +{ + for (auto &it : *al) { + if (ast->attributes.count(it.first) > 0) + delete ast->attributes[it.first]; + ast->attributes[it.first] = it.second->clone(); + } +} + +static void free_attr(std::map *al) +{ + for (auto &it : *al) + delete it.second; + delete al; +} + +%} + +%name-prefix "frontend_verilog_yy" + +%union { + std::string *string; + struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast; + std::map *al; + bool boolean; +} + +%token TOK_STRING TOK_ID TOK_CONST TOK_REALVAL TOK_PRIMITIVE +%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END +%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM +%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG +%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL +%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT +%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR +%token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT +%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK +%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL +%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE +%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED +%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_PROPERTY + +%type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int +%type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list +%type opt_label tok_prim_wrapper hierarchical_id +%type opt_signed +%type attr + +// operator precedence from low to high +%left OP_LOR +%left OP_LAND +%left '|' OP_NOR +%left '^' OP_XNOR +%left '&' OP_NAND +%left OP_EQ OP_NE OP_EQX OP_NEX +%left '<' OP_LE OP_GE '>' +%left OP_SHL OP_SHR OP_SSHL OP_SSHR +%left '+' '-' +%left '*' '/' '%' +%left OP_POW +%right UNARY_OPS + +%expect 2 +%debug + +%% + +input: { + ast_stack.push_back(current_ast); +} design { + ast_stack.pop_back(); + log_assert(GetSize(ast_stack) == 0); + for (auto &it : default_attr_list) + delete it.second; + default_attr_list.clear(); +}; + +design: + module design | + defattr design | + task_func_decl design | + /* empty */; + +attr: + { + for (auto &it : attr_list) + delete it.second; + attr_list.clear(); + for (auto &it : default_attr_list) + attr_list[it.first] = it.second->clone(); + } attr_opt { + std::map *al = new std::map; + al->swap(attr_list); + $$ = al; + }; + +attr_opt: + attr_opt ATTR_BEGIN opt_attr_list ATTR_END | + /* empty */; + +defattr: + DEFATTR_BEGIN { + for (auto &it : default_attr_list) + delete it.second; + default_attr_list.clear(); + for (auto &it : attr_list) + delete it.second; + attr_list.clear(); + } opt_attr_list { + default_attr_list = attr_list; + attr_list.clear(); + } DEFATTR_END; + +opt_attr_list: + attr_list | /* empty */; + +attr_list: + attr_assign | + attr_list ',' attr_assign; + +attr_assign: + hierarchical_id { + if (attr_list.count(*$1) != 0) + delete attr_list[*$1]; + attr_list[*$1] = AstNode::mkconst_int(1, false); + delete $1; + } | + hierarchical_id '=' expr { + if (attr_list.count(*$1) != 0) + delete attr_list[*$1]; + attr_list[*$1] = $3; + delete $1; + }; + +hierarchical_id: + TOK_ID { + $$ = $1; + } | + hierarchical_id '.' TOK_ID { + if ($3->substr(0, 1) == "\\") + *$1 += "." + $3->substr(1); + else + *$1 += "." + *$3; + delete $3; + $$ = $1; + }; + +module: + attr TOK_MODULE TOK_ID { + do_not_require_port_stubs = false; + AstNode *mod = new AstNode(AST_MODULE); + ast_stack.back()->children.push_back(mod); + ast_stack.push_back(mod); + current_ast_mod = mod; + port_stubs.clear(); + port_counter = 0; + mod->str = *$3; + append_attr(mod, $1); + delete $3; + } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE { + if (port_stubs.size() != 0) + frontend_verilog_yyerror("Missing details for module port `%s'.", + port_stubs.begin()->first.c_str()); + ast_stack.pop_back(); + log_assert(ast_stack.size() == 1); + current_ast_mod = NULL; + }; + +module_para_opt: + '#' '(' module_para_list ')' | /* empty */; + +module_para_list: + single_module_para | + single_module_para ',' module_para_list | + /* empty */; + +single_module_para: + TOK_PARAMETER { + astbuf1 = new AstNode(AST_PARAMETER); + astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + } param_signed param_integer param_range single_param_decl { + delete astbuf1; + }; + +module_args_opt: + '(' ')' | /* empty */ | '(' module_args optional_comma ')'; + +module_args: + module_arg | module_args ',' module_arg; + +optional_comma: + ',' | /* empty */; + +module_arg_opt_assignment: + '=' expr { + if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { + AstNode *wire = new AstNode(AST_IDENTIFIER); + wire->str = ast_stack.back()->children.back()->str; + if (ast_stack.back()->children.back()->is_reg) + ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2)))); + else + ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); + } else + frontend_verilog_yyerror("Syntax error."); + } | + /* empty */; + +module_arg: + TOK_ID { + if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { + AstNode *node = ast_stack.back()->children.back()->clone(); + node->str = *$1; + node->port_id = ++port_counter; + ast_stack.back()->children.push_back(node); + } else { + if (port_stubs.count(*$1) != 0) + frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str()); + port_stubs[*$1] = ++port_counter; + } + delete $1; + } module_arg_opt_assignment | + attr wire_type range TOK_ID { + AstNode *node = $2; + node->str = *$4; + node->port_id = ++port_counter; + if ($3 != NULL) + node->children.push_back($3); + if (!node->is_input && !node->is_output) + frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str()); + if (node->is_reg && node->is_input && !node->is_output) + frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str()); + ast_stack.back()->children.push_back(node); + append_attr(node, $1); + delete $4; + } module_arg_opt_assignment | + '.' '.' '.' { + do_not_require_port_stubs = true; + }; + +wire_type: + { + astbuf3 = new AstNode(AST_WIRE); + } wire_type_token_list { + $$ = astbuf3; + }; + +wire_type_token_list: + wire_type_token | wire_type_token_list wire_type_token; + +wire_type_token: + TOK_INPUT { + astbuf3->is_input = true; + } | + TOK_OUTPUT { + astbuf3->is_output = true; + } | + TOK_INOUT { + astbuf3->is_input = true; + astbuf3->is_output = true; + } | + TOK_WIRE { + } | + TOK_REG { + astbuf3->is_reg = true; + } | + TOK_INTEGER { + astbuf3->is_reg = true; + astbuf3->range_left = 31; + astbuf3->range_right = 0; + astbuf3->is_signed = true; + } | + TOK_GENVAR { + astbuf3->type = AST_GENVAR; + astbuf3->is_reg = true; + astbuf3->range_left = 31; + astbuf3->range_right = 0; + } | + TOK_SIGNED { + astbuf3->is_signed = true; + }; + +non_opt_range: + '[' expr ':' expr ']' { + $$ = new AstNode(AST_RANGE); + $$->children.push_back($2); + $$->children.push_back($4); + } | + '[' expr TOK_POS_INDEXED expr ']' { + $$ = new AstNode(AST_RANGE); + $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true))); + $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true))); + } | + '[' expr TOK_NEG_INDEXED expr ']' { + $$ = new AstNode(AST_RANGE); + $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true))); + $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4)); + } | + '[' expr ']' { + $$ = new AstNode(AST_RANGE); + $$->children.push_back($2); + }; + +non_opt_multirange: + non_opt_range non_opt_range { + $$ = new AstNode(AST_MULTIRANGE, $1, $2); + } | + non_opt_multirange non_opt_range { + $$ = $1; + $$->children.push_back($2); + }; + +range: + non_opt_range { + $$ = $1; + } | + /* empty */ { + $$ = NULL; + }; + +range_or_multirange: + range { $$ = $1; } | + non_opt_multirange { $$ = $1; }; + +range_or_signed_int: + range { + $$ = $1; + } | + TOK_INTEGER { + $$ = new AstNode(AST_RANGE); + $$->children.push_back(AstNode::mkconst_int(31, true)); + $$->children.push_back(AstNode::mkconst_int(0, true)); + $$->is_signed = true; + }; + +module_body: + module_body module_body_stmt | + /* the following line makes the generate..endgenrate keywords optional */ + module_body gen_stmt | + /* empty */; + +module_body_stmt: + task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt | + always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property; + +task_func_decl: + attr TOK_DPI_FUNCTION TOK_ID TOK_ID { + current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4)); + current_function_or_task->str = *$4; + append_attr(current_function_or_task, $1); + ast_stack.back()->children.push_back(current_function_or_task); + delete $3; + delete $4; + } opt_dpi_function_args ';' { + current_function_or_task = NULL; + } | + attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID { + current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3)); + current_function_or_task->str = *$6; + append_attr(current_function_or_task, $1); + ast_stack.back()->children.push_back(current_function_or_task); + delete $3; + delete $5; + delete $6; + } opt_dpi_function_args ';' { + current_function_or_task = NULL; + } | + attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID { + current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5))); + current_function_or_task->str = *$8; + append_attr(current_function_or_task, $1); + ast_stack.back()->children.push_back(current_function_or_task); + delete $3; + delete $5; + delete $7; + delete $8; + } opt_dpi_function_args ';' { + current_function_or_task = NULL; + } | + attr TOK_TASK TOK_ID ';' { + current_function_or_task = new AstNode(AST_TASK); + current_function_or_task->str = *$3; + append_attr(current_function_or_task, $1); + ast_stack.back()->children.push_back(current_function_or_task); + ast_stack.push_back(current_function_or_task); + current_function_or_task_port_id = 1; + delete $3; + } task_func_body TOK_ENDTASK { + current_function_or_task = NULL; + ast_stack.pop_back(); + } | + attr TOK_FUNCTION opt_signed range_or_signed_int TOK_ID ';' { + current_function_or_task = new AstNode(AST_FUNCTION); + current_function_or_task->str = *$5; + append_attr(current_function_or_task, $1); + ast_stack.back()->children.push_back(current_function_or_task); + ast_stack.push_back(current_function_or_task); + AstNode *outreg = new AstNode(AST_WIRE); + outreg->str = *$5; + outreg->is_signed = $3; + if ($4 != NULL) { + outreg->children.push_back($4); + outreg->is_signed = $3 || $4->is_signed; + $4->is_signed = false; + } + current_function_or_task->children.push_back(outreg); + current_function_or_task_port_id = 1; + delete $5; + } task_func_body TOK_ENDFUNCTION { + current_function_or_task = NULL; + ast_stack.pop_back(); + }; + +dpi_function_arg: + TOK_ID TOK_ID { + current_function_or_task->children.push_back(AstNode::mkconst_str(*$1)); + delete $1; + delete $2; + } | + TOK_ID { + current_function_or_task->children.push_back(AstNode::mkconst_str(*$1)); + delete $1; + }; + +opt_dpi_function_args: + '(' dpi_function_args ')' | + /* empty */; + +dpi_function_args: + dpi_function_args ',' dpi_function_arg | + dpi_function_args ',' | + dpi_function_arg | + /* empty */; + +opt_signed: + TOK_SIGNED { + $$ = true; + } | + /* empty */ { + $$ = false; + }; + +task_func_body: + task_func_body behavioral_stmt | + /* empty */; + +param_signed: + TOK_SIGNED { + astbuf1->is_signed = true; + } | /* empty */; + +param_integer: + TOK_INTEGER { + if (astbuf1->children.size() != 1) + frontend_verilog_yyerror("Syntax error."); + astbuf1->children.push_back(new AstNode(AST_RANGE)); + astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true)); + astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true)); + astbuf1->is_signed = true; + } | /* empty */; + +param_real: + TOK_REAL { + if (astbuf1->children.size() != 1) + frontend_verilog_yyerror("Syntax error."); + astbuf1->children.push_back(new AstNode(AST_REALVALUE)); + } | /* empty */; + +param_range: + range { + if ($1 != NULL) { + if (astbuf1->children.size() != 1) + frontend_verilog_yyerror("Syntax error."); + astbuf1->children.push_back($1); + } + }; + +param_decl: + TOK_PARAMETER { + astbuf1 = new AstNode(AST_PARAMETER); + astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + } param_signed param_integer param_real param_range param_decl_list ';' { + delete astbuf1; + }; + +localparam_decl: + TOK_LOCALPARAM { + astbuf1 = new AstNode(AST_LOCALPARAM); + astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + } param_signed param_integer param_real param_range param_decl_list ';' { + delete astbuf1; + }; + +param_decl_list: + single_param_decl | param_decl_list ',' single_param_decl; + +single_param_decl: + TOK_ID '=' expr { + AstNode *node = astbuf1->clone(); + node->str = *$1; + delete node->children[0]; + node->children[0] = $3; + ast_stack.back()->children.push_back(node); + delete $1; + }; + +defparam_decl: + TOK_DEFPARAM defparam_decl_list ';'; + +defparam_decl_list: + single_defparam_decl | defparam_decl_list ',' single_defparam_decl; + +single_defparam_decl: + range hierarchical_id '=' expr { + AstNode *node = new AstNode(AST_DEFPARAM); + node->str = *$2; + node->children.push_back($4); + if ($1 != NULL) + node->children.push_back($1); + ast_stack.back()->children.push_back(node); + delete $2; + }; + +wire_decl: + attr wire_type range { + albuf = $1; + astbuf1 = $2; + astbuf2 = $3; + if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { + if (astbuf2) { + frontend_verilog_yyerror("Syntax error."); + } else { + astbuf2 = new AstNode(AST_RANGE); + astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true)); + astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true)); + } + } + if (astbuf2 && astbuf2->children.size() != 2) + frontend_verilog_yyerror("Syntax error."); + } wire_name_list ';' { + delete astbuf1; + if (astbuf2 != NULL) + delete astbuf2; + free_attr(albuf); + } | + attr TOK_SUPPLY0 TOK_ID ';' { + ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); + ast_stack.back()->children.back()->str = *$3; + append_attr(ast_stack.back()->children.back(), $1); + ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1))); + ast_stack.back()->children.back()->children[0]->str = *$3; + delete $3; + } | + attr TOK_SUPPLY1 TOK_ID ';' { + ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); + ast_stack.back()->children.back()->str = *$3; + append_attr(ast_stack.back()->children.back(), $1); + ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1))); + ast_stack.back()->children.back()->children[0]->str = *$3; + delete $3; + }; + +wire_name_list: + wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign; + +wire_name_and_opt_assign: + wire_name | + wire_name '=' expr { + AstNode *wire = new AstNode(AST_IDENTIFIER); + wire->str = ast_stack.back()->children.back()->str; + if (astbuf1->is_reg) + ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3)))); + else + ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3)); + }; + +wire_name: + TOK_ID range_or_multirange { + AstNode *node = astbuf1->clone(); + node->str = *$1; + append_attr_clone(node, albuf); + if (astbuf2 != NULL) + node->children.push_back(astbuf2->clone()); + if ($2 != NULL) { + if (node->is_input || node->is_output) + frontend_verilog_yyerror("Syntax error."); + if (!astbuf2) { + AstNode *rng = new AstNode(AST_RANGE); + rng->children.push_back(AstNode::mkconst_int(0, true)); + rng->children.push_back(AstNode::mkconst_int(0, true)); + node->children.push_back(rng); + } + node->type = AST_MEMORY; + node->children.push_back($2); + } + if (current_function_or_task == NULL) { + if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { + port_stubs[*$1] = ++port_counter; + } + if (port_stubs.count(*$1) != 0) { + if (!node->is_input && !node->is_output) + frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str()); + if (node->is_reg && node->is_input && !node->is_output) + frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str()); + node->port_id = port_stubs[*$1]; + port_stubs.erase(*$1); + } else { + if (node->is_input || node->is_output) + frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str()); + } + } else { + if (node->is_input || node->is_output) + node->port_id = current_function_or_task_port_id++; + } + ast_stack.back()->children.push_back(node); + delete $1; + }; + +assign_stmt: + TOK_ASSIGN assign_expr_list ';'; + +assign_expr_list: + assign_expr | assign_expr_list ',' assign_expr; + +assign_expr: + expr '=' expr { + ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3)); + }; + +cell_stmt: + attr TOK_ID { + astbuf1 = new AstNode(AST_CELL); + append_attr(astbuf1, $1); + astbuf1->children.push_back(new AstNode(AST_CELLTYPE)); + astbuf1->children[0]->str = *$2; + delete $2; + } cell_parameter_list_opt cell_list ';' { + delete astbuf1; + } | + attr tok_prim_wrapper { + astbuf1 = new AstNode(AST_PRIMITIVE); + astbuf1->str = *$2; + append_attr(astbuf1, $1); + delete $2; + } prim_list ';' { + delete astbuf1; + }; + +tok_prim_wrapper: + TOK_PRIMITIVE { + $$ = $1; + } | + TOK_OR { + $$ = new std::string("or"); + }; + +cell_list: + single_cell | + cell_list ',' single_cell; + +single_cell: + TOK_ID { + astbuf2 = astbuf1->clone(); + if (astbuf2->type != AST_PRIMITIVE) + astbuf2->str = *$1; + delete $1; + ast_stack.back()->children.push_back(astbuf2); + } '(' cell_port_list ')' | + TOK_ID non_opt_range { + astbuf2 = astbuf1->clone(); + if (astbuf2->type != AST_PRIMITIVE) + astbuf2->str = *$1; + delete $1; + ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2)); + } '(' cell_port_list ')'; + +prim_list: + single_prim | + prim_list ',' single_prim; + +single_prim: + single_cell | + /* no name */ { + astbuf2 = astbuf1->clone(); + ast_stack.back()->children.push_back(astbuf2); + } '(' cell_port_list ')'; + +cell_parameter_list_opt: + '#' '(' cell_parameter_list ')' | /* empty */; + +cell_parameter_list: + /* empty */ | cell_parameter | + cell_parameter ',' cell_parameter_list; + +cell_parameter: + expr { + AstNode *node = new AstNode(AST_PARASET); + astbuf1->children.push_back(node); + node->children.push_back($1); + } | + '.' TOK_ID '(' expr ')' { + AstNode *node = new AstNode(AST_PARASET); + node->str = *$2; + astbuf1->children.push_back(node); + node->children.push_back($4); + delete $2; + }; + +cell_port_list: + /* empty */ | cell_port | + cell_port ',' cell_port_list | + /* empty */ ',' { + AstNode *node = new AstNode(AST_ARGUMENT); + astbuf2->children.push_back(node); + } cell_port_list; + +cell_port: + expr { + AstNode *node = new AstNode(AST_ARGUMENT); + astbuf2->children.push_back(node); + node->children.push_back($1); + } | + '.' TOK_ID '(' expr ')' { + AstNode *node = new AstNode(AST_ARGUMENT); + node->str = *$2; + astbuf2->children.push_back(node); + node->children.push_back($4); + delete $2; + } | + '.' TOK_ID '(' ')' { + AstNode *node = new AstNode(AST_ARGUMENT); + node->str = *$2; + astbuf2->children.push_back(node); + delete $2; + }; + +always_stmt: + attr TOK_ALWAYS { + AstNode *node = new AstNode(AST_ALWAYS); + append_attr(node, $1); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } always_cond { + AstNode *block = new AstNode(AST_BLOCK); + ast_stack.back()->children.push_back(block); + ast_stack.push_back(block); + } behavioral_stmt { + ast_stack.pop_back(); + ast_stack.pop_back(); + } | + attr TOK_INITIAL { + AstNode *node = new AstNode(AST_INITIAL); + append_attr(node, $1); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + AstNode *block = new AstNode(AST_BLOCK); + ast_stack.back()->children.push_back(block); + ast_stack.push_back(block); + } behavioral_stmt { + ast_stack.pop_back(); + ast_stack.pop_back(); + }; + +always_cond: + '@' '(' always_events ')' | + '@' '(' '*' ')' | + '@' ATTR_BEGIN ')' | + '@' '(' ATTR_END | + '@' '*' | + /* empty */; + +always_events: + always_event | + always_events TOK_OR always_event | + always_events ',' always_event; + +always_event: + TOK_POSEDGE expr { + AstNode *node = new AstNode(AST_POSEDGE); + ast_stack.back()->children.push_back(node); + node->children.push_back($2); + } | + TOK_NEGEDGE expr { + AstNode *node = new AstNode(AST_NEGEDGE); + ast_stack.back()->children.push_back(node); + node->children.push_back($2); + } | + expr { + AstNode *node = new AstNode(AST_EDGE); + ast_stack.back()->children.push_back(node); + node->children.push_back($1); + }; + +opt_label: + ':' TOK_ID { + $$ = $2; + } | + /* empty */ { + $$ = NULL; + }; + +assert: + TOK_ASSERT '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $3)); + }; + +assert_property: + TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $4)); + }; + +simple_behavioral_stmt: + lvalue '=' expr { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $3); + ast_stack.back()->children.push_back(node); + } | + lvalue OP_LE expr { + AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $3); + ast_stack.back()->children.push_back(node); + }; + +// this production creates the obligatory if-else shift/reduce conflict +behavioral_stmt: + defattr | assert | wire_decl | + simple_behavioral_stmt ';' | + hierarchical_id attr { + AstNode *node = new AstNode(AST_TCALL); + node->str = *$1; + delete $1; + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + append_attr(node, $2); + } opt_arg_list ';'{ + ast_stack.pop_back(); + } | + attr TOK_BEGIN opt_label { + AstNode *node = new AstNode(AST_BLOCK); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + append_attr(node, $1); + if ($3 != NULL) + node->str = *$3; + } behavioral_stmt_list TOK_END opt_label { + if ($3 != NULL && $7 != NULL && *$3 != *$7) + frontend_verilog_yyerror("Syntax error."); + if ($3 != NULL) + delete $3; + if ($7 != NULL) + delete $7; + ast_stack.pop_back(); + } | + attr TOK_FOR '(' { + AstNode *node = new AstNode(AST_FOR); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + append_attr(node, $1); + } simple_behavioral_stmt ';' expr { + ast_stack.back()->children.push_back($7); + } ';' simple_behavioral_stmt ')' { + AstNode *block = new AstNode(AST_BLOCK); + ast_stack.back()->children.push_back(block); + ast_stack.push_back(block); + } behavioral_stmt { + ast_stack.pop_back(); + ast_stack.pop_back(); + } | + attr TOK_WHILE '(' expr ')' { + AstNode *node = new AstNode(AST_WHILE); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + append_attr(node, $1); + AstNode *block = new AstNode(AST_BLOCK); + ast_stack.back()->children.push_back($4); + ast_stack.back()->children.push_back(block); + ast_stack.push_back(block); + } behavioral_stmt { + ast_stack.pop_back(); + ast_stack.pop_back(); + } | + attr TOK_REPEAT '(' expr ')' { + AstNode *node = new AstNode(AST_REPEAT); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + append_attr(node, $1); + AstNode *block = new AstNode(AST_BLOCK); + ast_stack.back()->children.push_back($4); + ast_stack.back()->children.push_back(block); + ast_stack.push_back(block); + } behavioral_stmt { + ast_stack.pop_back(); + ast_stack.pop_back(); + } | + attr TOK_IF '(' expr ')' { + AstNode *node = new AstNode(AST_CASE); + AstNode *block = new AstNode(AST_BLOCK); + AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block); + ast_stack.back()->children.push_back(node); + node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4)); + node->children.push_back(cond); + ast_stack.push_back(node); + ast_stack.push_back(block); + append_attr(node, $1); + } behavioral_stmt optional_else { + ast_stack.pop_back(); + ast_stack.pop_back(); + } | + attr case_type '(' expr ')' { + AstNode *node = new AstNode(AST_CASE, $4); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + append_attr(node, $1); + } opt_synopsys_attr case_body TOK_ENDCASE { + case_type_stack.pop_back(); + ast_stack.pop_back(); + }; + +case_type: + TOK_CASE { + case_type_stack.push_back(0); + } | + TOK_CASEX { + case_type_stack.push_back('x'); + } | + TOK_CASEZ { + case_type_stack.push_back('z'); + }; + +opt_synopsys_attr: + opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE { + if (ast_stack.back()->attributes.count("\\full_case") == 0) + ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false); + } | + opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE { + if (ast_stack.back()->attributes.count("\\parallel_case") == 0) + ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false); + } | + /* empty */; + +behavioral_stmt_opt: + behavioral_stmt | + ';' ; + +behavioral_stmt_list: + behavioral_stmt_list behavioral_stmt | + /* empty */; + +optional_else: + TOK_ELSE { + AstNode *block = new AstNode(AST_BLOCK); + AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block); + ast_stack.pop_back(); + ast_stack.back()->children.push_back(cond); + ast_stack.push_back(block); + } behavioral_stmt | + /* empty */; + +case_body: + case_body case_item | + /* empty */; + +case_item: + { + AstNode *node = new AstNode(AST_COND); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } case_select { + AstNode *block = new AstNode(AST_BLOCK); + ast_stack.back()->children.push_back(block); + ast_stack.push_back(block); + case_type_stack.push_back(0); + } behavioral_stmt_opt { + case_type_stack.pop_back(); + ast_stack.pop_back(); + ast_stack.pop_back(); + }; + +gen_case_body: + gen_case_body gen_case_item | + /* empty */; + +gen_case_item: + { + AstNode *node = new AstNode(AST_COND); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } case_select { + case_type_stack.push_back(0); + } gen_stmt_or_null { + case_type_stack.pop_back(); + ast_stack.pop_back(); + }; + +case_select: + case_expr_list ':' | + TOK_DEFAULT; + +case_expr_list: + TOK_DEFAULT { + ast_stack.back()->children.push_back(new AstNode(AST_DEFAULT)); + } | + expr { + ast_stack.back()->children.push_back($1); + } | + case_expr_list ',' expr { + ast_stack.back()->children.push_back($3); + }; + +rvalue: + hierarchical_id '[' expr ']' '.' rvalue { + $$ = new AstNode(AST_PREFIX, $3, $6); + $$->str = *$1; + delete $1; + } | + hierarchical_id range { + $$ = new AstNode(AST_IDENTIFIER, $2); + $$->str = *$1; + delete $1; + } | + hierarchical_id non_opt_multirange { + $$ = new AstNode(AST_IDENTIFIER, $2); + $$->str = *$1; + delete $1; + }; + +lvalue: + rvalue { + $$ = $1; + } | + '{' lvalue_concat_list '}' { + $$ = $2; + }; + +lvalue_concat_list: + expr { + $$ = new AstNode(AST_CONCAT); + $$->children.push_back($1); + } | + expr ',' lvalue_concat_list { + $$ = $3; + $$->children.push_back($1); + }; + +opt_arg_list: + '(' arg_list optional_comma ')' | + /* empty */; + +arg_list: + arg_list2 | + /* empty */; + +arg_list2: + single_arg | + arg_list ',' single_arg; + +single_arg: + expr { + ast_stack.back()->children.push_back($1); + }; + +module_gen_body: + module_gen_body gen_stmt_or_module_body_stmt | + /* empty */; + +gen_stmt_or_module_body_stmt: + gen_stmt | module_body_stmt; + +// this production creates the obligatory if-else shift/reduce conflict +gen_stmt: + TOK_FOR '(' { + AstNode *node = new AstNode(AST_GENFOR); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } simple_behavioral_stmt ';' expr { + ast_stack.back()->children.push_back($6); + } ';' simple_behavioral_stmt ')' gen_stmt_block { + ast_stack.pop_back(); + } | + TOK_IF '(' expr ')' { + AstNode *node = new AstNode(AST_GENIF); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + ast_stack.back()->children.push_back($3); + } gen_stmt_block opt_gen_else { + ast_stack.pop_back(); + } | + case_type '(' expr ')' { + AstNode *node = new AstNode(AST_GENCASE, $3); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } gen_case_body TOK_ENDCASE { + case_type_stack.pop_back(); + ast_stack.pop_back(); + } | + TOK_BEGIN opt_label { + AstNode *node = new AstNode(AST_GENBLOCK); + node->str = $2 ? *$2 : std::string(); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } module_gen_body TOK_END opt_label { + if ($2 != NULL) + delete $2; + if ($6 != NULL) + delete $6; + ast_stack.pop_back(); + }; + +gen_stmt_block: + { + AstNode *node = new AstNode(AST_GENBLOCK); + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } gen_stmt_or_module_body_stmt { + ast_stack.pop_back(); + }; + +gen_stmt_or_null: + gen_stmt_block | ';'; + +opt_gen_else: + TOK_ELSE gen_stmt_or_null | /* empty */; + +expr: + basic_expr { + $$ = $1; + } | + basic_expr '?' attr expr ':' expr { + $$ = new AstNode(AST_TERNARY); + $$->children.push_back($1); + $$->children.push_back($4); + $$->children.push_back($6); + append_attr($$, $3); + }; + +basic_expr: + rvalue { + $$ = $1; + } | + '(' expr ')' TOK_CONST { + if ($4->substr(0, 1) != "'") + frontend_verilog_yyerror("Syntax error."); + AstNode *bits = $2; + AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + if (val == NULL) + log_error("Value conversion failed: `%s'\n", $4->c_str()); + $$ = new AstNode(AST_TO_BITS, bits, val); + delete $4; + } | + hierarchical_id TOK_CONST { + if ($2->substr(0, 1) != "'") + frontend_verilog_yyerror("Syntax error."); + AstNode *bits = new AstNode(AST_IDENTIFIER); + bits->str = *$1; + AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + if (val == NULL) + log_error("Value conversion failed: `%s'\n", $2->c_str()); + $$ = new AstNode(AST_TO_BITS, bits, val); + delete $1; + delete $2; + } | + TOK_CONST TOK_CONST { + $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + if ($$ == NULL || (*$2)[0] != '\'') + log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str()); + delete $1; + delete $2; + } | + TOK_CONST { + $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + if ($$ == NULL) + log_error("Value conversion failed: `%s'\n", $1->c_str()); + delete $1; + } | + TOK_REALVAL { + $$ = new AstNode(AST_REALVALUE); + char *p = strdup($1->c_str()), *q; + for (int i = 0, j = 0; !p[j]; j++) + if (p[j] != '_') + p[i++] = p[j], p[i] = 0; + $$->realvalue = strtod(p, &q); + log_assert(*q == 0); + delete $1; + free(p); + } | + TOK_STRING { + $$ = AstNode::mkconst_str(*$1); + delete $1; + } | + hierarchical_id attr { + AstNode *node = new AstNode(AST_FCALL); + node->str = *$1; + delete $1; + ast_stack.push_back(node); + append_attr(node, $2); + } '(' arg_list optional_comma ')' { + $$ = ast_stack.back(); + ast_stack.pop_back(); + } | + TOK_TO_SIGNED attr '(' expr ')' { + $$ = new AstNode(AST_TO_SIGNED, $4); + append_attr($$, $2); + } | + TOK_TO_UNSIGNED attr '(' expr ')' { + $$ = new AstNode(AST_TO_UNSIGNED, $4); + append_attr($$, $2); + } | + '(' expr ')' { + $$ = $2; + } | + '{' concat_list '}' { + $$ = $2; + } | + '{' expr '{' expr '}' '}' { + $$ = new AstNode(AST_REPLICATE, $2, $4); + } | + '~' attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_BIT_NOT, $3); + append_attr($$, $2); + } | + basic_expr '&' attr basic_expr { + $$ = new AstNode(AST_BIT_AND, $1, $4); + append_attr($$, $3); + } | + basic_expr '|' attr basic_expr { + $$ = new AstNode(AST_BIT_OR, $1, $4); + append_attr($$, $3); + } | + basic_expr '^' attr basic_expr { + $$ = new AstNode(AST_BIT_XOR, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_XNOR attr basic_expr { + $$ = new AstNode(AST_BIT_XNOR, $1, $4); + append_attr($$, $3); + } | + '&' attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_AND, $3); + append_attr($$, $2); + } | + OP_NAND attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_AND, $3); + append_attr($$, $2); + $$ = new AstNode(AST_LOGIC_NOT, $$); + } | + '|' attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_OR, $3); + append_attr($$, $2); + } | + OP_NOR attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_OR, $3); + append_attr($$, $2); + $$ = new AstNode(AST_LOGIC_NOT, $$); + } | + '^' attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_XOR, $3); + append_attr($$, $2); + } | + OP_XNOR attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_XNOR, $3); + append_attr($$, $2); + } | + basic_expr OP_SHL attr basic_expr { + $$ = new AstNode(AST_SHIFT_LEFT, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_SHR attr basic_expr { + $$ = new AstNode(AST_SHIFT_RIGHT, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_SSHL attr basic_expr { + $$ = new AstNode(AST_SHIFT_SLEFT, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_SSHR attr basic_expr { + $$ = new AstNode(AST_SHIFT_SRIGHT, $1, $4); + append_attr($$, $3); + } | + basic_expr '<' attr basic_expr { + $$ = new AstNode(AST_LT, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_LE attr basic_expr { + $$ = new AstNode(AST_LE, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_EQ attr basic_expr { + $$ = new AstNode(AST_EQ, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_NE attr basic_expr { + $$ = new AstNode(AST_NE, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_EQX attr basic_expr { + $$ = new AstNode(AST_EQX, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_NEX attr basic_expr { + $$ = new AstNode(AST_NEX, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_GE attr basic_expr { + $$ = new AstNode(AST_GE, $1, $4); + append_attr($$, $3); + } | + basic_expr '>' attr basic_expr { + $$ = new AstNode(AST_GT, $1, $4); + append_attr($$, $3); + } | + basic_expr '+' attr basic_expr { + $$ = new AstNode(AST_ADD, $1, $4); + append_attr($$, $3); + } | + basic_expr '-' attr basic_expr { + $$ = new AstNode(AST_SUB, $1, $4); + append_attr($$, $3); + } | + basic_expr '*' attr basic_expr { + $$ = new AstNode(AST_MUL, $1, $4); + append_attr($$, $3); + } | + basic_expr '/' attr basic_expr { + $$ = new AstNode(AST_DIV, $1, $4); + append_attr($$, $3); + } | + basic_expr '%' attr basic_expr { + $$ = new AstNode(AST_MOD, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_POW attr basic_expr { + $$ = new AstNode(AST_POW, $1, $4); + append_attr($$, $3); + } | + '+' attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_POS, $3); + append_attr($$, $2); + } | + '-' attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_NEG, $3); + append_attr($$, $2); + } | + basic_expr OP_LAND attr basic_expr { + $$ = new AstNode(AST_LOGIC_AND, $1, $4); + append_attr($$, $3); + } | + basic_expr OP_LOR attr basic_expr { + $$ = new AstNode(AST_LOGIC_OR, $1, $4); + append_attr($$, $3); + } | + '!' attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_LOGIC_NOT, $3); + append_attr($$, $2); + }; + +concat_list: + expr { + $$ = new AstNode(AST_CONCAT, $1); + } | + expr ',' concat_list { + $$ = $3; + $$->children.push_back($1); + }; + -- cgit v1.2.3 From c3e9922b5d871269bf4ee33da24318d3b5199ac3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 15 Oct 2014 01:12:53 +0200 Subject: Replaced readsome() with read() and gcount() --- frontends/verilog/preproc.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index b4e77c31b..da658410d 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -196,14 +196,16 @@ static std::string next_token(bool pass_newline = false) static void input_file(std::istream &f, std::string filename) { char buffer[513]; - int rc; insert_input(""); auto it = input_buffer.begin(); input_buffer.insert(it, "`file_push " + filename + "\n"); - while ((rc = readsome(f, buffer, sizeof(buffer)-1)) > 0) { - buffer[rc] = 0; + while (1) { + f.read(buffer, sizeof(buffer)-1); + if (f.gcount() <= 0) + break; + buffer[f.gcount()] = 0; input_buffer.insert(it, buffer); } input_buffer.insert(it, "\n`file_pop\n"); -- cgit v1.2.3 From f65e1c309fbfd0eae719270bfc8b6887c9e05d9e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 15 Oct 2014 01:14:38 +0200 Subject: Updated .gitignore file for ilang and verilog frontends --- frontends/ilang/.gitignore | 8 ++++---- frontends/verilog/.gitignore | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'frontends') diff --git a/frontends/ilang/.gitignore b/frontends/ilang/.gitignore index 72b06b0bf..43106a814 100644 --- a/frontends/ilang/.gitignore +++ b/frontends/ilang/.gitignore @@ -1,4 +1,4 @@ -lexer.cc -parser.output -parser.tab.cc -parser.tab.h +ilang_lexer.cc +ilang_parser.output +ilang_parser.tab.cc +ilang_parser.tab.h diff --git a/frontends/verilog/.gitignore b/frontends/verilog/.gitignore index 72b06b0bf..1d4ae9e5c 100644 --- a/frontends/verilog/.gitignore +++ b/frontends/verilog/.gitignore @@ -1,4 +1,4 @@ -lexer.cc -parser.output -parser.tab.cc -parser.tab.h +verilog_lexer.cc +verilog_parser.output +verilog_parser.tab.cc +verilog_parser.tab.h -- cgit v1.2.3 From 6b05a9e8075af923c67ec3bb1b74573294ac8838 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 16 Oct 2014 00:44:23 +0200 Subject: Fixed handling of invalid array access in mem2reg code --- frontends/ast/ast.h | 1 + frontends/ast/simplify.cc | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 0a4016736..56f5d888d 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -209,6 +209,7 @@ namespace AST void mem2reg_as_needed_pass1(std::map> &mem2reg_places, std::map &mem2reg_flags, std::map &proc_flags, uint32_t &status_flags); void mem2reg_as_needed_pass2(std::set &mem2reg_set, AstNode *mod, AstNode *block); + bool mem2reg_check(std::set &mem2reg_set); void meminfo(int &mem_width, int &mem_size, int &addr_bits); // additional functionality for evaluating constant functions diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 9f33ea780..7e15283c4 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2179,14 +2179,25 @@ void AstNode::mem2reg_as_needed_pass1(std::map> } } +bool AstNode::mem2reg_check(std::set &mem2reg_set) +{ + if (type != AST_IDENTIFIER || !id2ast || !mem2reg_set.count(id2ast)) + return false; + + if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1) + log_error("Invalid array access at %s:%d.\n", filename.c_str(), linenum); + + return true; +} + // actually replace memories with registers void AstNode::mem2reg_as_needed_pass2(std::set &mem2reg_set, AstNode *mod, AstNode *block) { if (type == AST_BLOCK) block = this; - if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && block != NULL && children[0]->id2ast && - mem2reg_set.count(children[0]->id2ast) > 0 && children[0]->children[0]->children[0]->type != AST_CONSTANT) + if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && block != NULL && + children[0]->mem2reg_check(mem2reg_set) && children[0]->children[0]->children[0]->type != AST_CONSTANT) { std::stringstream sstr; sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++); @@ -2242,7 +2253,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set &mem2reg_set, AstNode * type = AST_ASSIGN_EQ; } - if (type == AST_IDENTIFIER && id2ast && mem2reg_set.count(id2ast) > 0) + if (mem2reg_check(mem2reg_set)) { AstNode *bit_part_sel = NULL; if (children.size() == 2) -- cgit v1.2.3 From 3838856a9ee6debb05f39ad2c17d2eba95afd329 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 16 Oct 2014 10:31:54 +0200 Subject: Print "SystemVerilog" in "read_verilog -sv" log messages --- frontends/verilog/verilog_frontend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 1e1cd852a..23d35f682 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -257,7 +257,7 @@ struct VerilogFrontend : public Frontend { } extra_args(f, filename, args, argidx); - log("Parsing Verilog input from `%s' to AST representation.\n", filename.c_str()); + log("Parsing %s input from `%s' to AST representation.\n", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); AST::current_filename = filename; AST::set_line_num = &frontend_verilog_yyset_lineno; -- cgit v1.2.3 From fda52f05f277720e12aadb4716415ec9bff616a5 Mon Sep 17 00:00:00 2001 From: William Speirs Date: Tue, 14 Oct 2014 17:16:50 -0400 Subject: Wrapped math in int constructor --- frontends/ast/simplify.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 7e15283c4..70976b68b 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1123,7 +1123,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); - result_width = abs(left_at_zero_ast->integer - right_at_zero_ast->integer) + 1; + result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; } did_something = true; newNode = new AstNode(AST_CASE, shift_expr); -- cgit v1.2.3 From 31267a1ae8d670c4b8749fc55b07c01d9285a488 Mon Sep 17 00:00:00 2001 From: William Speirs Date: Thu, 16 Oct 2014 12:06:54 -0400 Subject: Header changes so it will compile on VS --- frontends/verific/verific.cc | 7 +++++-- frontends/vhdl2verilog/vhdl2verilog.cc | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) (limited to 'frontends') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5e1894cfd..44dfba0a8 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -20,11 +20,14 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/log.h" -#include #include #include #include -#include + +#ifndef _WIN32 +# include +# include +#endif USING_YOSYS_NAMESPACE diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index 39b4f1496..82ff7b502 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -20,14 +20,17 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" -#include #include #include #include -#include #include #include +#ifndef _WIN32 +# include +# include +#endif + YOSYS_NAMESPACE_BEGIN struct Vhdl2verilogPass : public Pass { -- cgit v1.2.3 From 84ffe04075bbddfd1b288295c07d036416923c3a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 18 Oct 2014 15:20:38 +0200 Subject: Fixed various VS warnings --- frontends/ast/simplify.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 70976b68b..e2d63de60 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2457,7 +2457,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) } log_assert(block != NULL); - log_assert(variables.count(str)); + log_assert(variables.count(str) != 0); while (!block->children.empty()) { -- cgit v1.2.3 From de8adb8ec538913b93662198cf12c0f2a3b72630 Mon Sep 17 00:00:00 2001 From: Parviz Palangpour Date: Sat, 18 Oct 2014 14:26:49 -0500 Subject: Builds on Mac 10.9.2 with LLVM 3.5. --- frontends/ast/ast.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 87b073ff3..e41416efc 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -32,7 +32,12 @@ #include #include + +#if defined(__APPLE__) +#include +#else #include +#endif YOSYS_NAMESPACE_BEGIN -- cgit v1.2.3 From 750c615e7f01d44db4a7d504024b3681a56d8a78 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 19 Oct 2014 18:42:03 +0200 Subject: minor indenting corrections --- frontends/ast/ast.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index e41416efc..7a7bd3038 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -34,9 +34,9 @@ #include #if defined(__APPLE__) -#include +# include #else -#include +# include #endif YOSYS_NAMESPACE_BEGIN -- cgit v1.2.3 From c5eb5e56b8911bb520a987761739bbb9d9328380 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 23 Oct 2014 10:47:21 +0200 Subject: Re-introduced Yosys::readsome() helper function (f.read() + f.gcount() made problems with lines > 16kB) --- frontends/ilang/ilang_lexer.l | 6 +----- frontends/verilog/preproc.cc | 8 +++----- frontends/verilog/verilog_lexer.l | 6 +----- 3 files changed, 5 insertions(+), 15 deletions(-) (limited to 'frontends') diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l index dcbc6b6d7..ace992fbd 100644 --- a/frontends/ilang/ilang_lexer.l +++ b/frontends/ilang/ilang_lexer.l @@ -35,11 +35,7 @@ USING_YOSYS_NAMESPACE #define YY_INPUT(buf,result,max_size) \ - do { \ - ILANG_FRONTEND::lexin->read(buf, max_size-1); \ - result = ILANG_FRONTEND::lexin->gcount(); \ - if (result >= 0) buf[result] = '\0'; \ - } while (0) + result = readsome(*ILANG_FRONTEND::lexin, buf, max_size) %} diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index da658410d..b4e77c31b 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -196,16 +196,14 @@ static std::string next_token(bool pass_newline = false) static void input_file(std::istream &f, std::string filename) { char buffer[513]; + int rc; insert_input(""); auto it = input_buffer.begin(); input_buffer.insert(it, "`file_push " + filename + "\n"); - while (1) { - f.read(buffer, sizeof(buffer)-1); - if (f.gcount() <= 0) - break; - buffer[f.gcount()] = 0; + while ((rc = readsome(f, buffer, sizeof(buffer)-1)) > 0) { + buffer[rc] = 0; input_buffer.insert(it, buffer); } input_buffer.insert(it, "\n`file_pop\n"); diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 0d28e2e7f..ae16ebf78 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -64,11 +64,7 @@ YOSYS_NAMESPACE_END return TOK_ID; #define YY_INPUT(buf,result,max_size) \ - do { \ - lexin->read(buf, max_size-1); \ - result = lexin->gcount(); \ - if (result >= 0) buf[result] = '\0'; \ - } while (0) + result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size) %} -- cgit v1.2.3 From 26cbe4a4e56c0b95483b7568914d0402ef955b72 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 25 Oct 2014 18:23:53 +0200 Subject: Fixed constant "cond ? string1 : string2" with strings of different size --- frontends/ast/ast.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 7a7bd3038..56ea64eff 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -706,6 +706,8 @@ AstNode *AstNode::mkconst_bits(const std::vector &v, bool is_signe AstNode *AstNode::mkconst_str(const std::vector &v) { AstNode *node = mkconst_str(RTLIL::Const(v).decode_string()); + while (GetSize(node->bits) < GetSize(v)) + node->bits.push_back(RTLIL::State::S0); log_assert(node->bits == v); return node; } -- cgit v1.2.3 From 70b2efdb05f24eb7a9f3e2f456e5452fff94a15e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 26 Oct 2014 20:33:10 +0100 Subject: Added support for $readmemh/$readmemb --- frontends/ast/ast.h | 1 + frontends/ast/simplify.cc | 112 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) (limited to 'frontends') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 56f5d888d..023755387 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -204,6 +204,7 @@ namespace AST // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc. // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL() bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param); + AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr); void expand_genblock(std::string index_var, std::string prefix, std::map &name_map); void replace_ids(const std::string &prefix, const std::map &rules); void mem2reg_as_needed_pass1(std::map> &mem2reg_places, diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index e2d63de60..f16c3d067 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -28,10 +28,12 @@ #include "kernel/log.h" #include "libs/sha1/sha1.h" +#include "frontends/verilog/verilog_frontend.h" #include "ast.h" #include #include +#include #include YOSYS_NAMESPACE_BEGIN @@ -1480,6 +1482,44 @@ skip_dynamic_range_lvalue_expansion:; log_error("Can't resolve function name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum); } if (type == AST_TCALL) { + if (str == "\\$readmemh" || str == "\\$readmemb") + { + if (GetSize(children) < 2 || GetSize(children) > 4) + log_error("System function %s got %d arguments, expected 2-4 at %s:%d.\n", + RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + + AstNode *node_filename = children[0]->clone(); + while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + if (node_filename->type != AST_CONSTANT) + log_error("Failed to evaluate system function `%s' with non-constant 1st argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + + AstNode *node_memory = children[1]->clone(); + while (node_memory->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY) + log_error("Failed to evaluate system function `%s' with non-memory 2nd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + + int start_addr = -1, finish_addr = -1; + + if (GetSize(children) > 2) { + AstNode *node_addr = children[2]->clone(); + while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + if (node_addr->type != AST_CONSTANT) + log_error("Failed to evaluate system function `%s' with non-constant 3rd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + start_addr = node_addr->asInt(false); + } + + if (GetSize(children) > 3) { + AstNode *node_addr = children[3]->clone(); + while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + if (node_addr->type != AST_CONSTANT) + log_error("Failed to evaluate system function `%s' with non-constant 4th argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + finish_addr = node_addr->asInt(false); + } + + newNode = readmem(str == "\\$readmemh", node_filename->bitsAsConst().decode_string(), node_memory->id2ast, start_addr, finish_addr); + goto apply_newNode; + } + if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK) log_error("Can't resolve task name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum); } @@ -1988,6 +2028,78 @@ static void replace_result_wire_name_in_function(AstNode *node, std::string &fro node->str = to; } +// replace a readmem[bh] TCALL ast node with a block of memory assignments +AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr) +{ + AstNode *block = new AstNode(AST_BLOCK); + + std::ifstream f; + f.open(mem_filename.c_str()); + + if (f.fail()) + log_error("Can not open file `%s` for %s at %s:%d.\n", mem_filename.c_str(), str.c_str(), filename.c_str(), linenum); + + // log_assert(GetSize(memory->children) == 2 && memory->children[0]->type == AST_RANGE && memory->children[0]->range_valid); + // int wordsize_left = memory->children[0]->range_left, wordsize_right = memory->children[0]->range_right; + // int wordsize = std::max(wordsize_left, wordsize_right) - std::min(wordsize_left, wordsize_right) + 1; + + bool in_comment = false; + int increment = (start_addr < finish_addr) || (start_addr < 0) || (finish_addr < 0) ? +1 : -1; + int cursor = start_addr < 0 ? 0 : start_addr; + + while (!f.eof()) + { + std::string line, token; + std::getline(f, line); + + for (int i = 0; i < GetSize(line); i++) { + if (in_comment && line.substr(i, 2) == "*/") { + line[i] = ' '; + line[i+1] = ' '; + in_comment = false; + continue; + } + if (!in_comment && line.substr(i, 2) == "/*") + in_comment = true; + if (in_comment) + line[i] = ' '; + } + + while (1) + { + token = next_token(line, " \t\r\n"); + if (token.empty() || token.substr(0, 2) == "//") + break; + + if (token[0] == '@') { + token = token.substr(1); + const char *nptr = token.c_str(); + char *endptr; + cursor = strtol(nptr, &endptr, 16); + if (!*nptr || *endptr) + log_error("Can not parse address `%s` for %s at %s:%d.\n", nptr, str.c_str(), filename.c_str(), linenum); + continue; + } + + AstNode *value = VERILOG_FRONTEND::const2ast((is_readmemh ? "'h" : "'b") + token); + + block->children.push_back(new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER, new AstNode(AST_RANGE, AstNode::mkconst_int(cursor, false))), value)); + block->children.back()->children[0]->str = memory->str; + block->children.back()->children[0]->id2ast = memory; + + if (cursor == finish_addr) + break; + cursor += increment; + } + + if (cursor == finish_addr) + break; + } + + // fixme + return block; +} + // annotate the names of all wires and other named objects in a generate block void AstNode::expand_genblock(std::string index_var, std::string prefix, std::map &name_map) { -- cgit v1.2.3 From c4a2b3c1e9be01a0b7cf7d2cc8b91aea72d7830c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 26 Oct 2014 23:29:36 +0100 Subject: Improvements in $readmem[bh] implementation --- frontends/ast/simplify.cc | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index f16c3d067..75a2a2364 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2039,13 +2039,19 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m if (f.fail()) log_error("Can not open file `%s` for %s at %s:%d.\n", mem_filename.c_str(), str.c_str(), filename.c_str(), linenum); - // log_assert(GetSize(memory->children) == 2 && memory->children[0]->type == AST_RANGE && memory->children[0]->range_valid); - // int wordsize_left = memory->children[0]->range_left, wordsize_right = memory->children[0]->range_right; - // int wordsize = std::max(wordsize_left, wordsize_right) - std::min(wordsize_left, wordsize_right) + 1; + log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid); + int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right; + int range_min = std::min(range_left, range_right), range_max = std::max(range_left, range_right); + + if (start_addr < 0) + start_addr = range_min; + + if (finish_addr < 0) + finish_addr = range_max; bool in_comment = false; - int increment = (start_addr < finish_addr) || (start_addr < 0) || (finish_addr < 0) ? +1 : -1; - int cursor = start_addr < 0 ? 0 : start_addr; + int increment = start_addr <= finish_addr ? +1 : -1; + int cursor = start_addr; while (!f.eof()) { @@ -2087,16 +2093,15 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m block->children.back()->children[0]->str = memory->str; block->children.back()->children[0]->id2ast = memory; - if (cursor == finish_addr) + if ((cursor == finish_addr) || (increment > 0 && cursor >= range_max) || (increment < 0 && cursor <= range_min)) break; cursor += increment; } - if (cursor == finish_addr) + if ((cursor == finish_addr) || (increment > 0 && cursor >= range_max) || (increment < 0 && cursor <= range_min)) break; } - // fixme return block; } -- cgit v1.2.3 From f9c096eedabdf7cd2cdd770da73bdd17d86559e7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 27 Oct 2014 13:21:57 +0100 Subject: Added support for task and function args in parentheses --- frontends/verilog/verilog_parser.y | 51 +++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index cf02a56a9..e1304bff2 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -449,7 +449,7 @@ task_func_decl: } opt_dpi_function_args ';' { current_function_or_task = NULL; } | - attr TOK_TASK TOK_ID ';' { + attr TOK_TASK TOK_ID { current_function_or_task = new AstNode(AST_TASK); current_function_or_task->str = *$3; append_attr(current_function_or_task, $1); @@ -457,11 +457,11 @@ task_func_decl: ast_stack.push_back(current_function_or_task); current_function_or_task_port_id = 1; delete $3; - } task_func_body TOK_ENDTASK { + } task_func_args_opt ';' task_func_body TOK_ENDTASK { current_function_or_task = NULL; ast_stack.pop_back(); } | - attr TOK_FUNCTION opt_signed range_or_signed_int TOK_ID ';' { + attr TOK_FUNCTION opt_signed range_or_signed_int TOK_ID { current_function_or_task = new AstNode(AST_FUNCTION); current_function_or_task->str = *$5; append_attr(current_function_or_task, $1); @@ -478,7 +478,7 @@ task_func_decl: current_function_or_task->children.push_back(outreg); current_function_or_task_port_id = 1; delete $5; - } task_func_body TOK_ENDFUNCTION { + } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION { current_function_or_task = NULL; ast_stack.pop_back(); }; @@ -512,6 +512,45 @@ opt_signed: $$ = false; }; +task_func_args_opt: + '(' ')' | /* empty */ | '(' { + albuf = nullptr; + astbuf1 = nullptr; + astbuf2 = nullptr; + } task_func_args optional_comma { + delete astbuf1; + if (astbuf2 != NULL) + delete astbuf2; + free_attr(albuf); + } ')'; + +task_func_args: + task_func_port | task_func_args ',' task_func_port; + +task_func_port: + attr wire_type range { + if (albuf) { + delete astbuf1; + if (astbuf2 != NULL) + delete astbuf2; + free_attr(albuf); + } + albuf = $1; + astbuf1 = $2; + astbuf2 = $3; + if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { + if (astbuf2) { + frontend_verilog_yyerror("Syntax error."); + } else { + astbuf2 = new AstNode(AST_RANGE); + astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true)); + astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true)); + } + } + if (astbuf2 && astbuf2->children.size() != 2) + frontend_verilog_yyerror("Syntax error."); + } wire_name | wire_name; + task_func_body: task_func_body behavioral_stmt | /* empty */; @@ -609,12 +648,12 @@ wire_decl: } if (astbuf2 && astbuf2->children.size() != 2) frontend_verilog_yyerror("Syntax error."); - } wire_name_list ';' { + } wire_name_list { delete astbuf1; if (astbuf2 != NULL) delete astbuf2; free_attr(albuf); - } | + } ';' | attr TOK_SUPPLY0 TOK_ID ';' { ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); ast_stack.back()->children.back()->str = *$3; -- cgit v1.2.3 From 37aa2e02db2f3070a153a1de04c0ce99d1369adb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 29 Oct 2014 08:29:51 +0100 Subject: AST simplifier: optimize constant AST_CASE nodes before recursively descending --- frontends/ast/simplify.cc | 66 +++++++++++++++++++++++++---------------------- 1 file changed, 35 insertions(+), 31 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 75a2a2364..d8fdb4c5e 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -384,6 +384,41 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } } + if (const_fold && type == AST_CASE) + { + while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { } + if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { + std::vector new_children; + new_children.push_back(children[0]); + for (int i = 1; i < GetSize(children); i++) { + AstNode *child = children[i]; + log_assert(child->type == AST_COND); + for (auto v : child->children) { + if (v->type == AST_DEFAULT) + goto keep_const_cond; + if (v->type == AST_BLOCK) + continue; + while (v->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { } + if (v->type == AST_CONSTANT && v->bits_only_01()) { + if (v->bits == children[0]->bits) { + while (i+1 < GetSize(children)) + delete children[++i]; + goto keep_const_cond; + } + continue; + } + goto keep_const_cond; + } + if (0) + keep_const_cond: + new_children.push_back(child); + else + delete child; + } + new_children.swap(children); + } + } + // simplify all children first // (iterate by index as e.g. auto wires can add new children in the process) for (size_t i = 0; i < children.size(); i++) { @@ -1883,37 +1918,6 @@ skip_dynamic_range_lvalue_expansion:; newNode->realvalue = -children[0]->asReal(sign_hint); } break; - case AST_CASE: - if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { - std::vector new_children; - new_children.push_back(children[0]); - for (int i = 1; i < GetSize(children); i++) { - AstNode *child = children[i]; - log_assert(child->type == AST_COND); - for (auto v : child->children) { - if (v->type == AST_DEFAULT) - goto keep_const_cond; - if (v->type == AST_BLOCK) - continue; - if (v->type == AST_CONSTANT && v->bits_only_01()) { - if (v->bits == children[0]->bits) { - while (i+1 < GetSize(children)) - delete children[++i]; - goto keep_const_cond; - } - continue; - } - goto keep_const_cond; - } - if (0) - keep_const_cond: - new_children.push_back(child); - else - delete child; - } - new_children.swap(children); - } - break; case AST_TERNARY: if (children[0]->isConst()) { -- cgit v1.2.3 From a21481b338933f9498fd0fb11492aa2e5b7a00cd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 30 Oct 2014 14:01:02 +0100 Subject: Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." --- frontends/verilog/verilog_parser.y | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e1304bff2..0902e58a2 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -240,7 +240,7 @@ module: }; module_para_opt: - '#' '(' module_para_list ')' | /* empty */; + '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */; module_para_list: single_module_para | @@ -249,11 +249,10 @@ module_para_list: single_module_para: TOK_PARAMETER { + if (astbuf1) delete astbuf1; astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); - } param_signed param_integer param_range single_param_decl { - delete astbuf1; - }; + } param_signed param_integer param_range single_param_decl | single_param_decl; module_args_opt: '(' ')' | /* empty */ | '(' module_args optional_comma ')'; @@ -607,6 +606,8 @@ param_decl_list: single_param_decl: TOK_ID '=' expr { + if (astbuf1 == nullptr) + frontend_verilog_yyerror("syntax error"); AstNode *node = astbuf1->clone(); node->str = *$1; delete node->children[0]; -- cgit v1.2.3 From acf010d30d650aef500952d5de4ea5ec939d78a0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 8 Nov 2014 11:38:44 +0100 Subject: Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions --- frontends/verific/build_amd64.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends') diff --git a/frontends/verific/build_amd64.txt b/frontends/verific/build_amd64.txt index 94615d38d..9bb6e3203 100644 --- a/frontends/verific/build_amd64.txt +++ b/frontends/verific/build_amd64.txt @@ -10,6 +10,7 @@ CONFIG := clang ENABLE_TCL := 0 ENABLE_QT4 := 0 ENABLE_ABC := 0 +ENABLE_PLUGINS := 0 ENABLE_VERIFIC := 1 CXXFLAGS += -m32 LDFLAGS += -m32 -- cgit v1.2.3 From fe829bdbdc436f425e082ab1cc8c3d276f168945 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 9 Nov 2014 10:44:23 +0100 Subject: Added log_warning() API --- frontends/ast/genrtlil.cc | 12 ++++++------ frontends/ast/simplify.cc | 8 ++++---- frontends/verific/verific.cc | 2 +- frontends/verilog/verilog_lexer.l | 12 ++++++------ 4 files changed, 17 insertions(+), 17 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 68c45179d..4a102370b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -869,7 +869,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_REALVALUE: { RTLIL::SigSpec sig = realAsConst(width_hint); - log("Warning: converting real value %e to binary %s at %s:%d.\n", + log_warning("converting real value %e to binary %s at %s:%d.\n", realvalue, log_signal(sig), filename.c_str(), linenum); return sig; } @@ -890,7 +890,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->name = str; if (flag_autowire) - log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); else log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum); } @@ -955,10 +955,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width); if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) { if (chunk.width == 1) - log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n", + log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n", str.c_str(), filename.c_str(), linenum); else - log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n", + log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n", str.c_str(), filename.c_str(), linenum, chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); } else { @@ -972,10 +972,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset += add_undef_bits_lsb; } if (add_undef_bits_lsb) - log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n", + log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n", str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb); if (add_undef_bits_msb) - log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n", + log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n", str.c_str(), filename.c_str(), linenum, add_undef_bits_msb); } } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index d8fdb4c5e..a78fafbd1 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -102,7 +102,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, verbose_activate: if (mem2reg_set.count(mem) == 0) { - log("Warning: Replacing memory %s with list of registers.", mem->str.c_str()); + log_warning("Replacing memory %s with list of registers.", mem->str.c_str()); bool first_element = true; for (auto &place : mem2reg_places[it.first]) { log("%s%s", first_element ? " See " : ", ", place.c_str()); @@ -648,7 +648,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width = children[1]->range_left - children[1]->range_right + 1; if (children[0]->type == AST_REALVALUE) { RTLIL::Const constvalue = children[0]->realAsConst(width); - log("Warning: converting real value %e to binary %s at %s:%d.\n", + log_warning("converting real value %e to binary %s at %s:%d.\n", children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum); delete children[0]; children[0] = mkconst_bits(constvalue.bits, sign_hint); @@ -690,7 +690,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } } if (current_scope.count(str) == 0) { - // log("Warning: Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str()); + // log_warning("Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str()); AstNode *auto_wire = new AstNode(AST_AUTOWIRE); auto_wire->str = str; current_ast_mod->children.push_back(auto_wire); @@ -1260,7 +1260,7 @@ skip_dynamic_range_lvalue_expansion:; std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN"; if (type == AST_ASSIGN_EQ) - log("Warning: Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n", + log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n", filename.c_str(), linenum); int mem_width, mem_size, addr_bits; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 44dfba0a8..79abcf245 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -730,7 +730,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::setIsOperator()) - log("Warning: Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name()); + log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name()); } else { if (import_netlist_instance_gates(module, net_map, inst)) continue; diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index ae16ebf78..5e739842b 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -254,8 +254,8 @@ supply1 { return TOK_SUPPLY1; } } "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" { - log("Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"); - log("It is strongly suggested to use `ifdef constructs instead!\n"); + log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n" + "It is strongly suggested to use `ifdef constructs instead!\n"); BEGIN(SYNOPSYS_TRANSLATE_OFF); } . /* ignore synopsys translate_off body */ @@ -266,13 +266,13 @@ supply1 { return TOK_SUPPLY1; } BEGIN(SYNOPSYS_FLAGS); } full_case { - log("Warning: Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"); - log("It is strongly suggested to use verilog x-values and default branches instead!\n"); + log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n" + "It is strongly suggested to use verilog x-values and default branches instead!\n"); return TOK_SYNOPSYS_FULL_CASE; } parallel_case { - log("Warning: Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"); - log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n"); + log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n" + "It is strongly suggested to use verilog `parallel_case' attributes instead!\n"); return TOK_SYNOPSYS_PARALLEL_CASE; } . /* ignore everything else */ -- cgit v1.2.3 From 4e5350b409877ecc804cb3ee9a8ab0cb1a3773d9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 12 Nov 2014 19:10:35 +0100 Subject: Fixed parsing of nested verilog concatenation and replicate --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 0902e58a2..e40bc188b 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1321,7 +1321,7 @@ basic_expr: '{' concat_list '}' { $$ = $2; } | - '{' expr '{' expr '}' '}' { + '{' expr '{' concat_list '}' '}' { $$ = new AstNode(AST_REPLICATE, $2, $4); } | '~' attr basic_expr %prec UNARY_OPS { -- cgit v1.2.3 From 87333f3ae236555ac1efb38b5e99b5f067900ddd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Nov 2014 19:59:50 +0100 Subject: Added warning for use of 'z' constants in HDL --- frontends/verilog/const2ast.cc | 10 +++++++++- frontends/verilog/verilog_frontend.h | 2 +- frontends/verilog/verilog_parser.y | 8 ++++---- 3 files changed, 14 insertions(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index a81e3010f..ca995915f 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -132,8 +132,16 @@ static void my_strtobin(std::vector &data, const char *str, int le } // convert the verilog code for a constant to an AST node -AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type) +AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn_z) { + if (warn_z) { + AstNode *ret = const2ast(code, case_type); + if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) + log_warning("Yosys does not support tri-state logic at the moment. (%s:%d)\n", + current_filename.c_str(), frontend_verilog_yyget_lineno()); + return ret; + } + const char *str = code.c_str(); // Strings diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index af6495f8f..e277f3e3c 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -43,7 +43,7 @@ namespace VERILOG_FRONTEND extern struct AST::AstNode *current_ast; // this function converts a Verilog constant to an AST_CONSTANT node - AST::AstNode *const2ast(std::string code, char case_type = 0); + AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false); // state of `default_nettype extern bool default_nettype_wire; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e40bc188b..75af46522 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1251,7 +1251,7 @@ basic_expr: if ($4->substr(0, 1) != "'") frontend_verilog_yyerror("Syntax error."); AstNode *bits = $2; - AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), true); if (val == NULL) log_error("Value conversion failed: `%s'\n", $4->c_str()); $$ = new AstNode(AST_TO_BITS, bits, val); @@ -1262,7 +1262,7 @@ basic_expr: frontend_verilog_yyerror("Syntax error."); AstNode *bits = new AstNode(AST_IDENTIFIER); bits->str = *$1; - AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), true); if (val == NULL) log_error("Value conversion failed: `%s'\n", $2->c_str()); $$ = new AstNode(AST_TO_BITS, bits, val); @@ -1270,14 +1270,14 @@ basic_expr: delete $2; } | TOK_CONST TOK_CONST { - $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), true); if ($$ == NULL || (*$2)[0] != '\'') log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str()); delete $1; delete $2; } | TOK_CONST { - $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), true); if ($$ == NULL) log_error("Value conversion failed: `%s'\n", $1->c_str()); delete $1; -- cgit v1.2.3 From 56c7d1e266cf6b2f9bfcb9f76f2ddf388ddc51ea Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 24 Nov 2014 14:39:24 +0100 Subject: Fixed two minor bugs in constant parsing --- frontends/verilog/const2ast.cc | 6 +++++- frontends/verilog/verilog_lexer.l | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index ca995915f..735bc5f99 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -182,7 +182,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn if (str == endptr) len_in_bits = -1; - // The "'s?[bodh]" syntax + // The "'s?[bodhBODH]" syntax if (*endptr == '\'') { std::vector data; @@ -194,15 +194,19 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn switch (*(endptr+1)) { case 'b': + case 'B': my_strtobin(data, endptr+2, len_in_bits, 2, case_type); break; case 'o': + case 'O': my_strtobin(data, endptr+2, len_in_bits, 8, case_type); break; case 'd': + case 'D': my_strtobin(data, endptr+2, len_in_bits, 10, case_type); break; case 'h': + case 'H': my_strtobin(data, endptr+2, len_in_bits, 16, case_type); break; default: diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 5e739842b..c3dfa8b92 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -177,12 +177,12 @@ YOSYS_NAMESPACE_END "genvar" { return TOK_GENVAR; } "real" { return TOK_REAL; } -[0-9]+ { +[0-9][0-9_]* { frontend_verilog_yylval.string = new std::string(yytext); return TOK_CONST; } -[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ { +[0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ { frontend_verilog_yylval.string = new std::string(yytext); return TOK_CONST; } -- cgit v1.2.3 From 76c83283c44267969b96dc53bf02775aa950b5be Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 24 Nov 2014 14:48:07 +0100 Subject: Fixed minor bug in parsing delays --- frontends/verilog/verilog_lexer.l | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index c3dfa8b92..74a66d964 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -342,7 +342,10 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { [ \t\r\n] /* ignore whitespaces */ \\[\r\n] /* ignore continuation sequence */ "//"[^\r\n]* /* ignore one-line comments */ -"#"[$a-zA-Z_0-9\.]+ /* ignore simulation timings */ + +"#"\ *[0-9][0-9_]* /* ignore simulation timings */ +"#"\ *[0-9][0-9_]*\.[0-9][0-9_]* /* ignore simulation timings */ +"#"\ *[$a-zA-Z_\.][$a-zA-Z_0-9\.]* /* ignore simulation timings */ . { return *yytext; } -- cgit v1.2.3 From 1282a113da11351dbac2b9df53e3e430d12def4a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 11 Dec 2014 13:56:20 +0100 Subject: Fixed supply0/supply1 with many wires --- frontends/verilog/verilog_parser.y | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 75af46522..621b6cc18 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -655,21 +655,33 @@ wire_decl: delete astbuf2; free_attr(albuf); } ';' | - attr TOK_SUPPLY0 TOK_ID ';' { + attr TOK_SUPPLY0 TOK_ID { ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); ast_stack.back()->children.back()->str = *$3; append_attr(ast_stack.back()->children.back(), $1); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1))); ast_stack.back()->children.back()->children[0]->str = *$3; delete $3; - } | - attr TOK_SUPPLY1 TOK_ID ';' { + } opt_supply_wires ';' | + attr TOK_SUPPLY1 TOK_ID { ast_stack.back()->children.push_back(new AstNode(AST_WIRE)); ast_stack.back()->children.back()->str = *$3; append_attr(ast_stack.back()->children.back(), $1); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1))); ast_stack.back()->children.back()->children[0]->str = *$3; delete $3; + } opt_supply_wires ';'; + +opt_supply_wires: + /* empty */ | + opt_supply_wires ',' TOK_ID { + AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone(); + AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone(); + wire_node->str = *$3; + assign_node->children[0]->str = *$3; + ast_stack.back()->children.push_back(wire_node); + ast_stack.back()->children.push_back(assign_node); + delete $3; }; wire_name_list: -- cgit v1.2.3 From edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 24 Dec 2014 09:51:17 +0100 Subject: Renamed extend() to extend_xx(), changed most users to extend_u0() --- frontends/ast/genrtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 4a102370b..238da2634 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -73,7 +73,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed) { if (width <= sig.size()) { - sig.extend(width, is_signed); + sig.extend_u0(width, is_signed); return; } -- cgit v1.2.3 From a6c96b986be313368b4fa03eba5cf6987448100c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 26 Dec 2014 10:53:21 +0100 Subject: Added Yosys::{dict,nodict,vector} container types --- frontends/ast/ast.cc | 2 +- frontends/ast/ast.h | 2 +- frontends/ilang/ilang_parser.y | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 56ea64eff..0f79352f7 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1018,7 +1018,7 @@ AstModule::~AstModule() } // create a new parametric module (when needed) and return the name of the generated module -RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map parameters) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict parameters) { std::string stripped_name = name.str(); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 023755387..27cf0ef3d 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -268,7 +268,7 @@ namespace AST AstNode *ast; bool nolatches, nomem2reg, mem2reg, lib, noopt, icells, autowire; virtual ~AstModule(); - virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters); virtual RTLIL::Module *clone() const; }; diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y index a5cc06898..4e0981b51 100644 --- a/frontends/ilang/ilang_parser.y +++ b/frontends/ilang/ilang_parser.y @@ -36,7 +36,7 @@ namespace ILANG_FRONTEND { RTLIL::Process *current_process; std::vector*> switch_stack; std::vector case_stack; - std::map attrbuf; + dict attrbuf; } using namespace ILANG_FRONTEND; YOSYS_NAMESPACE_END -- cgit v1.2.3 From 12ca6538a4e429ef318f47b5bb07f6a2a8dd2538 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 27 Dec 2014 03:26:30 +0100 Subject: Fixed mem2reg warning message --- frontends/ast/simplify.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index a78fafbd1..b76701943 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -102,13 +102,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, verbose_activate: if (mem2reg_set.count(mem) == 0) { - log_warning("Replacing memory %s with list of registers.", mem->str.c_str()); + std::string message = stringf("Replacing memory %s with list of registers.", mem->str.c_str()); bool first_element = true; for (auto &place : mem2reg_places[it.first]) { - log("%s%s", first_element ? " See " : ", ", place.c_str()); + message += stringf("%s%s", first_element ? " See " : ", ", place.c_str()); first_element = false; } - log("\n"); + log_warning("%s\n", message.c_str()); } silent_activate: -- cgit v1.2.3 From 7751c491fb08eccb13f2b5f5609d3fd6d2a8ffef Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 27 Dec 2014 03:40:27 +0100 Subject: Improved some warning messages --- frontends/verilog/verilog_lexer.l | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 74a66d964..42b5bf7ea 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -254,8 +254,12 @@ supply1 { return TOK_SUPPLY1; } } "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" { - log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n" - "It is strongly suggested to use `ifdef constructs instead!\n"); + static bool printed_warning = false; + if (!printed_warning) { + log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n" + "Yosys does support them but it is recommended to use `ifdef constructs instead!\n"); + printed_warning = true; + } BEGIN(SYNOPSYS_TRANSLATE_OFF); } . /* ignore synopsys translate_off body */ @@ -266,13 +270,21 @@ supply1 { return TOK_SUPPLY1; } BEGIN(SYNOPSYS_FLAGS); } full_case { - log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n" - "It is strongly suggested to use verilog x-values and default branches instead!\n"); + static bool printed_warning = false; + if (!printed_warning) { + log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n" + "Yosys does support them but it is recommended to use verilog `full_case' attributes instead!\n"); + printed_warning = true; + } return TOK_SYNOPSYS_FULL_CASE; } parallel_case { - log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n" - "It is strongly suggested to use verilog `parallel_case' attributes instead!\n"); + static bool printed_warning = false; + if (!printed_warning) { + log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n" + "Yosys does support them but it is recommended to use verilog `parallel_case' attributes instead!\n"); + printed_warning = true; + } return TOK_SYNOPSYS_PARALLEL_CASE; } . /* ignore everything else */ -- cgit v1.2.3 From 137f35373f4ef0d1ddf212187e537e48d077b1f4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 28 Dec 2014 19:24:24 +0100 Subject: Changed more code to dict<> and pool<> --- frontends/ast/ast.cc | 2 +- frontends/ast/ast.h | 4 ++-- frontends/ast/genrtlil.cc | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 0f79352f7..8ef60079b 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -56,7 +56,7 @@ namespace AST_INTERNAL { bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; AstNode *current_ast, *current_ast_mod; std::map current_scope; - const std::map *genRTLIL_subst_ptr = NULL; + const dict *genRTLIL_subst_ptr = NULL; RTLIL::SigSpec ignoreThisSignalsInInitial; AstNode *current_top_block, *current_block, *current_block_child; AstModule *current_module; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 27cf0ef3d..1a7ac576b 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -231,7 +231,7 @@ namespace AST // for expressions the resulting signal vector is returned // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false); - RTLIL::SigSpec genWidthRTLIL(int width, const std::map *new_subst_ptr = NULL); + RTLIL::SigSpec genWidthRTLIL(int width, const dict *new_subst_ptr = NULL); // compare AST nodes bool operator==(const AstNode &other) const; @@ -293,7 +293,7 @@ namespace AST_INTERNAL extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map current_scope; - extern const std::map *genRTLIL_subst_ptr; + extern const dict *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; extern AST::AstNode *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 238da2634..a86d08d56 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -254,7 +254,7 @@ struct AST_INTERNAL::ProcessGenerator // create initial assignments for the temporary signals if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) { - subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from))); + subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from))); } else { addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from); } @@ -1391,9 +1391,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or // signals must be substituted before beeing used as input values (used by ProcessGenerator) // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL(). -RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const std::map *new_subst_ptr) +RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict *new_subst_ptr) { - const std::map *backup_subst_ptr = genRTLIL_subst_ptr; + const dict *backup_subst_ptr = genRTLIL_subst_ptr; if (new_subst_ptr) genRTLIL_subst_ptr = new_subst_ptr; -- cgit v1.2.3 From 90bc71dd906935def78048e13e7c9f214af0486c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 29 Dec 2014 03:11:50 +0100 Subject: dict/pool changes in ast --- frontends/ast/ast.cc | 4 ++++ frontends/ast/ast.h | 12 ++++++++---- frontends/ast/simplify.cc | 24 ++++++++++++------------ 3 files changed, 24 insertions(+), 16 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 8ef60079b..fbb726922 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -180,6 +180,10 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id) // (the optional child arguments make it easier to create AST trees) AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2) { + static unsigned int hashidx_count = 123456789; + hashidx_count = mkhash_xorshift(hashidx_count); + hashidx_ = hashidx_count; + this->type = type; filename = current_filename; linenum = get_line_num(); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 1a7ac576b..180646267 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -142,6 +142,10 @@ namespace AST // The AST is built using instances of this struct struct AstNode { + // for dict<> and pool<> + unsigned int hashidx_; + unsigned int hash() const { return hashidx_; } + // this nodes type AstNodeType type; @@ -207,10 +211,10 @@ namespace AST AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr); void expand_genblock(std::string index_var, std::string prefix, std::map &name_map); void replace_ids(const std::string &prefix, const std::map &rules); - void mem2reg_as_needed_pass1(std::map> &mem2reg_places, - std::map &mem2reg_flags, std::map &proc_flags, uint32_t &status_flags); - void mem2reg_as_needed_pass2(std::set &mem2reg_set, AstNode *mod, AstNode *block); - bool mem2reg_check(std::set &mem2reg_set); + void mem2reg_as_needed_pass1(dict> &mem2reg_places, + dict &mem2reg_flags, dict &proc_flags, uint32_t &status_flags); + void mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, AstNode *block); + bool mem2reg_check(pool &mem2reg_set); void meminfo(int &mem_width, int &mem_size, int &addr_bits); // additional functionality for evaluating constant functions diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index b76701943..2ce2d57dc 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -67,12 +67,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (!flag_nomem2reg && !get_bool_attribute("\\nomem2reg")) { - std::map> mem2reg_places; - std::map mem2reg_candidates, dummy_proc_flags; + dict> mem2reg_places; + dict mem2reg_candidates, dummy_proc_flags; uint32_t flags = flag_mem2reg ? AstNode::MEM2REG_FL_ALL : 0; mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, dummy_proc_flags, flags); - std::set mem2reg_set; + pool mem2reg_set; for (auto &it : mem2reg_candidates) { AstNode *mem = it.first; @@ -2184,8 +2184,8 @@ void AstNode::replace_ids(const std::string &prefix, const std::map> &mem2reg_places, - std::map &mem2reg_candidates, AstNode *that) +static void mark_memories_assign_lhs_complex(dict> &mem2reg_places, + dict &mem2reg_candidates, AstNode *that) { for (auto &child : that->children) mark_memories_assign_lhs_complex(mem2reg_places, mem2reg_candidates, child); @@ -2199,8 +2199,8 @@ static void mark_memories_assign_lhs_complex(std::map> &mem2reg_places, - std::map &mem2reg_candidates, std::map &proc_flags, uint32_t &flags) +void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg_places, + dict &mem2reg_candidates, dict &proc_flags, uint32_t &flags) { uint32_t children_flags = 0; int ignore_children_counter = 0; @@ -2262,7 +2262,7 @@ void AstNode::mem2reg_as_needed_pass1(std::map> if (type == AST_MODULE && get_bool_attribute("\\mem2reg")) children_flags |= AstNode::MEM2REG_FL_ALL; - std::map *proc_flags_p = NULL; + dict *proc_flags_p = NULL; if (type == AST_ALWAYS) { int count_edge_events = 0; @@ -2271,12 +2271,12 @@ void AstNode::mem2reg_as_needed_pass1(std::map> count_edge_events++; if (count_edge_events != 1) children_flags |= AstNode::MEM2REG_FL_ASYNC; - proc_flags_p = new std::map; + proc_flags_p = new dict; } if (type == AST_INITIAL) { children_flags |= AstNode::MEM2REG_FL_INIT; - proc_flags_p = new std::map; + proc_flags_p = new dict; } uint32_t backup_flags = flags; @@ -2300,7 +2300,7 @@ void AstNode::mem2reg_as_needed_pass1(std::map> } } -bool AstNode::mem2reg_check(std::set &mem2reg_set) +bool AstNode::mem2reg_check(pool &mem2reg_set) { if (type != AST_IDENTIFIER || !id2ast || !mem2reg_set.count(id2ast)) return false; @@ -2312,7 +2312,7 @@ bool AstNode::mem2reg_check(std::set &mem2reg_set) } // actually replace memories with registers -void AstNode::mem2reg_as_needed_pass2(std::set &mem2reg_set, AstNode *mod, AstNode *block) +void AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, AstNode *block) { if (type == AST_BLOCK) block = this; -- cgit v1.2.3 From 0bb6b24c117fa685dce34abf82cb0f9ef73a7661 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 29 Dec 2014 14:30:33 +0100 Subject: Added global yosys_celltypes --- frontends/ast/ast.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index fbb726922..68b3327f9 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -26,7 +26,7 @@ * */ -#include "kernel/log.h" +#include "kernel/yosys.h" #include "libs/sha1/sha1.h" #include "ast.h" -- cgit v1.2.3 From eefe78be094f8009cdb4a7a0e657e86b9624adf1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 1 Jan 2015 12:56:01 +0100 Subject: Fixed memory->start_offset handling --- frontends/ast/genrtlil.cc | 13 +++++++------ frontends/ilang/ilang_parser.y | 3 +++ 2 files changed, 10 insertions(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index a86d08d56..17d62d4dd 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -839,14 +839,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); memory->name = str; memory->width = children[0]->range_left - children[0]->range_right + 1; - memory->start_offset = children[0]->range_right; - memory->size = children[1]->range_left - children[1]->range_right; + if (children[1]->range_right < children[1]->range_left) { + memory->start_offset = children[1]->range_right; + memory->size = children[1]->range_left - children[1]->range_right + 1; + } else { + memory->start_offset = children[1]->range_left; + memory->size = children[1]->range_right - children[1]->range_left + 1; + } current_module->memories[memory->name] = memory; - if (memory->size < 0) - memory->size *= -1; - memory->size += std::min(children[1]->range_left, children[1]->range_right) + 1; - for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) log_error("Attribute `%s' with non-constant value at %s:%d!\n", diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y index 4e0981b51..4661d5772 100644 --- a/frontends/ilang/ilang_parser.y +++ b/frontends/ilang/ilang_parser.y @@ -183,6 +183,9 @@ memory_options: memory_options TOK_SIZE TOK_INT { current_memory->size = $3; } | + memory_options TOK_OFFSET TOK_INT { + current_memory->start_offset = $3; + } | /* empty */; cell_stmt: -- cgit v1.2.3 From 1bd67d792eefeb7e72bf74f80776b0d5e41d771a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Jan 2015 17:11:54 +0100 Subject: Define YOSYS and SYNTHESIS in preproc --- frontends/verilog/preproc.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index b4e77c31b..4e5d16599 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -221,7 +221,8 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons input_buffer_charp = 0; input_file(f, filename); - defines_map["__YOSYS__"] = "1"; + defines_map["YOSYS"] = "1"; + defines_map["SYNTHESIS"] = "1"; while (!input_buffer.empty()) { -- cgit v1.2.3 From fff6f00b3c8704473bbb8149c82a2805fb1c32d2 Mon Sep 17 00:00:00 2001 From: Fabio Utzig Date: Thu, 8 Jan 2015 09:56:20 -0200 Subject: Enable bison to be customized --- frontends/ilang/Makefile.inc | 2 +- frontends/verilog/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/ilang/Makefile.inc b/frontends/ilang/Makefile.inc index 984d436c6..c15e2cc47 100644 --- a/frontends/ilang/Makefile.inc +++ b/frontends/ilang/Makefile.inc @@ -5,7 +5,7 @@ GENFILES += frontends/ilang/ilang_parser.output GENFILES += frontends/ilang/ilang_lexer.cc frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y - $(P) bison -d -r all -b frontends/ilang/ilang_parser frontends/ilang/ilang_parser.y + $(P) $(BISON) -d -r all -b frontends/ilang/ilang_parser frontends/ilang/ilang_parser.y $(Q) mv frontends/ilang/ilang_parser.tab.c frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_parser.tab.h: frontends/ilang/ilang_parser.tab.cc diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc index 1b6854bb5..92cbd0b87 100644 --- a/frontends/verilog/Makefile.inc +++ b/frontends/verilog/Makefile.inc @@ -5,7 +5,7 @@ GENFILES += frontends/verilog/verilog_parser.output GENFILES += frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y - $(P) bison -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y + $(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y $(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc -- cgit v1.2.3 From 8e8e791fb5dba3eb0a236cbed8c13bd5ac5ce96c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 15 Jan 2015 12:41:52 +0100 Subject: Consolidate "Blocking assignment to memory.." msgs for the same line --- frontends/ast/simplify.cc | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 2ce2d57dc..5ab778e66 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -51,6 +51,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { AstNode *newNode = NULL; bool did_something = false; + static pair last_blocking_assignment_warn; #if 0 log("-------------\n"); @@ -62,6 +63,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (stage == 0) { log_assert(type == AST_MODULE); + last_blocking_assignment_warn = pair(); while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { } @@ -1259,9 +1261,13 @@ skip_dynamic_range_lvalue_expansion:; sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++); std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN"; - if (type == AST_ASSIGN_EQ) - log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n", - filename.c_str(), linenum); + if (type == AST_ASSIGN_EQ) { + pair this_blocking_assignment_warn(filename, linenum); + if (this_blocking_assignment_warn != last_blocking_assignment_warn) + log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n", + filename.c_str(), linenum); + last_blocking_assignment_warn = this_blocking_assignment_warn; + } int mem_width, mem_size, addr_bits; children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits); -- cgit v1.2.3 From a588a4a5c95d14e62678c98b14af139903980be3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 15 Jan 2015 12:53:12 +0100 Subject: Fixed handling of "input foo; reg [0:0] foo;" --- frontends/ast/simplify.cc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 5ab778e66..552fc04bc 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -186,6 +186,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *first_node = this_wire_scope[node->str]; if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0) goto wires_are_compatible; + if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) { + AstNode *r = node->children[0]; + if (r->range_valid && r->range_left == 0 && r->range_right == 0) { + delete r; + node->children.pop_back(); + } + } if (first_node->children.size() != node->children.size()) goto wires_are_incompatible; for (size_t j = 0; j < node->children.size(); j++) { -- cgit v1.2.3 From df9d096a7d88955dcf44d9e30a9ba49238b478db Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 15 Jan 2015 13:08:19 +0100 Subject: Ignoring more system task and functions --- frontends/ast/simplify.cc | 4 +++- frontends/verilog/verilog_lexer.l | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 552fc04bc..6128ac684 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -157,7 +157,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, return false; // deactivate all calls to non-synthesis system taks - if ((type == AST_FCALL || type == AST_TCALL) && (str == "$display" || str == "$stop" || str == "$finish")) { + if ((type == AST_FCALL || type == AST_TCALL) && (str == "$display" || str == "$strobe" || str == "$monitor" || str == "$time" || str == "$stop" || str == "$finish" || + str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) { + log_warning("Ignoring call to system %s %s at %s:%d.\n", type == AST_FCALL ? "function" : "task", str.c_str(), filename.c_str(), linenum); delete_children(); str = std::string(); } diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 42b5bf7ea..cb8fafcb2 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -240,7 +240,7 @@ and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { supply0 { return TOK_SUPPLY0; } supply1 { return TOK_SUPPLY1; } -"$"(display|time|stop|finish) { +"$"(display|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) { frontend_verilog_yylval.string = new std::string(yytext); return TOK_ID; } -- cgit v1.2.3 From 2a9ad48eb63a5f019c528fe46ceca0065364a44d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 24 Jan 2015 12:16:46 +0100 Subject: Added ENABLE_NDEBUG makefile options --- frontends/ast/simplify.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 6128ac684..e9750eba6 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2309,8 +2309,10 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg flags &= ~children_flags | backup_flags; if (proc_flags_p) { +#ifndef NDEBUG for (auto it : *proc_flags_p) log_assert((it.second & ~0xff000000) == 0); +#endif delete proc_flags_p; } } -- cgit v1.2.3 From c8305e3a6d1e195391eb6962aac5bf7e1c548b5d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 8 Feb 2015 00:48:23 +0100 Subject: Fixed a bug with autowire bit size (removed leftover from when we tried to auto-size the wires) --- frontends/ast/genrtlil.cc | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 17d62d4dd..f48101934 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1294,15 +1294,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // add entries to current_module->connections for assignments (outside of always blocks) case AST_ASSIGN: { - if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) { - RTLIL::SigSpec right = children[1]->genRTLIL(); - RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.size()); - current_module->connect(RTLIL::SigSig(left, right)); - } else { - RTLIL::SigSpec left = children[0]->genRTLIL(); - RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size()); - current_module->connect(RTLIL::SigSig(left, right)); - } + RTLIL::SigSpec left = children[0]->genRTLIL(); + RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size()); + current_module->connect(RTLIL::SigSig(left, right)); } break; -- cgit v1.2.3 From 234a45a3d5d4b36e12d40033d58ac2ac3250fa27 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 8 Feb 2015 00:58:03 +0100 Subject: Ignore explicit assignments to constants in HDL code --- frontends/ast/genrtlil.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index f48101934..71248663e 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1296,6 +1296,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) { RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size()); + if (left.has_const()) { + RTLIL::SigSpec new_left, new_right; + for (int i = 0; i < GetSize(left); i++) + if (left[i].wire) { + new_left.append(left[i]); + new_right.append(right[i]); + } + log_warning("Ignoring assignment to constant bits at %s:%d:\n" + " old assignment: %s = %s\n new assignment: %s = %s.\n", + filename.c_str(), linenum, log_signal(left), log_signal(right), + log_signal(new_left), log_signal(new_right)); + left = new_left; + right = new_right; + } current_module->connect(RTLIL::SigSig(left, right)); } break; -- cgit v1.2.3 From 4f68a77e3f03aac0dc18caeb02b19b100f04879d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 10 Feb 2015 12:17:29 +0100 Subject: Improved read_verilog support for empty behavioral statements --- frontends/verilog/verilog_parser.y | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 621b6cc18..23cea27f1 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -946,7 +946,7 @@ simple_behavioral_stmt: // this production creates the obligatory if-else shift/reduce conflict behavioral_stmt: defattr | assert | wire_decl | - simple_behavioral_stmt ';' | + simple_behavioral_stmt ';' | ';' | hierarchical_id attr { AstNode *node = new AstNode(AST_TCALL); node->str = *$1; @@ -1060,10 +1060,6 @@ opt_synopsys_attr: } | /* empty */; -behavioral_stmt_opt: - behavioral_stmt | - ';' ; - behavioral_stmt_list: behavioral_stmt_list behavioral_stmt | /* empty */; @@ -1092,7 +1088,7 @@ case_item: ast_stack.back()->children.push_back(block); ast_stack.push_back(block); case_type_stack.push_back(0); - } behavioral_stmt_opt { + } behavioral_stmt { case_type_stack.pop_back(); ast_stack.pop_back(); ast_stack.pop_back(); -- cgit v1.2.3 From cd919abdf1177ddd5148fbf236201ce5e649ead0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 13 Feb 2015 12:33:12 +0100 Subject: Added AstNode::simplify() recursion counter --- frontends/ast/simplify.cc | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index e9750eba6..27b278be9 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -49,12 +49,16 @@ using namespace AST_INTERNAL; // nodes that link to a different node using names and lexical scoping. bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param) { + static int recursion_counter = 0; + static pair last_blocking_assignment_warn; + recursion_counter++; + AstNode *newNode = NULL; bool did_something = false; - static pair last_blocking_assignment_warn; #if 0 log("-------------\n"); + log("AST simplify[%d] depth %d at %s:%d,\n", stage, recursion_counter, filename.c_str(), linenum); log("const_fold=%d, at_zero=%d, in_lvalue=%d, stage=%d, width_hint=%d, sign_hint=%d, in_param=%d\n", int(const_fold), int(at_zero), int(in_lvalue), int(stage), int(width_hint), int(sign_hint), int(in_param)); dumpAst(NULL, "> "); @@ -145,6 +149,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } while (simplify(const_fold, at_zero, in_lvalue, 2, width_hint, sign_hint, in_param)) { } + recursion_counter--; return false; } @@ -153,8 +158,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // we do not look inside a task or function // (but as soon as a task of function is instanciated we process the generated AST as usual) - if (type == AST_FUNCTION || type == AST_TASK) + if (type == AST_FUNCTION || type == AST_TASK) { + recursion_counter--; return false; + } // deactivate all calls to non-synthesis system taks if ((type == AST_FCALL || type == AST_TCALL) && (str == "$display" || str == "$strobe" || str == "$monitor" || str == "$time" || str == "$stop" || str == "$finish" || @@ -2036,6 +2043,7 @@ apply_newNode: if (!did_something) basic_prep = true; + recursion_counter--; return did_something; } -- cgit v1.2.3 From ef151b0b30c7b7253aceba6d184e7721a4eff0c0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Feb 2015 08:41:03 +0100 Subject: Fixed handling of "//" in filenames in verilog pre-processor --- frontends/verilog/preproc.cc | 2 +- frontends/verilog/verilog_lexer.l | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 4e5d16599..e2118630e 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -201,7 +201,7 @@ static void input_file(std::istream &f, std::string filename) insert_input(""); auto it = input_buffer.begin(); - input_buffer.insert(it, "`file_push " + filename + "\n"); + input_buffer.insert(it, "`file_push \"" + filename + "\"\n"); while ((rc = readsome(f, buffer, sizeof(buffer)-1)) > 0) { buffer[rc] = 0; input_buffer.insert(it, buffer); diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index cb8fafcb2..13b3e2bfc 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -85,6 +85,10 @@ YOSYS_NAMESPACE_END fn_stack.push_back(current_filename); ln_stack.push_back(frontend_verilog_yyget_lineno()); current_filename = yytext+11; + if (!current_filename.empty() && current_filename.front() == '"') + current_filename = current_filename.substr(1); + if (!current_filename.empty() && current_filename.back() == '"') + current_filename = current_filename.substr(0, current_filename.size()-1); frontend_verilog_yyset_lineno(0); } -- cgit v1.2.3 From a8e9d37c14427527c9a810d83e183309cc5ca503 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Feb 2015 10:49:30 +0100 Subject: Creating $meminit cells in verilog front-end --- frontends/ast/ast.cc | 3 ++- frontends/ast/ast.h | 3 ++- frontends/ast/genrtlil.cc | 15 ++++++----- frontends/ast/simplify.cc | 69 ++++++++++++++++++++++++++++++----------------- 4 files changed, 57 insertions(+), 33 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 68b3327f9..589b08e1d 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -58,7 +58,7 @@ namespace AST_INTERNAL { std::map current_scope; const dict *genRTLIL_subst_ptr = NULL; RTLIL::SigSpec ignoreThisSignalsInInitial; - AstNode *current_top_block, *current_block, *current_block_child; + AstNode *current_always, *current_top_block, *current_block, *current_block_child; AstModule *current_module; } @@ -132,6 +132,7 @@ std::string AST::type2str(AstNodeType type) X(AST_TERNARY) X(AST_MEMRD) X(AST_MEMWR) + X(AST_MEMINIT) X(AST_TCALL) X(AST_ASSIGN) X(AST_CELL) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 180646267..3523d0754 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -107,6 +107,7 @@ namespace AST AST_TERNARY, AST_MEMRD, AST_MEMWR, + AST_MEMINIT, AST_TCALL, AST_ASSIGN, @@ -299,7 +300,7 @@ namespace AST_INTERNAL extern std::map current_scope; extern const dict *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; - extern AST::AstNode *current_top_block, *current_block, *current_block_child; + extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; struct ProcessGenerator; } diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 71248663e..7a78743b9 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1235,28 +1235,31 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // generate $memwr cells for memory write ports case AST_MEMWR: + case AST_MEMINIT: { std::stringstream sstr; - sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << linenum << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memwr"); + RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit"); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); int addr_bits = 1; while ((1 << addr_bits) < current_module->memories[str]->size) addr_bits++; - cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits)); cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width)); - cell->setPort("\\EN", children[2]->genRTLIL()); cell->parameters["\\MEMID"] = RTLIL::Const(str); cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits); cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width); - cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); - cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); + if (type == AST_MEMWR) { + cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); + cell->setPort("\\EN", children[2]->genRTLIL()); + cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); + cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); + } cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1); } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 27b278be9..6e5692011 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -262,6 +262,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, auto backup_current_block = current_block; auto backup_current_block_child = current_block_child; auto backup_current_top_block = current_top_block; + auto backup_current_always = current_always; + + if (type == AST_ALWAYS || type == AST_INITIAL) + current_always = this; int backup_width_hint = width_hint; bool backup_sign_hint = sign_hint; @@ -501,6 +505,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, current_block = backup_current_block; current_block_child = backup_current_block_child; current_top_block = backup_current_top_block; + current_always = backup_current_always; for (auto it = backup_scope.begin(); it != backup_scope.end(); it++) { if (it->second == NULL) @@ -1300,11 +1305,14 @@ skip_dynamic_range_lvalue_expansion:; current_scope[wire_data->str] = wire_data; while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } - AstNode *wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); - wire_en->str = id_en; - current_ast_mod->children.push_back(wire_en); - current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } + AstNode *wire_en = nullptr; + if (current_always->type != AST_INITIAL) { + wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); + wire_en->str = id_en; + current_ast_mod->children.push_back(wire_en); + current_scope[wire_en->str] = wire_en; + while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } + } std::vector x_bits_addr, x_bits_data, set_bits_en; for (int i = 0; i < addr_bits; i++) @@ -1320,13 +1328,17 @@ skip_dynamic_range_lvalue_expansion:; AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); assign_data->children[0]->str = id_data; - AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); - assign_en->children[0]->str = id_en; + AstNode *assign_en = nullptr; + if (current_always->type != AST_INITIAL) { + assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); + assign_en->children[0]->str = id_en; + } AstNode *default_signals = new AstNode(AST_BLOCK); default_signals->children.push_back(assign_addr); default_signals->children.push_back(assign_data); - default_signals->children.push_back(assign_en); + if (current_always->type != AST_INITIAL) + default_signals->children.push_back(assign_en); current_top_block->children.insert(current_top_block->children.begin(), default_signals); assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone()); @@ -1341,15 +1353,16 @@ skip_dynamic_range_lvalue_expansion:; std::vector padding_x(offset, RTLIL::State::Sx); - for (int i = 0; i < mem_width; i++) - set_bits_en[i] = offset <= i && i < offset+width ? RTLIL::State::S1 : RTLIL::State::S0; - assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_CONCAT, mkconst_bits(padding_x, false), children[1]->clone())); assign_data->children[0]->str = id_data; - assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false)); - assign_en->children[0]->str = id_en; + if (current_always->type != AST_INITIAL) { + for (int i = 0; i < mem_width; i++) + set_bits_en[i] = offset <= i && i < offset+width ? RTLIL::State::S1 : RTLIL::State::S0; + assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false)); + assign_en->children[0]->str = id_en; + } } else { @@ -1364,16 +1377,17 @@ skip_dynamic_range_lvalue_expansion:; log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; - for (int i = 0; i < mem_width; i++) - set_bits_en[i] = i < width ? RTLIL::State::S1 : RTLIL::State::S0; - assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone())); assign_data->children[0]->str = id_data; - assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), - new AstNode(AST_SHIFT_LEFT, mkconst_bits(set_bits_en, false), offset_ast->clone())); - assign_en->children[0]->str = id_en; + if (current_always->type != AST_INITIAL) { + for (int i = 0; i < mem_width; i++) + set_bits_en[i] = i < width ? RTLIL::State::S1 : RTLIL::State::S0; + assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), + new AstNode(AST_SHIFT_LEFT, mkconst_bits(set_bits_en, false), offset_ast->clone())); + assign_en->children[0]->str = id_en; + } delete left_at_zero_ast; delete right_at_zero_ast; @@ -1385,23 +1399,28 @@ skip_dynamic_range_lvalue_expansion:; assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone()); assign_data->children[0]->str = id_data; - assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false)); - assign_en->children[0]->str = id_en; + if (current_always->type != AST_INITIAL) { + assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false)); + assign_en->children[0]->str = id_en; + } } newNode = new AstNode(AST_BLOCK); newNode->children.push_back(assign_addr); newNode->children.push_back(assign_data); - newNode->children.push_back(assign_en); + if (current_always->type != AST_INITIAL) + newNode->children.push_back(assign_en); - AstNode *wrnode = new AstNode(AST_MEMWR); - wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); + AstNode *wrnode = new AstNode(current_always->type == AST_INITIAL ? AST_MEMINIT : AST_MEMWR); wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); + if (current_always->type != AST_INITIAL) + wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); wrnode->str = children[0]->str; wrnode->children[0]->str = id_addr; wrnode->children[1]->str = id_data; - wrnode->children[2]->str = id_en; + if (current_always->type != AST_INITIAL) + wrnode->children[2]->str = id_en; current_ast_mod->children.push_back(wrnode); goto apply_newNode; -- cgit v1.2.3 From 7f1a1759d7cdbbb528c451bf8fc8baf3b7e72893 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Feb 2015 11:21:12 +0100 Subject: Added "read_verilog -nomeminit" and "nomeminit" attribute --- frontends/ast/ast.cc | 8 ++++++-- frontends/ast/ast.h | 6 +++--- frontends/ast/simplify.cc | 6 +++++- frontends/verilog/verilog_frontend.cc | 16 +++++++++++++++- 4 files changed, 29 insertions(+), 7 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 589b08e1d..0de24013c 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -53,7 +53,7 @@ namespace AST { // instanciate global variables (private API) namespace AST_INTERNAL { - bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; + bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; AstNode *current_ast, *current_ast_mod; std::map current_scope; const dict *genRTLIL_subst_ptr = NULL; @@ -958,6 +958,7 @@ static AstModule* process_module(AstNode *ast, bool defer) current_module->ast = ast_before_simplify; current_module->nolatches = flag_nolatches; + current_module->nomeminit = flag_nomeminit; current_module->nomem2reg = flag_nomem2reg; current_module->mem2reg = flag_mem2reg; current_module->lib = flag_lib; @@ -969,13 +970,14 @@ static AstModule* process_module(AstNode *ast, bool defer) } // create AstModule instances for all modules in the AST tree and add them to 'design' -void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire) +void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire) { current_ast = ast; flag_dump_ast1 = dump_ast1; flag_dump_ast2 = dump_ast2; flag_dump_vlog = dump_vlog; flag_nolatches = nolatches; + flag_nomeminit = nomeminit; flag_nomem2reg = nomem2reg; flag_mem2reg = mem2reg; flag_lib = lib; @@ -1037,6 +1039,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dictast = ast->clone(); new_mod->nolatches = nolatches; + new_mod->nomeminit = nomeminit; new_mod->nomem2reg = nomem2reg; new_mod->mem2reg = mem2reg; new_mod->lib = lib; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 3523d0754..0c1135620 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -265,13 +265,13 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions struct AstModule : RTLIL::Module { AstNode *ast; - bool nolatches, nomem2reg, mem2reg, lib, noopt, icells, autowire; + bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; virtual ~AstModule(); virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters); virtual RTLIL::Module *clone() const; @@ -295,7 +295,7 @@ namespace AST namespace AST_INTERNAL { // internal state variables - extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; + extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map current_scope; extern const dict *genRTLIL_subst_ptr; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 6e5692011..10b651000 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -83,11 +83,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { AstNode *mem = it.first; uint32_t memflags = it.second; + bool this_nomeminit = flag_nomeminit; log_assert((memflags & ~0x00ffff00) == 0); if (mem->get_bool_attribute("\\nomem2reg")) continue; + if (mem->get_bool_attribute("\\nomeminit") || get_bool_attribute("\\nomeminit")) + this_nomeminit = true; + if (memflags & AstNode::MEM2REG_FL_FORCED) goto silent_activate; @@ -97,7 +101,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (memflags & AstNode::MEM2REG_FL_SET_ASYNC) goto verbose_activate; - if ((memflags & AstNode::MEM2REG_FL_SET_INIT) && (memflags & AstNode::MEM2REG_FL_SET_ELSE)) + if ((memflags & AstNode::MEM2REG_FL_SET_INIT) && (memflags & AstNode::MEM2REG_FL_SET_ELSE) && this_nomeminit) goto verbose_activate; if (memflags & AstNode::MEM2REG_FL_CMPLX_LHS) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 23d35f682..41561e80c 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -83,11 +83,20 @@ struct VerilogFrontend : public Frontend { log(" this can also be achieved by setting the 'nomem2reg'\n"); log(" attribute on the respective module or register.\n"); log("\n"); + log(" This is potentially dangerous. Usually the front-end has good\n"); + log(" reasons for converting an array to a list of registers.\n"); + log(" Prohibiting this step will likely result in incorrect synthesis\n"); + log(" results.\n"); + log("\n"); log(" -mem2reg\n"); log(" always convert memories to registers. this can also be\n"); log(" achieved by setting the 'mem2reg' attribute on the respective\n"); log(" module or register.\n"); log("\n"); + log(" -nomeminit\n"); + log(" do not infer $meminit cells and instead convert initialized\n"); + log(" memories to registers directly in the front-end.\n"); + log("\n"); log(" -ppdump\n"); log(" dump verilog code after pre-processor\n"); log("\n"); @@ -139,6 +148,7 @@ struct VerilogFrontend : public Frontend { bool flag_dump_ast2 = false; bool flag_dump_vlog = false; bool flag_nolatches = false; + bool flag_nomeminit = false; bool flag_nomem2reg = false; bool flag_mem2reg = false; bool flag_ppdump = false; @@ -186,6 +196,10 @@ struct VerilogFrontend : public Frontend { flag_nolatches = true; continue; } + if (arg == "-nomeminit") { + flag_nomeminit = true; + continue; + } if (arg == "-nomem2reg") { flag_nomem2reg = true; continue; @@ -288,7 +302,7 @@ struct VerilogFrontend : public Frontend { child->attributes[attr] = AST::AstNode::mkconst_int(1, false); } - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; -- cgit v1.2.3 From e9368a1d7e13bc691f86f25cd80981110b937cab Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Feb 2015 14:21:15 +0100 Subject: Various fixes for memories with offsets --- frontends/ast/genrtlil.cc | 10 ++++------ frontends/ast/simplify.cc | 1 + 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 7a78743b9..4b3310501 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1214,9 +1214,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width); wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - int addr_bits = 1; - while ((1 << addr_bits) < current_module->memories[str]->size) - addr_bits++; + int mem_width, mem_size, addr_bits; + id2ast->meminfo(mem_width, mem_size, addr_bits); cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits)); @@ -1243,9 +1242,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit"); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); - int addr_bits = 1; - while ((1 << addr_bits) < current_module->memories[str]->size) - addr_bits++; + int mem_width, mem_size, addr_bits; + id2ast->meminfo(mem_width, mem_size, addr_bits); cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits)); cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width)); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 10b651000..095649729 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1421,6 +1421,7 @@ skip_dynamic_range_lvalue_expansion:; if (current_always->type != AST_INITIAL) wrnode->children.push_back(new AstNode(AST_IDENTIFIER)); wrnode->str = children[0]->str; + wrnode->id2ast = children[0]->id2ast; wrnode->children[0]->str = id_addr; wrnode->children[1]->str = id_data; if (current_always->type != AST_INITIAL) -- cgit v1.2.3 From c2ba4fb2fdfde25c10930d7399bacee390a3cc65 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 18 Feb 2015 23:35:23 +0100 Subject: Convert floating point cell parameters to strings --- frontends/ast/genrtlil.cc | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 4b3310501..4a84e0a9e 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1336,16 +1336,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) continue; } if (child->type == AST_PARASET) { - if (child->children[0]->type != AST_CONSTANT) - log_error("Parameter `%s' with non-constant value at %s:%d!\n", - child->str.c_str(), filename.c_str(), linenum); - if (child->str.size() == 0) { - char buf[100]; - snprintf(buf, 100, "$%d", ++para_counter); - cell->parameters[buf] = child->children[0]->asParaConst(); - } else { - cell->parameters[child->str] = child->children[0]->asParaConst(); + IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str; + if (child->children[0]->type == AST_REALVALUE) { + log_warning("Replacing floating point parameter %s.%s = %f with string at %s:%d.\n", + log_id(cell), log_id(paraname), child->children[0]->realvalue, + filename.c_str(), linenum); + auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue)); + strnode->cloneInto(child->children[0]); + delete strnode; } + if (child->children[0]->type != AST_CONSTANT) + log_error("Parameter %s.%s with non-constant value at %s:%d!\n", + log_id(cell), log_id(paraname), filename.c_str(), linenum); + cell->parameters[paraname] = child->children[0]->asParaConst(); continue; } if (child->type == AST_ARGUMENT) { -- cgit v1.2.3 From e0e6d130cd083a8285ea2991629e0049023da234 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 19 Feb 2015 13:36:54 +0100 Subject: YosysJS stuff --- frontends/verilog/verilog_parser.y | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 23cea27f1..f2bc9c573 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -139,6 +139,7 @@ static void free_attr(std::map *al) %% input: { + ast_stack.clear(); ast_stack.push_back(current_ast); } design { ast_stack.pop_back(); -- cgit v1.2.3 From dc1a0f06fcfe545825f0a432cd42297785c98c1a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 20 Feb 2015 10:21:36 +0100 Subject: Parser support for complex delay expressions --- frontends/ast/simplify.cc | 2 +- frontends/verilog/verilog_parser.y | 27 ++++++++++++++++++++------- 2 files changed, 21 insertions(+), 8 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 095649729..ed767514b 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -61,7 +61,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log("AST simplify[%d] depth %d at %s:%d,\n", stage, recursion_counter, filename.c_str(), linenum); log("const_fold=%d, at_zero=%d, in_lvalue=%d, stage=%d, width_hint=%d, sign_hint=%d, in_param=%d\n", int(const_fold), int(at_zero), int(in_lvalue), int(stage), int(width_hint), int(sign_hint), int(in_param)); - dumpAst(NULL, "> "); + // dumpAst(NULL, "> "); #endif if (stage == 0) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index f2bc9c573..fee438a9f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -310,10 +310,17 @@ module_arg: do_not_require_port_stubs = true; }; +non_opt_delay: + '#' '(' expr ')' { delete $3; } | + '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; }; + +delay: + non_opt_delay | /* empty */; + wire_type: { astbuf3 = new AstNode(AST_WIRE); - } wire_type_token_list { + } wire_type_token_list delay { $$ = astbuf3; }; @@ -742,7 +749,7 @@ wire_name: }; assign_stmt: - TOK_ASSIGN assign_expr_list ';'; + TOK_ASSIGN delay assign_expr_list ';'; assign_expr_list: assign_expr | assign_expr_list ',' assign_expr; @@ -762,7 +769,7 @@ cell_stmt: } cell_parameter_list_opt cell_list ';' { delete astbuf1; } | - attr tok_prim_wrapper { + attr tok_prim_wrapper delay { astbuf1 = new AstNode(AST_PRIMITIVE); astbuf1->str = *$2; append_attr(astbuf1, $1); @@ -935,18 +942,19 @@ assert_property: }; simple_behavioral_stmt: - lvalue '=' expr { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $3); + lvalue '=' delay expr { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4); ast_stack.back()->children.push_back(node); } | - lvalue OP_LE expr { - AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $3); + lvalue OP_LE delay expr { + AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4); ast_stack.back()->children.push_back(node); }; // this production creates the obligatory if-else shift/reduce conflict behavioral_stmt: defattr | assert | wire_decl | + non_opt_delay behavioral_stmt | simple_behavioral_stmt ';' | ';' | hierarchical_id attr { AstNode *node = new AstNode(AST_TCALL); @@ -1327,6 +1335,11 @@ basic_expr: '(' expr ')' { $$ = $2; } | + '(' expr ':' expr ':' expr ')' { + delete $2; + $$ = $4; + delete $6; + } | '{' concat_list '}' { $$ = $2; } | -- cgit v1.2.3 From d5ce9a32ef51cd56810b3a1842dff846c1c8eab6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 20 Feb 2015 10:33:20 +0100 Subject: Added deep recursion warning to AST simplify --- frontends/ast/simplify.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index ed767514b..404dab4e8 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -51,7 +51,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { static int recursion_counter = 0; static pair last_blocking_assignment_warn; - recursion_counter++; + static bool deep_recursion_warning = false; + + if (recursion_counter++ == 1000 && deep_recursion_warning) { + log_warning("Deep recursion in AST simplifier.\nDoes this design contain insanely long expressions?\n"); + deep_recursion_warning = false; + } AstNode *newNode = NULL; bool did_something = false; @@ -69,6 +74,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(type == AST_MODULE); last_blocking_assignment_warn = pair(); + deep_recursion_warning = true; while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { } if (!flag_nomem2reg && !get_bool_attribute("\\nomem2reg")) -- cgit v1.2.3 From 1f1deda888ea32ade2478fca9fcb510ada477606 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 26 Feb 2015 18:47:39 +0100 Subject: Added non-std verilog assume() statement --- frontends/ast/ast.cc | 1 + frontends/ast/ast.h | 1 + frontends/ast/genrtlil.cc | 11 +++++++---- frontends/ast/simplify.cc | 7 +++---- frontends/verilog/verilog_frontend.cc | 12 +++++++++++- frontends/verilog/verilog_frontend.h | 3 +++ frontends/verilog/verilog_lexer.l | 5 +++-- frontends/verilog/verilog_parser.y | 10 ++++++++-- 8 files changed, 37 insertions(+), 13 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 0de24013c..0b63248d8 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -90,6 +90,7 @@ std::string AST::type2str(AstNodeType type) X(AST_IDENTIFIER) X(AST_PREFIX) X(AST_ASSERT) + X(AST_ASSUME) X(AST_FCALL) X(AST_TO_BITS) X(AST_TO_SIGNED) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 0c1135620..d57e91e5a 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -64,6 +64,7 @@ namespace AST AST_IDENTIFIER, AST_PREFIX, AST_ASSERT, + AST_ASSUME, AST_FCALL, AST_TO_BITS, diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 4a84e0a9e..c421364a3 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1265,19 +1265,22 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // generate $assert cells case AST_ASSERT: + case AST_ASSUME: { log_assert(children.size() == 2); RTLIL::SigSpec check = children[0]->genRTLIL(); - log_assert(check.size() == 1); + if (GetSize(check) != 1) + check = current_module->ReduceBool(NEW_ID, check); RTLIL::SigSpec en = children[1]->genRTLIL(); - log_assert(en.size() == 1); + if (GetSize(en) != 1) + en = current_module->ReduceBool(NEW_ID, en); std::stringstream sstr; - sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << (type == AST_ASSERT ? "$assert$" : "$assume$") << filename << ":" << linenum << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$assert"); + RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_ASSERT ? "$assert" : "$assume"); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); for (auto &attr : attributes) { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 404dab4e8..a65d2dbb1 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1211,7 +1211,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } skip_dynamic_range_lvalue_expansion:; - if (stage > 1 && type == AST_ASSERT && current_block != NULL) + if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && current_block != NULL) { std::stringstream sstr; sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++); @@ -1255,7 +1255,7 @@ skip_dynamic_range_lvalue_expansion:; newNode->children.push_back(assign_check); newNode->children.push_back(assign_en); - AstNode *assertnode = new AstNode(AST_ASSERT); + AstNode *assertnode = new AstNode(type); assertnode->children.push_back(new AstNode(AST_IDENTIFIER)); assertnode->children.push_back(new AstNode(AST_IDENTIFIER)); assertnode->children[0]->str = id_check; @@ -1266,9 +1266,8 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } - if (stage > 1 && type == AST_ASSERT && children.size() == 1) + if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && children.size() == 1) { - children[0] = new AstNode(AST_REDUCE_BOOL, children[0]->clone()); children.push_back(mkconst_int(1, false, 1)); did_something = true; } diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 41561e80c..635c9ce47 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -54,6 +54,10 @@ struct VerilogFrontend : public Frontend { log(" enable support for SystemVerilog features. (only a small subset\n"); log(" of SystemVerilog is supported)\n"); log("\n"); + log(" -formal\n"); + log(" enable support for assert() and assume() statements\n"); + log(" (assert support is also enabled with -sv)\n"); + log("\n"); log(" -dump_ast1\n"); log(" dump abstract syntax tree (before simplification)\n"); log("\n"); @@ -164,6 +168,7 @@ struct VerilogFrontend : public Frontend { frontend_verilog_yydebug = false; sv_mode = false; + formal_mode = false; log_header("Executing Verilog-2005 frontend.\n"); @@ -176,6 +181,10 @@ struct VerilogFrontend : public Frontend { sv_mode = true; continue; } + if (arg == "-formal") { + formal_mode = true; + continue; + } if (arg == "-dump_ast1") { flag_dump_ast1 = true; continue; @@ -271,7 +280,8 @@ struct VerilogFrontend : public Frontend { } extra_args(f, filename, args, argidx); - log("Parsing %s input from `%s' to AST representation.\n", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); + log("Parsing %s%s input from `%s' to AST representation.\n", + formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); AST::current_filename = filename; AST::set_line_num = &frontend_verilog_yyset_lineno; diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index e277f3e3c..5561f54cd 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -51,6 +51,9 @@ namespace VERILOG_FRONTEND // running in SystemVerilog mode extern bool sv_mode; + // running in -formal mode + extern bool formal_mode; + // lexer input stream extern std::istream *lexin; } diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 13b3e2bfc..3a57514aa 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -166,8 +166,9 @@ YOSYS_NAMESPACE_END "always_ff" { SV_KEYWORD(TOK_ALWAYS); } "always_latch" { SV_KEYWORD(TOK_ALWAYS); } -"assert" { SV_KEYWORD(TOK_ASSERT); } -"property" { SV_KEYWORD(TOK_PROPERTY); } +"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); } +"assume" { if (formal_mode) return TOK_ASSUME; return TOK_ID; } +"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); } "logic" { SV_KEYWORD(TOK_REG); } "bit" { SV_KEYWORD(TOK_REG); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index fee438a9f..d935cab37 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -57,7 +57,7 @@ namespace VERILOG_FRONTEND { std::vector case_type_stack; bool do_not_require_port_stubs; bool default_nettype_wire; - bool sv_mode; + bool sv_mode, formal_mode; std::istream *lexin; } YOSYS_NAMESPACE_END @@ -111,7 +111,7 @@ static void free_attr(std::map *al) %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED -%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_PROPERTY +%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME TOK_PROPERTY %type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int %type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list @@ -934,11 +934,17 @@ opt_label: assert: TOK_ASSERT '(' expr ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $3)); + } | + TOK_ASSUME '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3)); }; assert_property: TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $4)); + } | + TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4)); }; simple_behavioral_stmt: -- cgit v1.2.3 From 422794c5840784cab11930cfa305ed9351bb1a98 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 1 Mar 2015 11:20:22 +0100 Subject: Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker() --- frontends/ast/genrtlil.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index c421364a3..8ed8c673a 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -567,9 +567,11 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; } else - if (id_ast->children[0]->type == AST_CONSTANT) { + if (id_ast->children[0]->type != AST_CONSTANT) + while (id_ast->simplify(true, false, false, 1, -1, false, true)) { } + if (id_ast->children[0]->type == AST_CONSTANT) this_width = id_ast->children[0]->bits.size(); - } else + else log_error("Failed to detect width for parameter %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum); if (children.size() != 0) range = children[0]; -- cgit v1.2.3 From a923a63a892b8f0c39aa740c8fe207462fe2d8c8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 25 Mar 2015 19:46:12 +0100 Subject: Ignore celldefine directive in verilog front-end --- frontends/verilog/verilog_lexer.l | 3 +++ 1 file changed, 3 insertions(+) (limited to 'frontends') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 3a57514aa..8fbaa953d 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -116,6 +116,9 @@ YOSYS_NAMESPACE_END "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */ +"`celldefine"[^\n]* /* ignore `celldefine */ +"`endcelldefine"[^\n]* /* ignore `endcelldefine */ + "`default_nettype"[ \t]+[^ \t\r\n/]+ { char *p = yytext; while (*p != 0 && *p != ' ' && *p != '\t') p++; -- cgit v1.2.3